Memory device and method of operation thereof

Abstract

A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods of operating thereof.

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing, to change the threshold voltage of each memory cell to a desired level. During a read / program / erase operation of flash memory, the bit lines of the flash memory must be discharged at the end of the algorithm. The amount of charge that needs to be discharged is determined by the number of bit lines. Summary of the Invention

[0003] This article discloses memory devices and operating methods.

[0004] In one aspect, a memory device is disclosed. The memory device includes a memory cell array, multiple bit lines, a current control circuit, and a discharge enable circuit. The memory cell array includes multiple rows of memory cells. The multiple bit lines are respectively coupled to the multiple rows of memory cells. The current control circuit is coupled to the multiple bit lines to control the discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges the charge on the multiple bit lines.

[0005] In another aspect, a memory system is disclosed. The memory system includes a memory device for storing data. The memory device includes a memory cell array, multiple bit lines, and a bit line discharge circuit. The memory cell array includes multiple rows of memory cells. The multiple bit lines are respectively coupled to the multiple rows of memory cells. The bit line discharge circuit is coupled to the multiple bit lines and includes multiple first transistors and multiple second transistors. Each first transistor is coupled to one of the multiple bit lines and a reference current generator to provide a discharge current to one of the multiple bit lines during a discharge operation. Each second transistor is coupled to one of the multiple first transistors to enable the discharge operation. The discharge operation discharges charge on the multiple bit lines.

[0006] In another aspect, a method for operating a memory device is disclosed. The memory device includes a memory cell array having multiple rows of memory cells. Multiple bit lines are coupled to the multiple rows of memory cells, respectively. A bit line discharge operation is performed on the multiple bit lines. A discharge current is provided to the multiple bit lines, and the discharge current is matched with a constant current source. The multiple bit lines are electrically coupled to a ground voltage source to discharge the multiple bit lines with the discharge current. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the description, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0008] Figure 1 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0009] Figure 2A An illustration of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0010] Figure 2B An illustration of an exemplary solid-state drive (SSD) having a memory device according to some aspects of this disclosure is shown.

[0011] Figure 3 A schematic diagram of an exemplary memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0012] Figure 4 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0013] Figure 5 Detailed block diagrams of exemplary memory devices including memory cell arrays and discharge circuits according to some aspects of this disclosure are shown.

[0014] Figure 6 A detailed block diagram of another exemplary memory device, including a memory cell array and a discharge circuit, is shown according to some aspects of this disclosure.

[0015] Figure 7A Timing diagrams of discharge operations performed by an exemplary memory device according to some aspects of this disclosure are shown.

[0016] Figure 7B A timing diagram is shown of a discharge operation performed by another exemplary memory device according to some aspects of this disclosure.

[0017] Figure 8 A flowchart of a method for discharging a memory device according to some aspects of this disclosure is shown.

[0018] Figure 9A and Figure 9B A timing diagram of a discharge operation performed by a memory device is shown.

[0019] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0020] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, it is apparent that this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, as well as in ways not specifically depicted in the drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0021] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0022] During read / program / erase operations in flash memory, a relatively high positive bias voltage can be applied to each bit line, and the bit lines of the flash memory must be discharged at the end of the algorithm. The capacitance in the bit lines is primarily due to the capacitance between the bit line and ground, and the capacitance between two adjacent bit lines via direct or indirect coupling. The voltage applied to the bit lines during the read / program / erase operation charges the capacitors between adjacent bit lines and between each bit line and ground; these capacitors need to be discharged at the end of the operation. The amount of charge to be discharged can be determined by the capacitance of the bit line, the capacitance between adjacent bit lines, and the number of bit lines.

[0023] Figure 9A A timing diagram 901 illustrating a discharge operation performed by a memory device is shown. According to the capacitor discharge current expression I = (U / R)e^(-t / RC), a peak current will appear at the start t0 of the discharge operation on the bit line, and this peak current may exceed the safety limits of the flash memory, leading to unexpected problems. In the capacitor discharge current expression, I is the discharge current, U is the voltage on the bit line, R is the total resistance of the bit line, and C is the sum of the capacitance between the bit line and ground and the capacitance between adjacent bit lines. Figure 9B Another timing diagram 902 is shown for a discharge operation performed by a memory device. Bit lines can be divided into multiple groups and can be discharged sequentially. In this case, the discharge current can be divided into multiple segments, and the peak current will appear at the beginning of each segment.

[0024] To address one or more of the aforementioned problems, this disclosure provides a solution in which the discharge current is controlled and limited to a predefined value, and thus peak current can be eliminated. Furthermore, by controlling the discharge current during the discharge operation, the discharge time of the flash memory can also be shortened. As used herein, the discharge operation can be an operation of discharging charge on bit lines stored in parasitic capacitors, such as capacitors between adjacent bit lines and capacitors between each bit line and ground.

[0025] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0026] Memory device 104 can be any memory device disclosed herein. As detailed below, memory device 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have a controlled and predefined discharge current during a bit-line discharge operation. According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments using SSDs or embedded multimedia cards (eMMCs) as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0027] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0028] Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include memory cell array device 301 and peripheral circuitry 302 coupled to memory cell array device 301. Memory cell array device 301 may be a three-dimensional (3D) NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0029] like Figure 3As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 can be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). It should be understood that multiple blocks 304 may be physically or electrically stacked, and the bit lines 316 of multiple blocks 304 may be coupled together.

[0030] Figure 4 A block diagram of an exemplary memory device 400, including a memory cell array 301 and some exemplary peripheral circuitry, is shown. The peripheral circuitry includes a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, a register 414, an interface 416, and a data bus 418. It should be understood that in some examples, additional components may be included. Figure 4 Other peripheral circuits not shown.

[0031] Page buffer / sensor amplifier 404 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 412. In one example, page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into a page of memory cell array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0032] During various operations of the flash memory (e.g., read / program / erase operations), the bit lines 316 of the memory cell array 301 need to be discharged at the end of the algorithm. In one example, during an erase operation, a relatively high positive bias voltage (e.g., above 20 volts) can be applied to each bit line 316. In another example, during read and program operations, a positive bias voltage (e.g., system voltage Vdd) can be applied to the bit lines 316 coupled to a selected NAND memory string or an unselected NAND memory string. However, the voltage applied to the bit lines 316 during read / program / erase operations can charge capacitors between adjacent bit lines 316 and between bit lines 316 and ground, which need to be discharged at the end of the operation. In some embodiments, the page buffer / sensor amplifier 404 may include discharge circuitry for discharging the bit lines 316 during a discharge operation. In some embodiments, the residual voltage at the start of the discharge operation is the system voltage Vdd or any other positive bias voltage (e.g., 1 volt), and the voltage at the end of the discharge operation is 0 volts (i.e., ground).

[0033] Figure 5 A detailed block diagram of an exemplary memory device 500, including a memory cell array 301 and a discharge circuit, is shown according to some aspects of this disclosure. The memory device 500 includes a memory cell array 301, bit lines 316, current control circuitry 502, and a discharge enable circuitry 504. Bit lines 316 are coupled to a plurality of memory cell columns, such as... Figure 3 As shown in the diagram, current control circuit 502 is coupled to bit line 316 to control the discharge current during the discharge operation. Discharge enable circuit 504 is coupled to current control circuit 502 to enable the discharge operation. The discharge operation discharges the charge on multiple bit lines 316.

[0034] like Figure 5As shown, the current control circuit 502 includes a plurality of transistors 508, and each transistor 508 is coupled to a bit line 316. The current control circuit 502 also includes a reference current generator 506. The reference current generator 506 may include a constant current source 510 and a transistor 512. The drain terminal of transistor 512 is coupled to the gate terminal of transistor 512, and the drain terminal of transistor 512 is also coupled to the constant current source 510. The constant current source 510 and transistor 512 jointly provide a reference current in the current control circuit 502. The gate terminal of transistor 508 is coupled to the drain terminal and the gate terminal of transistor 512. Through these connections, transistors 508, 512, and the constant current source 510 collectively serve as a current mirror. The current value through each transistor 508 will be matched with the current value of the constant current source 510. In some embodiments, the matched current value may be the same as the current value of the constant current source 510. In some implementations, by adjusting the channel length and width of each transistor 508 and transistor 512, the matched current value can be proportional to the current value of the constant current source 510. By coupling the drain terminal of each transistor 508 to each bit line 316, the discharge current of each bit line 316 can be controlled to a matched current value.

[0035] In some embodiments, the current control circuit 502 may include an isolation signal input 524 for turning off transistor 508 and isolating bit line 316 from the discharge enable circuit 504 when the memory device 500 is not in a bit line discharge operation. The isolation signal input 524 and the reference current generator 506 may be coupled to a multiplexer. In some embodiments, the reference current generator 506 may be coupled to the gate terminal of each transistor 508 via the multiplexer during a bit line discharge operation, and the isolation signal input 524 may be coupled to the gate terminal of each transistor 508 via the multiplexer when the memory device 500 is not in a bit line discharge operation. In some embodiments, the multiplexer may include multiple switches, for example, Figure 5 Switches 514 and 516 are included. In some embodiments, the multiplexer may be included in the reference current generator 506.

[0036] This disclosure shows Figure 5 The metal-oxide-semiconductor field-effect transistor (MOSFET) current mirror is used for explanation. However, it should be understood that other variations of the current mirror can also be applied to the memory device 500, such as bipolar junction transistor (BJT) current mirrors, cascode current mirrors, self-biased cascode current mirrors, Widlar current sources, or Wilson current mirrors.

[0037] like Figure 5As shown, the discharge enable circuit 504 may include a plurality of transistors 518. In some embodiments, the discharge enable circuit 504 may be included in the page buffer / sensor amplifier 404. In some embodiments, the discharge enable circuit 504 may be a separate circuit between the page buffer / sensor amplifier 404 and the memory cell array 301. Each transistor 518 may be coupled between the source terminal of each transistor 508 and a ground voltage source 520. In some embodiments, the ground voltage source 520 is a voltage relative to the power supply voltage of the memory device 500, and the ground voltage source 520 may be 0 volts or a negative voltage corresponding to the power supply voltage of the memory device 500. The gate terminal of each transistor 518 may be coupled to a discharge enable signal 522. In a bit line discharge operation, the discharge enable signal 522 may turn on each transistor 518 to couple the bit line 316 to the ground voltage source 520.

[0038] In the bit line discharge operation, each transistor 508 is turned on, and a discharge current is provided to each transistor 508 by a reference current generator 506. Transistor 518 is turned on by a discharge enable signal 522 and electrically couples each bit line 316 to a ground voltage source 520. In some embodiments, transistor 508 may be a high-voltage (HV) transistor. In some embodiments, transistor 518 may be a low-voltage (LV) transistor. In some embodiments, transistor 508 may be an HV transistor, and transistor 518 may be an LV transistor. An HV transistor can operate at a voltage higher than that of an LV transistor. For example, an HV transistor can operate above the system voltage (e.g., at 6 volts), and an LV transistor can operate between 0 volts and the system voltage Vdd (e.g., at 2.5 volts).

[0039] Figure 5 The transistor 518 is shown to be turned on / off by the discharge enable signal 522. However, it should be understood that other types of switches capable of coupling the current control circuit 502 to the ground voltage source 520 can also be applied to the memory device 500.

[0040] Figure 7A A timing diagram 701 is shown of a discharge operation performed by a memory device 500 according to some aspects of this disclosure. For example... Figure 7A As shown, at the beginning of the bit line discharge operation, the discharge current of the memory device 500 is controlled at the discharge current I1. Since transistors 508 and 518 operate as current mirrors in the saturation region, the discharge current can be maintained at I1 during the bit line discharge operation until the discharge is complete and gradually decreases to zero.

[0041] Peak current can be eliminated by controlling and limiting the discharge current to a predefined value. Additionally, the discharge time of flash memory can be shortened by controlling the discharge current during bit line discharge operations.

[0042] Figure 6 A detailed block diagram of another exemplary memory device 600, including a memory cell array 301 and a discharge circuit, is shown according to some aspects of this disclosure. The memory device 600 includes a memory cell array 301, a bit line 316, a current control circuit 502, and a discharge enable circuit 604. Figure 6 The memory cell array 301, bit line 316, and current control circuit 502 in the memory cell array 301 and bit line 316 are related to the current control circuit 502. Figure 5 The memory cell array 301, bit line 316, and current control circuit 502 are the same or similar.

[0043] The discharge enable circuit 604 may include multiple transistors 518. For example... Figure 6 As shown, transistors 518 are divided into multiple groups, and the gate terminals of transistors 518 within the same group are connected. The discharge enable circuit 604 may also include multiple groups of delay elements 602. In some embodiments, each delay element 602 may be a digital clock delay device for delaying the discharge enable signal 522. In some embodiments, the delay element 602 may be an analog clock delay device for delaying the discharge enable signal 522. In some embodiments, the delay element 602 may be a shift register or a clock offset. In some embodiments, the delay element 602 may be one or more inverters.

[0044] The gate terminals of transistors 518 in different groups are connected to delay elements 602 at different stages, and the transistors 518 in different groups are delayed for different time periods. In other words, the transistors 512 in different groups can be sequentially enabled by interleaving the discharge enable signal 522 at different time periods.

[0045] Figure 7B A timing diagram 702 illustrates a discharge operation performed by a memory device 600 according to some aspects of this disclosure. Figure 7B In this configuration, transistors 518 are divided into four groups, and the bit line discharge operation of the memory device 600 is divided into four time periods. During each time period, the bit lines 316 of one group are enabled to discharge via a discharge enable signal 522, and the discharge current is controlled and limited to a discharge current I2. During the bit line discharge operation of each group of bit lines 316, the discharge current can be maintained at I2 until the discharge is complete and gradually decreases to zero. Then, the bit lines 316 of the next group can begin their bit line discharge operation.

[0046] Compare Figure 5The discharge enable circuit 504 and Figure 6 The discharge enable circuit 604, Figure 6 The transistors 518 in the memory device 600 are divided into four groups, and the bit line discharge operation of the memory device 600 is divided into four time periods. Therefore, in the memory device 600, the total charge on the memory cell array 301 that needs to be discharged is distributed across four time periods, and in each time period, one-quarter of all bit lines 316 of the memory cell array 301 are discharged.

[0047] Because the discharge load in each time period of memory device 600 is less than the discharge load of memory device 500, therefore Figure 7B The discharge current I2 can be designed to match a current source lower than I1. This can be achieved by using... Figure 6 The discharge enable circuit 604 can reduce the hardware requirements for the constant current source 510 and further reduce manufacturing costs.

[0048] Figure 8 A flowchart of a method 800 for discharging a memory device according to some aspects of this disclosure is shown. The memory device includes a memory cell array, and the memory cell array includes a plurality of memory cell columns. Multiple bit lines are coupled to the plurality of memory cell columns, respectively. A bit line discharge operation is performed on the multiple bit lines. In the bit line discharge operation, a discharge current can be provided to the multiple bit lines, and the discharge current is matched with a constant current source. Reference will be made together with the following for a better explanation of this disclosure. Figure 5 The memory device 500 in the middle.

[0049] In operation 802, a current mirror including a reference current generator 506 is provided to generate a reference current. Transistors 508, 512, and a constant current source 510 collectively serve as the current mirror, and the constant current source 510 and transistor 512 collectively generate the reference current. The current value through each transistor 508 is matched to the current value of the constant current source 510. In some embodiments, the matched current value may be the same as the current value of the constant current source 510. In some embodiments, the matched current value may be proportional to the current value of the constant current source 510 by adjusting the channel length and width of each transistor 508 and transistor 512.

[0050] In operation 804, a discharge current is supplied to bit line 316, and the discharge current of each bit line 316 is controlled to a matched current by coupling the drain terminal of each transistor 508 to each bit line 316.

[0051] In operation 806, a discharge enable signal 522 is provided to the gate terminal of transistor 518 to turn on transistor 518. As described above, in some embodiments, the gate terminals of all transistors 518 may be coupled to the same discharge enable signal 522 and may be turned on together. In some embodiments, transistors 518 may be divided into multiple groups, and different groups of transistors 518 may be turned on sequentially by delaying the discharge enable signal 522.

[0052] By enabling transistor 518, bit line 316 can be electrically coupled to ground voltage source 520 during operation 808, and the discharge current is controlled by current control circuit 502 matched with constant circuit source 510. Additionally, when memory device 500 is not in bit line discharge operation, isolation signal input 524 can be provided to turn off transistor 508 and isolate bit line 316 from discharge enable circuit 504.

[0053] Peak current can be eliminated by controlling and limiting the discharge current to a predefined value. Additionally, the discharge time of flash memory can be shortened by controlling the discharge current during bit line discharge operations.

[0054] According to one aspect of this disclosure, a memory device is disclosed. The memory device includes a memory cell array, multiple bit lines, a current control circuit, and a discharge enable circuit. The memory cell array includes multiple rows of memory cells. The multiple bit lines are respectively coupled to the multiple rows of memory cells. The current control circuit is coupled to the multiple bit lines to control the discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges the charge on the multiple bit lines.

[0055] In some embodiments, the current control circuit includes a current mirror having a discharge current matched to a reference current to discharge multiple bit lines during a discharge operation. In some embodiments, the current control circuit includes: a first transistor set having a plurality of first transistors, each first transistor coupled to one of the multiple bit lines; and a reference current generator coupled to the first transistor set to control the discharge current of each first transistor during a discharge operation.

[0056] In some embodiments, the reference current generator includes a constant current source providing a reference current, and each first transistor has a discharge current matched to the reference current to discharge one of the plurality of bit lines. In some embodiments, the current control circuitry also includes an isolation signal input coupled to the first transistor set to turn off the plurality of first transistors when the memory device is not in discharge operation and to isolate the plurality of bit lines from the discharge enable circuitry.

[0057] In some embodiments, the current control circuitry further includes a multiplexer coupled between a reference current generator, an isolation signal input, and a first transistor set. The reference current generator is coupled to the first transistor set via the multiplexer during discharge operation, and the isolation signal input is coupled to the first transistor set via the multiplexer when the memory device is not in discharge operation. In some embodiments, the plurality of first transistors are high-voltage transistors.

[0058] In some embodiments, the discharge enable circuit includes a plurality of second transistors, each second transistor being coupled to one of a plurality of bit lines via a current control circuit. In some embodiments, each second transistor is also coupled to a ground voltage source. In some embodiments, each second transistor is controlled by a discharge enable signal to turn on the discharge enable circuit during a discharge operation. In some embodiments, the plurality of second transistors are low-voltage transistors.

[0059] In some embodiments, multiple bit lines are divided into multiple groups, and a discharge enable circuit is configured to provide multiple interleaved signals to sequentially perform discharge operations on multiple groups of the multiple bit lines. In some embodiments, the discharge enable circuit includes multiple delay elements connected in series to provide different delays for the discharge enable signals. In some embodiments, each of the multiple delay elements is a digital clock delay device or an analog clock delay device.

[0060] In some embodiments, the discharge enable circuit is peripheral circuitry of the memory device. In some embodiments, the discharge enable circuit is located within the page buffer circuitry of the memory device. In some embodiments, the reference current is a constant current. In some embodiments, the current control circuitry is configured to control the discharge current to match a constant current source during the discharge operation. In some embodiments, the memory device is a three-dimensional (3D) NAND flash memory device, and the column of memory cells corresponds to a NAND memory string of the 3D NAND flash memory device.

[0061] According to another aspect of this disclosure, a memory system is disclosed. The memory system includes a memory device for storing data. The memory device includes a memory cell array, multiple bit lines, and a bit line discharge circuit. The memory cell array includes multiple rows of memory cells. The multiple bit lines are respectively coupled to the multiple rows of memory cells. The bit line discharge circuit is coupled to the multiple bit lines and includes multiple first transistors and multiple second transistors. Each first transistor is coupled to one of the multiple bit lines and a reference current generator to provide a discharge current to one of the multiple bit lines during a discharge operation. Each second transistor is coupled to one of the multiple first transistors to enable the discharge operation. The discharge operation discharges charge on the multiple bit lines.

[0062] In some embodiments, the reference current generator includes a third transistor and a constant current source, and the third transistor, the constant current source, and each first transistor form a current mirror. In some embodiments, the discharge current is matched to the constant current source through the current mirror. In some embodiments, each second transistor is also coupled to a ground voltage source. In some embodiments, each second transistor is controlled by a discharge enable signal to turn on multiple second transistors during discharge operation.

[0063] In some embodiments, multiple bit lines are divided into multiple groups, and discharge enable signals are sequentially provided to the multiple groups of bit lines to sequentially perform a discharge operation on each of the multiple groups of bit lines. In some embodiments, the bit line discharge circuit further includes multiple delay elements connected in series to provide different delays for sequentially providing the discharge enable signals to the multiple groups of bit lines. In some embodiments, each of the multiple delay elements is a digital clock delay device or an analog clock delay device.

[0064] In some implementations, the bit line discharge circuit further includes an isolation signal input coupled to a plurality of first transistors to turn off the plurality of first transistors when the memory device is not in discharge operation and to isolate the plurality of bit lines from the plurality of second transistors.

[0065] In some embodiments, the bit-line discharge circuit further includes a multiplexer coupled between a reference current generator, an isolation signal input, and a plurality of first transistors. The reference current generator is coupled to the plurality of first transistors via the multiplexer during discharge operation, and the isolation signal input is coupled to the plurality of first transistors via the multiplexer when the memory device is not in discharge operation. In some embodiments, the plurality of first transistors are high-voltage transistors. In some embodiments, the plurality of second transistors are low-voltage transistors.

[0066] In some implementations, the memory device is a three-dimensional (3D) NAND flash memory device, and the column of memory cells corresponds to the NAND memory string of the 3D NAND flash memory device.

[0067] According to another aspect of this disclosure, a method for operating a memory device is disclosed. The memory device includes a memory cell array having a plurality of memory cell columns. A plurality of bit lines are respectively coupled to the plurality of memory cell columns. A bit line discharge operation is performed on the plurality of bit lines. A discharge current is provided to the plurality of bit lines, and the discharge current is matched with a constant current source. The plurality of bit lines are electrically coupled to a ground voltage source to discharge the plurality of bit lines with the discharge current.

[0068] In some embodiments, a current mirror with a reference current is provided to generate a discharge current, and the discharge current is provided to multiple bit lines. In some embodiments, a constant current source is provided coupled to the drain terminal of a first transistor, and the drain terminal of the first transistor is connected to the gate terminal of the first transistor. A plurality of second transistors are provided coupled to the multiple bit lines, the drain terminal of each second transistor being coupled to one of the multiple bit lines, and the gate terminal of the first transistor being coupled to the gate terminal of each second transistor.

[0069] In some embodiments, a discharge enable signal is provided to turn on a plurality of third transistors to electrically couple multiple bit lines to a ground voltage source. In some embodiments, a plurality of third transistors are provided coupled between a plurality of second transistors and a ground voltage source, and the drain terminal of each third transistor is coupled to the source terminal of each second transistor. A discharge enable signal is provided to the plurality of third transistors to enable bit line discharge operation, and the discharge enable signal is input to the gate terminal of each third transistor. In some embodiments, when the memory device does not perform a bit line discharge operation, the multiple bit lines are isolated from the ground voltage source.

[0070] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0071] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: A memory cell array, the memory cell array comprising multiple columns of memory cells; Multiple bit lines, each of which is coupled to one of the multiple memory cell columns; A current control circuit coupled to the plurality of bit lines to control the discharge current during a discharge operation, wherein the discharge operation discharges charges on the plurality of bit lines; and A discharge enabling circuit, coupled to the current control circuit, enables the discharge operation. The discharge enable circuit includes multiple delay elements connected in series to provide different delays for the discharge enable signal. The memory device is a three-dimensional (3D) NAND flash memory device, and The current control circuit includes: A first transistor set, the first transistor set having a plurality of first transistors, each first transistor coupled to one of the plurality of bit lines; and A reference current generator, coupled to the first transistor set, is used to control the discharge current of each first transistor during the discharge operation.

2. The memory device according to claim 1, wherein, The current control circuit includes a current mirror having a discharge current matched to a reference current to discharge the plurality of bit lines during the discharge operation.

3. The memory device according to claim 1, wherein, The reference current generator includes a constant current source that provides the reference current, and each first transistor has a discharge current matched to the reference current to discharge one of the plurality of bit lines.

4. The memory device according to any one of claims 1-3, wherein, The current control circuit further includes: An isolation signal input is coupled to the first transistor set to turn off the plurality of first transistors when the memory device is not in the discharge operation and to isolate the plurality of bit lines from the discharge enable circuit.

5. The memory device according to claim 4, wherein, The current control circuit further includes: A multiplexer coupled between the reference current generator, the isolated signal input, and the first transistor set. The reference current generator is coupled to the first transistor set via the multiplexer during the discharge operation, and the isolation signal input is coupled to the first transistor set via the multiplexer when the memory device is not in the discharge operation.

6. The memory device according to any one of claims 1-3, wherein, The plurality of first transistors are high-voltage transistors.

7. The memory device according to claim 1, wherein, The discharge enable circuit includes a plurality of second transistors, each of which is coupled to one of the plurality of bit lines through the current control circuit.

8. The memory device according to claim 7, wherein, Each second transistor is also coupled to a ground voltage source.

9. The memory device according to any one of claims 7-8, wherein, Each second transistor is controlled by the discharge enable signal to turn on the discharge enable circuit during the discharge operation.

10. The memory device according to any one of claims 7-8, wherein, The plurality of second transistors are low-voltage transistors.

11. The memory device according to claim 1, wherein, The multiple bit lines are divided into multiple groups, and the discharge enable circuit is configured to provide multiple interleaved signals to sequentially perform the discharge operation on the multiple groups of the multiple bit lines.

12. The memory device according to claim 1, wherein, Each of the plurality of delay elements is a digital clock delay device or an analog clock delay device.

13. The memory device according to claim 1, wherein, The discharge enable circuit is a peripheral circuit of the memory device.

14. The memory device according to claim 1, wherein, The discharge enable circuit is located in the page buffer circuit of the memory device.

15. The memory device according to claim 2, wherein, The reference current is a constant current.

16. The memory device according to claim 1, wherein, The current control circuit is configured to control the discharge current to match the constant current source in the discharge operation.

17. The memory device according to claim 1, wherein, The memory cell column corresponds to the NAND memory string of the three-dimensional NAND flash memory device.

18. A memory system comprising: A memory device configured to store data, the memory device comprising: A memory cell array, the memory cell array comprising multiple columns of memory cells; Multiple bit lines, each bit line being coupled to one of the multiple columns of memory cells; and Bit line discharge circuit, coupled to the plurality of bit lines, the bit line discharge circuit comprising: A plurality of first transistors, each first transistor coupled to one of the plurality of bit lines and a reference current generator, are configured to provide a discharge current to one of the plurality of bit lines during a discharge operation, wherein the discharge operation discharges charge on the plurality of bit lines; and Multiple second transistors, each coupled to one of the multiple first transistors, to enable the discharge operation. The bit line discharge circuit further includes multiple delay elements connected in series to provide different delays for the discharge enable signal. The memory device is a three-dimensional (3D) NAND flash memory device.

19. The memory system according to claim 18, wherein, The reference current generator includes a third transistor and a constant current source, and the third transistor, the constant current source, and each first transistor form a current mirror.

20. The memory system of claim 19, wherein, The discharge current is matched with the constant current source through the current mirror.

21. The memory system according to claim 18, wherein, Each second transistor is also coupled to a ground voltage source.

22. The memory system according to any one of claims 18-21, wherein, Each second transistor is controlled by the discharge enable signal to turn on the plurality of second transistors during the discharge operation.

23. The memory system according to any one of claims 18-21, wherein, The multiple bit lines are divided into multiple groups, and the discharge enable signal is sequentially provided to the multiple groups of the multiple bit lines to sequentially perform the discharge operation for each of the multiple groups of the multiple bit lines.

24. The memory system according to claim 23, wherein, The series-connected multiple delay elements are used to sequentially provide different delays to the multiple groups of the multiple bit lines for the discharge enable signal.

25. The memory system according to any one of claims 18-21 and 24, wherein, Each of the plurality of delay elements is a digital clock delay device or an analog clock delay device.

26. The memory system according to claim 18, wherein, The bit line discharge circuit further includes: An isolation signal input is coupled to the plurality of first transistors to turn off the plurality of first transistors when the memory device is not in the discharge operation, and to isolate the plurality of bit lines from the plurality of second transistors.

27. The memory system according to claim 26, wherein, The bit line discharge circuit further includes: A multiplexer coupled between the reference current generator, the isolated signal input, and the plurality of first transistors. The reference current generator is coupled to the plurality of first transistors via the multiplexer during the discharge operation, and the isolation signal input is coupled to the plurality of first transistors via the multiplexer when the memory device is not in the discharge operation.

28. The memory system according to claim 26, wherein, The plurality of first transistors are high-voltage transistors.

29. The memory system according to claim 26, wherein, The plurality of second transistors are low-voltage transistors.

30. The memory system according to claim 18, wherein, The memory cell column corresponds to the NAND memory string of the three-dimensional NAND flash memory device.

31. A method for operating a memory device, the memory device comprising a memory cell array and a plurality of bit lines, the memory cell array comprising a plurality of memory cell columns, the plurality of bit lines being respectively coupled to the plurality of memory cell columns, the method comprising: A current control circuit coupled to the multiple bit lines performs a bit line discharge operation on the multiple bit lines, including: Discharge current is provided to the plurality of bit lines, wherein the discharge current is matched with a constant current source; and The plurality of bit lines are electrically coupled to a ground voltage source so that the plurality of bit lines are discharged using the discharge current. The method further includes using multiple delay elements connected in series to provide different delays for the discharge enable signal. The memory device is a three-dimensional (3D) NAND flash memory device, and The current control circuit includes: A second transistor set, the second transistor set having a plurality of second transistors, each second transistor coupled to one of the plurality of bit lines; and A reference current generator, coupled to the second transistor set, is used to control the discharge current of each second transistor during the discharge operation.

32. The method according to claim 31, wherein, Providing the discharge current to the plurality of bit lines includes: A current mirror with a reference current is provided to generate the discharge current; and The discharge current is provided to the plurality of bit lines.

33. The method according to claim 32, wherein, Providing the current mirror with the reference current to generate the discharge current includes: A constant current source is provided coupled to the drain terminal of a first transistor, wherein the drain terminal of the first transistor is connected to the gate terminal of the first transistor; and The plurality of second transistors are provided coupled to the plurality of bit lines, wherein the drain terminal of each second transistor is coupled to one of the plurality of bit lines, and the gate terminal of the first transistor is coupled to the gate terminal of each second transistor.

34. The method according to any one of claims 31-33, wherein, Electrically coupling the plurality of bit lines to the ground voltage source to discharge the plurality of bit lines with the discharge current includes: The discharge enable signal is provided to turn on a plurality of third transistors to electrically couple the plurality of bit lines to the ground voltage source.

35. The method according to claim 34, wherein, Providing the discharge enable signal to turn on the plurality of third transistors to electrically couple the plurality of bit lines to the ground voltage source includes: Provides a plurality of third transistors coupled between the plurality of second transistors and the ground voltage source, wherein the drain terminal of each third transistor is coupled to the source terminal of each second transistor; and The discharge enable signal is provided to the plurality of third transistors to enable the bit line discharge operation, wherein the discharge enable signal is input to the gate terminal of each third transistor.

36. The method of claim 31, further comprising: When the memory device does not perform the bit line discharge operation, the multiple bit lines are isolated from the ground voltage source.

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