Memory device with failed-bank repair using redundant bank

Abstract

In certain aspects, a memory device includes an array of memory cells, input / output (I / O) circuitry, and control logic coupled to the I / O circuitry. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer and N is greater than M. The I / O circuitry is coupled to the N main banks and the M redundant banks and is configured to direct N data segments to or from N active banks, respectively. The control circuitry is configured to determine N active banks from the N main banks and the M redundant banks based on bank failure information indicating K failed main banks of the N main banks. The N active banks include K redundant banks of the M redundant banks, where K is a positive integer no greater than M. The control circuitry is further configured to control the I / O circuitry to direct K data segments of the N data segments to or from the K redundant banks, respectively.

Description

BACKGROUND

[0001] The disclosure relates to a memory device and an operating method thereof.

[0002] Flash memory is a low cost, high density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory or NAND flash memory. As the number of memory cells in a flash memory continues to increase, faulty (bad) memory cells can occur during fabrication of the memory device.

[0003] For example, most NAND flash memory devices ship from foundries with some faulty memory cells. These cells are typically identified according to a specified faulty cell marking strategy. By allowing some bad cells, manufacturers can achieve higher yields than would be possible if all cells had to be verified as good. This significantly reduces NAND flash memory cost and only slightly reduces the storage capacity of the component. SUMMARY

[0004] In one aspect, a memory device includes an array of memory cells, an input / output (I / O) circuit, and control logic coupled to the I / O circuit. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. The I / O circuit is coupled to the N main banks and the M redundant banks and is configured to direct N data segments to or from N active banks, respectively. The control circuit is configured to determine the N active banks from the N main banks and the M redundant banks based on bank failure information indicating K faulty main banks of the N main banks. The N active banks include K redundant banks of the M redundant banks, where K is a positive integer not greater than M. The control circuit is further configured to control the I / O circuit to direct K data segments of the N data segments to or from the K redundant banks, respectively.

[0005] In another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells, I / O circuitry, and control logic coupled to the I / O circuitry. The array of memory cells includes N number of main banks and M number of redundant banks, where each of N and M is a positive integer and N is greater than M. The I / O circuitry is coupled to the N number of main banks and the M number of redundant banks and is configured to direct N number of data segments to or from N number of working banks, respectively. The control circuitry is configured to determine the N number of working banks from the N number of main banks and the M number of redundant banks based on bank failure information indicating K number of failed main banks of the N number of main banks. The N number of working banks includes K number of redundant banks of the M number of redundant banks, where K is a positive integer not greater than M. The control circuitry is further configured to control the I / O circuitry to direct K number of data segments of the N number of data segments to or from the K number of redundant banks, respectively.

[0006] In yet another aspect, a method for operating a memory device is provided. The memory device includes an array of memory cells, the array of memory cells including N number of main banks and M number of redundant banks, where each of N and M is a positive integer and N is greater than M. N number of working banks are determined from the N number of main banks and the M number of redundant banks based on bank failure information indicating K number of failed main banks of the N number of main banks. The N number of working banks includes K number of redundant banks of the M number of redundant banks, where K is a positive integer not greater than M. K number of data segments of N number of data segments are directed to or from K number of redundant banks, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0008] Figure 1 A block diagram of an exemplary system having a memory device is shown in accordance with some aspects of the present disclosure.

[0009] Figure 2A A diagram of an exemplary memory card having a memory device is shown in accordance with some aspects of the present disclosure.

[0010] Figure 2B A diagram of an exemplary solid state drive (SSD) having a memory device is shown in accordance with some aspects of the present disclosure.

[0011] Figure 3 A diagram of an exemplary memory device including peripheral circuitry is shown in accordance with some aspects of the present disclosure.

[0012] Figure 4 A block diagram illustrating an exemplary memory device including an array of memory cells and peripheral circuitry is shown in accordance with some aspects of the present disclosure.

[0013] Figure 5 A block diagram of a memory device implementing a failed main bank repair scheme using a redundant bank is shown.

[0014] Figure 6A and Figure 6B A failed main bank repair scheme using a redundant bank implemented by a memory device in Figure 5 is shown.

[0015] Figure 7 A block diagram illustrating an exemplary memory device implementing a failed main bank repair scheme using a redundant bank in data input is shown in accordance with some aspects of the present disclosure.

[0016] Figure 8 A block diagram illustrating an exemplary memory device implementing a failed main bank repair scheme using a redundant bank in data output is shown in accordance with some aspects of the present disclosure.

[0017] Figure 9 A block diagram illustrating exemplary control logic of a memory device in Figure 7 and Figure 8 is shown.

[0018] Figures 10A-10C A failed main bank repair scheme using a redundant bank implemented by a memory device in Figures 7-9 is shown.

[0019] Figure 11 A flow diagram illustrating an exemplary method for operating a memory device having a failed main bank and a redundant bank is shown in accordance with some aspects of the present disclosure.

[0020] Figure 12 A flow diagram illustrating another exemplary method for operating a memory device having a failed main bank and a redundant bank is shown in accordance with some aspects of the present disclosure.

[0021] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the disclosure. Moreover, it will be apparent that the disclosure can be employed preformed in numerous other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified, both separately and in various combinations, and in ways not specifically described in the figures, such that the combinations, adjustments, and modifications are within the scope of the disclosure.

[0023] Generally, the terminology can be understood at least in part from usage of the terms in the context in which they are used. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics, in the plural, depending at least in part upon context. Similarly, terms, such as "a" and "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily requiring exclusively factual derivations and instead can allow for approximation based on learned information, as little as a single bit of information, again, depending at least in part on context.

[0024] As the number of memory cells continues to increase to meet the ever-increasing demand for greater storage capacity, the opportunity for memory cell failure also increases during the manufacture of the memory device. One way to handle failed memory cells is to add a region of redundant memory cells (e.g., a redundant bank, also known as a redundant column or redundant group) in addition to a region of main memory cells (e.g., a main bank, also known as a main column or main group). For each memory device, if the number of failed memory cell regions identified during post-manufacture testing is below a limit (e.g., no greater than the number of redundant memory cell regions), a repair scheme can be employed such that the redundant memory cell regions can replace the failed memory cell regions for reading and writing data while the memory device is in operation.

[0025] Some known memory devices (e.g., NAND flash memory devices) can perform parallel data input / output (I / O) operations to write 8 pieces of data (e.g., 8 bytes) to or read 8 pieces of data (e.g., 8 bytes) from 8 physically separate regions of main memory cells (e.g., main banks). An equal number of 8 regions of redundant memory cells (e.g., redundant banks) are respectively coupled to the regions of main memory cells. According to known repair schemes, once a region of main memory cells is identified as a faulty region of main memory cells, the corresponding region of redundant memory cells replaces the faulty region of memory cells in the data input and output. However, such repair schemes and redundant bank designs have various problems. For example, a large number of redundant banks can waste chip area because typically not all of the banks are used. The relatively large number of redundant banks can also affect the flexibility of the repair scheme. In addition, the extra length of wiring used to couple each main bank and the corresponding redundant bank can increase skew of the data lines.

[0026] To address one or more of the concerns described above, the present disclosure introduces a solution in which fewer redundant banks than the number of main banks can be used to handle faulty main banks in a memory device (e.g., a NAND flash memory device) along with a flexible repair scheme. Consistent with certain aspects of the present disclosure, multiplexers can be used to couple adjacent banks so that input or output data can be shifted between adjacent banks (main or redundant). As a result, the redundant banks are no longer dedicated to a particular main bank and can replace any faulty main bank without being coupled to each main bank. Thus, the total chip area of the redundant banks and the opportunity to waste redundant bank area can be significantly reduced. In addition, because of the data shift-based repair scheme, each bank is coupled to only adjacent bank(s), the skew between each data line can also be reduced and the length of the wiring of the data lines is shortened. The redundant bank design and data shift-based repair scheme disclosed herein can increase repair flexibility even with fewer redundant banks compared to known methods.

[0027] Figure 1 A block diagram of an exemplary system 100 having a memory device is shown in accordance with some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1, the system 100 includes a memory device 102, a processor 104, and a bus 106. The bus 106 can be a hardware / software interface that enables the processor 104 to communicate with the memory device 102. The bus 106 can include a data bus, a control bus, and a power bus. The bus 106 can be a proprietary bus, a PCI bus, a HyperTransport® bus, a USB bus, a 1394 bus, or any other suitable bus. Figure 1As shown in the middle, the system 100 can include a host 108 and a storage system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 can be configured to send or receive data to or from the memory device 104.

[0028] The memory device 104 can be any memory device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device) can include fewer redundant banks than the number of main banks and implement a flexible data shift based repair scheme in data input and output operations to handle faulty main banks identified during post-manufacturing testing of the memory device 104.

[0029] According to some embodiments, a memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptops, etc. and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0030] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. For example, the memory system 102 can be implemented and packaged into a mobile phone, a tablet computer, a laptop computer, a digital camera, a digital camcorder, a digital audio player, a digital video player, a digital radio, a global positioning system (GPS) device, a smart watch, a smart home device, a smart car, a smart appliance, a smart city device, a smart grid device, a smart meter, a smart card, a smart card reader, a smart card terminal, a smart card Figure 2AIn one example shown in FIG. 1, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1). In another example shown in FIG. 2, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. Figure 1 Figure 2B Figure 1

[0031] Figure 3 A schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit is shown in accordance with some aspects of the present disclosure. The memory device 300 can be an example of the memory device 104 in FIG. 1. The memory device 300 can include a memory cell array device 301 and a peripheral circuit 302 coupled to the memory cell array device 301. The memory cell array device 301 can be a NAND flash memory cell array in which memory cells 306 are provided in an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or a charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge trapping transistor. Figure 1

[0032] ​​​​In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0033] like Figure 3 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the SSG 310 of the NAND memory strings 308 in the same block 304 is coupled to, for example, ground via the same source line (SL) 314 (e.g., common SL). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0034] like Figure 3As shown in FIG. 3, the NAND memory strings 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314. In some embodiments, each block 304 is the basic unit of data for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. Memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic unit of data for program operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by a word line 318 in one block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding page 320 as well as a gate line that couples the control gates.

[0035] The peripheral circuitry 302 can be coupled to the memory cell array 301 by the bit lines 316, the word lines 318, the source lines 314, the SSG lines 315, and the DSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the SSG lines 315, and the DSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Some example peripheral circuitry 302 is shown, including page buffers / sense amplifiers 404, column decoders / bit line drivers 406, I / O circuitry 407, row decoders / word line drivers 408, voltage generators 410, control logic 412, registers 414, an interface 416, and a data bus 418. It should be understood that additional peripheral circuitry not shown in FIG. 3 can also be included in some examples. Figure 4

[0036] ​The page buffer / sense amplifier 404 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 can store a page of program data (write data) to be programmed into one of the pages 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 404 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 404 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify the small voltage swings to identifiable logic levels in read operations.

[0037] The column decoder / bit line driver 406 can be configured to be controlled by the control logic 412 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 410. The I / O circuitry 407 can be coupled to the page buffer / sense amplifier 404 and / or the column decoder / bit line driver 406 and configured to direct (route) data input from the data bus 418 to a desired memory cell region (e.g., bank) of the memory cell array 301 and direct (route) data output from the desired memory cell region to the data bus 418. As described in detail below, the I / O circuitry 407 can include a multiplexer (MUX) array to implement the flexible data shift based repair scheme disclosed herein as controlled by the control logic 412.

[0038] The row decoder / word line driver 408 can be configured to be controlled by the control logic 412 and select the blocks 304 of the memory cell array 301 and the word lines 318 of the selected blocks 304. The row decoder / word line driver 408 can also be configured to drive the selected word lines 318 using word line voltages generated from the voltage generator 410. The voltage generator 410 can be configured to be controlled by the control logic 412 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be supplied to the memory cell array 301.

[0039] Control logic 412 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 414 can be coupled to control logic 412 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits. Interface 416 can be coupled to control logic 412 and act as a control buffer to buffer control commands received from a host (not shown) and forward them to control logic 412, and to buffer status information received from control logic 412 and forward them to the host. Interface 416 can also be coupled to I / O circuitry 407 via data bus 418 and act as a data I / O interface and data buffer to buffer write data received from the host (not shown) and forward them to I / O circuitry 407, and to buffer read data from I / O circuitry 407 and forward them to the host. For example, interface 416 can include data I / O 417 coupled to data bus 418.

[0040] Figure 5 A block diagram of a memory device 500 implementing a failed-bank repair scheme using redundant banks is shown. An array of memory cells 301 in memory device 500 includes i groups of 8 main banks 502 (<0>… and <7>) and j groups of 8 redundant banks 504 (<0>… and <7>), and each main bank 502 is coupled to a respective redundant bank 504 via a respective data line (L<0>…, or L<7>). That is, in the case where a main bank 502 is identified as a failed main bank during post-manufacture testing, each main bank 502 has its dedicated redundant bank 504 as a backup thereof. Memory device 500 is capable of inputting or outputting 8 data segments (e.g., 8 bytes) in parallel to or from 8 main banks 502, respectively. Memory device 500 includes i groups of 8 main banks 502 and j groups of 8 redundant banks 504.

[0041] Column decoders / bit line drivers 406 of memory device 500 include i main decoders 510 coupled to i groups of 8 main banks 502, respectively, and j redundant decoders 511 coupled to j groups of 8 redundant banks 504, respectively. Column decoders / bit line drivers 406 of memory device 500 further include a main predecoder 506 coupled to i main decoders 510 and a redundant (RED) predecoder 508 coupled to j redundant decoders 511. Control logic 412 of memory device 500 implements the failed-bank repair scheme by controlling main predecoder 506 and redundant predecoder 508 via control signals (e.g., a redundant enable signal (RED EN)). Based on the control signals from control logic 412, main predecoder 506 uses select / deselect signals (YSEL<0>…, and YSEL<7>) to select or deselect i main decoders 510, and redundant predecoder 508 uses select / deselect signals (YSEL<0>…, and YSEL<7>) to select or deselect j redundant decoders 511. For example, in the case where a main bank 502 is identified as a failed main bank, control logic 412 can control main predecoder 506 and redundant predecoder 508 to select the main decoder 510 and the redundant decoder 511 corresponding to the failed main bank 502, respectively. ) to disable any of the 8 main banks 502 in the respective main bank group that is a faulty main bank. On the other hand, based on a control signal from the control logic 412, the redundant pre-decoder 508 uses select / deselect signals (YREDSEL<0>..., and YREDSEL <j>Each of the j redundant decoders 511 enables any one of the 8 redundant banks 504 in the respective redundant bank group coupled to the corresponding failing main bank through the respective bit line. The page buffers / sense amplifiers 404 of the memory device 500 are shared by the main banks 502 and the redundant banks 504 for read and write operations.

[0042] Figure 6A and Figure 6B shows the use of the failing main bank repair scheme using redundant banks implemented by the memory device 500 in Figure 5 . Figure 6A and Figure 6B shows a set of 8 main banks 502 and a set of 8 redundant banks 504. The 8 main banks 502 include bank 0 low (B0_L), bank 0 high (B0_H), bank 1 low (B1_L), bank 1 high (B1_H), bank 2 low (B2_L), bank 2 high (B2_H), bank 3 low (B3_L), and bank 3 high (B3_H). The 8 main banks 502 are isolated from each other, meaning that a data segment directed to one main bank 502 cannot be redirected to another main bank 502 as they are not coupled through data lines. Instead, each main bank 502 is coupled to a respective redundant bank 504 (e.g., B0_L to B0_R, B0_H to B0_R, B1_L to B1_R, B1_H to B1_R, B2_L to B2_R, B2_H to B2_R, B3_L to B3_R, and B3_H to B3_R) through a data line (e.g., L<0>…, or L<7>) on the right side adjacent to the respective redundant bank 504. Figure 6A and Figure 6B . Figure 5

[0043] Figure 6A shows a case where all 8 main banks 502 are working banks, i.e., no failing main bank is identified by post-manufacturing testing. In this case, the first 8 data segments (0…, and 7) are directed to or from the 8 main banks 502, respectively, without using all 8 redundant banks 504, i.e., no data (marked as “x”). Similarly, the second 8 data segments (8…, and 15) are again directed to or from the 8 main banks 502, respectively, without all 8 redundant banks 504 remaining unused, i.e., no data (marked as “x”).

[0044] Figure 6B ​One of the eight main banks 502 is shown to be a failed main bank identified through post-manufacturing testing. In one example where B2_H is the failed main bank, seven of the first eight data segments (0, 1, 2, 3, 4, 6, and 7) are directed to or from the seven working main banks 502 (except B2_H) respectively, while data (5) is redirected to or from B2_H. That is, the failed main bank B2_H is replaced by a dedicated backup redundant bank 504 coupled to B2_H for data input and output. In another example where B0_L is the failed main bank, seven of the second eight data segments (9…, and 15) are directed to or from the seven working main banks 502 (except B0_L) respectively, while data (8) is redirected to or from the redundant bank 504 coupled to B0_L. That is, the failed main bank B0_L is replaced by a dedicated backup redundant bank 504 coupled to B0_L for data input and output.

[0045] As described above, Figure 5 , Figure 6A and Figure 6B The redundant bank designs and associated repair schemes shown in

[0046] To overcome one or more of these problems, the present disclosure provides an improved redundant bank design with a smaller number of redundant banks and an associated flexible data shift-based repair scheme. Consistent with the scope of the present disclosure, a memory device can include a memory cell array (e.g., the memory cell array 301 in Figure 3 and Figure 4 the I / O circuit 407 in Figure 4 and Figure 4 the control logic 412 in Figure 5 Similar to memory device 500 in FIG. 6, the memory cell array can include a plurality of sets of N main banks and a plurality of sets of M redundant banks. However, N is the number of data segments that can be input (written / programmed) to and output (read) from the memory cell array in parallel. It should also be understood that the term "bank" (in the context of "main bank," "redundant bank," or "working bank") as used herein can refer to a region of memory cells to or from which one of the N parallel data segments is directed. For example, a bank can be a portion of a page, block, or face in the memory cell array.

[0047] The I / O circuitry can be coupled to the N main banks and the M redundant banks and configured to direct the N data segments to or from the N working banks, respectively. In some embodiments, the I / O circuitry is coupled to each pair of adjacent banks in the N main banks and the M redundant banks, such that the I / O circuitry is configured to direct one of the N data segments to or from either bank in the pair of adjacent banks.

[0048] In some embodiments, M is equal to 1. That is, a single redundant bank can be used to repair a set of N (2, 3, 4, 5, etc.) main banks, which can significantly reduce the chip area of the redundant bank and waste of unused redundant banks. For example, Figure 7 and Figure 8 A block diagram of an exemplary memory device 700 that implements a failed main bank repair scheme using a redundant bank in data input and data output, respectively, in accordance with some aspects of the present disclosure is shown. Memory device 700 can be an example of memory device 300 in Figure 3 and Figure 4 For ease of description, details of components in memory device 300 can be omitted in the description of memory device 700 and can be similarly applied to memory device 700. As Figure 7 and Figure 8 As shown in FIG. 6, memory device 700 can include a memory cell array 301 having 8 main banks 702 (B0_L, B0_H, B1_L, B1_H, B2_L, B2_H, B3_L, and B3_H) and 1 redundant bank 704 (RED). That is, in memory device 700, N is equal to 8 and M is equal to 1. In other words, according to some embodiments, memory cell array 301 includes 9 banks, the 9 banks including 8 main banks 702 and 1 redundant bank 704.

[0049] I / O circuitry 407 can be coupled to the 8 main banks 702 and the 1 redundant bank 704, for example, through page buffers / sense amplifiers 404 and column decoders / bit line drivers 406. In Figure 7 In some implementations shown in FIG. 4, in data input (e.g., write operation), page buffer / sense amplifier 404 and column decoder / bit line driver 406 include 9 drivers 706 coupled to 8 main banks 702 and 1 redundant bank 704, respectively. In Figure 8 In some implementations shown in FIG. 4, in data output (e.g., read operation), page buffer / sense amplifier 404 and column decoder / bit line driver 406 include 9 sense amplifiers 802 coupled to 8 main banks 702 and 1 redundant bank 704, respectively.

[0050] I / O circuit 407 can be configured to direct 8 data segments to or from 8 working banks, respectively. In Figure 7 In some implementations shown in FIG. 4, in data input, I / O circuit 407 is configured to direct 8 input data segments (e.g., write data: gwd<7:0>, gwd<15:8>, gwd<23:16>, gwd<31:24>, gwd<39:32>, gwd<47:40>, gwd<55:48>, and gwd<63:56>) to 8 working banks (e.g., 7 main banks 702 and 1 redundant bank 704) out of 9 banks (i.e., 8 main banks 702 and 1 redundant bank 704). In Figure 8 In some implementations shown in FIG. 4, in data output, I / O circuit 407 is configured to direct 8 output data segments (e.g., read data: grd<7:0>, grd<15:8>, grd<23:16>, grd<31:24>, grd<39:32>, grd<47:40>, grd<55:48>, and grd<63:56>) from 8 working banks (e.g., 7 main banks 702 and 1 redundant bank 704) out of 9 banks. As Figure 7 and Figure 8 As shown in FIG. 4, in some implementations, I / O circuit 407 is coupled to each pair of adjacent banks such that I / O circuit 407 is configured to direct one write data segment (gwd) to or from either bank in a pair of adjacent banks. A pair of adjacent banks can be two main banks 702 or can be one main bank 702 and one redundant bank 704. In some implementations, redundant bank 704 is coupled to two main banks 702 by I / O circuit 407. It should be understood that although redundant bank 704 is coupled to two main banks 702 (B1_H and B2_L) by I / O circuit 407 in between 8 main banks 702, as shown in FIG. 4, redundant bank 704 can be coupled to two main banks 702 (B1_H and B2_L) by I / O circuit 407 in between any two main banks 702. Figure 7 and Figure 8 As shown, however, in some examples, the redundant library 704 can be coupled to any two main libraries 702 via I / O circuit 407, or coupled to only one main library 702 at the end of the eight main libraries 702 (e.g., B0_L or B3_H).

[0051] The I / O circuit 407 can be implemented using a MUX array. Figure 7 In some embodiments shown, the I / O circuitry 407 of the memory device 700 includes a set of nine write MUXs 708 coupled to eight main libraries 702 and one redundant library 704 for data input. Each write MUX 708 may include an output (Out), two inputs (A and B), and a select port (S). The output of each write MUX 708 is coupled to a corresponding library 702 or 704. The select port of the write MUX 708 can be configured to receive a write select signal (red_en_b0_l_wt…, red_en_b12_wt…, or red_en_b3_h_wt) indicating the selection of an input (A or B). For example, a positive bias write select signal (i.e., an enable write select signal) can select input B. In some implementations, in addition to the write MUX 708 coupled at the ends to two master libraries 702 (B0_L and B3_H) (i.e., coupled to only one other master library 702), each write MUX 708 coupled to a respective master library 702 has two inputs configured to input two data segments, each including a write data segment intended for the respective master library 702 and another write data segment intended for an adjacent master library 702. For example, the write MUX 708 coupled to B0_H may have input A configured to input write data gwd<15:8> and input B configured to input write data gwd<7:0>. As for the write MUX 708 coupled to the redundant library 704, it may have two inputs configured to input two data segments, each including a write data segment intended for one adjacent master library 702 and another write data segment intended for another adjacent master library 702. For example, a write MUX 708 coupled to RED can have input A configured to input write data gwd<31:24> and input B configured to input write data gwd<39:32>. In other words, each write data segment can be coupled to both inputs of two adjacent libraries and can be input to either input of the two adjacent libraries. As for the write MUX 708 coupled at the ends to two master libraries 702 (B0_L and B3_H), one of its inputs can be configured to input a write data segment intended for the corresponding master library 702, and the other of its inputs can be configured to input a signal indicating data inactivation due to a library failure (e.g., system voltage Vdd).

[0052] exist Figure 8 In some embodiments shown, the I / O circuitry 407 of the memory device 700 includes a set of eight read MUX 804s coupled to one redundant library 704 of eight main libraries 702 for data output. Each read MUX 804 may include an output (Out), two inputs (A and B), and a select port (S). The select port of the read MUX 804 may be configured to receive a read select signal (red_en_b0_l_rd…, or red_en_b3_h_rd) indicating the selection of an input (A or B). For example, a positive bias read select signal (i.e., an enable read select signal) can select input B. In some embodiments, each read MUX 804 has two inputs coupled to two adjacent libraries. For example, the leftmost read MUX 804 may have input A coupled to B0_L and input B coupled to B0_H; the middle read MUX 804 may have input A coupled to B1_H and input B coupled to RED. In other words, in addition to the two master libraries 702 (B0_L and B3_H) at the ends, each library 702 or 704 can be coupled to the inputs of two read MUX 804s respectively. The output of each read MUX 804 can be configured to output a data segment from input A or input B based on a corresponding read selection signal, i.e., any data segment stored in the two adjacent libraries. For example, the read data gwd<7:0> output from the leftmost read MUX 804 can come from B0_L or B0_H; the read data gwd<31:24> output from the middle read MUX 804 can come from B1_H or RED.

[0053] As mentioned above Figure 9 and Figure 7 The I / O circuit 407 can be coupled to each pair of adjacent libraries and is configured to direct data segments to or from any library in each pair of adjacent libraries. It should be understood that although the exemplary design of the MUX array in the I / O circuit 407 was described above with respect to a memory device 700 having 8 master libraries 702 and 1 redundant library 704, similar designs can generally be applied to memory devices having M master libraries and N redundant libraries, where each of N and M is a positive integer, and N is greater than M. Based on the design of the redundant libraries in the memory cell array and the MUX array in the I / O circuit, flexible data shift-based repair schemes can be implemented. Control logic can be coupled to the I / O circuit and is configured to determine N working libraries from the N master libraries and M redundant libraries based on library fault information indicating K faulty master libraries among the N master libraries. The N working libraries may include K redundant libraries among the M redundant libraries, where K is a positive integer not greater than M. The control logic can also be configured to control the I / O circuitry to direct K data segments out of N data segments to K redundant libraries or to direct K data segments out of N data segments from K redundant libraries.

[0054] For example, such as Figure 8 As shown, control logic 412 may include read redundancy enable logic 902, write redundancy enable logic 904, and working library logic 906. Each logic 902, 904, or 906 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below. In some embodiments, one or more of the read redundancy enable logic 902, write redundancy enable logic 904, and working library logic 906 are implemented using content-addressable memory (CAM).

[0055] In some embodiments, the working bank logic 906 is coupled to the registers 414 and configured to obtain bank failure information indicating one or more failed banks in the primary banks of the memory device (e.g., the memory device 700), e.g., K failed banks out of N primary banks. During post-manufacture testing, bad (non-functional) memory cells can be detected from the memory device, and each bank that includes at least one bad memory cell can be identified as a failed bank. In some embodiments, the bank failure information indicates each of the failed banks of the memory device and is saved in the memory device (e.g., in the registers 414). Thus, each memory device can have its own bank failure information. Prior to operating the memory device, the working bank logic 906 can obtain the bank failure information from the registers 414 and determine N working banks of the memory device that can be used for data input and output. According to some embodiments, the number of working banks (N) is the same as the number of parallel input / output data segments (N) (e.g., 8 in the memory device 700). That is, the working bank logic 906 can replace the K failed primary banks with the same number (K) of redundant banks, such that the N working banks can include the K redundant banks and N-K primary banks. In the memory device 700, one failed primary bank out of the 8 primary banks 702 can be replaced by a redundant bank 704 to form 8 working banks, as determined by the working bank logic 906 of the control logic 412.

[0056] Based on the determined N working banks, the read redundancy enable logic 902 and the write redundancy enable logic 904 can be configured to control the I / O circuit 407 to direct K data segments out of the N data segments to or from the K redundant banks, respectively. In some embodiments, for data input, the write redundancy enable logic 904 is coupled to the write MUXs 708 of the I / O circuit 407 and configured to provide 9 write select signals (e.g., red_en_b0_l_wt…, red_en_b12_wt…, and red_en_b3_h_wt) to the 9 write MUXs 708, respectively, based on the determined 8 working banks. In some embodiments, for data output, the read redundancy enable logic 902 is coupled to the read MUXs 804 of the I / O circuit 407 and configured to provide 8 read select signals (e.g., red_en_b0_l_rd…, and red_en_b3_h_rd) to the 8 read MUXs 804, respectively, based on the determined 8 working banks. In some embodiments, the read redundancy enable logic 902 and the write redundancy enable logic 904 also provide a synchronization signal to the strobe clock of the read MUXs 804 and the write MUXs 708, respectively, to align the data and select signals.

[0057] Each selection signal can be enabled (e.g., positively biased) or disabled (e.g., negatively biased) based on the K failing master banks. In some implementations, if a first bank in a pair of adjacent banks is one of the K failing master banks, the read redundancy enable logic 902 and the write redundancy enable logic 904 are configured to control the I / O circuitry 407 to direct data segments to or from a second bank in the pair of adjacent banks. That is, according to some implementations, the control logic 412 is configured to select one of each pair of adjacent banks based on the bank failure information and control the I / O circuitry 407 to direct data segments to or from the selected bank in each pair of adjacent banks.

[0058] Referring now to Figures 10A-10C In data input, the write redundancy enable logic 904 can be configured to control a first write MUX 708 coupled to a first bank (i.e., a failing master bank) to disable inputting a data segment from an input A of the first write MUX 708 and to disable outputting the data segment to the first bank. Conversely, the write redundancy enable logic 904 can be configured to control a second write MUX 708 coupled to a second bank (e.g., a master bank 702 or a redundant bank 704 adjacent to the first bank) to enable inputting the data segment from an input B of the second write MUX 708 and to enable outputting the data segment to the second bank. That is, as controlled by the write redundancy enable logic 904, a data segment intended for a failing master bank can be redirected by a write MUX 708 coupled to the failing master bank to its adjacent bank (a master bank 702 or a redundant bank 704). The same operation can be applied to each pair of adjacent banks such that data input is shifted between adjacent banks.

[0059] For example, assume that B0_L is the failed primary bank, then the write redundancy enable logic 904 can enable red_en_b0_l_wt and red_en_b0_h_wt so that Vdd is input from input B to B0_L and gwd<7:0> is redirected and input from input B to B0_H. To shift the data input, the write redundancy enable logic 904 can also enable red_en_b1_l_wt and red_en_b1_h_wt so that gwd<15:8> is redirected and input from input B to B1_L and gwd<23:16> is redirected and input from input B to B1_H. The write redundancy enable logic 904 can also disable red_en_b12_wt so that gwd<31:24> is redirected and input from input A to RED. That is, thus, the input data can be shifted from the failed primary bank B0_L to the redundant bank RED. For the other primary banks B2_L, B2_H, B3_L, and B3_H, no input data shift can be needed so that the write redundancy enable logic 904 can disable red_en_b2_l_wt, red_en_b2_h_wt, red_en_b3_l_wt, and red_en_b3_h_wt. As a result, each of B2_L, B2_H, B3_L, and B3_H can still input data from input A without data shift.

[0060] Referring now to Figure 10A At data output, the read redundancy enable logic 902 can be configured to control the read MUX 804 coupled to the first and second banks (i.e., the failed primary bank and the primary bank 702 or the redundant bank 704 adjacent to the failed primary bank) to enable output of a data segment from the second bank (e.g., the primary bank 702 or the redundant bank 704 adjacent to the failed primary bank). That is, as controlled by the read redundancy enable logic 902, a data segment intended for the failed primary bank can be redirected by the read MUX 804 from its adjacent bank (the primary bank 702 or the redundant bank). The same operation can be applied to each pair of adjacent banks so that the data output is shifted between the adjacent banks.

[0061] For example, assume that B0_L is the failed primary bank, then read redundancy enable logic 902 can enable red_en_b0_l_rd so that grd<7:0> is redirected and output from B0_H coupled to input B. To shift the data output, read redundancy enable logic 902 can also enable red_en_b0_h_rd, red_en_b1_l_rd, and red_en_b1_h_rd so that grd<15:8> is redirected and output from B1_L coupled to input B, grd<23:16> is redirected and output from B1_H coupled to input B, and grd<31:24> is redirected and output from RED coupled to input B. That is, thus, the output data can be shifted from the failed primary bank B0_L to the redundant bank RED. For the other primary banks B2_L, B2_H, B3_L, and B3_H, no output data shift can be needed so that read redundancy enable logic 902 can disable red_en_b2_l_rd, red_en_b2_h_rd, red_en_b3_l_rd, and red_en_b3_h_rd. As a result, data can still be output from B2_L, B2_H, B3_L, and B3_H from input A without data shift.

[0062] Figure 10B Other examples of using the failed primary bank repair scheme by the redundant bank 704 implemented by the memory device 700 are shown in accordance with some aspects of the present disclosure. Figure 10C A case where all 8 primary banks 702 are working banks, i.e., no failed primary bank is identified by post-manufacture testing, is shown. In this case, the first 8 data segments (0…, and 7) can be directed to or from the 8 primary banks 702, respectively, without using the redundant bank 704, i.e., no data (marked as “x”). Similarly, the second 8 data segments (8…, and 15) can be directed to or from the 8 primary banks 702, respectively, again without using the redundant bank 704, i.e., no data (marked as “x”).

[0063] Figure 10B and Figure 10C A case where one of the 8 primary banks 702 is a failed primary bank identified by post-manufacture testing is shown. As Figure 11 As shown in the middle, in one example where B2_H is the failed primary, the first 4 data segments (1, 2, 3, and 4) of the first 8 data segments can be directed to or from the corresponding working primaries B0_L, B0_H, B1_L, and B1_H (which are separated from B2_H by the redundant 704) respectively. Data intended for B2_H (5) can be redirected to the adjacent working primary B2_L, and data intended for B2_L (4) can be redirected to the redundant 704 (data shifted left). B2_H can become unused. That is, data shifting can occur between B2_H and the redundant 704. The last 2 data segments (6 and 7) of the first 8 data segments can be directed to or from the corresponding working primaries B3_L and B3_H respectively without data shifting. In another example where B0_L is the failed primary, the first 4 data segments (8, 9, 10, and 11) of the second 8 data segments can be directed to or from the adjacent working primaries B0_H, B1_L, and B1_H, and the redundant 704 respectively (data shifted right). B0_L can become unused. That is, data shifting can occur between B0_L and the redundant 704. The last 4 data segments (12, 13, 14, and 15) of the second 8 data segments can be directed to or from the corresponding working primaries B2_L, B2_H, B3_L, and B3_H respectively without data shifting.

[0064] As Figure 11 In the example where B1_L is the failed primary, as shown in FIG. 6, the first 2 data segments (0 and 1) of the first 8 data segments can be directed to or from the corresponding working primaries B0_L and B0_H, respectively. The next 2 data segments (2 and 3) of the first 8 data segments can be redirected to or from the adjacent working primary B1_H and the redundant bank 704, respectively (data shifted right). B1_L can become unused. That is, data shifting can occur between B1_L and the redundant bank 704. The last 4 data segments (4, 5, 6, and 7) of the first 8 data segments can be directed to or from the corresponding working primaries B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting. In another example where B2_L is the failed primary, the first 4 data segments (8, 9, 10, and 11) of the second 8 data segments can be directed to or from the corresponding working primaries B0_L, B0_H, B1_L, and B1_H (which are separated from B2_L by the redundant bank 704), respectively. Data intended for B2_L (12) can be redirected to or from the redundant bank 704 (data shifted left), and B2_L can become unused. That is, data shifting can occur between B2_L and the redundant bank 704. The last 3 data segments (13, 14, and 15) of the second 8 data segments can be directed to or from the 3 corresponding working primaries B2_H, B3_L, and B3_H, respectively, without data shifting.

[0065] Figure 11 A flow chart illustrating an exemplary method 1100 for operating a memory device having a failed primary and a redundant bank, in accordance with some aspects of the present disclosure is shown. The memory device can be any suitable memory device disclosed herein. The method 1100 can be implemented by the control logic 412. It should be understood that the operations shown in the method 1100 are not exhaustive and that other operations can also be performed before, after, or in between any of the operations shown. Furthermore, some operations can be performed concurrently, or in a different order than shown in the method 1100. Figure 11

[0066] Reference is made to Figure 11 ​Method 1100 begins, at operation 1102, where bank failure information is obtained that indicates a failed primary bank of a plurality of primary banks. The failed primary bank can be identified by post-manufacture testing of the memory device. For example, prior to operation of the memory device, bank failure information can be obtained by working bank logic 906 from registers 414.

[0067] Method 1100 proceeds to operation 1104, as shown in Figure 11 which determines a plurality of working banks from the plurality of primary banks and the redundant bank based on the bank failure information. The plurality of working banks can include the redundant bank. For example, working bank logic 906 can determine working banks that include the redundant bank and remaining primary banks.

[0068] Method 1100 proceeds to operation 1106, as shown in Figure 12 which selects one bank of each pair of adjacent banks of the plurality of banks based on the bank failure information. According to some embodiments, the selected bank is a working bank. For example, working bank logic 906 can select one working bank of each pair of adjacent banks based on the bank failure information.

[0069] Method 1100 proceeds to operation 1108, as shown in Figure 12 which controls directing of data segments to or from the selected bank of each pair of adjacent banks. According to some embodiments, to control directing of data segments, it is determined that a first bank of a pair of adjacent banks is a failed primary bank, and the directing of data segments is controlled to or from a second bank of the pair of adjacent banks. In one example, write redundancy enable logic 904 can control first write MUX 708 to disable output of data segments to the first bank, and control second write MUX 708 to enable output of data segments to the second bank. In another example, read redundancy enable logic 902 can control read MUX 804 to enable output of data segments from the second bank.

[0070] Figure 12 A flow chart illustrating another example method 1200 for operating a memory device having a failed primary bank and a redundant bank, according to some aspects of the present disclosure, is shown. The memory device can be any suitable memory device disclosed herein. Method 1200 can be implemented by control logic 412. It should be understood that the operations shown in method 1200 are not exhaustive and that other operations can also be performed before, after, or in between any of the shown operations. Furthermore, some operations can be performed concurrently, or in a different order than shown in Figure 12 .

[0071] Reference is made to Figure 12 Method 1200 begins at operation 1202, where bank failure information is obtained that indicates K failed banks of N primary banks. K can be a positive integer that is not greater than N. The K failed banks can be identified through post-manufacture testing of the memory device. For example, prior to operation of the memory device, bank failure information can be obtained by working bank logic 906 from registers 414.

[0072] Method 1200 proceeds to operation 1204, where N working banks are determined from the N primary banks and the M redundant banks based on the bank failure information, as shown in ​ For example, working bank logic 906 can determine the N working banks to include the K redundant banks and the remaining primary banks. In some embodiments, M is equal to 1, and one working bank is selected from each pair of adjacent banks of the N primary banks and the redundant bank based on the bank failure information.

[0073] Method 1200 proceeds to operation 1206, where K data segments of the N data segments are directed to or from the K redundant banks, respectively, as shown in ​ In some embodiments, M is equal to 1, and one data segment of the K data segments is directed to or from the selected working bank of each pair of adjacent banks of the N primary banks and the redundant bank.

[0074] According to one aspect of the disclosure, a memory device includes a memory cell array, I / O circuitry, and control logic coupled to the I / O circuitry. The memory cell array includes N primary banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. The I / O circuitry is coupled to the N primary banks and the M redundant banks, and is configured to direct the N data segments to or from N working banks, respectively. The control circuitry is configured to determine the N working banks from the N primary banks and the M redundant banks based on bank failure information that indicates K failed primary banks of the N primary banks. The N working banks include K redundant banks of the M redundant banks, where K is a positive integer that is not greater than M. The control circuitry is further configured to control the I / O circuitry to direct K data segments of the N data segments to or from the K redundant banks, respectively.

[0075] In some embodiments, the I / O circuitry is coupled to each pair of adjacent banks of the N primary banks and the M redundant banks, such that the I / O circuitry is configured to direct one data segment of the N data segments to or from either bank of the pair of adjacent banks.

[0076] In some embodiments, at least one pair of adjacent banks are primary banks.

[0077] In some embodiments, a first bank in a pair of adjacent banks is one of the K failed primary banks, and the control logic is configured to control the I / O circuit to direct the data segment to or from a second bank in the pair of adjacent banks.

[0078] In some embodiments, the I / O circuit includes a set of write MUXs coupled to the N primary banks and the M redundant banks, respectively. In some embodiments, the set of write MUXs includes: a first write MUX having two inputs and an output coupled to a first bank, one of the two inputs configured to input the data segment, a second write MUX having two inputs and an output coupled to a second bank, the two inputs configured to input the data segment and another data segment, respectively.

[0079] In some embodiments, the control logic is further configured to control the first write MUX to disable output of the data segment to the first bank, and to control the second write MUX to enable output of the data segment to the second bank.

[0080] In some embodiments, the I / O circuit includes a set of read MUXs coupled to the N primary banks and the M redundant banks, and the set of read MUXs includes a read MUX having two inputs coupled to a first bank and a second bank, respectively, and an output configured to output the data segment.

[0081] In some embodiments, the control logic is further configured to control the read MUX to enable output of the data segment from the second bank.

[0082] In some embodiments, M is equal to 1.

[0083] In some embodiments, the redundant bank is coupled to two of the N primary banks through the I / O circuit.

[0084] In some embodiments, the memory device includes a 3D NAND memory device.

[0085] According to another aspect of the present disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells, I / O circuitry, and control logic coupled to the I / O circuitry. The array of memory cells includes N primary banks and M redundant banks, where each of N and M is a positive integer and N is greater than M. The I / O circuitry is coupled to the N primary banks and the M redundant banks and is configured to direct N data segments to or from the N active banks, respectively. The control circuitry is configured to determine N active banks from the N primary banks and the M redundant banks based on bank failure information indicating K failed primary banks of the N primary banks. The N active banks include K redundant banks of the M redundant banks, where K is a positive integer no greater than M. The control circuitry is further configured to control the I / O circuitry to direct K data segments of the N data segments to or from the K redundant banks, respectively.

[0086] In some embodiments, the system further includes a host coupled to the memory controller and configured to send or receive data.

[0087] In some embodiments, the I / O circuitry is coupled to each pair of adjacent banks of the N primary banks and the M redundant banks such that the I / O circuitry is configured to direct one data segment of the N data segments to or from either bank of the pair of adjacent banks.

[0088] In some embodiments, each pair of adjacent banks is a pair of primary banks.

[0089] In some embodiments, a first bank of the pair of adjacent banks is one failed primary bank of the K failed primary banks, and the control logic is configured to control the I / O circuitry to direct the data segment to or from a second bank of the pair of adjacent banks.

[0090] In some embodiments, the I / O circuitry includes a set of write MUXs coupled to the N primary banks and the M redundant banks, respectively. In some embodiments, the set of write MUXs includes a first write MUX having two inputs and an output coupled to a first bank, one of the two inputs configured to input a data segment, a second write MUX having two inputs and an output coupled to a second bank, the two inputs configured to input the data segment and another data segment, respectively.

[0091] In some embodiments, the control logic is further configured to control the first write MUX to disable output of the data segment to the first bank and to control the second write MUX to enable output of the data segment to the second bank.

[0092] In some embodiments, the I / O circuitry includes a set of read MUXs coupled to the N main banks and the M redundant banks, and the set of read MUXs includes a read MUX having two inputs coupled to the first bank and the second bank, respectively, and an output configured to output the data segment.

[0093] In some embodiments, the control logic is further configured to control the read MUX to enable the output of the data segment from the second bank.

[0094] In some embodiments, M is equal to 1.

[0095] In some embodiments, the redundant bank is coupled to two of the N main banks by the I / O circuitry.

[0096] According to yet another aspect of the disclosure, a method for operating a memory device is provided. The memory device includes an array of memory cells including N main banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. N active banks are determined from the N main banks and the M redundant banks based on bank failure information indicating K failed main banks of the N main banks. The N active banks include K redundant banks of the M redundant banks, where K is a positive integer no greater than M. K data segments of N data segments are directed to or from the K redundant banks, respectively.

[0097] In some embodiments, the bank failure information indicating K failed main banks of the N main banks is obtained.

[0098] In some embodiments, M is equal to 1.

[0099] In some embodiments, to determine, one active bank is selected from each pair of adjacent banks of the N main banks and the redundant banks based on the bank failure information.

[0100] In some embodiments, to direct, one data segment of the K data segments is directed to or from the selected active bank of each pair of adjacent banks of the N main banks and the redundant banks.

[0101] The foregoing description of the specific implementations will be readily appreciated by those skilled in the art as being illustrative of the broader aspects of the disclosure. Accordingly, the teachings of the present disclosure are intended to be construed broadly and are to be accorded with the broadest interpretation so as to encompass all related and equivalent aspects of the present disclosure.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.< / j>

Claims

1. A memory device comprising: an array of memory cells including N primary banks and M redundant banks, where each of N and M is a positive integer and N is greater than M; input / output (I / O) circuitry coupled to the N primary banks and the M redundant banks and configured to direct N data segments to or from N active banks, respectively, where the I / O circuitry includes a plurality of write multiplexers and a plurality of read multiplexers; and control logic coupled to the I / O circuitry and configured to: determine the N active banks from the N primary banks and the M redundant banks based on bank failure information indicating K failed primary banks of the N primary banks, the N active banks including K redundant banks of the M redundant banks, where K is a positive integer no greater than M; and control the I / O circuitry to direct K data segments of the N data segments to or from the K redundant banks, respectively, where one redundant bank of the M redundant banks is located between two primary banks of the N primary banks, and where the one redundant bank is coupled to one write multiplexer of the plurality of write multiplexers and to two read multiplexers of the plurality of read multiplexers. the I / O circuitry is coupled to each pair of adjacent banks of the N primary banks and the M redundant banks such that the I / O circuitry is configured to direct one data segment of the N data segments to or from either bank of a pair of adjacent banks.

2. The memory device of claim 1, wherein, at least one pair of adjacent banks are primary banks.

3. The memory device of claim 2, wherein, 4. The memory device of claim 2 or 3, where a first bank of the pair of adjacent banks is one failed primary bank of the K failed primary banks; and the control logic is configured to control the I / O circuitry to direct a data segment to or from a second bank of the pair of adjacent banks.

5. The memory device of claim 4, where the plurality of write multiplexers are coupled to the N primary banks and the M redundant banks; and the plurality of write multiplexers include: a first write multiplexer having two inputs and an output coupled to the first bank, one of the two inputs configured to input the data segment; and a second write multiplexer having two inputs and an output coupled to the second bank, the two inputs configured to input the data segment and another data segment, respectively. the control logic is further configured to: control the first write multiplexer to inhibit output of the data segment to the first bank; and control the second write multiplexer to output the another data segment to the second bank.

6. The memory device of claim 5, wherein, ​ ​ the second write multiplexer to enable output of the data segment to the second bank.

7. The memory device of claim 4, wherein, the plurality of read multiplexers are coupled to the N number of main banks and the M number of redundant banks; and the plurality of read multiplexers include a read multiplexer having two inputs coupled to the first bank and the second bank, respectively, and an output configured to output the data segment.

8. The memory device of claim 7, wherein, the control logic is further configured to control the read multiplexer to enable output of the data segment from the second bank.

9. The memory device of any one of claims 1-3 and 5-8, wherein, M is equal to 1.

10. The memory device of claim 9, wherein, the redundant bank is coupled to two of the N number of main banks through the input / output circuit.

11. The memory device of claim 1, wherein, the memory device includes a three-dimensional (3D) NAND memory device.

12. A memory system, comprising: a memory device configured to store data, the memory device comprising: an array of memory cells, the array of memory cells comprising N number of main banks and M number of redundant banks, wherein each of N and M is a positive integer, and N is greater than M; input / output (I / O) circuitry coupled to the N number of main banks and the M number of redundant banks, and configured to direct N number of data segments to or from N number of active banks, respectively, wherein the input / output circuitry comprises a plurality of write multiplexers and a plurality of read multiplexers; and control logic coupled to the input / output circuitry, and configured to: determine the N number of active banks from the N number of main banks and the M number of redundant banks based on bank failure information indicative of K number of failed main banks of the N number of main banks, the N number of active banks comprising K number of redundant banks of the M number of redundant banks, wherein K is a positive integer not greater than M; and control the input / output circuitry to direct K number of data segments of the N number of data segments to or from the K number of redundant banks, respectively; and a memory controller coupled to the memory device and configured to control the memory device, wherein one of the M number of redundant banks is located between two of the N number of main banks, and wherein the one redundant bank is coupled to one of the plurality of write multiplexers, and to two of the plurality of read multiplexers.

13. The memory system of claim 12, further comprising a host coupled to the memory controller and configured to send or receive the data.

14. The memory system of claim 12, wherein, the input / output circuitry is coupled to each pair of adjacent banks of the N number of main banks and the M number of redundant banks, such that the input / output circuitry is configured to direct one data segment of the N number of data segments to or from either bank of a pair of adjacent banks.

15. The memory system of claim 14, wherein, each pair of adjacent banks is a pair of main banks. each pair of adjacent banks is a pair of main banks.

16. The memory system of claim 14 or 15, wherein a first bank of the pair of adjacent banks is one of the K failed main banks; and the control logic is configured to control the input / output circuit to direct a piece of data to or from a second bank of the pair of adjacent banks.

17. The memory system of claim 16, wherein the plurality of write multiplexers is coupled to the N main banks and the M redundant banks; and the plurality of write multiplexers includes: a first write multiplexer having two inputs and an output coupled to the first bank, one of the two inputs configured to input the piece of data; and a second write multiplexer having two inputs and an output coupled to the second bank, the two inputs configured to input the piece of data and another piece of data, respectively. the control logic is further configured to:

18. The memory system of claim 17, wherein, control the first write multiplexer to disable output of the piece of data to the first bank; and control the second write multiplexer to enable output of the piece of data to the second bank.

19. The memory system of claim 16, wherein the plurality of read multiplexers is coupled to the N main banks and the M redundant banks; and the plurality of read multiplexers includes a read multiplexer having two inputs coupled to the first bank and the second bank, respectively, and an output configured to output the piece of data. the control logic is further configured to control the read multiplexer to enable output of the piece of data from the second bank.

20. The memory system of claim 19, wherein, M is equal to 1.

21. The memory system according to any one of claims 12-15 and 17-20, wherein, the redundant bank is coupled to two of the N main banks through the input / output circuit.

22. The memory system of claim 21, wherein, each of N and M is a positive integer, and N is greater than M, the method comprising:

23. A method for operating a memory device, the memory device comprising an array of memory cells and input / output (I / O) circuitry, the array of memory cells comprising N main banks and M redundant banks, the I / O circuitry comprising a plurality of write multiplexers and a plurality of read multiplexers, wherein, determining N active banks from the N main banks and the M redundant banks based on bank failure information indicating K failed main banks of the N main banks, the N active banks including K of the M redundant banks, where K is a positive integer no greater than M; and directing K of N pieces of data to or from the K of the M redundant banks, respectively, where one of the M redundant banks is located between two of the N main banks, and where the one redundant bank is coupled to one of the plurality of write multiplexers and to two of the plurality of read multiplexers.

24. The method of claim 23, further comprising obtaining the bank failure information indicating the K failed main banks of the N main banks. M is equal to 1.

25. The method of claim 23 or 24, wherein, determining includes selecting one active bank from each pair of adjacent banks of the N main banks and the redundant bank based on the bank failure information.

26. The method of claim 25, wherein, ​ 27. The method of claim 26, wherein, Directing includes directing one of the K data segments to a selected working bank or from a selected working bank in each pair of adjacent banks of the N primary banks and the redundant bank.

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