Semiconductor device and method of manufacturing the same

Abstract

The present invention provides a semiconductor device having a multilayer structure composed of a plurality of substrates, wherein: the propagation of noise or heat between elements formed on the upper substrate and the lower substrate can be suppressed; and the deterioration of the characteristics of the elements can also be suppressed. The semiconductor device is provided with: a first substrate including a first element layer containing a first active element, a first wiring layer disposed on the first element layer, and a shielding layer disposed on the first wiring layer and containing a conductive material; and a second substrate including a second element layer disposed on the shielding layer and containing a second active element, and a second wiring layer disposed on the second element layer. The first substrate and the second substrate are stacked on top of each other.

Description

Technical Field

[0001] The technology according to the present disclosure (this technology) relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In the past, a method of increasing the vertical density of elements such as transistors by laminating a plurality of substrate layers each formed with an element has been known (see PTL 1). This method has a feature that not only one plane is used, but also as the number of planes used increases to two or three and they are laminated together, the number of elements increases. In the case where this method is applied to elements with a limited area size, the number of elements can be increased, and a complex circuit can be constructed within a small area size.

[0003] In an image sensor, the pixel size is fixed, and the area size of the elements formed for each pixel is limited by the pixel size. Therefore, the size of the elements cannot be freely changed, and furthermore, there are limitations in increasing the number of elements in order to form a complex circuit. Therefore, for a device such as an image sensor in which the area size of the elements is limited, a method of increasing the area size of the elements by forming a stacked structure of a plurality of substrates is a very beneficial method.

[0004] [Citation List]

[0005] [Patent Document]

[0006] [PTL 1]

[0007] JP 2014-99582A Summary of the Invention

[0008] [Technical Problem]

[0009] In a stacked structure of a plurality of substrates, noise such as electromagnetic waves, infrared rays, or surges and heat may propagate between the elements formed in the upper substrate and the lower substrate, and the characteristics of the elements deteriorate.

[0010] An object of this technology is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can suppress the propagation of noise and heat between the elements formed in the upper substrate and the lower substrate in a stacked structure of a plurality of substrates, and suppress the deterioration of the characteristics of the elements.

[0011] [Solution to the Problem]

[0012] According to the gist of a semiconductor device according to an aspect of the present technology, the semiconductor device includes: a first substrate including a first element layer containing a first active element, a first wiring layer disposed on the first element layer, and a shielding layer containing a conductive material disposed on the first wiring layer; and a second substrate including a second element layer containing a second active element disposed on the shielding layer and a second wiring layer disposed on the second element layer, wherein the first substrate and the second substrate are stacked on each other.

[0013] According to the gist of a method of manufacturing a semiconductor device according to another aspect of the present technology, the method of manufacturing the semiconductor device includes: forming a first wiring layer on a first element layer containing a first active element; forming a first substrate including the first element layer, the first wiring layer, and the shielding layer by forming a shielding layer containing a conductive material on the first wiring layer; preparing a second substrate in which a second element layer containing a second active element is formed; forming the second element layer on the shielding layer by bonding the second element layer side of the second substrate to the shielding layer side of the first substrate; and forming a second wiring layer on the second element layer.

[0014] According to the gist of a semiconductor device according to another aspect of the present technology, the semiconductor device includes: a first substrate including a first element layer containing a first active element and a first wiring layer disposed on the first element layer; and a second substrate including a second element layer containing a second active element and a second wiring layer disposed on the second element layer, wherein the first substrate and the second substrate are stacked on each other, and the semiconductor device further includes an electromagnetic shielding layer containing a conductive material between the first substrate and the second substrate.

[0015] According to the gist of a method of manufacturing a semiconductor device according to another aspect of the present technology, the method of manufacturing the semiconductor device includes: forming a first substrate including the first element layer and the first wiring layer by forming a first wiring layer on a first element layer containing a first active element; preparing a second substrate; forming an electromagnetic shielding layer containing a conductive material on the first substrate or the second substrate; bonding the first substrate and the second substrate together with the electromagnetic shielding layer interposed therebetween; forming a second element layer containing a second active element on the second substrate; and forming a second wiring layer on the second element layer.

[0016] According to the gist of a semiconductor device according to another aspect of the present technology, the semiconductor device includes: a first substrate including a first element layer containing a first active element, a first wiring layer disposed on the first element layer, and a photoelectric conversion unit disposed below the first element layer; and a second substrate including a second element layer containing a second active element and a second wiring layer disposed on the second element layer, wherein the first substrate and the second substrate are stacked on each other, and the semiconductor device further includes a light attenuation unit made of a material having a refractive index higher than that of the surrounding material between the second active element and the photoelectric conversion unit.

[0017] According to the gist of a manufacturing method of a semiconductor device according to another aspect of the present technology, the manufacturing method of the semiconductor device includes: forming a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion unit by forming a first wiring layer on a first element layer containing a first active element and forming a photoelectric conversion unit below the first element layer; preparing a second substrate; forming a light attenuation unit made of a material having a refractive index higher than that of the surrounding material in the second substrate; bonding the first substrate to the light attenuation unit side of the second substrate; forming a second element layer containing a second active element on the second substrate; and forming a second wiring layer on the second element layer.

[0018] According to the gist of a semiconductor device according to another aspect of the present technology, the semiconductor device includes: a first substrate including a first element layer containing a first active element, a first wiring layer disposed on the first element layer, and a photoelectric conversion unit disposed below the first element layer; a second substrate including a second element layer containing a second active element and a second wiring layer disposed on the second element layer; and an antireflection unit made of a material having a refractive index lower than that of the semiconductor material included in the second substrate, wherein the first substrate and the second substrate are stacked on each other, and the antireflection unit is disposed at least between the second active element and the photoelectric conversion unit.

[0019] According to the gist of the method for manufacturing a semiconductor device according to another aspect of the present technology, the method for manufacturing the semiconductor device includes: forming a first wiring layer on a first element layer including a first active element and forming a photoelectric conversion portion below the first element layer to form a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion portion; preparing a second substrate; forming an antireflection portion in the second substrate, the antireflection portion being made of a material having a refractive index lower than that of the semiconductor material included in the second substrate; bonding the first substrate to the antireflection portion side of the second substrate; forming a second element layer including a second active element on the second substrate; and forming a second wiring layer on the second element layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. is a diagram showing an example of a schematic configuration of an imaging device according to a first embodiment of the present technology.

[0021] Figure 2 FIG. shows Figure 1 an example of sensor pixels and a readout circuit in

[0022] Figure 3 FIG. is a diagram showing an example of a connection manner of a plurality of readout circuits and a plurality of vertical signal lines.

[0023] Figure 4 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0024] Figure 5 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0025] Figure 6 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0026] Figure 7 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0027] Figure 8 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0028] Figure 9 FIG. shows Figure 1 an example of a cross-sectional configuration of the imaging device in

[0029] Figure 10This is a diagram showing an example of the circuit configuration of an imaging device including an imaging device according to the above-described embodiments and their modifications.

[0030] Figure 11 This is a diagram showing an example of forming an imaging device Figure 10 in the above by stacking three substrates.

[0031] Figure 12 This is a diagram showing an example of forming a logic circuit by using separate substrates, namely a substrate provided with sensor pixels and a substrate provided with a readout circuit.

[0032] Figure 13 This is a diagram showing an example of forming a logic circuit on a third substrate.

[0033] Figure 14 This is a diagram showing an example of the schematic configuration of an imaging system including an imaging device according to the above-described embodiments and their modifications.

[0034] Figure 15 This is a diagram showing Figure 14 an example of the imaging process in the imaging system above.

[0035] Figure 16 This is a schematic configuration diagram of a semiconductor device according to the first embodiment of the present technology.

[0036] Figure 17 This is a conceptual diagram of the stacking of substrates of a semiconductor device according to the first embodiment of the present technology.

[0037] Figure 18 This is the equivalent circuit of the pixel region of a semiconductor device according to the first embodiment of the present technology.

[0038] Figure 19 This is a cross-sectional view of the main part of the pixel region of a semiconductor device according to the first embodiment of the present technology.

[0039] Figure 20 This is a cross-sectional view in the horizontal direction seen from the Figure 19 A-A direction above.

[0040] Figure 21 This is a cross-sectional view of the steps of the manufacturing method of a semiconductor device according to the first embodiment of the present technology.

[0041] Figure 22 This is a cross-sectional view of the steps subsequent to Figure 21 the manufacturing method of a semiconductor device according to the first embodiment of the present technology.

[0042] Figure 23 This is a cross-sectional view of the steps subsequent to the manufacturing method of a semiconductor device according to the first embodiment of the present technology.Figure 22 Cross-sectional view of subsequent steps.

[0043] Figure 24 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 23 Cross-sectional view of subsequent steps.

[0044] Figure 25 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 24 Cross-sectional view of subsequent steps.

[0045] Figure 26 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 25 Cross-sectional view of subsequent steps.

[0046] Figure 27 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 26 Cross-sectional view of subsequent steps.

[0047] Figure 28 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 27 Cross-sectional view of subsequent steps.

[0048] Figure 29 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 28 Cross-sectional view of subsequent steps.

[0049] Figure 30 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 29 Cross-sectional view of subsequent steps.

[0050] Figure 31 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 30 Cross-sectional view of subsequent steps.

[0051] Figure 32 It is a cross-sectional view of subsequent steps of the method for manufacturing a semiconductor device according to the first embodiment of the present technology. Figure 31 Cross-sectional view of subsequent steps.

[0052] Figure 33 It is a cross-sectional view of the main part of the pixel region of a semiconductor device according to the second embodiment of the present technology.

[0053] Figure 34 It is a cross-sectional view in the horizontal direction seen from the A-A direction of Figure 33 .

[0054] Figure 35AIt is a cross-sectional view of the main part of the pixel region of a semiconductor device according to the third embodiment of the present technology.

[0055] Figure 35B It is a schematic diagram showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221 of a semiconductor device according to the third embodiment of the present technology.

[0056] Figure 36A It is a cross-sectional view of the steps of a manufacturing method of a semiconductor device according to the third embodiment of the present technology.

[0057] Figure 36B It is a cross-sectional view of the steps of a manufacturing method of a semiconductor device according to the third embodiment of the present technology.

[0058] Figure 36C It is a cross-sectional view of the steps of a manufacturing method of a semiconductor device according to the third embodiment of the present technology.

[0059] Figure 36D It is a cross-sectional view of the steps of a manufacturing method of a semiconductor device according to the third embodiment of the present technology.

[0060] Figure 37 It is a schematic cross-sectional view showing the manufacturing method of a semiconductor device according to the first modification of the third embodiment of the present technology.

[0061] Figure 38 It is a cross-sectional view of the main part of the pixel region of a semiconductor device according to the second modification of the third embodiment of the present technology.

[0062] Figure 39 It is a schematic cross-sectional view showing the electromagnetic shielding layer 1302 of a semiconductor device according to the third modification of the third embodiment of the present technology.

[0063] Figure 40A It is a schematic cross-sectional view showing the electromagnetic shielding layer 1302 of a semiconductor device according to the fourth modification of the third embodiment of the present technology, and is also a cross-sectional view of the main part of the pixel region.

[0064] Figure 40B It is a schematic diagram showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221 of a semiconductor device according to the fourth modification of the third embodiment of the present technology.

[0065] Figure 41A It is a schematic cross-sectional view showing the electromagnetic shielding layer 1302 of a semiconductor device according to the fifth modification of the third embodiment of the present technology, and is also a cross-sectional view of the main part of the pixel region.

[0066] Figure 41BIt is a schematic cross-sectional view showing the electromagnetic shielding layer 1302 of a fifth modification of a semiconductor device according to the third embodiment of the present technology, and is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221.

[0067] Figure 42 It is a cross-sectional view of a main part of a pixel region of a semiconductor device according to the fourth embodiment of the present technology.

[0068] Figure 43A It is a schematic view showing an enlarged view of a portion around the light attenuation portions 1501 and 1502, and Figure 43A It is a cross-sectional view showing the path of light that has entered the light attenuation portions 1501 and 1502.

[0069] Figure 43B It is a schematic view showing an enlarged view of a portion around the light attenuation portions 1501 and 1502, and is a schematic top view showing a configuration example of the light attenuation portions 1501 and 1502.

[0070] Figure 44A It is a cross-sectional view of steps of a manufacturing method of a semiconductor device according to the fourth embodiment of the present technology.

[0071] Figure 44B It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 44A and is a cross-sectional view of subsequent steps.

[0072] Figure 44C It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 44B and is a cross-sectional view of subsequent steps.

[0073] Figure 45D It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 44C and is a cross-sectional view of subsequent steps.

[0074] Figure 45E It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 45D and is a cross-sectional view of subsequent steps.

[0075] Figure 45F It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 45E and is a cross-sectional view of subsequent steps.

[0076] Figure 46G It is a continuation of the manufacturing method of a semiconductor device according to the fourth embodiment of the present technology Figure 45F and is a cross-sectional view of subsequent steps.

[0077] Figure 46His a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology Figure 46G subsequent to that.

[0078] Figure 47I is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology Figure 46H subsequent to that.

[0079] Figure 47J is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology Figure 47I subsequent to that.

[0080] Figure 48 is a partially enlarged cross-sectional view of a semiconductor device according to the first modification of the fourth embodiment of the present technology

[0081] Figure 49 is a partially enlarged cross-sectional view of a semiconductor device according to the second modification of the fourth embodiment of the present technology

[0082] Figure 50A is a cross-sectional view of the steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology

[0083] Figure 50B is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 50A subsequent to that.

[0084] Figure 50C is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 50B subsequent to that.

[0085] Figure 51D is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 50C subsequent to that.

[0086] Figure 51E is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 51D subsequent to that.

[0087] Figure 51F is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 51E subsequent to that.

[0088] Figure 52G is a cross-sectional view of the subsequent steps of the method for manufacturing a semiconductor device according to the second modification of the fourth embodiment of the present technology Figure 51F subsequent to that.

[0089] Figure 52H It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a second modification of the fourth embodiment of the present technology. Figure 52G Subsequent step.

[0090] Figure 53 It is a partially enlarged cross-sectional view of a semiconductor device according to a third modification of the fourth embodiment of the present technology.

[0091] Figure 54A It is a cross-sectional view of a step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology.

[0092] Figure 54B It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology. Figure 54A Subsequent step.

[0093] Figure 54C It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology. Figure 54B Subsequent step.

[0094] Figure 55D It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology. Figure 54C Subsequent step.

[0095] Figure 55E It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology. Figure 55D Subsequent step.

[0096] Figure 55F It is a cross-sectional view of a subsequent step of a method for manufacturing a semiconductor device according to a third modification of the fourth embodiment of the present technology. Figure 55E Subsequent step.

[0097] Figure 56 It is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modification of the fourth embodiment of the present technology.

[0098] Figure 57 It is a partially enlarged cross-sectional view of a semiconductor device according to a fifth modification of the fourth embodiment of the present technology.

[0099] Figure 58 It is a partially enlarged cross-sectional view of a semiconductor device according to the fifth embodiment of the present technology.

[0100] Figure 59 It is a schematic diagram showing the positional relationship between the antireflection portion 1701 and the connection wiring 1666.

[0101] Figure 60 A cross-sectional view of the steps of a method for manufacturing a semiconductor device according to the fifth embodiment of the present technology.

[0102] Figure 61 A cross-sectional view of the subsequent steps of a method for manufacturing a semiconductor device according to the fifth embodiment of the present technology. Figure 60 of the steps.

[0103] Figure 62 A partially enlarged cross-sectional view of a semiconductor device according to the first modification of the fifth embodiment of the present technology.

[0104] Figure 63 A cross-sectional view of the steps of a method for manufacturing a semiconductor device according to the first modification of the fifth embodiment of the present technology.

[0105] Figure 64 A partially enlarged cross-sectional view of a semiconductor device according to the second modification of the fifth embodiment of the present technology.

[0106] Figure 65 A cross-sectional view of the steps of a method for manufacturing a semiconductor device according to the second modification of the fifth embodiment of the present technology.

[0107] Figure 66 A partially enlarged cross-sectional view of a semiconductor device according to the third modification of the fifth embodiment of the present technology.

[0108] Figure 67 A partially enlarged cross-sectional view of a semiconductor device according to the fourth modification of the fifth embodiment of the present technology.

[0109] Figure 68 A partially enlarged cross-sectional view of a semiconductor device according to the fifth modification of the fifth embodiment of the present technology.

[0110] Figure 69 A schematic configuration diagram of an electronic device according to another embodiment of the present technology.

[0111] Figure 70 A block diagram showing an example of the functional configuration of an imaging device according to an embodiment of the present disclosure.

[0112] Figure 71 Shows Figure 70 A plan view showing the schematic configuration of the imaging device shown in

[0113] Figure 72 Shows along Figure 71 A schematic diagram showing the cross-sectional configuration along the line III-III' shown in

[0114] Figure 73 IsFigure 70 The equivalent circuit diagram of the pixel sharing unit shown in

[0115] Figure 74 It is a diagram showing an example of the connection mode of multiple pixel sharing units and multiple vertical signal lines.

[0116] Figure 75 It shows Figure 72 A cross-sectional schematic diagram showing an example of the specific structure of the imaging device shown in

[0117] Figure 76A It shows Figure 75 A schematic diagram showing an example of the planar structure of the main part of the first substrate shown in

[0118] Figure 76B It is related to Figure 76A A schematic diagram showing the planar structure of the pad part shown together with the main part of the first substrate shown in

[0119] Figure 77 It shows Figure 75 A schematic diagram showing an example of the planar structure of the second substrate (semiconductor layer) shown in

[0120] Figure 78 It is related to Figure 75 A schematic diagram showing an example of the planar structure of the pixel circuit and the main part of the first substrate shown together with the first wiring layer shown in

[0121] Figure 79 It shows Figure 75 A schematic diagram showing an example of the planar structure of the first wiring layer and the second wiring layer shown in

[0122] Figure 80 It shows Figure 75 A schematic diagram showing an example of the planar structure of the second wiring layer and the third wiring layer shown in

[0123] Figure 81 It shows Figure 75 A schematic diagram showing an example of the planar structure of the third wiring layer and the fourth wiring layer shown in

[0124] Figure 82 It is used to explain Figure 72 A schematic diagram of the path of the input signal of the imaging device shown in

[0125] Figure 83 It is used to explain Figure 72 A schematic diagram of the signal path of the pixel signal of the imaging device shown in

[0126] Figure 84 It shows Figure 77Schematic diagram of a modified example of the planar configuration of the second substrate (semiconductor layer) shown in [].

[0127] Figure 85 It is Figure 84 Schematic diagram of the planar configuration of the main part of the first wiring layer and the first substrate shown together with the pixel circuit shown in [].

[0128] Figure 86 It is Figure 85 Schematic diagram of an example of the planar configuration of the second wiring layer shown together with the first wiring layer shown in [].

[0129] Figure 87 It is Figure 86 Schematic diagram of an example of the planar configuration of the third wiring layer shown together with the second wiring layer shown in [].

[0130] Figure 88 It is Figure 87 Schematic diagram of an example of the planar configuration of the fourth wiring layer shown together with the third wiring layer shown in [].

[0131] Figure 89 It shows Figure 76A Schematic diagram of a modified example of the planar configuration of the first substrate shown in [].

[0132] Figure 90 It shows Figure 89 Schematic diagram of an example of the planar configuration of the second substrate (semiconductor layer) laminated on the first substrate shown in [].

[0133] Figure 91 It is Figure 90 Schematic diagram of an example of the planar configuration of the first wiring layer shown together with the pixel circuit shown in [].

[0134] Figure 92 It is Figure 91 Schematic diagram of an example of the planar configuration of the second wiring layer shown together with the first wiring layer shown in [].

[0135] Figure 93 It is Figure 92 Schematic diagram of an example of the planar configuration of the third wiring layer shown together with the second wiring layer shown in [].

[0136] Figure 94 It is Figure 93 Schematic diagram of an example of the planar configuration of the fourth wiring layer shown together with the third wiring layer shown in [].

[0137] Figure 95 It shows Figure 89 Schematic diagram of another example of the planar configuration of the first substrate shown in [].

[0138] Figure 96 is a schematic diagram showing an example of the planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in Figure 95 .

[0139] Figure 97 is a schematic diagram showing an example of the planar configuration of a first wiring layer shown together with the pixel circuit shown in Figure 96 .

[0140] Figure 98 is a schematic diagram showing an example of the planar configuration of a second wiring layer shown together with the first wiring layer shown in Figure 97 .

[0141] Figure 99 is a schematic diagram showing an example of the planar configuration of a third wiring layer shown together with the second wiring layer shown in Figure 98 .

[0142] Figure 100 is a schematic diagram showing an example of the planar configuration of a fourth wiring layer shown together with the third wiring layer shown in Figure 99 .

[0143] Figure 101 is a cross-sectional schematic diagram showing another example of the imaging device shown in Figure 72 .

[0144] Figure 102 is a schematic diagram for explaining the path of the input signal of the imaging device shown in Figure 101 .

[0145] Figure 103 is a schematic diagram for explaining the signal path of the pixel signal of the imaging device shown in Figure 101 .

[0146] Figure 104 is a cross-sectional schematic diagram showing another example of the imaging device shown in Figure 75 .

[0147] Figure 105 is a diagram showing another example of the equivalent circuit shown in Figure 73 .

[0148] Figure 106 is a planar schematic diagram showing another example of the pixel separation section shown in Figure 76A etc.

[0149] Figure 107 is a cross-sectional view in the thickness direction showing a configuration example of the imaging device according to the seventh embodiment of the present disclosure.

[0150] Figure 108 is a cross-sectional view in the thickness direction showing a configuration example of an imaging device according to the seventh embodiment of the present disclosure.

[0151] Figure 109 is a cross-sectional view in the thickness direction showing a configuration example of an imaging device according to the seventh embodiment of the present disclosure.

[0152] Figure 110 is a cross-sectional view in the horizontal direction showing a layout example of a plurality of pixel units according to the seventh embodiment of the present disclosure.

[0153] Figure 111 is a cross-sectional view in the horizontal direction showing a layout example of a plurality of pixel units according to the seventh embodiment of the present disclosure.

[0154] Figure 112 is a cross-sectional view in the horizontal direction showing a layout example of a plurality of pixel units according to the seventh embodiment of the present disclosure.

[0155] Figure 113 is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified examples.

[0156] Figure 114 is showing Figure 113 a diagram showing an example of an imaging process of the imaging system shown in.

[0157] Figure 115 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0158] Figure 116 is a diagram assisting in explaining an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0159] Figure 117 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0160] Figure 118 is a block diagram showing an example of a functional configuration of a camera head and a camera control unit (CCU). Detailed Description of the Invention

[0161] In the following, the first to seventh embodiments of the present technology will be described with reference to the accompanying drawings. In the descriptions of the accompanying drawings mentioned in the following, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic diagrams, and the relationships between the thickness and the planar dimensions, the ratios of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, the specific thicknesses and dimensions should be determined in consideration of the following descriptions. In addition, of course, the dimensions shown in different drawings may have different relationships and ratios to each other. It should be noted that the effects described in this specification are only for illustrative purposes, and the effects of the present disclosure are not limited to these effects, and there may be other effects.

[0162] (First Embodiment)

[0163] [Configuration]

[0164] Figure 1 An example of the schematic configuration of the imaging device 1 according to the first embodiment of the present technology is shown. The imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 is an imaging device having a three-dimensional structure formed by three substrates (a first substrate 10, a second substrate 20, and a third substrate 30) joined together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked on top of each other in sequence.

[0165] The first substrate 10 has a semiconductor substrate 11, and the semiconductor substrate 11 has a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix in the pixel region 13 of the first substrate 10. The second substrate 20 has a semiconductor substrate 21, and the semiconductor substrate 21 has a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixels 12 for every group of four sensor pixels 12. The semiconductor substrate 21 corresponds to a specific example of the "second semiconductor substrate" of the present technology. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a semiconductor substrate 31, and the semiconductor substrate 31 has a logic circuit 32 that processes pixel signals. The semiconductor substrate 31 corresponds to a specific example of the "third semiconductor substrate" of the present technology. For example, the logic circuit 32 has a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside. For example, the logic circuit 32 has impurity diffusion regions in contact with the source electrode and the drain electrode, and the front surface of the impurity diffusion region may have a low-resistance region made of a silicide such as CoSi2 or NiSi formed by using a Self Aligned Silicide process.

[0166] For example, the vertical drive circuit 33 sequentially selects each row of the plurality of sensor pixels 12. For example, the column signal processing circuit 34 performs correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, by performing the CDS processing, the column signal processing circuit 34 extracts the signal level of the pixel signal and holds the pixel data corresponding to the amount of light received by each sensor pixel 12. For example, the horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. For example, the system control circuit 36 controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0167] Figure 2 An example of the sensor pixel 12 and the readout circuit 22 is shown. In the case described below, as Figure 2 shown, four sensor pixels 12 share one readout circuit 22. Here, "sharing" means that the outputs of the four sensor pixels 12 are input to the common readout circuit 22.

[0168] The sensor pixels 12 have the same constituent elements. In order to distinguish between the constituent elements of the sensor pixel 12, in Figure 2 , identification numbers (1, 2, 3, and 4) are given at the ends of the reference numerals of the constituent elements of the sensor pixel 12. Hereinafter, in cases where it is necessary to distinguish between the constituent elements of the sensor pixel 12, identification numbers are given at the ends of the reference numerals of the constituent elements of the sensor pixel 12, but in cases where it is not necessary to distinguish between the constituent elements of the sensor pixel 12, the identification numbers at the ends of the reference numerals of the constituent elements of the sensor pixel 12 are omitted.

[0169] For example, each sensor pixel 12 has a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of the "photoelectric conversion element" of the present technology. The photodiode PD performs photoelectric conversion and generates charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion section FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23. For example, the transfer transistor TR is a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0170] The floating diffusion sections FD of the sensor pixels 12 sharing a readout circuit 22 are electrically connected to each other and to the input terminal of the common readout circuit 22. For example, the readout circuit 22 has a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. It should be noted that the selection transistor SEL can be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion section FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0171] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion section FD. For example, as described later in Figure 4As shown, the gate of the transfer transistor TR (transfer gate TG) extends from the front surface of the semiconductor substrate 11 through the well layer 42 to reach the depth of the PD 41. The reset transistor RST resets the potential of the floating diffusion section FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion section FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held at the floating diffusion section FD as the pixel signal. The amplification transistor AMP is composed of a source follower type amplifier and outputs a pixel signal of a voltage corresponding to the level of the charge generated at the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion section FD and outputs a voltage corresponding to this potential to the column signal processing circuit 34 via the vertical signal line 24. For example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are CMOS transistors.

[0172] The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, the FD transfer transistor FDG is provided between the source of the reset transistor RST and the gate of the amplification transistor AMP, and the gate of the amplification transistor AMP is electrically connected to the source of the FD transfer transistor FDG.

[0173] When switching the conversion efficiency, the FD transfer transistor FDG is used. Generally, when shooting in the dark, the pixel signal is small. Based on Q = CV, when performing charge-voltage conversion, if the capacitance of the floating diffusion section FD (FD capacitance C) is large, then V when converted into a voltage by the amplification transistor AMP must necessarily become small. On the other hand, in the bright area, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion section FD cannot fully receive the charge of the photodiode PD. Further, in order to prevent V from becoming too large when converted into a voltage by the amplification transistor AMP (in other words, to make V smaller), the FD capacitance C must be made large. Considering these, when the FD transfer transistor FDG is turned on, the gate capacitance increases by an amount corresponding to the FD transfer transistor FDG, and thus the entire FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the entire FD capacitance C becomes small. In this way, the FD capacitance C can be made variable by turning on and off the FD transfer transistor FDG, and the conversion efficiency can be switched.

[0174] Figure 3An example of the connection manner of a plurality of readout circuits 22 and a plurality of vertical signal lines 24 is shown. When the plurality of readout circuits 22 are arranged side by side with each other in the extending direction (e.g., column direction) of the vertical signal lines 24, each of the plurality of vertical signal lines 24 can be assigned to one of the readout circuits 22. For example, as Figure 3 shown, when four readout circuits 22 are arranged side by side with each other in the extending direction (e.g., column direction) of the vertical signal lines 24, each of the four vertical signal lines 24 can be assigned to one of the readout circuits 22. It should be noted that in Figure 3 , in order to distinguish between the vertical signal lines 24, identification numbers (1, 2, 3, and 4) are given at the ends of the reference numerals of the vertical signal lines 24.

[0175] Figure 4 An example of the cross-sectional configuration of the imaging device 1 in the vertical direction is shown. Figure 4 The cross-sectional configuration at a position in the imaging device 1 and opposite to the sensor pixel 12 is shown. The imaging device 1 includes a first substrate 10, a second substrate 20, and a third substrate 30 that are stacked on each other in sequence, and further includes a color filter 40 and an optical receiving lens 50 on the back surface (light incident surface side) of the first substrate 10. For example, a set of the color filter 40 and the optical receiving lens 50 is provided for each sensor pixel 12. That is, the imaging device 1 is a back-illuminated type imaging device.

[0176] The first substrate 10 includes an insulating layer 46 laminated on a semiconductor substrate 11. The insulating layer 46 corresponds to a specific example of the "first insulating layer" of the present technology. The first substrate 10 has the insulating layer 46 as a part of the interlayer insulating film 51. The insulating layer 46 is provided at a gap between the semiconductor substrate 11 and a semiconductor substrate 21 described later. The semiconductor substrate 11 is composed of a silicon substrate. For example, in a part of its front surface and in the vicinity thereof, the semiconductor substrate 11 has a p-well layer 42, and in another region (a region deeper than the p-well layer 42), the semiconductor substrate 11 has a PD 41 whose conductivity type is different from that of the p-well layer 42. The p-well layer 42 is composed of a p-type semiconductor region. The PD 41 is composed of a semiconductor region whose conductivity type (specifically, n-type) is different from that of the p-well layer 42. In the p-well layer 42, the semiconductor substrate 11 has a floating diffusion portion FD that is a semiconductor region whose conductivity type (specifically, n-type) is different from that of the p-well layer 42.

[0177] For each sensor pixel 12, the first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion section FD. On a part of the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11, the first substrate 10 includes the transfer transistor TR and the floating diffusion section FD. The first substrate 10 has an element isolation section 43 that separates the sensor pixels 12 from each other. Each element isolation section 43 is formed as a part that extends in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the front surface of the semiconductor substrate 11). The element isolation section 43 is provided between two adjacent sensor pixels 12. The element isolation section 43 electrically isolates the adjacent sensor pixels 12 from each other. For example, the element isolation section 43 is made of silicon oxide. For example, the element isolation section 43 penetrates the semiconductor substrate 11. For example, the first substrate 10 further has a p-well layer 44 that contacts the side surface of the element isolation section 43 and the surface on the photodiode PD side. Each p-well layer 44 is formed of a semiconductor region having a conductivity type (specifically, p-type) different from that of the photodiode PD. For example, the first substrate 10 further has a fixed charge film 45 that contacts the back surface of the semiconductor substrate 11. In order to suppress the generation of dark current caused by interface states on the light receiving surface side of the semiconductor substrate 11, the fixed charge film 45 is negatively charged. For example, each fixed charge film 45 is formed of an insulating film having negative fixed charges. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface of the semiconductor substrate 11. For example, the color filter 40 is provided in contact with the fixed charge film 45 and is located opposite to the sensor pixel 12 with the fixed charge film 45 interposed therebetween. For example, the light receiving lens 50 is provided in contact with the color filter 40 and is located opposite to the sensor pixel 12 with the color filter 40 and the fixed charge film 45 interposed therebetween.

[0178] The second substrate 20 includes an insulating layer 52 laminated on the semiconductor substrate 21. The insulating layer 52 corresponds to a specific example of the "third insulating layer" of the present technology. The second substrate 20 has the insulating layer 52 as part of the interlayer insulating film 51. The insulating layer 52 is provided at the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is composed of a silicon substrate. The second substrate 20 has one readout circuit 22 for each set of four sensor pixels 12. The second substrate 20 includes the readout circuit 22 provided at a part on the front surface side (the third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 such that the back surface of the semiconductor substrate 21 faces the front surface side of the semiconductor substrate 11. That is, the second substrate 20 is bonded to the first substrate 10 in a back-to-back manner. In the layer having the semiconductor substrate 21, the second substrate 20 further has an insulating layer 53 penetrating the semiconductor substrate 21. The insulating layer 53 corresponds to a specific example of the "second insulating layer" of the present technology. The second substrate 20 has the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side surface of a through-wiring 54 described later.

[0179] The laminate including the first substrate 10 and the second substrate 20 has an interlayer insulating film 51 and a through-wiring 54 provided in the interlayer insulating film 51. The through-wiring 54 corresponds to a specific example of the "first through-wiring" of the present technology. The above laminate has one through-wiring 54 for each sensor pixel 12. The through-wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate the position in the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through-wiring 54. Specifically, the through-wiring 54 is electrically connected to the floating diffusion portion FD and a connection wiring 55 described later.

[0180] The laminate including the first substrate 10 and the second substrate 20 further has through-wirings 47 and 48 provided in the interlayer insulating film 51 (see Figure 6 described later). The through-wiring 48 corresponds to a specific example of the "first through-wiring" of the present technology. The above laminate has one through-wiring 47 and one through-wiring 48 for each sensor pixel 12. Each through-wiring 47 or 48 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate the position in the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through-wirings 47 and 48. Specifically, the through-wiring 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and a wiring in the second substrate 20. The through-wiring 48 is electrically connected to the transfer gate TG and the pixel driving line 23.

[0181] For example, in the insulating layer 52, the second substrate 20 has a plurality of connection portions 59 that are electrically connected to the readout circuit 22 and the semiconductor substrate 21. For example, the second substrate 20 further has a wiring layer 56 on the insulating layer 52. For example, the wiring layer 56 has an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 57. For example, in the insulating layer 57, the wiring layer 56 further has a plurality of connection wirings 55, and each connection wiring 55 is provided for each set of four sensor pixels 12. The connection wiring 55 electrically connects the through wirings 54 that are electrically connected to the floating diffusion portions FD included in the four sensor pixels 12 of the shared readout circuit 22 to each other. Here, the total number of the through wirings 54 and 48 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is twice the total number of the sensor pixels 12 included in the first substrate 10. In addition, the total number of the through wirings 54, 48, and 47 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is three times the total number of the sensor pixels 12 included in the first substrate 10.

[0182] For example, in the insulating layer 57, the wiring layer 56 further has a plurality of pad electrodes 58. For example, each pad electrode 58 is made of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed at the front surface of the wiring layer 56. Each pad electrode 58 is used to electrically connect the second substrate 20 to the third substrate 30 and bond the second substrate 20 to the third substrate 30 together. For example, each of the plurality of pad electrodes 58 is provided for one of the pixel drive lines 23 and the vertical signal lines 24. Here, the total number of the pad electrodes 58 (or the total number of the bonding points between the pad electrodes 58 and the pad electrodes 64 (described later)) is less than the total number of the sensor pixels 12 included in the first substrate 10.

[0183] For example, the third substrate 30 includes an interlayer insulating film 61 laminated on the semiconductor substrate 31. It should be noted that, as will be described later, the third substrate 30 and the second substrate 20 are joined together on the surfaces on their front surface sides. Therefore, when describing the configuration of the third substrate 30, its up / down direction is the opposite direction of the up / down direction in the drawing. The semiconductor substrate 31 is composed of a silicon substrate. The third substrate 30 includes a logic circuit 32 provided at a part on the front surface side of the semiconductor substrate 31. For example, the third substrate 30 further has a wiring layer 62 on the interlayer insulating film 61. For example, the wiring layer 62 has an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. For example, each pad electrode 64 is composed of Cu (copper). Each pad electrode 64 is exposed on the front surface of the wiring layer 62. Each pad electrode 64 is used to electrically connect the second substrate 20 and the third substrate 30 and join the second substrate 20 and the third substrate 30 together. In addition, it is not necessary to have a plurality of pad electrodes 64, but even one pad electrode 64 can form an electrical connection with the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other through the joining point between the pad electrodes 58 and 64. That is, the gate of the transfer transistor TR (transfer gate TG) is electrically connected to the logic circuit 32 via the through-wiring 54, the pad electrodes 58 and 64. The third substrate 30 is joined to the second substrate 20 such that the front surface of the semiconductor substrate 31 faces the front surface side of the semiconductor substrate 21. That is, the third substrate 30 is joined to the second substrate 20 in a face-to-face manner.

[0184] [Effect]

[0185] In the past, miniaturization of the pixel area size of an imaging device having a two-dimensional structure has been achieved by introducing a fine process and increasing the mounting density. In recent years, in order to achieve further size reduction of the imaging device and miniaturization of the pixel area size, an imaging device having a three-dimensional structure has been developed. For example, in an imaging device having a three-dimensional structure, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by the sensor pixels are laminated on each other. As a result, the integration degree of the sensor pixels can be further improved, the size of the signal processing circuit can be further increased, etc., where the chip size is equal to the conventional chip size.

[0186] On the other hand, in the case where three semiconductor chips are laminated on each other in an imaging device having a three-dimensional structure, it is not possible to join all the semiconductor substrates together on the surfaces on their front surface sides (in a face-to-face manner). In the case where the three semiconductor substrates are randomly laminated on each other, there is a possibility that the structure for electrically connecting the semiconductor substrates necessarily increases the chip size, suppressing miniaturization of the pixel area size, etc.

[0187] On the other hand, in the present embodiment, the sensor pixel 12 and the readout circuit 22 are formed in different substrates (the first substrate 10 and the second substrate 20). Thus, compared with the case where the sensor pixel 12 and the readout circuit 22 are formed in the same substrate, the area sizes of the sensor pixel 12 and the readout circuit 22 can be enlarged. Therefore, the photoelectric conversion efficiency can be improved, the transistor noise can be reduced, etc. In addition, the first substrate 10 having the sensor pixel 12 and the second substrate 20 having the readout circuit 22 are electrically connected to each other through the through-wiring 54 provided in the interlayer insulating film 51. Thus, compared with the case where the first substrate 10 and the second substrate 20 are electrically connected to each other through the bonding point between the pad electrodes or the through-wiring penetrating the semiconductor substrate (for example, TSV (Through Si Via)), the chip size can be further reduced. In addition, the further miniaturization of the per-pixel area size can further improve the resolution. In addition, in the case of adopting a chip size similar to the conventional chip size, the formation region of the sensor pixel 12 can be enlarged. In addition, in the present embodiment, the readout circuit 22 and the logic circuit 32 are formed in different substrates (the second substrate 20 and the third substrate 30). Thus, compared with the case where the readout circuit 22 and the logic circuit 32 are formed in the same substrate, the area sizes of the readout circuit 22 and the logic circuit 32 can be enlarged. In addition, since the area sizes of the readout circuit 22 and the logic circuit 32 are not limited by the element isolation part 43, the noise characteristics can be improved. In addition, in the present embodiment, the second substrate 20 and the third substrate 30 are electrically connected to each other through the bonding point between the pad electrodes 58 and 64. Here, since the readout circuit 22 is formed in the second substrate 20 and the logic circuit 32 is formed in the third substrate 30, compared with the structure for electrically connecting the first substrate 10 and the second substrate 20, the structure for electrically connecting the second substrate 20 and the third substrate 30 can be formed with a layout that is free in terms of constitution, the number of contacts for connection, etc. Therefore, the bonding point between the pad electrodes 58 and 64 can be used for the electrical connection between the second substrate 20 and the third substrate 30. In this way, in the present embodiment, the electrical connection between the substrates is formed according to the integration degree of the substrates. Therefore, the structure for electrically connecting the substrates will not necessarily require an increase in the chip size, suppression of the miniaturization of the per-pixel area size, etc. Therefore, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to the conventional chip size and does not suppress the miniaturization of the per-pixel area size.

[0188] In addition, in the present embodiment, the sensor pixel 12 having a photodiode PD, a transfer transistor TR, and a floating diffusion section FD is formed in the first substrate 10, while the readout circuit 22 having a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is formed in the second substrate 20. As a result, compared with the case where the sensor pixel 12 and the readout circuit 22 are formed in the same substrate, the area sizes of the sensor pixel 12 and the readout circuit 22 can be increased. Therefore, even when the joint between the pad electrodes 58 and 64 is used for the electrical connection between the second substrate 20 and the third substrate 30, the chip size does not increase, nor is the miniaturization of the per-pixel area size inhibited, etc. Accordingly, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size. Specifically, since fewer transistors are provided in the first substrate 10, the area size of the photodiode PD of the sensor pixel 12 can be particularly increased. Therefore, the saturation signal charge amount of the photoelectric conversion can be increased, and the photoelectric conversion efficiency can be improved. In the second substrate 20, the degree of freedom in the layout of the transistors in the readout circuit 22 can be ensured. In addition, since the area size of the transistor can be increased particularly by increasing the area size of the amplification transistor AMP, the noise affecting the pixel signal can be reduced. Even when the joint between the pad electrodes 58 and 64 is used for the electrical connection between the second substrate 20 and the third substrate 30, the chip size does not increase, nor is the miniaturization of the per-pixel area size inhibited, etc. Accordingly, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size.

[0189] In addition, in the present embodiment, the second substrate 20 is bonded to the first substrate 10 by opposing the back surface of the semiconductor substrate 21 to the front surface side of the semiconductor substrate 11, and the third substrate 30 is bonded to the second substrate 20 by opposing the front surface side of the semiconductor substrate 31 to the front surface side of the semiconductor substrate 21. As a result, by using the through-wiring 54 for the electrical connection between the first substrate 10 and the second substrate 20, and using the joint between the pad electrodes 58 and 64 for the electrical connection between the second substrate 20 and the third substrate 30, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size.

[0190] In addition, in the present embodiment, the cross-sectional area size of the through-wiring 54 is smaller than the cross-sectional area size at the joint between the pad electrodes 58 and 64. Therefore, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size.

[0191] In addition, the logic circuit 32 of the present embodiment has impurity diffusion regions in contact with the source and drain electrodes, and the front surface of the impurity diffusion regions has a low-resistance region formed of a silicide such as CoSi2 or NiSi by using a Self Aligned Silicide process. The low-resistance region formed of the silicide includes a metal compound and the material of the semiconductor substrate. Here, the logic circuit 32 is provided in the third substrate 30. Therefore, the logic circuit 32 can be formed by a process different from the process of forming the sensor pixels 12 and the readout circuit 22. Therefore, when forming the sensor pixels 12 and the readout circuit 22, a high-temperature process such as thermal oxidation can be used. In addition, a silicide, which is a low heat-resistant material, can also be used for the logic circuit 32. Therefore, in the case where the low-resistance region formed of the silicide is provided on the front surface of the impurity diffusion region in contact with the source and drain electrodes of the logic circuit 32, the contact resistance can be reduced; thus, the calculation speed of the logic circuit 32 can be increased.

[0192] In addition, in the present embodiment, the first substrate 10 is provided with element isolation portions 43 that separate the sensor pixels 12 from each other. However, in the present embodiment, the sensor pixels 12 having a photodiode PD, a transfer transistor TR, and a floating diffusion portion FD are formed in the first substrate 10, and the readout circuit 22 having a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is formed in the second substrate 20. Thereby, even when the size of the area surrounded by the element isolation portions 43 becomes smaller due to the miniaturization of the per-pixel area size, the area sizes of the sensor pixels 12 and the readout circuit 22 can be enlarged. Therefore, even when using the element isolation portions 43, the chip size does not increase, and the miniaturization of the per-pixel area size and the like are not inhibited. Therefore, a imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size.

[0193] In addition, in the present embodiment, the element isolation portions 43 penetrate the semiconductor substrate 11. Thereby, even when the distance between the sensor pixels 12 becomes shorter due to the miniaturization of the per-pixel area size, signal crosstalk between adjacent sensor pixels 12 can be suppressed, and deterioration of the resolution of the reproduced image and deterioration of the image quality due to color mixing can be suppressed.

[0194] In addition, in the present embodiment, the laminate including the first substrate 10 and the second substrate 20 has three through wirings 54, 47, and 48 for each sensor pixel 12. Each through wiring 54 is electrically connected to the floating diffusion section FD, each through wiring 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11, and each through wiring 48 is electrically connected to the gate of the transfer transistor TR (transfer gate TG). That is, the number of the through wirings 54, 47, and 48 is larger than the number of the sensor pixels 12 included in the first substrate 10. However, in the present embodiment, the through wiring 54 having a smaller cross-sectional area size is used for the electrical connection between the first substrate 10 and the second substrate 20. As a result, the chip size can be further reduced, and the per-pixel area size in the first substrate 10 can also be further miniaturized. Therefore, the imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit the miniaturization of the per-pixel area size.

[0195] (Modification example)

[0196] Hereinafter, a modification example of the imaging device 1 according to the above-described embodiment will be described. It should be noted that, in the following modification examples, the same components as those in the above-described embodiment are given the same reference numerals.

[0197] [Modification example A]

[0198] Figure 5 A modification example of the cross-sectional configuration of the imaging device 1 according to the above-described embodiment in the vertical direction is shown. Figure 5 Shows Figure 4 A modification example of the cross-sectional configuration described in. In this modification example, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the well layer 42 and is formed only on the front surface of the semiconductor substrate 11. Even when the planar transfer gate TG is used for the transfer transistor TR, the imaging device 1 provides an effect similar to that of the above-described embodiment.

[0199] [Modification example B]

[0200] Figure 6 And Figure 7 A modification example of the cross-sectional configuration of the imaging device 1 according to the above-described embodiment in the horizontal direction is shown. Figure 6 And Figure 7 The upper illustration in shows Figure 4 A modification example of the cross-sectional configuration of the cross-section Sec1 in, while Figure 6 And Figure 7 The lower illustration in shows Figure 4 A modification example of the cross-sectional configuration of the cross-section Sec2 in. It should be noted that in Figure 6 And Figure 7In the cross-sectional view on the upper side of, it is shown that Figure 4 In, a diagram of a modified example of the front surface of the semiconductor substrate 11 is placed above a diagram of a modified example of the cross-sectional configuration of the cross-section Sec1 in Figure 4 , and the insulating layer 46 is also omitted. Further, in Figure 6 and Figure 7 In the cross-sectional view on the lower side of, a diagram of a modified example of the arrangement of the front surface of the semiconductor substrate 21 is placed above a diagram of a modified example of the cross-sectional configuration of the cross-section Sec2 in Figure 4 .

[0201] As Figure 6 and Figure 7 shown in, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 (a plurality of points arranged in a matrix in the figure) are arranged side by side in a band shape in the first direction H (in the Figure 6 and Figure 7 figure, the left / right direction) on the surface of the first substrate 10. It should be noted that Figure 6 and Figure 7 show a case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in two columns in the first direction H. For example, in four sensor pixels 12 sharing a readout circuit 22, four floating diffusion portions FD are arranged close to each other with an element isolation portion 43 therebetween. In four sensor pixels 12 sharing a readout circuit 22, four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four floating diffusion portions FD, and, for example, the four transfer gates TG form an annular shape.

[0202] The insulating layer 53 is composed of a plurality of blocks extending in the first direction H. The semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the first direction H and arranged side by side in a second direction V orthogonal to the first direction H with the insulating layer 53 therebetween. For example, each block 21A is provided with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. For example, each readout circuit 22 shared by four sensor pixels 12 is not arranged directly facing the four sensor pixels 12, but is arranged to be offset in the second direction V.

[0203] In Figure 6 , on the second substrate 20, each readout circuit 12 shared by four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in a region offset in the second direction V from the region facing the four sensor pixels 12. For example, each readout circuit 22 shared by four sensor pixels 12 includes an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0204] InFigure 7 In [the structure of the second substrate 20], each readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG located in a region that is offset in the second direction V from the region facing the four sensor pixels 12. For example, each readout circuit 22 shared by four sensor pixels 12 includes the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG in one block 21A.

[0205] In this modification example, for example, each readout circuit 22 shared by four sensor pixels 12 is not arranged directly facing the four sensor pixels 12, but is arranged to be offset in the second direction V from the position directly facing the four sensor pixels 12. In the case of adopting such an arrangement, the wiring 25 can be shortened, or the wiring 25 can be omitted, and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be formed through a common impurity region. Therefore, the size of the readout circuit 22 can be reduced to increase the size of other parts of the readout circuit 22, etc.

[0206] [Modification Example C]

[0207] Figure 8 A modification example of the cross-sectional structure of the imaging device 1 according to the above-described embodiment in the horizontal direction is shown. Figure 8 Shown is Figure 6 a modification example of the cross-sectional structure in

[0208] In this modification example, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction H and the second direction V with an insulating layer 53 therebetween. For example, each block 21A is provided with a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In the case of adopting such an arrangement, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and deterioration in the resolution of the reproduced image and deterioration in the image quality due to color mixing can be suppressed.

[0209] [Modification Example D]

[0210] Figure 9 An example of the cross-sectional structure of the imaging device 1 according to the above-described embodiment and its modification examples in the horizontal direction is shown.

[0211] In this modification example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and each floating diffusion portion FD is shared by four sensor pixels 12. Therefore, in this modification example, a through-wiring 54 is provided for each group of four sensor pixels 12.

[0212] Among a plurality of sensor pixels 12 arranged in a matrix, for convenience, four sensor pixels 12 corresponding to a region obtained by shifting a unit region corresponding to four sensor pixels 12 sharing a floating diffusion portion FD in a first direction H by an amount corresponding to one sensor pixel 12 are referred to as four sensor pixels 12A. At this time, in this modification example, in the first substrate 10, each through-wiring 47 is shared by a set of four sensor pixels 12A. Therefore, in this modification example, one through-wiring 47 is provided for each set of four sensor pixels 12A.

[0213] In this modification example, the first substrate 10 has an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR of each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation portion 43 does not completely surround the sensor pixel 12, but has gaps (regions where the element isolation portion 43 is not formed) near the floating diffusion portion FD (through-wiring 54) and near the through-wiring 47. Then, the gaps allow one through-wiring 54 to be shared by four sensor pixels 12 and one through-wiring 47 to be shared by four sensor pixels 12A. In this modification example, the second substrate 20 has a readout circuit 22 for each set of four sensor pixels 12 sharing the floating diffusion portion FD.

[0214] [Modification Example E]

[0215] Figure 10 An example of the circuit configuration of the imaging device 1 according to the above-described embodiments and modification examples is shown. The imaging device 1 according to this modification example is a CMOS image sensor on which a column-parallel ADC is mounted.

[0216] As Figure 10 shown, in addition to a pixel region 13 including a plurality of sensor pixels 12 including photoelectric conversion elements arranged two-dimensionally in a matrix (matrix shape), the imaging device 1 according to this modification example further has a configuration including the following: a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0217] In this system configuration, based on the master clock MCK, the system control circuit 36 generates clock signals, control signals, etc. that are used as reference signals for the operations of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., and supplies them to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0218] In addition, the vertical drive circuit 33 is formed together with the sensor pixels 12 in the pixel region 13 in the first substrate 10, and is further formed in the second substrate 20 in which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed in the third substrate 30.

[0219] As the sensor pixel 12, although not shown in the figure here, for example, a sensor pixel 12 having the following configuration can be used: in addition to the photodiode PD, it further has a transfer transistor TR that transfers the charge obtained by photoelectric conversion at the photodiode PD to the floating diffusion portion FD. In addition, as the readout circuit 22, although not shown in the figure here, for example, a readout circuit 22 having a three-transistor configuration including the following can be used respectively: a reset transistor RST that controls the potential of the floating diffusion portion FD, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion portion FD, and a selection transistor SEL that performs pixel selection.

[0220] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally. In this pixel arrangement including m rows × n columns, the pixel drive lines 23 are arranged row by row, and the vertical signal lines 24 are arranged column by column. One end of each of the plurality of pixel drive lines 23 is connected to each output terminal of the vertical drive circuit 33 corresponding to one row. The vertical drive circuit 33 includes a shift register or the like, and controls the row addressing and row scanning of the pixel region 13 via the plurality of pixel drive lines 23.

[0221] For example, the column signal processing circuit 34 has ADCs (analog-to-digital conversion circuits) 34-1 to 34-m respectively provided for one pixel column in the pixel region 13 (that is, for one vertical signal line 24), converts the analog signals output from each column of sensor pixels 12 in the pixel region 13 into digital signals, and outputs the digital signals.

[0222] For example, the reference voltage supply unit 38 has a DAC (digital-to-analog conversion circuit) 38A as a device for generating a reference voltage Vref having a so-called ramp waveform whose level gradually changes over time. It should be noted that the device for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0223] Under the control of the control signal CS1 given by the system control circuit 36, the DAC 38A generates a reference voltage Vref having a ramp waveform based on the clock CK given by the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column processing unit 15.

[0224] Note that each of ADCs 34-1 to 34-m is configured to be able to selectively perform AD conversion operations corresponding to various operation modes, and the various operation modes include: a normal frame rate mode in a line-by-line scanning method of reading information of all sensor pixels 12; and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N, and the frame rate is N times higher than the frame rate in the normal frame rate mode, for example, twice as high. This switching of the operation mode is performed under the control of control signals CS2 and CS3 given by the system control circuit 36. In addition, instruction information for switching the operation mode between the normal frame rate mode and the high frame rate mode is given from an external system controller (not shown) to the system control circuit 36.

[0225] ADCs 34-1 to 34-m all have the same configuration, and here ADC 34-m is taken as an example for illustration. ADC 34-m has a comparator 34A, an up / down counter (represented as U / DCNT in the figure) 34B as a counting device, a switching switch 34C, and a storage device 34D.

[0226] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the n-th column of the pixel region 13 with a reference voltage Vref having a ramp waveform provided by the reference voltage supply unit 38. For example, when the reference voltage Vref is higher than the signal voltage Vx, the output Vcc is at the "H" level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vcc is at the "L" level.

[0227] The up / down counter 34B is an asynchronous counter. Under the control of the control signal CS2 given by the system control circuit 36, the clock CK from the system control circuit 36 is given to the up / down counter 34B simultaneously with the DAC 38A, and the up / down counter 34B counts down (DOWN) or counts up (UP) synchronously with the clock CK, thereby measuring the comparison period from the start to the end of the comparison operation at the comparator 34A.

[0228] Specifically, in the normal frame rate mode, in the operation of reading a signal from one sensor pixel 12, counting down is performed during the first read operation to measure the comparison time during the first read operation, and counting up is performed during the second read operation to measure the comparison time during the second read operation.

[0229] On the other hand, in the high frame rate mode, the counting result of the sensor pixels 12 in a row remains as it is. Subsequently, regarding the sensor pixels 12 in the next row, during the first read operation, a down-count is performed from the previous counting result to measure the comparison time during the first read operation, and during the second read operation, an up-count is performed to measure the comparison time during the second read operation.

[0230] Under the control of the control signal CS3 given by the system control circuit 36, at the time point when the counting operation of the up / down counter 34B for a row of sensor pixels 12 has been completed, the changeover switch 34C in the normal frame rate mode is turned on (closed), and the counting result of the up / down counter 34B is transmitted to the storage device 34D.

[0231] On the other hand, for example, in the high frame rate mode with N = 2, at the time point when the counting operation of the up / down counter 34B for a row of sensor pixels 12 has been completed, the changeover switch 34C remains off (open). Subsequently, at the time point when the counting operation of the up / down counter 34B for the sensor pixels 12 in the next row has been completed, the changeover switch 34C is turned on, and the counting results of the two vertical pixels regarding the up / down counter 34B are transmitted to the storage device 34D.

[0232] In this way, through the operations of each of the comparators 34A in the ADCs 34-1 to 34-m and the up / down counter 34B, the analog signals provided from each column of sensor pixels 12 in the pixel region 13 through the vertical signal lines 24 are converted into N-bit digital signals, and the digital signals are stored on the storage device 34D.

[0233] The horizontal drive circuit 35 includes a shift register and the like, and controls the column addressing and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the AD-converted N-bit digital signals obtained at each of the ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37 and output as imaging data through the horizontal output line 37.

[0234] It should be noted that, although not particularly shown because it is not directly related to the present technology, in addition to the above-described components, a circuit or the like that performs various signal processes on the imaging data output through the horizontal output line 37 may also be provided.

[0235] In the imaging device 1 having the above configuration and on which the column parallel ADC is mounted according to this modification example, the counting result of the up / down counter 34B can be selectively transmitted to the storage device 34D via the changeover switch 34C. Therefore, the counting operation of the up / down counter 34B and the operation of reading out the counting result of the up / down counter 34B to the horizontal output line 37 can be controlled independently.

[0236] [Modification example F]

[0237] Figure 11 An example is shown Figure 10 in which the imaging device includes three substrates (first substrate 10, second substrate 20, and third substrate 30) stacked on top of each other. In this modification example, a pixel region 13 including a plurality of sensor pixels 12 is formed in the central portion of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. In addition, a readout circuit region 15 including a plurality of readout circuits 22 is formed in the central portion of the second substrate 20, and a vertical drive circuit 33 is formed around the readout circuit region 15. A column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed in the third substrate 30. Thus, similar to the above-described embodiments and their modification examples, the structure of electrically connecting the substrates necessarily does not require an increase in chip size and does not inhibit miniaturization of the area size per pixel, etc. Therefore, an imaging device 1 having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not inhibit miniaturization of the area size per pixel. It should be noted that the vertical drive circuit 33 may be formed only in the first substrate 10 or may be formed only in the second substrate 20.

[0238] [Modification example G]

[0239] Figure 12 A modification example of the cross-sectional configuration of the imaging device 1 according to the above-described embodiments and their modification examples is shown. In the above-described embodiments and their modification examples, the imaging device 1 includes three substrates (first substrate 10, second substrate 20, and third substrate 30) stacked on top of each other. However, in the above-described embodiments and their modification examples, the imaging device 1 may include two substrates (first substrate 10 and second substrate 20) stacked on top of each other. At this time, for example, as Figure 12As shown, each logic circuit 32 is separately formed in the first substrate 10 and the second substrate 20. Here, the circuit 32A in the logic circuit 32 provided on the first substrate 10 side is provided with a transistor having the following gate structure: a high dielectric constant film made of a material (e.g., high-k) capable of withstanding high-temperature processes and a metal gate electrode are laminated on each other. On the other hand, the circuit 32B on the second substrate 20 side has an impurity diffusion region in contact with the source electrode and the drain electrode, and the front surface of the impurity diffusion region has a low-resistance region 26 made of a silicide such as CoSi2 or NiSi formed by using a Self Aligned Silicide process. The low-resistance region made of a silicide is formed of a metal compound and the material of the semiconductor substrate. Thus, when forming the sensor pixel 12, high-temperature processes such as thermal oxidation can be used. In addition, when the circuit 32B in the logic circuit 32 provided on the second substrate 20 side has an impurity diffusion region in contact with the source electrode and the drain electrode and the front surface of the impurity diffusion region is provided with the low-resistance region 26 made of a silicide, the contact resistance can be reduced. Therefore, the calculation speed of the logic circuit 32 can be improved.

[0240] Figure 13 A modified example of the cross-sectional configuration of the imaging device 1 according to the above-described embodiment and its modified examples is shown. The logic circuit 32 of the third substrate 30 according to the above-described embodiment and its modified examples has an impurity diffusion region in contact with the source electrode and the drain electrode, and the front surface of the impurity diffusion region may have a low-resistance region 37 made of a silicide such as CoSi2 or NiSi formed by using a Self Aligned Silicide process. Thus, when forming the sensor pixel 12, high-temperature processes such as thermal oxidation can be used. In addition, when the logic circuit 32 has an impurity diffusion region in contact with the source electrode and the drain electrode and the front surface of the impurity diffusion region is provided with the low-resistance region 37 made of a silicide, the contact resistance can be reduced. Therefore, the calculation speed of the logic circuit 32 can be improved.

[0241] [Modified Example H]

[0242] In the above-described embodiment and its modified examples, the conductivity type may be opposite. For example, in the description of the above-described embodiment and its modified examples, p-type may be read as n-type, and n-type may be read as p-type. Even in the case of adopting such an arrangement, effects similar to those of the above-described embodiment and its modified examples can be achieved.

[0243] (Applicable Example)

[0244] Figure 14An example of a schematic configuration of an imaging system 2 including the imaging device 1 according to the above-described embodiments and their modifications is shown.

[0245] For example, the imaging system 2 is an electronic device, such as an imaging device such as a digital camera or a video camera, or a mobile terminal device such as a smart phone or a tablet terminal. For example, the imaging system 2 includes the imaging device 1 according to the above-described embodiments and their modifications, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the imaging device 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 according to the above-described embodiments and their modifications are connected to each other via a bus 147.

[0246] The imaging device 1 according to the above-described embodiments and their modifications outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes signals (image data) output from the imaging device 1 according to the above-described embodiments and their modifications. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 in units of frames. For example, the display unit 143 includes a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above-described embodiments and their modifications. The storage unit 144 records the image data of the moving image or the still image captured by the imaging device 1 according to the above-described embodiments and their modifications on a recording medium such as a semiconductor memory or a hard disk. According to the user's operation, the operation unit 145 gives operation instructions for various functions of the imaging system 2. Appropriately, the power supply unit 146 supplies various power supplies to the imaging device 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145 as operation power supplies for these supply targets.

[0247] Next, the imaging process of the imaging system 2 will be described.

[0248] Figure 15 An example of a flowchart of the imaging operation of the imaging system 2 is shown. The user operates the operation unit 145 to give an instruction to start imaging (step S101). Then, the operation unit 145 sends an imaging instruction to the imaging device 1 (step S102). When the imaging instruction is received, the imaging device 1 (specifically, the system control circuit 36) performs imaging by a predetermined imaging method (step S103).

[0249] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data corresponding to all pixels of the pixel signals generated based on the charges temporarily held in the floating diffusion section FD. Based on the image data input from the imaging device 1, the DSP circuit 141 performs predetermined signal processing (for example, noise reduction processing, etc.) (step S104). The DSP circuit 141 causes the frame memory 142 to hold the image data that has undergone the predetermined signal processing, and the frame memory 142 stores the image data on the storage section 144 (step S105). In this way, imaging is performed in the imaging system 2.

[0250] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to the imaging system 2. Thereby, an imaging device 1 with a smaller size or higher resolution can be realized, and thus an imaging system 2 with a smaller size or higher resolution can be provided.

[0251] (More specific configuration of the first embodiment)

[0252] (Configuration of the semiconductor device)

[0253] As a more specific configuration of the semiconductor device according to the first embodiment of the present technology, a back-illuminated type CMOS image sensor (solid-state imaging device) is shown. As Figure 16 shown, the semiconductor device according to the first embodiment of the present technology includes a pixel region (unit cell region) 1001, a vertical drive circuit 1003, a column signal processing circuit 1004, a horizontal drive circuit 1005, an output circuit 1006, and a control circuit 1007.

[0254] The pixel region 1001 has a plurality of pixels (unit cells) 1002 arranged in a two-dimensional matrix. Each of the plurality of pixels 1002 has a photoelectric conversion section and a plurality of pixel transistors (unit circuits). As the plurality of pixel transistors, for example, four transistors (transfer transistor, reset transistor, selection transistor, and amplification transistor) can be employed.

[0255] For example, the vertical drive circuit 1003 includes a shift register. The vertical drive circuit 1003 sequentially selects the pixel drive lines 1008a, supplies the pulses for driving the pixels 1002 to the selected pixel drive lines 1008a, and drives the pixels 1002 in each row. That is, the vertical drive circuit 1003 vertically and sequentially selectively scans each row of pixels 1002 in the pixel region 1001, and supplies the output signal (pixel signal) from the pixels based on the signal charges generated by the photoelectric conversion sections of the pixels 1002 to the column signal processing circuit 1004 through the vertical signal lines 1008b.

[0256] For example, each column signal processing circuit 1004 is arranged for one column of pixels 1002, and performs signal processing such as noise removal on the signals output from one row of pixels 1002 for each pixel column. For example, the column signal processing circuit 1004 performs signal processing such as correlated double sampling (CDS) for removing fixed pattern noise specific to pixels or analog / digital (AD) conversion.

[0257] For example, the horizontal drive circuit 1005 includes a shift register. The horizontal drive circuit 1005 sequentially outputs horizontal scan pulses to the column signal processing circuits 1004, sequentially selects the column signal processing circuits 1004, and causes the selected column signal processing circuits 1004 to output pixel signals that have undergone signal processing to the horizontal signal lines 1009. The output circuit 1006 performs signal processing on the pixel signals sequentially provided from each column signal processing circuit 1004 via the horizontal signal lines 1009, and outputs the pixel signals.

[0258] Based on the vertical synchronization signal, horizontal synchronization signal, and main clock signal, the control circuit 1007 generates a clock signal and a control signal to be used as reference signals for the operations of the vertical drive circuit 1003, column signal processing circuits 1004, horizontal drive circuit 1005, etc. Then, the control circuit 1007 outputs the generated clock signal and control signal to the vertical drive circuit 1003, column signal processing circuits 1004, horizontal drive circuit 1005, etc.

[0259] As Figure 17 shown, the semiconductor device according to the first embodiment of the present technology has a three-dimensional structure formed by stacking the Figure 16 structures shown. That is, the semiconductor device according to the first embodiment of the present technology is configured to have a stacked structure formed by bonding three substrates, namely, a first substrate (sensor substrate) 1101, a second substrate (pixel transistor substrate) 1102, and a third substrate (logic substrate) 1103.

[0260] The first substrate 1101 includes a photoelectric conversion portion forming region 1101a in which a photoelectric conversion portion that performs photoelectric conversion of incident light is formed. At least some pixel transistors such as transfer transistors that control signal charges for photoelectric conversion can be formed in the photoelectric conversion portion forming region 1101a in addition to the photoelectric conversion portion.

[0261] The second substrate 1102 includes a pixel transistor formation region 1102a in which at least some pixel transistors for controlling signal charges for photoelectric conversion are formed. For example, at least some pixel transistors such as a reset transistor, a selection transistor, or an amplification transistor may be formed in the pixel transistor formation region 1102a. It should be noted that, for example, only the amplification transistor among the pixel transistors may be provided in the second substrate 1102, and either or both of the reset transistor and the selection transistor may be provided in the third substrate 1103.

[0262] The third substrate 1103 includes a logic circuit formation region 1103a in which a logic circuit for performing signal processing is formed. For example, as the logic circuit, the logic circuit formation region 1103a may include Figure at least a part of the vertical drive circuit 1003, the column signal processing circuit 1004, the horizontal drive circuit 1005, the output circuit 1006, and the control circuit 1007 shown in

[0263] It should be noted that although ​ a stacked structure formed by bonding three substrates (the first substrate 1101, the second substrate 1102, and the third substrate 1103) together is shown, for example, the stacked structure may also be formed by bonding two substrates (the first substrate 1101 and the second substrate 1102) together. In this case, for example, the logic circuit formation region 1103a of the third substrate 1103 may be formed in the second substrate 1102 or the like. In addition, the stacked structure may be formed by further bonding one or more substrates on the third substrate 1103.

[0264] ​ An example of an equivalent circuit of a pixel 1002 in a semiconductor device according to a first embodiment of the present technology is shown. As represented by the boundary line shown by the dotted line in ​ the pixel 1002 includes a circuit having an active element provided in the first substrate 1101 and a circuit having an active element provided in the second substrate 1102. An "active element" is a semiconductor element such as a transistor having an amplification function or a switching function.

[0265] As ​As shown in the figure, the first substrate 1101 includes a photodiode PD, which is a photoelectric conversion section grounded at the anode, and a transfer transistor T1, whose source is connected to the cathode of the photodiode PD, as active elements therein. The drain of the transfer transistor T1 is connected to a charge accumulation region (floating diffusion region) FD in a floating state. The charge accumulation region FD is connected to the source of a reset transistor T2, which is an active element provided in the second substrate 1102, and the gate of an amplification transistor T3, which is an active element. A selection transistor T4 is further provided as an active element in the second substrate 1102. The source of the amplification transistor T3 is connected to the drain of the selection transistor T4, and the drain of the amplification transistor T3 is connected to a power supply Vdd. The source of the selection transistor T4 is connected to a vertical signal line VSL. The drain of the reset transistor T2 is connected to the power supply Vdd.

[0266] When operating the semiconductor device according to the first embodiment, the signal charges generated by the photodiode PD are accumulated in the charge accumulation region FD via the transfer transistor T1, and the signal charges accumulated in the charge accumulation region FD are read out and applied to the gate of the amplification transistor T3. A horizontal line selection control signal is supplied from the vertical shift register to the gate of the selection transistor T4. By making the selection control signal a high (H)-level signal, the selection transistor T4 becomes conductive, and a current corresponding to the potential of the charge accumulation region FD amplified at the amplification transistor T3 flows to the vertical signal line VSL. Further, by making the reset control signal applied to the gate of the reset transistor T2 a high (H)-level signal, the reset transistor T2 becomes conductive, and the signal charges accumulated in the charge accumulation region FD are reset.

[0267] ​ A part of the cross-sectional structure of the semiconductor device according to the first embodiment is schematically shown. The semiconductor device according to the first embodiment has a stacked structure formed by bonding three substrates (the first substrate 1101, the second substrate 1102, and the third substrate 1103) together. The semiconductor device according to the first embodiment is a back-illuminated solid-state imaging device and receives light incident from the back ( ​ the lower side).

[0268] The first substrate 1101 includes: a sensor layer 1010; a first element layer 1020 disposed on the sensor layer 1010 and including a first active element 1021; a first wiring layer 1030 disposed on the first element layer 1020; and a shield layer 1040 disposed on the first wiring layer 1030. The second substrate 1102 includes: a second element layer 1050 disposed on the shield layer 1040 via an interlayer insulating film 1042 and including second active elements 1052, 1053, 1054, and 1055; and a second wiring layer 1060 disposed on the second element layer 1050. The third substrate 1103 includes: a third wiring layer 1070 disposed on the second wiring layer 1060; and a third element layer 1080 disposed on the third wiring layer 1070 and including third active elements 1082 and 1083.

[0269] The sensor layer 1010 has a plurality of photoelectric conversion portions 1011a, 1011b, and 1011c formed in a semiconductor substrate (Si substrate) 1011 made of silicon (Si) or the like. Each of the photoelectric conversion portions 1011a, 1011b, and 1011c is constituted by a photodiode. The photodiode is constituted by a pn junction between a p-type well region (not shown) and an n-type charge generation region (not shown) formed in the Si substrate 1011.

[0270] Adjacent photoelectric conversion portions 1011a, 1011b, and 1011c are separated by an element isolation portion 1012. For example, when viewed from the lower side of ​ , the element isolation portion 1012 is formed like a grid. The element isolation portion 1012 has a function of electrically and optically isolating adjacent photoelectric conversion portions 1011a, 1011b, and 1011c from each other. For example, the element isolation portion 1012 may be constituted by an insulating film embedded in a groove portion provided in the Si substrate 1011. For example, the insulating film may be a structure formed by laminating a fixed charge film such as a hafnium oxide film (HfO2 film) and a silicon oxide film (SiO2 film). Alternatively, the element isolation portion 1012 may be constituted by an insulating film embedded in a groove portion provided in the Si substrate 1011 and a light-shielding metal film made of tungsten (W) or the like embedded in the groove portion via the insulating film. A light-shielding film (not shown) made of tungsten (W) or the like may be disposed on the lower side of the element isolation portion 1012.

[0271] A planarization film 1091, a color filter 1092, a microlens 1093, wirings (not shown), etc. are arranged on the back surface of the sensor layer 1010. The planarization film 1091 planarizes the back surfaces of the photoelectric conversion portions 1011a, 1011b, and 1011c. The microlens 1093 converges incident light onto the photoelectric conversion portions 1011a, 1011b, and 1011c. The color filter 1092 separates the colors of the incident light incident on the photoelectric conversion portions 1011a, 1011b, and 1011c.

[0272] For example, the first element layer 1020 constitutes a first unit circuit that independently extracts electrical signals generated by photoelectrically converting incident light by the plurality of photoelectric conversion portions 1011a, 1011b, and 1011c. The first element layer 1020 includes a first active element 1021, and the first active element 1021 is formed on the front surface of the Si substrate 1011 and is included in the first unit circuit. For example, the first active element 1021 may be constituted by ​ the transfer transistor T1 shown in. Although the transfer transistor T1 may be constituted by a MOS transistor as an active element, more typically, the transfer transistor T1 may be an insulated gate type transistor (MIS transistor) such as a MISFET or a MISSIT that includes a material other than an oxide film (SiO2 film) in the gate insulating film.

[0273] For convenience, ​ only the gate electrode of the first active element 1021 is schematically shown. For example, the gate electrode of the first active element 1021 may be a vertical gate having a T-shaped cross-sectional shape. It should be noted that although this is different from the ​ circuit configuration shown in, in addition to the transfer transistor T1, the first element layer 1020 may further include at least one of pixel transistors such as a reset transistor T2, an amplification transistor T3, and a selection transistor T4.

[0274] The first wiring layer 1030 is electrically connected to the first element layer 1020. The first wiring layer 1030 has wirings 1031, 1032, 1033, and 1034 embedded in the interlayer insulating film 1035. As the material of the wirings 1031, 1032, 1033, and 1034, for example, a metal such as copper (Cu) can be used, and as the material of the interlayer insulating film 1035, a silicon oxide film (SiO2 film) or the like can be used. ​The case where the lower wirings 1031 and 1032 and the upper wirings 1033 and 1034 form a double-layer wiring structure is shown, but the number of wiring layers in the first wiring layer 1030 is not limited thereto. For example, the number of wiring layers in the first wiring layer 1030 may be one layer, or may be three or more layers. The lower wirings 1031 and 1032 and the upper wirings 1033 and 1034 may be electrically connected through vias (not shown).

[0275] The shielding layer 1040 has the function of shielding heat, light, and electromagnetism between the first element layer 1020 disposed below the shielding layer 1040 and the second element layer 1050 disposed above the shielding layer 1040. The shielding layer 1040 may have the function of blocking the transmission of infrared rays, and may have the function of forming a capacitor to prevent surges.

[0276] As the material of the shielding layer 1040, for example, a material including a conductive material such as a metal (such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), or tungsten (W), etc.) or any alloy of these metals can be used. In addition, if necessary, a ferromagnetic material such as ferrite can also be used as the material of the shielding layer 1040. The material of the shielding layer 1040 may be another conductive material as long as it can shield heat, light, and electromagnetism.

[0277] For example, the thickness of the shielding layer 1040 is approximately equal to or greater than 300 nm but equal to or less than 500 nm, but it may be less than 300 nm or may be greater than 500 nm. Although not shown in the figure, the shielding layer 1040 is connected to the ground potential via the Si substrate 1011. Although ​ The case where the shielding layer 1040 is a single layer is shown, but it may be a laminated structure formed by laminating a plurality of conductive materials made of different materials on each other. The shielding layer 1040 is provided with openings (vias) 1041a and 1041b for allowing the connection wirings 1066 and 1067 to pass through therein.

[0278] For example, the second element layer 1050 constitutes a second unit circuit connected to the first element layer 1020 corresponding to each of the plurality of pixels 1002. The second element layer 1050 has second active elements 1052, 1053, 1054, and 1055 formed in a semiconductor substrate (Si substrate) 1051 made of Si and included in the second unit circuit. For example, each of the second active elements 1052, 1053, 1054, and 1055 may include ​ at least one of the reset transistor T2, the amplification transistor T3, and the selection transistor T4 shown in. Each of the reset transistor T2, the amplification transistor T3, and the selection transistor T4 may be composed of a MOS transistor, but more generally, may be a MIS transistor. For convenience,​ Only the gate electrodes of the second active elements 1052, 1053, 1054, and 1055 are schematically shown.

[0279] The second wiring layer 1060 is electrically connected to the second element layer 1050. The second wiring layer 1060 has wirings 1061, 1062, 1063, and 1064 embedded in the interlayer insulating film 1065. As the material of the wirings 1061, 1062, 1063, and 1064, for example, a metal such as copper (Cu) can be used, and as the material of the interlayer insulating film 1065, a silicon oxide film (SiO2 film) or the like can be used. ​ A case where the lower wirings 1061 and 1062 and the upper wirings 1063 and 1064 form a double-layer wiring structure is shown, but the number of wiring layers of the second wiring layer 1060 is not limited thereto. For example, the number of wiring layers of the second wiring layer 1060 can be one layer, or can be three or more layers. The lower wirings 1061 and 1062 and the upper wirings 1063 and 1064 can be electrically connected through vias (not shown).

[0280] The wiring 1061 located on the lowermost layer of the second wiring layer 1060 is connected to the upper end of the connection wiring 1066. The connection wiring 1066 extends vertically to penetrate the second element layer 1050, the shielding layer 1040, and the first wiring layer 1030. The connection wiring 1066 is provided to penetrate the opening 1041a of the shielding layer 1040. The lower end of the connection wiring 1066 is connected to a contact portion (not shown) included in the first element layer 1020 provided on the upper portion of the Si substrate 1011. For example, the connection wiring 1066 can electrically connect the gate electrode of the amplification transistor constituted by the second active element 1053 electrically connected via the wiring 1061 and the charge accumulation region included in the first element layer 1020 and formed on the upper portion of the Si substrate 1011.

[0281] In addition, the wiring 1062 located on the lowermost layer of the second wiring layer 1060 is connected to the upper end of the connection wiring 1067. The connection wiring 1067 extends vertically to penetrate the second element layer 1050 and the shielding layer 1040. The connection wiring 1067 is provided to penetrate the opening 1041b of the shielding layer 1040. The lower end of the connection wiring 1067 is connected to the wiring 1034 of the first wiring layer 1030.

[0282] ​ A cross-sectional view in the horizontal direction when viewed along the ​ A - A direction in ​ is shown. The vertical cross-section when viewed along the ​ B - B direction in ​As shown, the connection wirings 1066 and 1067 and the interlayer insulating film 1042 have a coaxial cross-sectional shape. For example, the openings 1041a and 1041b of the shielding layer 1040 have a circular cross-sectional shape and are arranged to surround the outer peripheral surfaces of the connection wirings 1066 and 1067 via the interlayer insulating film 1042 respectively. It should be noted that the horizontal cross-sectional pattern of the shielding layer 1040 is not limited to this. For example, the horizontal cross-sectional pattern of the shielding layer 1040 can be a pattern having stripes extending parallel to each other, a grid pattern, or a dot pattern.

[0283] The third wiring layer 1070 has wirings 1071, 1072, 1073, and 1074 embedded in the interlayer insulating film 1075. As the material of the wirings 1071, 1072, 1073, and 1074, for example, a metal such as copper (Cu) can be used. ​ A case where the lower side wirings 1071 and 1072 and the upper side wirings 1073 and 1074 form a double-layer wiring structure is shown, but the number of wiring layers of the third wiring layer 1070 is not limited to this. For example, the number of wiring layers of the third wiring layer 1070 can be one layer, or can be three or more layers. The wirings 1071 and 1072 on the lowermost layer are electrically connected to the wirings 1063 and 1064 on the uppermost layer of the second wiring layer 1060.

[0284] The third element layer 1080 has third active elements 1082 and 1083 formed on a semiconductor substrate (Si substrate) 1081 made of Si and constituting a logic circuit. Each of the third active elements 1082 and 1083 can be constituted by a MOS transistor, but more generally, can be a MIS transistor. For convenience, ​ Only the gate electrodes of the third active elements 1082 and 1083 are schematically shown.

[0285] Since the semiconductor device according to the first embodiment has the shielding layer 1040 between the first element layer 1020 formed in the first substrate 1101 and the second element layer 1050 formed in the second substrate 1102, the shielding layer 1040 is used for optical, electromagnetic, and thermal shielding between the first element layer 1020 arranged below the shielding layer 1040 and the second element layer 1050 arranged above the shielding layer 1040. Therefore, the mutual influence of noise and heat propagated between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 is eliminated, and noise, operation errors, etc. that affect the element characteristics can be suppressed. Therefore, the deterioration of the element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 can be suppressed.

[0286] <Method of manufacturing a semiconductor device>

[0287] Next, with reference to ​ an example of a method of manufacturing a semiconductor device according to the first embodiment will be described.

[0288] First, a photoresist film is coated on the Si substrate 1011, and the photoresist film is patterned by using lithography. Using the patterned photoresist film as an etching mask, a deep groove portion (trench) having vertical sidewalls is formed by dry etching such as reactive ion etching (RIE). Thereafter, the photoresist film is removed, and the Si substrate 1011 is cleaned. Then, an insulating film or a structure formed by laminating an insulating film and a metal film on each other is embedded in the groove portion by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or the like. Thereafter, the insulating film and the metal film on the Si substrate 1011 are removed by etch back, chemical mechanical polishing (CMP), or the like. Thus, as ​ shown in

[0289] a wall-like element isolation portion 1012 is formed on the upper portion of the Si substrate 1011. ​ shown in

[0290] Next, as ​ shown in

[0291] an interlayer insulating film 1035 and wirings 1031, 1032, 1033, and 1034 are alternately laminated on the Si substrate 1011 by a dual damascene method or the like, thereby forming a first wiring layer 1030. ​As shown in [reference], openings 1041a and 1041b are formed in the shielding layer 1040 to expose the front surface of the interlayer insulating film 1035. Thereafter, by means of CVD method or the like, as ​ shown in [reference], the interlayer insulating film 1042 is deposited on the shielding layer 1040 to fill the openings 1041a and 1041b of the shielding layer 1040.

[0292] On the other hand, as ​ shown in [reference], the Si substrate 1051 is separately prepared, and the source regions and drain regions of the second active elements 1052, 1053, 1054 and 1055 are formed on the upper part of the Si substrate 1051 by means of photolithography, ion implantation, heat treatment, etc. In addition, the gate insulating film and gate electrodes of the second active elements 1052, 1053, 1054 and 1055 are formed on the Si substrate 1051 by means of CVD method, photolithography, etching, etc. Thus, the second active elements 1052, 1053, 1054 and 1055 are formed. Thereafter, by means of CVD method or the like, the interlayer insulating film 1056 is deposited on the Si substrate 1051.

[0293] Next, by using an adhesive or the like, the support substrate 1057 is bonded to the Si substrate 1051 on the surface side (front surface) where the second active elements 1052, 1053, 1054 and 1055 are formed. Then, by using CMP or the like, by polishing the surface (back surface) of the Si substrate 1051 opposite to the surface where the second active elements 1052, 1053, 1054 and 1055 are formed, as ​ shown in [reference], the Si substrate 1051 is thinned.

[0294] Next, the ​ surface (back surface) of the Si substrate 1051 opposite to the surface where the second active elements 1052, 1053, 1054 and 1055 are formed shown in [reference] and ​ the front surface of the interlayer insulating film 1042 of the first substrate 1101 shown in [reference] are opposed to each other, and are bonded to each other as ​ shown in [reference]. As a bonding method, for example, after irradiating the wafers with plasma, the wafers are washed with water, and the wafers are bonded to each other by a wafer bonding device. However, it should be noted that the bonding method is not limited thereto, and the wafers can be bonded to each other by using an adhesive or the like, for example. Further, the support substrate 1057 is peeled off, and the adhesive used for bonding to the support substrate 1057 is removed by cleaning.

[0295] Next, through dry etching such as photoresist technology or RIE, a groove portion is formed that penetrates the second element layer 1050, the shielding layer 1040, and the first wiring layer 1030, exposing the front surface of the Si substrate 1011 and used for forming the connection wiring 1066; and a groove portion is formed that penetrates the second element layer 1050 and the shielding layer 1040, exposing the front surface of the wiring 1034 and used for forming the connection wiring 1067. Then, by means of CVD method or the like, a metal film is deposited so as to fill the groove portion, and the metal film on the interlayer insulating film 1056 is removed by etch back, CMP, etc. Thus, as ​ shown in, the connection wiring 1066 whose lower end is connected to the Si substrate 1011 and the connection wiring 1067 whose lower end is connected to the wiring 1034 are formed.

[0296] The connection wirings 1066 and 1067 are formed to penetrate the openings 1041a and 1041b of the shielding layer 1040. In addition, an insulating structure is formed in the Si substrate 1051 of the second element layer 1050 so as to surround the outer peripheral surfaces of the connection wirings 1066 and 1067. It should be noted that in the case where an insulating layer is formed in advance in the portion of the Si substrate 1051 of the second element layer 1050 penetrated by the connection wirings 1066 and 1067, it is not necessary to form an insulating structure on the Si substrate 1051.

[0297] Next, by means of the dual damascene method or the like, as ​ shown in, the interlayer insulating film 1065 and the wirings 1061, 1062, 1063, and 1064 are alternately laminated on the interlayer insulating film 1056, thereby forming the second wiring layer 1060. The wiring 1061 of the second wiring layer 1060 is formed to be connected to the upper end of the connection wiring 1066. The wiring 1062 of the second wiring layer 1060 is formed to be connected to the upper end of the connection wiring 1067.

[0298] On the other hand, as ​ shown in, the Si substrate 1081 is separately prepared, and the source regions and drain regions of the third active elements 1082 and 1083 are formed on the upper part of the Si substrate 1081 by means of photolithography technology, ion implantation, heat treatment, etc. In addition, the gate insulating film and gate electrodes of the third active elements 1082 and 1083 are formed by means of CVD method, photolithography technology, etching, etc. Thus, the third active elements 1082 and 1083 are formed, and the third element layer 1080 is formed. Further, by means of the dual damascene method or the like, the interlayer insulating film 1075 and the wirings 1071, 1072, 1073, and 1074 are alternately laminated on the Si substrate 1081, thereby forming the third wiring layer 1070. Thus, the third substrate 1103 is formed.

[0299] Next, ​The side of the third wiring layer 1070 of the third substrate 1103 shown in [Figure] where wirings 1071 and 1072 are formed faces ​ the side of the second wiring layer 1060 of the second substrate 1102 shown in [Figure] where wirings 1063 and 1064 are formed, and they are bonded together as shown in ​ [Figure]. Thereafter, the Si substrate 1081 is polished from the front surface side by CMP or the like, so that the Si substrate 1081 becomes thinner.

[0300] Next, the Si substrate 1011 is polished from the back surface by CMP or the like, so that the element separation portion 1012 is exposed, and the photoelectric conversion portions 1011a, 1011b, and 1011c as elements are separated. Further, wirings (not shown), a planarization film 1091, a color filter 1092, a microlens 1093, etc. are formed on the back surface of the Si substrate 1011. Thus, the semiconductor device according to the first embodiment shown in ​ [Figure] is completed.

[0301] According to the manufacturing method of the semiconductor device according to the first embodiment, the shielding layer 1040 formed between the first element layer 1020 and the second element layer 1050 performs optical, electromagnetic, and thermal shielding between the first element layer 1020 disposed below the shielding layer 1040 and the second element layer 1050 disposed above the shielding layer 1040. Therefore, the mutual propagation of noise and heat between the first element layer 1020 and the second element layer 1050 can be suppressed. Therefore, a semiconductor device can be manufactured that can suppress the deterioration of the element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050.

[0302] (Second Embodiment)

[0303] As shown in ​ [Figure], the semiconductor device according to the second embodiment of the present technology is different from the semiconductor device according to the first embodiment shown in ​ [Figure] in terms of the structure of the shielding layer 1040. In other aspects, the configuration of the semiconductor device according to the second embodiment of the present technology is similar to the semiconductor device according to the first embodiment shown in ​ [Figure], and thus repeated descriptions are omitted.

[0304] It should be noted that in ​The planarization film, color filter, microlens, etc. on the back side of the Si substrate 1011 are not shown. In addition, although a stacked structure formed by bonding two substrates (the first substrate 1101 and the second substrate 1102) is shown as the semiconductor device according to the second embodiment of the present technology, another substrate such as the third substrate 1103 shown in Figure 19 can be further stacked on the second substrate 1102.

[0305] In the semiconductor device according to the second embodiment of the present technology, as a part of the shielding layer 1040, sheath portions 1043 and 1044 are respectively provided around the openings 1041a and 1041b of the shielding layer 1040. The sheath portions 1043 and 1044 are electrically connected to the shielding layer 1040. As the material of the sheath portions 1043 and 1044, similar to the shielding layer 1040, for example, a material including a conductive material such as a metal (such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), or tungsten (W)) or any alloy of these metals can be used. As the material of the sheath portions 1043 and 1044, the same material as that of the shielding layer 1040 can be used, or different materials can be used.

[0306] The sheath portion 1043 extends vertically to surround the outer peripheral surface of the connection wiring 1066. The upper end of the sheath portion 1043 is located near the wiring 1061 of the second wiring layer 1060. The lower end of the sheath portion 1043 is located near the Si substrate 1011. An insulating structure is formed between the sheath portion 1043 and the connection wiring 1066 and between the sheath portion 1043 and the second element layer 1050.

[0307] The sheath portion 1044 extends vertically to surround the outer peripheral surface of the connection wiring 1067. The upper end of the sheath portion 1044 is located near the wiring 1062 of the second wiring layer 1060. The lower end of the sheath portion 1044 is located near the wiring 1034 of the first wiring layer 1030. An insulating structure is formed between the sheath portion 1044 and the connection wiring 1067 and between the sheath portion 1044 and the second element layer 1050.

[0308] Figure 34 A cross-sectional view in the horizontal direction when viewed from the A-A direction in Figure 33 is shown. The vertical cross-section when viewed from the B-B direction in Figure 34 corresponds to Figure 33 . As shown in Figure 34 , the connection wirings 1066 and 1067 have a coaxial cross-sectional shape with the interlayer insulating film 1042. The sheath portions 1043 and 1044 have a cylindrical cross-sectional shape and are arranged coaxially with the connection wirings 1066 and 1067 so as to surround the connection wirings 1066 and 1067 with the interlayer insulating film 1042 interposed therebetween. It should be noted that although Figure 34Illustrated is a case where sheaths 1043 and 1044 have a cylindrical cross-sectional shape, but the cross-sectional pattern of sheaths 1043 and 1044 is not limited to this.

[0309] When manufacturing a semiconductor device according to the second embodiment of the present technology, for example, a second element layer 1050 is formed, and then, by dry etching such as CVD method or RIE, metal films, interlayer insulating films, and connection wirings 1066 and 1067 serving as sheaths 1043 and 1044 are sequentially embedded in groove portions penetrating through the second element layer 1050, the shielding layer 1040, etc., so that connection wirings 1066 and 1067 and sheaths 1043 and 1044 can be formed. Other manufacturing steps of the semiconductor device according to the second embodiment of the present technology are similar to those of the semiconductor device according to the first embodiment of the present technology, and thus repeated descriptions are omitted.

[0310] Similar to the semiconductor device according to the first embodiment of the present technology, since the semiconductor device according to the second embodiment of the present technology has a shielding layer 1040 between the first element layer 1020 formed in the first substrate 1101 and the second element layer 1050 formed in the second substrate 1102, the shielding layer 1040 performs optical, electromagnetic, and thermal shielding between the first element layer 1020 disposed below the shielding layer 1040 and the second element layer 1050 disposed above the shielding layer 1040. Therefore, the mutual influence of noise and heat propagation between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 is eliminated, and noise, operation errors, etc. that affect element characteristics can be suppressed. Therefore, the deterioration of the element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 can be suppressed.

[0311] Furthermore, since the semiconductor device according to the second embodiment of the present technology includes sheaths 1043 and 1044 as part of the shielding layer 1040 such that they extend along the outer peripheral surfaces of the connection wirings 1066 and 1067, the connection wirings 1066 and 1067 inside the sheaths 1043 and 1044 can stably propagate signals without being affected by capacitive coupling or the like.

[0312] (Third Embodiment)

[0313] The semiconductor device according to the third embodiment of the present technology is described with reference to FIGS. 35 and 36. The semiconductor device according to the third embodiment is a back-illuminated solid-state imaging device and receives light incident from the back side (the lower side in FIG. 35). In other respects, the configuration of the semiconductor device according to the third embodiment of the present technology is the same asFigure 19 is similar to the semiconductor device according to the first embodiment shown in, so the repeated configurations are not shown in the figure and will not be described.

[0314] As Figure 35A shown, the semiconductor device according to the present embodiment includes a semiconductor substrate 1211, a first active element 1221, a first wiring layer 1230, an opening 1241a, an interlayer insulating film 1242, a semiconductor substrate 1251, a second active element 1252, a wiring 1261, interlayer insulating films 1256 and 1265, a connection wiring 1266, an electromagnetic shielding layer 1302, and anti-diffusion layers 1301 and 1303. Figure 35B is a schematic diagram showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221. In the present embodiment, the electromagnetic shielding layer 1302 is formed over the entire region of each photoelectric conversion portion included in the pixel, and in a plan view, the electromagnetic shielding layer 1302 covers a plurality of first active elements 1221.

[0315] The electromagnetic shielding layer 1302 is a layer made of a conductive material and is formed to cover at least the first active element 1221 between the first wiring layer 1230 and the interlayer insulating film 1242. The electromagnetic shielding layer 1302 has such a conductivity that makes the potential of the electromagnetic shielding layer 1302 constant, and has a function of preventing the potential fluctuation on the first active element 1221 side from affecting the electromagnetic shielding of the second active element 1252. As the material constituting the electromagnetic shielding layer 1302, a metal layer or a semiconductor layer can be used, and particularly, tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C), or polysilicon (Si) is preferably used to prevent the constituent atoms from diffusing in subsequent steps. The electromagnetic shielding layer 1302 is connected to wirings and the like not shown, preferably, a fixed potential is applied to the electromagnetic shielding layer 1302, and more preferably, a ground potential is applied to the electromagnetic shielding layer 1302.

[0316] The anti-diffusion layers 1301 and 1303 are layers made of a dielectric material formed on the upper and lower surfaces of the electromagnetic shielding layer 1302, and prevent atoms such as oxygen that have been absorbed into the electromagnetic shielding layer 1302 when the electromagnetic shielding layer 1302 is formed from diffusing into the first wiring layer 1230 or the interlayer insulating film 1242. For example, the material constituting the anti-diffusion layers 1301 and 1303 is not limited to any specific type, and SiN can be used.

[0317] Next, the manufacturing method of the semiconductor device according to the present embodiment will be described with reference to FIG. 36. FIG. 36 shows a cross-sectional view of the steps of the manufacturing method of the semiconductor device according to the present embodiment. First, as Figure 36AAs shown in [reference], a first substrate having a first wiring layer 1230 formed on a semiconductor substrate 1211 and including a first active element 1221 was prepared. In addition, as Figure 36B shown in [reference], a substrate was prepared. In this substrate, an interlayer insulating film 1242 was formed on one surface of the semiconductor substrate 1251, and a diffusion prevention layer 1303, an electromagnetic shielding layer 1302, and a diffusion prevention layer 1301 were sequentially stacked on the front surface of the interlayer insulating film 1242. Then, as Figure 36C shown in [reference], the first wiring layer 1230 and the diffusion prevention layer 1301 were joined together. Then, as Figure 36D shown in [reference], a second active element 1252 was formed on the semiconductor substrate 1251, an interlayer insulating film 1256 was formed, an opening 1241a was formed to form a connection wiring 1266, and a wiring 1261 and an interlayer insulating film 1265 were formed.

[0318] In the semiconductor device according to the third embodiment of the present technology, potential fluctuations generated when driving the first active element 1221 are electromagnetically shielded by the electromagnetic shielding layer 1302. As a result, substrate bias fluctuations can be prevented, and noise of the second active element 1252 can be reduced. In particular, from the aspect of reducing noise, it is preferable to fix the electromagnetic shielding layer 1302 to the ground potential. In addition, in the present embodiment, in a semiconductor device that does not include a photoelectric conversion unit in the first substrate, the electromagnetic shielding layer 1302 provided between the first active element 1221 and the second active element 1252 can also prevent substrate bias fluctuations and reduce noise.

[0319] In addition, if tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C), or polysilicon (Si), which is a high melting point material, is used as the material constituting the electromagnetic shielding layer 1302, even if there are steps performed in a high temperature environment such as forming the second active element 1252 after joining the first substrate and the second substrate, the electromagnetic shielding layer 1302 can be prevented from diffusing into the first wiring layer 1230 or the interlayer insulating film 1242.

[0320] (First modification of the third embodiment)

[0321] Figure 37 FIG. [figure number] is a schematic cross-sectional view showing a manufacturing method of a semiconductor device according to a first modification of the third embodiment. In this first modification, as Figure 37 shown in [reference], a first substrate was prepared. In the first substrate, a first wiring layer 1230 including a first active element 1221 was formed on a semiconductor substrate 1211, and a diffusion prevention layer 1301, an electromagnetic shielding layer 1302, and a diffusion prevention layer 1303 were sequentially stacked on the front surface of the first wiring layer 1230. Although Figures 36A to 36DAn example is shown in which the electromagnetic shielding layer 1302 is formed on the second substrate side and bonded, but it may also be formed on the first substrate side as shown in Figure 37 . In this case, the front surface of the interlayer insulating film 1242 on the second substrate side remains exposed, and the interlayer insulating film 1242 and the anti-diffusion layer 1303 are bonded together.

[0322] In this first modification example, the potential fluctuations generated when driving the first active element 1221 are electromagnetically shielded by the electromagnetic shielding layer 1302, and substrate bias fluctuations can be prevented, thereby reducing the noise of the second active element 1252.

[0323] (Second Modification Example of the Third Embodiment)

[0324] Figure 38 FIG. is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a second modification example of the third embodiment. As shown in Figure 38 , in this second modification example, the semiconductor device further has a stacked structure including a first wiring layer 1230 as a third substrate on the interlayer insulating film 1265, an opening 1241a, an interlayer insulating film 1242, a semiconductor substrate 1251, a second active element 1252, a wiring 1261, interlayer insulating films 1256 and 1265, a connection wiring 1266, an electromagnetic shielding layer 1302, and anti-diffusion layers 1301 and 1303.

[0325] As in this modification example, in a stacked structure of three or more substrates, by disposing the electromagnetic shielding layer 1302 between the active elements, the potential fluctuations generated when driving each active element can also be electromagnetically shielded by the electromagnetic shielding layer 1302. Therefore, substrate bias fluctuations can be prevented, and the noise of the active elements can be reduced.

[0326] (Third Modification Example of the Third Embodiment)

[0327] Figure 39 FIG. is a schematic cross-sectional view of the electromagnetic shielding layer 1302 of a semiconductor device according to a third modification example of the third embodiment. The difference between this third modification example and the third embodiment is that the electromagnetic shielding layer 1302 is selectively formed in the region of the photoelectric conversion portion, and an anti-diffusion layer 1304 is also formed around the electromagnetic shielding layer 1302. If the region where the electromagnetic shielding layer 1302 is formed covers at least the first active element 1221, and thus after the electromagnetic shielding layer 1302 is formed on the entire surface of the anti-diffusion layer 1303, the electromagnetic shielding layer 1302 is patterned by using a known photolithography technique, that is sufficient. Thereafter, the portion around the electromagnetic shielding layer 1302 is also filled, thereby simultaneously forming the anti-diffusion layer 1304 and the anti-diffusion layer 1301.

[0328] In this modified example, since the electromagnetic shielding layer 1302 is restrictively formed in a desired region, the regions where wirings can be formed and wirings can be connected inside the first wiring layer 1230 and the interlayer insulating film 1242 can be enlarged, and the degree of freedom in element design can be improved.

[0329] (Fourth Modified Example of the Third Embodiment)

[0330] FIG. 40 shows a schematic cross-sectional view of the electromagnetic shielding layer 1302 of a semiconductor device according to a fourth modified example of the third embodiment. Figure 40A It is a cross-sectional view of a main part of the pixel region, Figure 40B and is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221. As Figure 40A shown, the semiconductor device in this fourth modified example includes a stacked structure similar to that Figure 35A shown in the third embodiment. In this fourth modified example, as Figure 40B shown, an electromagnetic shielding layer 1302 shared by a plurality of photoelectric conversion parts included in pixels is formed, and the electromagnetic shielding layer 1302 commonly covers a plurality of first active elements 1221 included in the photoelectric conversion parts.

[0331] In this modified example, since the electromagnetic shielding layer 1302 is formed at a position outside the region directly above the photoelectric conversion part, it is easier to connect wirings and connecting wirings to the electromagnetic shielding layer 1302, and a ground potential as a fixed potential is applied to the electromagnetic shielding layer 1302. In addition, the electromagnetic shielding layer 1302 can be partially extended to be connected to a ground wiring.

[0332] (Fifth Modified Example of the Third Embodiment)

[0333] FIG. 41 shows a schematic cross-sectional view of the electromagnetic shielding layer 1302 of a semiconductor device according to a fifth modified example of the third embodiment. Figure 41A It is a cross-sectional view of a main part of the pixel region, while Figure 41B is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221. As Figure 41A shown, in the semiconductor device of this fifth modified example, a connection wiring 1311 is formed to penetrate the interlayer insulating films 1242, 1256, and 1265, the semiconductor substrate 1251, and the anti-diffusion layer 1303, and the lower end of the connection wiring 1311 is electrically connected to the electromagnetic shielding layer 1302. In addition, a ground potential as a fixed potential is applied to the electromagnetic shielding layer 1302 via the connection wiring 1311.

[0334] In this modification example, although the planar shape of the electromagnetic shielding layer 1302 is not limited to any specific type, as shown in Figure 41B , an electromagnetic shielding layer 1302 shared by a plurality of photoelectric conversion units can be formed. In addition, the connection wiring 1311 is not limited to being formed as connection wiring that penetrates the uppermost layer and reaches the electromagnetic shielding layer 1302, and can be constituted by wirings each provided in a layer, for example.

[0335] In this modification example, since the connection wiring 1311 is formed in the thickness direction of the semiconductor device and is electrically connected to the electromagnetic shielding layer 1302, a fixed potential can be applied while reducing the area size of the electromagnetic shielding layer 1302.

[0336] (Fourth Embodiment)

[0337] A semiconductor device according to the fourth embodiment of the present technology will be described with reference to Figure 42 and FIG. 43. The semiconductor device according to the fourth embodiment is a back-illuminated solid-state imaging device and receives light incident from the back side (the lower side in Figure 42 ). In other respects, the configuration of the semiconductor device according to the fourth embodiment of the present technology is similar to that of the semiconductor device according to the first embodiment shown in Figure 4 , so the repeated configurations are not shown in the figures and will not be described.

[0338] Figure 42 is a cross-sectional view of a main part of the pixel region of the semiconductor device according to the fourth embodiment of the present technology. As shown in Figure 42 , the semiconductor device according to the present embodiment includes a first substrate 1410, a second substrate 1420, and a third substrate 1430 stacked on top of each other in sequence. In addition, the first substrate 1410, the second substrate 1420, and the third substrate 1430 include: a semiconductor substrate 1411, a photodiode 1441, a floating diffusion portion FD, a transfer transistor TR, a transfer gate TG, an insulating layer 1446, light attenuation portions 1501 and 1502, a semiconductor substrate 1421, a readout circuit 1422, an insulating layer 1452, a wiring layer 1462, a semiconductor substrate 1431, and a logic circuit 1432. The photodiode PD, the transfer transistor TR, and the readout circuit 1422 correspond to the photoelectric conversion unit, the first active element, and the second active element in the present technology, respectively.

[0339] The light attenuation portions 1501 and 1502 are minute structures provided in the insulating layer 1446 and are made of a material having a refractive index higher than that of the material constituting the insulating layer 1446. The shapes of the light attenuation portions 1501 and 1502 are not limited, and Figure 42A case where the shape is substantially cylindrical is shown. The arrangement positions of the optical attenuation portions 1501 and 1502 are between the photodiode PD and the readout circuit 1422. The materials constituting the optical attenuation portions 1501 and 1502 are not limited, and preferably, the optical attenuation portions 1501 and 1502 are made of Si when the surrounding insulating layer 1446 is made of SiO2.

[0340] FIG. 43 shows a schematic diagram showing an enlarged view of the peripheral portion of the optical attenuation portions 1501 and 1502. Figure 43A It is a cross-sectional view showing the path of the light that has entered the optical attenuation portions 1501 and 1502. Figure 43B It is a schematic top view showing an arrangement example of the optical attenuation portions 1501 and 1502. As Figure 43A shown, since the optical attenuation portions 1501 and 1502 are made of a material having a refractive index higher than that of the surrounding material, the light that has entered the optical attenuation portions 1501 and 1502 is totally reflected at the interface between the optical attenuation portions 1501 and 1502 and the insulating layer 1446, as indicated by the arrows in the figure. When the light is repeatedly totally reflected inside the optical attenuation portions 1501 and 1502, the light intensity is attenuated, and the light is absorbed there.

[0341] Generally, in a semiconductor device, when driving the readout circuit 1422 and the logic circuit 1432, in some cases, synchrotron radiation due to hot carriers is generated. Since the intensity of synchrotron radiation is inversely proportional to the square of the distance, noise is generated when synchrotron radiation enters the photodiode PD arranged at a position closer to the region where synchrotron radiation is generated. In the semiconductor device according to the present embodiment, the synchrotron radiation that has entered the optical attenuation portions 1501 and 1502 is attenuated due to repeated reflection inside the optical attenuation portions 1501 and 1502. Thereby, the intensity of synchrotron radiation due to hot carriers reaching the photodiode PD can be reduced, and the noise at the photodiode PD can be reduced. Preferably, the height of the optical attenuation portions 1501 and 1502 is 1.1 μm or more, and preferably, the interval between adjacent optical attenuation portions 1501 and 1502 is 0.38 μm or less. By making the height of the optical attenuation portions 1501 and 1502 1.1 μm or more, even synchrotron radiation that has entered vertically from above and has not been totally reflected can be absorbed by approximately 90% while passing through the optical attenuation portions 1501 and 1502.

[0342] In addition, when the insulating layer 1446 is made of SiO2 and the light attenuation portions 1501 and 1502 are made of Si, since the refractive index of SiO2 is approximately 1.48 and the refractive index of Si is approximately 3.88, the critical angle at the interface between the light attenuation portions 1501 and 1502 and the insulating layer 1446 is approximately 22 degrees. As a result, the region where the light that has entered the light attenuation portions 1501 and 1502 is totally reflected therein can become larger, and the effect of repeated total reflection and optical absorption of light can be enhanced.

[0343] In addition, as Figure 43A and Figure 43B shown, the light attenuation portion 1501 and the light attenuation portion 1502 are formed at different depths of the insulating layer 1446 and are complementarily arranged in a plan view. As a result, synchrotron radiation generated from the readout circuit 1422 or the logic circuit 1432 arranged above enters the light attenuation portion 1501 or the light attenuation portion 1502 during the process of advancing toward the photodiode PD, so that the synchrotron radiation reaching the photodiode PD can be effectively blocked.

[0344] Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 44 to 47. First, as Figure 44A shown, an SOI (Silicon on Insulator) substrate having an insulating layer 1512 made of SiO2 and a semiconductor layer 1511 made of Si formed on one surface of a semiconductor substrate 1421 made of Si is prepared. Next, as Figure 44B shown, an insulating layer 1446 made of SiO2 is deposited on the other surface of the semiconductor substrate 1421 by a CVD method or the like. Next, as Figure 44C shown, a resist mask 1513 is patterned on the insulating layer 1446 by using a photolithography technique, and a recess 1514 is formed in the insulating layer 1446 by etching.

[0345] Next, as Figure 45D shown, the resist mask 1513 is removed, Si is deposited on the insulating layer 1446 by using a CVD technique, and planarization is performed by a CMP technique, and the recess 1514 is filled with the light attenuation portion 1502. Next, as Figure 45E shown, Si is deposited by a CVD technique, and the insulating layer 1446 is also formed on the light attenuation portion 1502. Next, as Figure 45F shown, photolithography and etching, Si deposition and planarization, and further Si deposition are repeatedly performed, and the light attenuation portion 1501 embedded in the insulating layer 1446 is formed.

[0346] Next, asFigure 46G As shown in, the SOI substrate is inverted, as Figure 46H shown in, the insulating layer 1512 and the semiconductor layer 1511 are peeled off, and a readout circuit 1422 is formed in the semiconductor substrate 1421. Next, as Figure 47I shown in, an insulating layer 1452 is formed on the semiconductor substrate 1421 to form a second substrate 1420, and the insulating layer 1446 of the first substrate 1410 that has been separately prepared is bonded to the insulating layer 1446 of the second substrate 1420. Finally, as Figure 47J shown in, the wiring layer 1462 of the third substrate 1430 is bonded to the insulating layer 1452, and a Figure 42 semiconductor device according to the present embodiment as shown in is obtained.

[0347] As shown in FIGS. 44 to 47, since the optical attenuation portions 1501 and 1502 are formed in the insulating layer 1446 through steps of photolithography and etching, and Si deposition and planarization, the optical attenuation portions 1501 and 1502 can be formed at desired positions between the photodiode PD and the readout circuit 1422. In addition, according to need, by repeating the steps of photolithography and etching, and Si deposition and planarization, the optical attenuation portions 1501 and 1502 can have a structure of three or more layers.

[0348] Since the semiconductor device according to the fourth embodiment of the present technology includes the optical attenuation portions 1501 and 1502 made of a material having a refractive index higher than that of the surrounding material between the photodiode PD and the readout circuit 1422, synchrotron radiation generated by hot carriers at the readout circuit 1422 or the logic circuit 1432 can be blocked from reaching the photodiode PD, and noise can be reduced.

[0349] (First modification of the fourth embodiment)

[0350] Figure 48 is a partially enlarged cross-sectional view of a semiconductor device according to the first modification of the fourth embodiment of the present technology. In this modification, the shapes of the optical attenuation portions 1521 and 1522 are different from those in the Figure 43A example shown in. As Figure 48 shown in, in the semiconductor device according to this modification, the optical attenuation portions 1521 and 1522 have a substantially cylindrical shape with raised portions 1521a and 1522a whose bottom surface portions are formed in a conical shape. Examples of the formation method of the optical attenuation portions 1521 and 1522 according to this modification include the following method: when forming the Figure 44C recess 1514 shown in, appropriately changing the shape or film thickness of the resist mask 1513, changing the etching conditions of the recess 1514, etc.

[0351] In the semiconductor device according to this modification example, since the bottom surface portions of the light attenuation portions 1521 and 1522 are formed as convex portions 1521a and 1522a, synchrotron radiation incident from directly above is also totally reflected at the convex portions 1521a and 1522a, and the synchrotron radiation can be effectively attenuated. Here, although a conical shape is shown as an example of the shape of the convex portions 1521a and 1522a, it is sufficient that they are formed to have an angle that allows reflection of synchrotron radiation reaching from above, and they can have a shape including an inclined surface, a minute uneven shape, a mortar-like shape, etc.

[0352] (Second Modification Example of the Fourth Embodiment)

[0353] Figure 49 is a partially enlarged cross-sectional view of a semiconductor device according to a second modification example of the fourth embodiment of the present technology. The difference between this modification example and the example shown in Figure 43A is that the light attenuation portion 1531 is formed as a quantum dot. As shown in Figure 49 , in the semiconductor device according to this modification example, a plurality of light attenuation portions 1531, which are quantum dots made of Si with a minute size, are formed in the insulating layer 1446. The diameter size of the light attenuation portion 1531 is approximately several nanometers to several tens of nanometers, and they are three-dimensionally distributed in the insulating layer 1446. When observing the insulating layer 1446 in a top view, preferably, the surface density of the light attenuation portion 1531 is 1 or more.

[0354] Next, the manufacturing method of the semiconductor device according to this modification example will be described with reference to FIGS. 50 to 52. First, as shown in Figure 50A , an SOI substrate is prepared, which has an insulating layer 1512 made of SiO2 and a semiconductor layer 1511 made of Si formed on one surface of a semiconductor substrate 1421 made of Si. Next, as shown in Figure 50B , an insulating layer 1446 made of SiO2 is deposited on the other surface of the semiconductor substrate 1421 by a CVD method or the like. At this time, as the SiO2 constituting the insulating layer 1446, Si-rich SiO2 is formed. The specific method for forming Si-rich SiO2 is not limited, and for example, an example thereof includes a method in which the ratio of dichlorosilane (SiH2Cl2) gas (DCS gas) to nitrous oxide (N2O) gas is set to 7 to 13:1, and Si-rich SiO2 is formed under a pressure of 0.8 to 1.5 atm. Next, as shown in Figure 50C , the insulating layer 1446 is annealed, and quantum dots made of Si are stacked in the insulating layer 1446 to form the light attenuation portion 1531. The specific annealing conditions are not limited, and for example, annealing is performed in an N2 atmosphere at 1000 °C for one hour.

[0355] Next, as shown in Figure 51D , the SOI substrate is inverted. As shown in Figure 51E , the insulating layer 1512 and the semiconductor layer 1511 are peeled off, and the semiconductor substrate 1421 is scraped and thinned by CMP technology. Next, as shown in Figure 51F , a readout circuit 1422 is formed on the semiconductor substrate 1421, an insulating layer 1452 is formed on the semiconductor substrate 1421 to form a second substrate 1420, and the insulating layer 1446 of the separately prepared first substrate 1410 is bonded to the insulating layer 1446 of the second substrate 1420. Finally, as shown in Figure 52G , the wiring layer 1462 of the third substrate 1430 is bonded to the insulating layer 1452, and a semiconductor device according to this modification example is obtained as shown in Figure 52H .

[0356] In the semiconductor device according to this modification example, since the light attenuation portion 1531 as Si quantum dots having a refractive index higher than that of the surrounding material is provided between the photodiode PD and the readout circuit 1422, synchrotron radiation generated by hot carriers at the readout circuit 1422 or the logic circuit 1432 can also be prevented from reaching the photodiode PD, and noise can be reduced.

[0357] (Third Modification Example of the Fourth Embodiment)

[0358] Figure 53 is a partially enlarged cross-sectional view of a semiconductor device according to the third modification example of the fourth embodiment of the present technology. The difference between this modification example and the example shown in Figure 43A is that the light attenuation portion 1542 is formed in the semiconductor substrate 1421. As shown in Figure 53 , in the semiconductor device according to this modification example, a recess 1541 is formed on the back surface of the semiconductor substrate 1421, and a part of the semiconductor substrate 1421 is arranged to protrude into the insulating layer 1446 as a convex light attenuation portion 1542. In this modification example, Si constituting the semiconductor substrate 1421 forms the light attenuation portion 1542 and protrudes into SiO2 constituting the insulating layer 1446. Therefore, the light attenuation portion 1542 has a refractive index higher than that of the surrounding insulating layer 1446.

[0359] Next, the manufacturing method of the semiconductor device according to this modification example will be described with reference to FIGS. 54 and 55. First, as shown in Figure 54A , a semiconductor substrate 1421 made of Si is prepared. Next, as shown in Figure 54BAs shown in [Fig.], a resist mask is patterned on one surface of the semiconductor substrate 1421 by using photolithography technology, and recesses 1541 and light attenuation portions 1542 are formed in the semiconductor substrate 1421 by etching. Next, as Figure 54C shown in [Fig.], the resist mask is removed, an insulating layer 1446 made of SiO2 is deposited on the semiconductor substrate 1421 by CVD or the like, the recesses 1541 are filled with the insulating layer 1446, and then it is planarized by CMP technology.

[0360] Next, as Figure 55D shown in [Fig.], the semiconductor substrate 1421 is inverted, and as Figure 55E shown in [Fig.], the semiconductor substrate 1421 is scraped and thinned by CMP technology. Next, as Figure 55F shown in [Fig.], the insulating layer 1446 of the first substrate 1410, which has been separately prepared, is bonded to the insulating layer 1446 of the second substrate 1420. The description of the formation of the readout circuit 1422 and the bonding to the third substrate 1430 is omitted.

[0361] In the semiconductor device according to this modification example, since synchrotron radiation is also totally reflected at the interface between the insulating layer 1446 and the convex light attenuation portion 1542 formed in the semiconductor substrate 1421, and the synchrotron radiation is attenuated in the light attenuation portion 1542, synchrotron radiation generated by hot carriers at the readout circuit 1422 or the logic circuit 1432 can be prevented from reaching the photodiode PD, and noise can be reduced.

[0362] (Fourth Modification Example of the Fourth Embodiment)

[0363] Figure 56 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modification example of the fourth embodiment of the present technology. This modification example is different from the example Figure 42 shown in [Fig.] in that only one layer of light attenuation portion 1501 is formed in the insulating layer 1446. In this modification example, by adopting light attenuation portions 1501 with appropriate sizes and arrangements, synchrotron radiation generated by hot carriers at the readout circuit 1422 or the logic circuit 1432 can also be prevented from reaching the photodiode PD, and noise can be reduced.

[0364] (Fifth Modification Example of the Fourth Embodiment)

[0365] Figure 57 is a partially enlarged cross-sectional view of a semiconductor device according to a fifth modification example of the fourth embodiment of the present technology. This modification example is different from Figure 42The difference from the example shown in is that the light attenuation portion 1501 formed in the insulating layer 1446 and the convex light attenuation portion 1542 formed in the semiconductor substrate 1421 are used in combination. In this modified example, by adopting the light attenuation portion 1501 and the light attenuation portion 1542 with appropriate sizes and arrangements, synchrotron radiation generated by hot carriers at the readout circuit 1422 or the logic circuit 1432 can also be prevented from reaching the photodiode PD, and noise can be reduced.

[0366] (Fifth Embodiment)

[0367] By using Figure 58 and Figure 59 a semiconductor device according to the fifth embodiment of the present technology will be described. The semiconductor device according to the fifth embodiment is a back-illuminated solid-state imaging device and receives light incident from the back side ( Figure 58 the lower side in ). In other respects, the configuration of the semiconductor device according to the fifth embodiment of the present technology is similar to that of the semiconductor device according to the first embodiment shown in Figure 19 , so the repeated configurations are not shown in the figures and will not be described.

[0368] Figure 58 is a partially enlarged cross-sectional view of the semiconductor device according to the fifth embodiment of the present technology. Figure 59 is a schematic diagram showing the positional relationship between the antireflection portion 1701 and the connection wiring 1666. As shown in Figure 58 and Figure 59 , the semiconductor device according to this embodiment includes Si substrates 1611 and 1651, an element isolation portion 1612, a first wiring layer 1630, interlayer insulating films 1656 and 1665, wirings 1661, connection wirings 1666, and an antireflection portion 1701. As mentioned in the first embodiment, the Si substrate 1651 includes the second active element in the present technology, and the Si substrate 1611 includes the photoelectric conversion portion in the present technology, but they are not shown in Figure 58 .

[0369] The antireflection portion 1701 is disposed at least between the second active element in the Si substrate 1651 and the photoelectric conversion portion in the Si substrate 1611 and has a function of reducing the reflectivity of light on the back surface of the Si substrate 1651. In the example shown in Figure 58 , the antireflection portion 1701 is provided to cover the entire back surface of the Si substrate 1651 ( Figure 58contacts the lower side) and is formed as a dielectric film having an intermediate refractive index between the refractive index of silicon dioxide (SiO2), which is an insulating material included in the first wiring layer 1630, and the refractive index of Si that constitutes the Si substrate 1651. For example, examples of the material that constitutes the antireflection portion 1701 include silicon nitride (SiN).

[0370] Next, by using Figure 60 and Figure 61 A method for manufacturing a semiconductor device according to the present embodiment will be described. First, as Figure 60 shown, a first substrate including a Si substrate 1611, an element isolation portion 1612, and a first wiring layer 1630 is prepared. In addition, a SiN film that constitutes the antireflection portion 1701 is formed on the back surface of the Si substrate 1651 by using a CVD technique or the like, and the antireflection portion 1701 and the first wiring layer 1630 are bonded together. Next, as Figure 61 shown, the front surface of the Si substrate 1651 is scraped and thinned, and a recess 1702 is formed downward in the middle portion of the first wiring layer 1630 by using a photolithography technique. Thereafter, the recess 1702 and the front surface of the substrate 1651 are filled with an interlayer insulating film 1656, and an interlayer insulating film 1665, wirings 1661, connecting wirings 1666, etc. are formed to obtain a semiconductor device according to the present embodiment. It should be noted that in Figure 60 step, the antireflection portion 1701 may not be provided on the Si substrate 1651 side, but on the upper surface side of the first wiring layer 1630.

[0371] In the case where the antireflection portion 1701 is not provided, since the refractive index difference between the SiO2 included in the first wiring layer 1630 and the Si substrate 1651 is large, total reflection at the interface between them is more likely to occur. Since there is a distance between the Si substrate 1611 and the Si substrate 1651, there is a possibility that light incident on the photoelectric conversion portion of the Si substrate 1611 and reflected by the Si substrate 1651 passes through the element isolation portion 1612 and enters another photoelectric conversion portion. The light reflected from the back surface of the Si substrate 1651 and incident on the photoelectric conversion portion is converted into an electrical signal by the photoelectric conversion portion, so noise is inevitably generated.

[0372] In the present embodiment, since the antireflection portion 1701 is provided between the second active element and the photoelectric conversion portion, and the antireflection portion 1701 is made of SiN having an intermediate refractive index of Si, the refractive index difference between SiN and Si becomes smaller compared to the case where the antireflection portion 1701 is not provided, total reflection on the Si substrate 1651 can be suppressed, and noise of the photoelectric conversion portion can be reduced.

[0373] (First Variation of the Fifth Embodiment)

[0374] Figure 62 is a partially enlarged cross-sectional view of a semiconductor device according to the first variation of the fifth embodiment of the present technology. The difference between this variation and the example shown in Figure 58 is that the antireflection portion 1711 is formed in a region larger than the Si substrate. As shown in Figure 62 in this variation, the antireflection portion 1711 is provided over the entire area of the semiconductor device, and the connection wiring 1666 is provided to penetrate through an opening formed in the antireflection portion 1711.

[0375] Figure 63 shows a manufacturing method of the semiconductor device according to this variation. First, similar to Figure 60 , a first substrate including an Si substrate 1611, an element isolation portion 1612, and a first wiring layer 1630 is prepared. In addition, an SiN film constituting the antireflection portion 1711 is formed on the back surface of the Si substrate 1651 by using a CVD technique or the like, and the antireflection portion 1711 is bonded to the first wiring layer 1630. Next, as shown in Figure 63 , the front surface of the Si substrate 1651 is scraped and thinned, and a concave portion 1702 is formed downward on the front surface of the antireflection portion 1711 by using a photolithography technique. Thereafter, the concave portion 1702 and the front surface of the Si substrate 1651 are filled with an interlayer insulating film 1656, and the interlayer insulating film 1665, the wiring 1661, the connection wiring 1666, etc. are formed to obtain the semiconductor device according to this variation.

[0376] In addition, in this variation, since the antireflection portion 1711 is provided between the second active element and the photoelectric conversion portion, and the antireflection portion 1711 is provided in a region larger than the Si substrate 1651, total reflection on the Si substrate 1651 can also be suppressed, and noise of the photoelectric conversion portion can be reduced.

[0377] (Second Variation of the Fifth Embodiment)

[0378] Figure 64 is a partially enlarged cross-sectional view of a semiconductor device according to the second variation of the fifth embodiment of the present technology. The difference between this variation and the example shown in Figure 62 is that, in addition to the antireflection portion 1721, an antireflection portion 1722 is also provided on the side surface of the Si substrate 1651. As shown in Figure 64 in this variation, the antireflection portion 1721 is provided over the entire area of the semiconductor device, and the connection wiring 1666 is provided to penetrate through an opening formed in the antireflection portion 1721. In addition, the antireflection portion 1722 is provided to cover the side surface of the Si substrate 1651.

[0379] Figure 65 shows a method of manufacturing a semiconductor device according to this modification. First, similar to Figure 60 , a first substrate including a Si substrate 1611, an element isolation part 1612, and a first wiring layer 1630 is prepared. In addition, a SiN film constituting an antireflection part 1721 is formed on the back surface of the Si substrate 1651 by using a CVD technique or the like, and the antireflection part 1721 and the first wiring layer 1630 are bonded together. Next, as shown in Figure 61 , the front surface of the Si substrate 1651 is scraped and thinned, a concave part 1702 is formed downward in the middle part of the first wiring layer 1630 by using a photolithography technique, and the front surface of the Si substrate 1651 is oxidized to form a SiO2 film. Next, as shown in Figure 65 , a SiN film is formed, a SiN film 1723 is formed on the SiO2 film on the front surface of the Si substrate 1651, and an antireflection part 1722 is also provided on the side surface of the Si substrate 1651 exposed inside the concave part 1702. Finally, the SiN film 1723 and the concave part 1702 are filled with an interlayer insulating film 1656, the interlayer insulating film 1656, the SiN film 1723, and the SiO2 film are polished until the front surface of the Si substrate 1651 is exposed, and an interlayer insulating film 1665, a wiring 1661, a connecting wiring 1666, etc. are formed to obtain a semiconductor device according to this embodiment.

[0380] In this modification, since the antireflection part 1721 is provided in a region larger than the Si substrate 1651 between the second active element and the photoelectric conversion part, and the antireflection part 1722 is provided on the side surface of the Si substrate 1651, total reflection on the Si substrate 1651 can also be suppressed, and the noise of the photoelectric conversion part can be reduced.

[0381] (Third modification of the fifth embodiment)

[0382] Figure 66 is a partial enlarged cross-sectional view of a semiconductor device according to the third modification of the fifth embodiment of the present technology. The difference between this modification and the example shown in Figure 58 is that the antireflection part 1731 formed on the back surface of the Si substrate 1651 has a multilayer structure. As shown in Figure 66 , in the semiconductor device according to this modification, the antireflection part 1731 is provided to cover the entire back surface of the Si substrate 1651 ( Figure 66contacts the lower side) and has a structure formed by laminating a plurality of dielectric layers having different refractive indexes on each other. The number of dielectric films constituting the antireflection portion 1731 is not limited to two layers and may be three or more layers. The dielectric material included in the antireflection portion 1731 is a material having a refractive index higher than that of SiO2 included in the first wiring layer 1630 but lower than that of Si of the Si substrate 1651, and is laminated so that the refractive index gradually decreases from the Si substrate 1651 side to the first wiring layer 1630. The specific material constituting the antireflection portion 1731 is not limited, and for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), aluminum oxide (Al2O3), hafnium oxide (HfO2), etc. can be used.

[0383] In this modification, since the antireflection portion 1731 is provided between the second active element and the photoelectric conversion portion and the refractive index gradually decreases from the Si substrate 1651 to the first wiring layer 1630, total reflection on the Si substrate 1651 can also be suppressed, and the noise of the photoelectric conversion portion can be reduced.

[0384] (Fourth modification of the fifth embodiment)

[0385] Figure 67 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modification of the fifth embodiment of the present technology. The difference between this modification and Figure 58 the example shown in is that an intermediate film 1732 having different refractive indexes is provided between the back surface of the Si substrate 1651 and the antireflection portion 1731. The intermediate film 1732 is made of a material having a refractive index lower than that of the material constituting the antireflection portion 1731 and is formed into a film thinner than the film thickness of the antireflection portion 1731. The film thickness of the intermediate film 1732 is not limited to any specific thickness, and if it has a film thickness of about 1 nm to several nanometers, even if the intermediate film 1732 has a refractive index lower than that of the antireflection portion 1731, the influence on the antireflection effect of light becomes smaller.

[0386] In this modification, since the antireflection portion 1731 is provided between the second active element and the photoelectric conversion portion, even if the intermediate film 1732 having different refractive indexes is provided between the antireflection portion 1731 and the Si substrate 1651, total reflection on the Si substrate 1651 can be suppressed, and the noise of the photoelectric conversion portion can be reduced.

[0387] (Fifth modification of the fifth embodiment)

[0388] Figure 68 is a partially enlarged cross-sectional view of a semiconductor device according to a fifth modification of the fifth embodiment of the present technology. The difference between this modification and Figure 58The difference in the example shown in [Fig.] is that the antireflection portion 1741 provided on the back surface of the Si substrate 1651 has an uneven structure. The antireflection portion 1741 is formed as a dielectric film having a refractive index that is an intermediate refractive index between the refractive index of SiO2, which is an insulating material included in the first wiring layer 1630, and the refractive index of Si that constitutes the Si substrate 1651, and on which a plurality of minute uneven portions are formed.

[0389] In the semiconductor device according to this modification example, when the size of the uneven structure of the antireflection portion 1741 is on the order of microns, which is larger than the wavelength of light, since the light reaching the antireflection portion 1741 is diffusely reflected, the light is reflected from the back surface of the Si substrate 1651, the amount of light entering the photoelectric conversion portion can be reduced, and the noise can be reduced. In addition, when the size of the uneven structure is on the order of nanometers, which is smaller than the wavelength of light, a moth-eye structure in which the refractive index gradually changes is formed, and thus the reflection of light from the back surface of the Si substrate 1651 can be suppressed, and the noise caused by the light incident on the photoelectric conversion portion can be reduced.

[0390] (Other embodiments)

[0391] As described above, the present technology has been described with reference to the first to fifth embodiments, and the statements and drawings that are part of this disclosure should not be construed as limiting the present technology. According to this disclosure, various alternative embodiments, implementation examples, and operation techniques will be apparent to those skilled in the art.

[0392] For example, the semiconductor device according to the first to fifth embodiments of the present technology can be applied to any type of electronic device having a photographing function, such as a camera system such as a digital camera or a video camera, or a mobile phone having a photographing function. For example, it can be applied to Figure 69 the electronic device (camera) shown in [Fig.]. For example, Figure 69 the electronic device shown in [Fig.] is a video camera that can capture still images or moving images, and includes a semiconductor device 2200, an optical system (optical lens) 2201, a shutter device 2202, a drive portion 2204 that drives the semiconductor device 2200 and the shutter device 2202, and a signal processing portion 2203.

[0393] The semiconductor device according to the first to fifth embodiments can be applied as the semiconductor device 2200. The optical system 2201 guides the image light (incident light) from the subject to the pixel region 2001 of the semiconductor device 2200. The optical system 2201 may include a plurality of optical lenses. The shutter device 2202 controls the light irradiation period and the light shielding period of the light directed toward the semiconductor device 2200. The driving unit 2204 controls the transfer operation of the semiconductor device 2200 and the shutter operation of the shutter device 2202. The signal processing unit 2203 performs various signal processes on the signal output from the semiconductor device 2200. The video signal after the signal process is stored in a storage medium such as a memory or output to a monitor or the like.

[0394] In the imaging device according to the embodiment of the present technology, since the electrical connection is established between the substrates according to the integration degree of the substrates, the structure for electrically connecting the substrates necessarily does not require an increase in the chip size, suppression of miniaturization of the area size per pixel, etc. Therefore, an imaging device having a three-layer structure can be provided, which has a chip size equal to that of a conventional chip and does not suppress miniaturization of the area size per pixel. It should be noted that the effects of the present technology are not necessarily limited to the effects described here, and may be any of the effects described in this specification.

[0395] Those skilled in the art can conceive of various modifications, combinations, sub-combinations, and changes according to requirements in terms of design and other factors, and it should be understood that they are included within the scope of the appended claims and their equivalents.

[0396] In addition, although a back-illuminated CMOS image sensor is shown as an example of the semiconductor device according to the first to fifth embodiments of the present technology, the semiconductor device according to the first to fifth embodiments of the present technology can also be applied to solid-state imaging devices such as back-illuminated CCD image sensors. Further, for example, the semiconductor device of the present technology can also be applied to various semiconductor devices other than solid-state imaging devices, such as a storage device using a semiconductor, a display device using a semiconductor, a sensor device using a semiconductor, or a computing device using a semiconductor.

[0397] For example, the semiconductor device of the present technology can be applied to the configuration of a semiconductor memory device such as a DRAM that has a memory cell instead of a pixel with a photoelectric conversion section as a unit cell. Although current DRAMs include single-transistor type memory cells (unit cells), by adopting the stacked structure of the present technology, a DRAM with a three-transistor type memory cell (unit cell) used in the 1970s can be configured without reducing the integration density. Further, by forming the above-mentioned shielding structure between the upper DRAM and the lower DRAM of a three-dimensional structure semiconductor memory device formed by stacking multiple DRAMs with single-transistor type memory cells (unit cells), thermal, optical, and electromagnetic shielding can be formed between the upper DRAM and the lower DRAM. Therefore, in operations involving power concentration in high-speed operation DRAMs, etc., noise, operation errors, etc. can be prevented.

[0398] In addition, in the semiconductor device according to the first to fifth embodiments of the present technology, although negative charges (electrons) are used as signal charges in the illustrative examples, the present technology can also be applied to cases where positive charges (holes) are used as signal charges. In the case where holes are used as signal charges, it is sufficient if the p-type region and the n-type region are configured in the opposite arrangement.

[0399] (Sixth Embodiment)

[0400] Hereinafter, the imaging device 1 according to the sixth embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that the description will be made in the following order.

[0401] 1. Embodiment (Imaging device with a stacked structure of three substrates)

[0402] 2. First Modified Example (Example 1 of planar configuration)

[0403] 3. Second Modified Example (Example 2 of planar configuration)

[0404] 4. Third Modified Example (Example 3 of planar configuration)

[0405] 5. Fourth Modified Example (Example in which a contact portion between substrates is included in the central portion of the pixel array section)

[0406] 6. Fifth Modified Example (Example in which a planar type transfer transistor is provided)

[0407] 7. Sixth Modified Example (Example in which one pixel circuit is connected to one pixel)

[0408] 8. Seventh Modified Example (Configuration example of pixel separation section)

[0409] <1. Embodiment>

[0410] [Functional Configuration of the Image Capture Device 1]

[0411] Figure 70 : is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1 ) according to an embodiment of the present disclosure.

[0412] For example, Figure 70 The imaging device 1 in the embodiment includes an input section 510A, a row driving section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0413] The pixel array section 540 includes pixels 541 that are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and is repeatedly arranged in an array in the row direction and the column direction. It should be noted that in this specification, for convenience, the row direction and the column direction orthogonal to the row direction are sometimes referred to as the "H direction" and the "V direction", respectively. Figure 70 In the example of FIG. 5 , one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). The pixels 541A, 541B, 541C, and 541D each include a photodiode PD (described below). Figure 73 Each pixel sharing unit 539 shares a pixel circuit (described below). Figure 73 210 in the pixel array unit). In other words, each group of four pixels (pixels 541A, 541B, 541C and 541D) has a pixel circuit (pixel circuit 210 described below). By operating the pixel circuit in a time-division manner, the pixel signals of each pixel 541A, 541B, 541C and 541D are read out in sequence. For example, pixels 541A, 541B, 541C and 541D are arranged in two rows × two columns. The pixel array unit 540 is provided with a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 as well as pixels 541A, 541B, 541C and 541D. The row drive signal line 542 drives the pixels 541 that are arranged side by side in the row direction in the pixel array unit 540 and included in each of the plurality of pixel sharing units 539. The row drive signal line 542 drives the pixels that are arranged side by side in the row direction in the pixel sharing unit 539. As described below with reference to Figure 73Specifically, each pixel sharing unit 539 is provided with a plurality of transistors. To drive each of the plurality of transistors, one pixel sharing unit 539 is connected to a plurality of row driving signal lines 542. The pixel sharing unit 539 is connected to a vertical signal line (column readout line) 543. Pixel signals are read out from respective pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 through the vertical signal line (column readout line) 543.

[0414] For example, the row driving unit 520 includes a row addressing control unit that determines the position of the row for driving the pixels, that is, a row decoding unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0415] For example, the column signal processing unit 550 includes a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539). The column signal processing unit 550 may include an amplification circuit unit that amplifies the signal read out from the pixel sharing unit 539 through the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. For example, the noise processing unit removes the system noise level from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0416] For example, the column signal processing unit 550 includes an analog-to-digital converter (ADC). The analog-to-digital converter converts the signal read out from the pixel sharing unit 539 or the analog signal that has undergone the above-mentioned noise processing into a digital signal. For example, the ADC includes a comparator unit and a counter unit. The comparator unit compares the analog signal to be converted with a reference signal as a comparison object. The counter unit measures the time until the comparison result in the comparator unit is inverted. The column signal processing unit 550 may include a horizontal scanning circuit unit that controls the scanning of the readout column.

[0417] The timing control unit 530 supplies signals for controlling the timing to the row driving unit 520 and the column signal processing unit 550 based on a reference clock signal and a timing control signal input to the device.

[0418] The image signal processing unit 560 is a circuit that performs various types of signal processing on the data obtained as a result of photoelectric conversion, that is, the data obtained as a result of the imaging operation in the imaging device 1. For example, the image signal processing unit 560 includes an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0419] An example of the signal processing performed in the image signal processing unit 560 is tone curve correction processing, in which the gray level is increased when the captured data after AD conversion is data obtained by shooting a dark subject, and the gray level is decreased when the captured data after AD conversion is data obtained by shooting a bright subject. In this case, regarding which tone curve to use for correcting the gray level of the captured data, it is desirable to pre-store the characteristic data of the tone curve in the data holding unit of the image signal processing unit 560.

[0420] For example, the input unit 510A inputs the above-mentioned reference clock signal, timing control signal, characteristic data, etc. into the imaging device 1 from outside the device. For example, the timing control signal is a vertical synchronization signal, a horizontal synchronization signal, etc. For example, the characteristic data will be stored in the data holding unit of the image signal processing unit 560. For example, the input unit 510A includes an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0421] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 inputs the signal input to the input terminal 511 into the imaging device 1. The input amplitude changing unit 513 changes the amplitude of the signal input through the input circuit unit 512 to an amplitude that is easy to use inside the imaging device 1. The input data conversion circuit unit 514 changes the order of the data array of the input data. For example, the input data conversion circuit unit 514 includes a serial-parallel conversion circuit. The serial-parallel conversion circuit converts the serial signal received as the input data into a parallel signal. It should be noted that in the input unit 510A, the input amplitude changing unit 513 and the input data conversion circuit unit 514 can be omitted. Based on the power supply supplied to the imaging device 1 from the outside, the power supply unit supplies power with various voltages set to be required inside the imaging device 1.

[0422] When the imaging device 1 is connected to an external storage device, the input unit 510A may include a memory interface circuit for receiving data from the external storage device. For example, the external storage device is a flash memory, SRAM, DRAM, etc.

[0423] The output unit 510B outputs the image data to the outside of the device. For example, the image data is the image data captured by the imaging device 1, the image data that has undergone the signal processing of the image signal processing unit 560, etc. For example, the output unit 510B includes an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0424] For example, the output data conversion circuit section 515 includes a parallel-to-serial conversion circuit, and the output data conversion circuit section 515 converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude change section 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude is easy to use in an external device connected to the outside of the imaging device 1. The output circuit section 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit section 517 drives the wiring outside the imaging device 1 connected to the output terminal 518. The output terminal 518 outputs data from the imaging device 1 to the outside of the device. In the output section 510B, the output data conversion circuit section 515 and the output amplitude change section 516 can be omitted.

[0425] When the imaging device 1 is connected to an external storage device, the output section 510B may include a memory interface circuit that outputs data to the external storage device. For example, the external storage device is a flash memory, SRAM, DRAM, etc.

[0426] [Schematic configuration of the imaging device 1]

[0427] Figure 71 and Figure 72 Examples of the schematic configuration of the imaging device 1 are shown respectively. The imaging device 1 includes three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). Figure 71 The planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300 is schematically shown, and Figure 72 The cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on each other is schematically shown. Figure 72 Corresponding to along Figure 71The cross-section taken along the line III-III’ shown. The imaging device 1 is an imaging device having a three-dimensional structure in which three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) are joined together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. In this document, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is referred to as the wiring layer (100T, 200T, and 300T) provided in each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked on top of each other in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order in the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described below. Figure 72 The arrows shown in indicate the incident direction of the light L incident on the imaging device 1. In this specification, for convenience, in the subsequent cross-sectional views, the light incident side in the imaging device 1 is sometimes referred to as the “lower part”, the “lower side”, or the “below”, and the side opposite to the light incident side is sometimes referred to as the “upper part”, the “upper side”, or the “above”. In addition, in this specification, for convenience, for a substrate including a semiconductor layer and a wiring layer, the side of the wiring layer is sometimes referred to as the front surface, and the side of the semiconductor layer is sometimes referred to as the back surface. It should be noted that the descriptions in the specification are not limited to the above naming. For example, the imaging device 1 is a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 including a photodiode.

[0428] The pixel array unit 540 and the pixel sharing unit 539 included in the pixel array unit 540 are both constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 includes a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each pixel 541 includes a photodiode (the photodiode PD described below) and a transfer transistor (the transfer transistor TR described below). The second substrate 200 includes a pixel circuit (the pixel circuit 210 described below) included in the pixel sharing unit 539. Each pixel circuit reads out a pixel signal transmitted from the photodiode of the pixel 541A, 541B, 541C, or 541D through the transfer transistor, or resets the photodiode. In addition to such pixel circuits, the second substrate 200 also includes a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes a power supply line 544 extending in the row direction. For example, the third substrate 300 includes an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. For example, the row driving unit 520 is provided in a region that partially overlaps with the pixel array unit 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driving unit 520 is provided in a region that partially overlaps with a portion near the end of the pixel array unit 540 in the H direction in the stacking direction ( Figure 71 ). For example, the column signal processing unit 550 is provided in a region that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is provided in a region that partially overlaps with a portion near the end of the pixel array unit 540 in the V direction in the stacking direction ( Figure 71 ). Although not shown, the input unit 510A and the output unit 510B may be arranged in a portion other than the third substrate 300, and for example, may be arranged in the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be provided on the back surface (light incident surface) side of the first substrate 100. It should be noted that the pixel circuits provided in the second substrate 200 are also referred to as pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term "pixel circuit" is used.

[0429] For example, the first substrate 100 and the second substrate 200 are connected by a through electrode (the Figure 75The through electrodes 120E and 121E) in [are] electrically connected to each other. For example, the second substrate 200 and the third substrate 300 are electrically connected to each other through the contact portions 201, 202, 301, and 302. The second substrate 200 is provided with the contact portions 201 and 202, and the third substrate 300 is provided with the contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array portion 540 and the row driving portion 520 in the stacking direction ( Figure 72 ). In other words, for example, the contact regions 201R and 301R are provided in a region where the row driving portion 520 (the third substrate 300) and the pixel array portion 540 (the second substrate 200) overlap each other in the stacking direction, or in a region near this region. For example, the contact regions 201R and 301R are arranged at the ends of such a region in the H direction ( Figure 71 ). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the row driving portion 520, specifically, the end of the row driving portion 520 in the H direction ( Figure 71 and Figure 72 ). For example, the contact portions 201 and 301 connect the row driving portion 520 provided in the third substrate 300 and the row driving signal line 542 provided in the second substrate 200 to each other. For example, the contact portions 201 and 301 can connect the input portion 510A provided in the third substrate 300 to the power supply line 544 and the reference potential line (the reference potential line VSS described below). The contact regions 202R and 302R are provided between the pixel array portion 540 and the column signal processing portion 550 in the stacking direction ( Figure 72 ). In other words, for example, the contact regions 202R and 302R are provided in a region where the column signal processing portion 550 (the third substrate 300) and the pixel array portion 540 (the second substrate 200) overlap each other in the stacking direction, or in a region near this region. The contact regions 202R and 302R are arranged at the ends of such a region in the V direction ( Figure 71 ). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the column signal processing portion 550, specifically, the end of the column signal processing portion 550 in the V direction ( Figure 71 and Figure 72)。For example, the contact portions 202 and 302 connect the pixel signals (signals corresponding to the amount of electric charge generated as a result of photoelectric conversion by the photodiodes) output from each of the plurality of pixel sharing units 539 included in the pixel array portion 540 to the column signal processing portion 550 provided in the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0430] Figure 72 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other through the wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other. Specifically, the contact portions 201, 202, 301, and 302 are respectively formed using electrodes made of a conductive material. For example, the conductive material is formed using a metal material such as copper (Cu), aluminum (Al), and gold (Au). For example, the contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate to each other by directly bonding the wiring formed as an electrode, which can input signals to and / or output signals from the second substrate 200 and the third substrate 300.

[0431] An electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other can be provided at a desired position. For example, as Figure 72 shown as the contact regions 201R, 202R, 301R, and 302R, the electrical connection portion can be provided in a region that overlaps the pixel array portion 540 in the stacking direction. In addition, the electrical connection portion can be provided in a region that does not overlap the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion can be provided in a region that overlaps the peripheral portion arranged outside the pixel array portion 540 in the stacking direction.

[0432] For example, the first substrate 100 and the second substrate 200 include connection hole portions Hl and H2. The connection hole portions H1 and H2 penetrate the first substrate 100 and the second substrate 200 ( Figure 72 ). The connection hole portions H1 and H2 are provided outside the pixel array portion 540 (or a portion that overlaps the pixel array portion 540) ( Figure 71)。For example, the connection hole portion H1 is disposed outside the pixel array portion 540 in the H direction, and the connection hole portion H2 is disposed outside the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input portion 510A provided in the third substrate 300, and the connection hole portion H2 reaches the output portion 510B provided in the third substrate 300. The connection hole portions H1 and H2 may be hollow or may at least partially include a conductive material. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which the electrode formed as the input portion 510A and / or the output portion 510B is connected to the conductive material provided in the connection hole portions H1 and H2. The conductive material provided in the connection hole portions H1 and H2 may be embedded in a part or all of the connection hole portions H1 and H2, or the conductive material may be formed on the side walls of the connection hole portions H1 and H2.

[0433] It should be noted that Figure 72 The structure in which the input portion 510A and the output portion 510B are provided in the third substrate 300 is shown, but this is not restrictive. For example, by adopting a configuration in which the signal of the third substrate 300 is transmitted to the second substrate 200 through the wiring layers 200T and 300T, the input portion 510A and / or the output portion 510B can be provided in the second substrate 200. Similarly, by adopting a configuration in which the signal of the second substrate 200 is transmitted to the first substrate 100 through the wiring layers 100T and 200T, the input portion 510A and / or the output portion 510B can be provided in the first substrate 100.

[0434] Figure 73 is an equivalent circuit diagram showing a configuration example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 73 Four pixels 541 are shown, namely, pixels 541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. For example, the pixel circuit 210 includes four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates one pixel circuit 210 in a time-division manner to sequentially output the pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. A mode in which one pixel circuit 210 is connected to a plurality of pixels 541 and the pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time-division manner is called a mode of "a plurality of pixels 541 sharing one pixel circuit 210".

[0435] Pixels 541A, 541B, 541C, and 541D include components common to each other. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, the identification number "1" is assigned to the end of the reference numeral of the component of pixel 541A, the identification number "2" is assigned to the end of the reference numeral of the component of pixel 541B, the identification number "3" is assigned to the end of the reference numeral of the component of pixel 541C, and the identification number "4" is assigned to the end of the reference numeral of the component of pixel 541D. In the case where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the ends of the reference numerals of the components of each of pixels 541A, 541B, 541C, and 541D are omitted.

[0436] For example, pixels 541A, 541B, 541C, and 541D respectively include a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light to generate charges corresponding to the amount of received light. For example, the transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR4) is an n-type CMOS (complementary metal oxide semiconductor) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion section FD, and the gate is electrically connected to a drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 (see Figure 70 ) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charges generated by the photodiode PD to the floating diffusion section FD. The floating diffusion section FD (floating diffusion sections FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. Each floating diffusion section FD is a charge holding device that temporarily holds the charges transferred from the photodiode PD and a charge-voltage conversion device that generates a voltage corresponding to the amount of charge.

[0437] Four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in a pixel sharing unit 539 are electrically connected to each other, and are electrically connected to the gate of an amplification transistor AMP and the source of an FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of a reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of a selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to a pixel sharing unit 539.

[0438] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. For example, the gate of the transfer transistor TR (transfer gate TG) includes a so-called vertical electrode and is arranged as described below Figure 75 shown, to extend from the front surface of the semiconductor layer (the semiconductor layer 100S described below Figure 75 ) to the depth reaching the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a voltage signal corresponding to the level of the charge held by the floating diffusion FD as a pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 through the selection transistor SEL. The amplification transistor AMP and a load circuit unit (see Figure 70 ) connected to the vertical signal line 543 in the column signal processing unit 550 are configured as a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 through the vertical signal line 543. For example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are N-type CMOS transistors.

[0439] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion section FD. Generally, when shooting in the dark, the pixel signal is small. Based on Q = CV, when performing charge-voltage conversion, if the capacitance of the floating diffusion section FD (FD capacitance C) is large, then the V when converted to voltage by the amplification transistor AMP is inevitably small. On the other hand, the pixel signal becomes large in the bright area; therefore, if the FD capacitance C is not large, it is impossible for the floating diffusion section FD to fully receive the charge of the photodiode PD. In addition, the FD capacitance C needs to be large to prevent V from becoming too large when converted to voltage at the amplification transistor AMP (in other words, to make V smaller). Considering these, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance for the FD conversion gain switching transistor FDG increases, resulting in an increase in the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes smaller. In this way, performing the ON / OFF switching of the FD conversion gain switching transistor FDG can make the FD capacitance C variable, thereby enabling the switching of the conversion efficiency. For example, the FD conversion gain switching transistor FDG is an N-type CMOS transistor.

[0440] It should be noted that in another possible configuration, the FD conversion gain switching transistor FDG is not provided. At this time, for example, the pixel circuit 210 includes three transistors, namely, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST. For example, the pixel circuit 210 includes at least one of pixel transistors such as the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0441] The selection transistor SEL can be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see Figure 70 ). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that although not shown, the number of pixels 541 sharing one pixel circuit 210 may not be 4. For example, two or eight pixels 541 can share one pixel circuit 210.

[0442] Figure 74An example of the connection between a plurality of pixel sharing units 539 and the vertical signal lines 543 is shown. For example, four pixel sharing units 539 arranged side by side in the column direction are divided into four groups, and the vertical signal lines 543 are connected to each of the four groups. For ease of explanation, Figure 74 An example is shown in which each of the four groups includes one pixel sharing unit 539; however, each of the four groups may include a plurality of pixel sharing units 539. In this way, in the imaging device 1, a plurality of pixel sharing units 539 arranged side by side in the column direction can be divided into groups each including one or more pixel sharing units 539. For example, the vertical signal lines 543 and the column signal processing unit 550 are connected to each group, which enables pixel signals to be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged side by side in the column direction. At this time, pixel signals are sequentially read out from the plurality of pixel sharing units 539 connected to one vertical signal line 543 in a time-division manner.

[0443] [Specific Configuration of Imaging Device 1]

[0444] Figure 75 An example of the cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 in the vertical direction with respect to the main surface is shown. For ease of understanding, Figure 75 The positional relationship of the components is schematically shown and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further includes an optical receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the optical receiving lens 401 and the first substrate 100. For example, an optical receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, the imaging device 1 is a back-illuminated imaging device. The imaging device 1 includes a pixel array unit 540 arranged in the central portion and a peripheral portion 540B arranged outside the pixel array unit 540.

[0445] The first substrate 100 sequentially includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T from the side of the optical receiving lens 401. For example, the semiconductor layer 100S is composed of a silicon substrate. For example, the semiconductor layer 100S includes a p-well layer 115 in a part of its front surface (the surface on the side of the wiring layer 100T) and its vicinity, and includes an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0446] Figure 76A Shows an example of the planar configuration of the first substrate 100. Figure 76A Mainly shows the planar configuration of the pixel separation portion 117, photodiode PD, floating diffusion portion FD, VSS contact region 118, and transfer transistor TR of the first substrate 100. Use Figure 76A and Figure 75 to illustrate the configuration of the first substrate 100 together.

[0447] The floating diffusion portion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion portion FD is composed of an n-type semiconductor region provided in the p-well layer 115. For example, the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D are provided close to each other in the central portion of the pixel sharing unit 539 ( Figure 76A ). As described in detail below, the four floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) included in the pixel sharing unit 539 are electrically connected to each other through electrical connection means (pad portion 120 described below) in the first substrate 100 (more specifically, in the wiring layer 100T). In addition, the floating diffusion portion FD is connected from the first substrate 100 to the second substrate 200 through an electrical device (through electrode 120E described below) (more specifically, from the wiring layer 100T to the wiring layer 200T). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion portion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG through electrical devices.

[0448] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is arranged separately from the floating diffusion portion FD. For example, in pixels 541A, 541B, 541C, and 541D, the floating diffusion portion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end ( Figure 76A ). For example, the VSS contact region 118 is composed of a p-type semiconductor region. For example, the VSS contact region 118 is connected to the ground potential or a fixed potential. Therefore, the reference potential is supplied to the semiconductor layer 100S.

[0449] The first substrate 100 includes a transfer transistor TR, a photodiode PD, a floating diffusion portion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite to the light incident surface side, the side of the second substrate 200). The transfer transistor TR includes a transfer gate TG. For example, the transfer gate TG includes a horizontal portion TGb opposite to the front surface of the semiconductor layer 100S and a vertical portion TGa provided inside the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. The vertical portion TGa has one end in contact with the horizontal portion TGb and the other end provided inside the n-type semiconductor region 114. The transfer transistor TR is constituted by such a vertical transistor, which suppresses the occurrence of pixel signal transfer failure, thereby improving the readout efficiency of the pixel signal.

[0450] For example, the horizontal portion TGb of the transfer gate TG extends in the H direction from the position opposite to the vertical portion TGa toward the central portion of the pixel sharing unit 539 ( Figure 76A ). This enables the position of the through electrode (through electrode TGV described below) reaching the transfer gate TG in the H direction to be close to the position of the through electrodes (through electrodes 120E and 121E described below) connected to the floating diffusion portion FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel sharing units 539 provided in the first substrate 100 have the same configuration as each other ( Figure 76A ).

[0451] The semiconductor layer 100S includes a pixel separation portion 117 that separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed as a portion extending in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel separation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from each other and has a planar lattice shape ( Figure 76A and Figure 76B)。For example, the pixel separation unit 117 electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other. For example, the pixel separation unit 117 includes a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light-shielding film 117A. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. For example, the insulating film 117B is made of silicon oxide (SiO). For example, the pixel separation unit 117 has an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the structure of the pixel separation unit 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, the pixel separation unit 117 may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separation unit 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0452] For example, the semiconductor layer 100S includes a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side surface of the pixel separation unit 117, specifically, between the pixel separation unit 117 and the p-well layer 115 or the n-type semiconductor region 114. For example, both the first pinning region 113 and the second pinning region 116 are formed of a p-type semiconductor region.

[0453] The fixed charge film 112 having negative fixed charges is disposed between the semiconductor layer 100S and the insulating film 111. The first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S by the electric field induced by the fixed charge film 112. This suppresses the generation of dark current caused by interface states on the light-receiving surface side of the semiconductor layer 100S. For example, the fixed charge film 112 is formed of an insulating film having negative fixed charges. Examples of materials for the insulating film having negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0454] The light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A disposed between the fixed charge film 112 and the insulating film 111 may be continuously provided with the light-shielding film 117A included in the pixel separation unit 117. For example, the light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively disposed at a position inside the semiconductor layer 100S opposite to the pixel separation unit 117. The insulating film 111 is provided to cover the light-shielding film 117A. For example, the insulating film 111 is made of silicon oxide.

[0455] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 includes, in order from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, the horizontal portion TGb of the transfer gate TG is disposed in the wiring layer 100T. The interlayer insulating film 119 is disposed on the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. For example, the interlayer insulating film 119 is made of a silicon oxide film. It should be noted that the configuration of the wiring layer 100T is not limited to the above configuration, as long as it has a configuration of wiring and insulating films.

[0456] Figure 76B The configuration of the pad portions 120 and 121 and Figure 76A the planar configuration shown. The pad portions 120 and 121 are disposed in selective regions on the interlayer insulating film 119. The pad portion 120 connects the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. For example, for each pixel sharing unit 539, the pad portion 120 is arranged in the central portion of the pixel sharing unit 539 in the plan view ( Figure 76B ). The pad portion 120 is provided to straddle the pixel separation portion 117 and is arranged to overlap at least a part of each of the floating diffusion portions FD1, FD2, FD3, and FD4 ( Figure 75 and Figure 76B ). Specifically, the pad portion 120 is formed in a region that overlaps at least a part of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a part of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 includes connection vias 120C for electrically connecting the pad portion 120 and the floating diffusion portions FD1, FD2, FD3, and FD4 to each other. The connection vias 120C are provided for each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 120 is embedded in the connection vias 120C to electrically connect the pad portion 120 and each of the floating diffusion portions FD1, FD2, FD3, and FD4 to each other.

[0457] The pad portion 121 connects a plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in pixels 541C and 541D of one pixel sharing unit 539 and the VSS contact regions 118 provided in pixels 541A and 541B of another pixel sharing unit 539, which are adjacent to each other in the V direction, are electrically connected to each other by the pad portion 121. For example, the pad portion 121 is provided to straddle the pixel separation portion 117 and is arranged to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the plurality of VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 includes connection vias 121C for electrically connecting the pad portion 121 and the VSS contact regions 118 to each other. The connection vias 121C are provided for each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection vias 121C to electrically connect the pad portion 121 and each VSS contact region 118 to each other. For example, the pad portions 120 and 121 of each of the plurality of pixel sharing units 539 arranged side by side in the V direction are arranged at substantially the same position in the H direction ( Figure 76B ).

[0458] The pad portion 120 is provided so that the wiring for connecting from the floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifying transistor AMP) can be reduced throughout the chip. Similarly, the pad portion 121 is provided so that the wiring for supplying potential to the VSS contact regions 118 can be reduced throughout the chip. This can achieve a reduction in the entire chip area, suppress electrical interference between wirings in miniaturized pixels, reduce costs by reducing the number of components, etc.

[0459] The pad portions 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 can be provided in one of the insulating regions 212 of the wiring layer 100T and the semiconductor layer 200S. When the pad portions 120 and 121 are provided in the wiring layer 100T, the pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, in a possible configuration, the pad portions 120 and 121 can be directly connected to at least a part of each of the floating diffusion portion FD and / or the VSS contact region 118. In addition, a configuration can be adopted in which connection vias 120C and 121C are provided from each of the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 are provided at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0460] Particularly, when the pad portions 120 and 121 are provided in the wiring layer 100T, the wiring in the insulating region 212 of the semiconductor layer 200S connected to the floating diffusion portion FD and / or the VSS contact region 118 can be reduced. Thereby, the area of the insulating region 212 for forming the through-wiring connecting the floating diffusion portion FD to the pixel circuit 210 in the second substrate 200 in which the pixel circuit 210 is formed can be reduced. Therefore, a larger area in the second substrate 200 in which the pixel circuit 210 is formed can be ensured. By ensuring that the pixel circuit 210 has a larger area size, larger pixel transistors can be formed, which helps to improve the image quality by reducing noise and the like.

[0461] Particularly, when the pixel separation portion 117 uses an FTI structure, the floating diffusion portion FD and / or the VSS contact region 118 are preferably provided in each pixel 541; therefore, the configuration using the pad portions 120 and 121 can significantly reduce the wiring connecting the first substrate 100 and the second substrate 200 to each other.

[0462] In addition, as Figure 76B shown, for example, the pad portions 120 respectively connected to a plurality of floating diffusion portions FD and the pad portions 121 respectively connected to a plurality of VSS contact regions 118 are alternately linearly arranged in the V direction. In addition, the pad portions 120 and 121 are formed at positions surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion portions FD. Thereby, elements other than the floating diffusion portion FD and the VSS contact region 118 can be freely arranged in the first substrate 100 in which a plurality of elements are formed, and an attempt can be made to improve the layout efficiency of the entire chip. In addition, the symmetry of the element layout formed in each pixel sharing unit 539 can be ensured, and the characteristic variation of each pixel 541 can be suppressed.

[0463] For example, the pad portions 120 and 121 are made of polysilicon (Poly Si), and more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 are preferably made of a conductive material having high heat resistance such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). Thus, the pixel circuit 210 can be formed after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason therefor will be described below. It should be noted that, in the following description, the method of forming the pixel circuit 210 after bonding the first substrate 100 to the semiconductor layer 200S of the second substrate 200 is referred to as the first manufacturing method.

[0464] In this document, in another possible method, the pixel circuit 210 is formed in the second substrate 200, and then the second substrate 200 is bonded to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are pre-formed on the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 200 (the front surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, at the same time, the electrodes for electrical connection formed on the front surface of the first substrate 100 and the front surface of the second substrate 200 come into contact with each other. Thus, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the configuration of the imaging device 1 formed using the second manufacturing method, for example, it can be manufactured using an appropriate process corresponding to the configuration of each of the first substrate 100 and the second substrate 200, and an imaging device having high quality and high performance can be manufactured.

[0465] In this second manufacturing method, when bonding the first substrate 100 and the second substrate 200 together, the manufacturing apparatus for bonding may sometimes cause alignment errors. Additionally, for example, the first substrate 100 and the second substrate 200 each have a diameter of approximately several tens of centimeters, and when bonding the first substrate 100 and the second substrate 200 together, there is a risk that expansion and contraction of the substrates will occur in the microscopic regions of each part of the first substrate 100 and the second substrate 200. The expansion and contraction of the substrates are caused by slight deviations in the time when the substrates come into contact with each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur at the positions of the electrodes formed on the front surfaces of the first substrate 100 and the second substrate 200 for electrical connection. In the second manufacturing method, even if such errors occur, it is preferable to take measures to ensure that the electrodes of the first substrate 100 and the second substrate 200 are in contact with each other. Specifically, in consideration of the above-mentioned errors, at least one of the electrodes of the first substrate 100 and the second substrate 200 is made larger, preferably both are made larger. Therefore, if the second manufacturing method is used, for example, the size of the electrode formed on the front surface of the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) becomes larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 in the thickness direction to the front surface.

[0466] On the other hand, if the pad portions 120 and 121 are made of a heat-resistant conductive material, the above-described first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (the semiconductor layer 200S) are bonded together. At this time, the second substrate 200 is in a state where the active elements and wiring layers and other patterns included in the pixel circuit 210 have not been formed. Since the patterns have not been formed in the second substrate 200, even if an error occurs at the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause an alignment error between the patterns of the first substrate 100 and the patterns of the second substrate 200. The reason is that the patterns of the second substrate 200 are formed after bonding the first substrate 100 and the second substrate 200 together. It should be noted that when forming the patterns of the second substrate, for example, the patterns formed in the first substrate are used as alignment targets in the exposure apparatus for pattern formation. For the above reasons, in the first manufacturing method, the error in the bonding position between the first substrate 100 and the second substrate 200 is not a problem in the manufacture of the imaging device 1. For the same reason, in the first manufacturing method, the error caused by the expansion and contraction of the substrates resulting from the second manufacturing method is also not a problem in the manufacture of the imaging device 1.

[0467] In the first manufacturing method, after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together in this manner, active elements are formed on the second substrate 200. Thereafter, through electrodes 120E and 121E and through electrodes TGV ( Figure 75 ) are formed. For example, in the formation of the through electrodes 120E, 121E, and TGV, a pattern of the through electrodes is formed from above the second substrate 200 by an exposure apparatus using reduction-projection exposure. Since reduction exposure projection is used, even if an alignment error occurs between the second substrate 200 and the exposure apparatus, the size of the error of the second substrate 200 is only a fraction (the reciprocal of the reduction exposure projection magnification) of the error in the above-described second manufacturing method. Therefore, by constructing the imaging device 1 using the first manufacturing method, alignment between the elements formed in the first substrate 100 and the second substrate 200 becomes easy, which makes it possible to manufacture an imaging device with high quality and high performance.

[0468] The imaging device 1 manufactured using this first manufacturing method has characteristics different from those of the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV all have a substantially uniform thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV all have a tapered shape, they have a tapered shape with a constant slope. In the imaging device 1 including such through electrodes 120E, 121E, and TGV, it is easy to miniaturize the pixel 541.

[0469] In this document, if the imaging device 1 is manufactured by the first manufacturing method, after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together, active elements are formed on the second substrate 200; therefore, the heating process required for forming the active elements also affects the first substrate 100. For this reason, as described above, the pad portions 120 and 121 provided in the first substrate 100 preferably use a conductive material with high heat resistance. For example, the pad portions 120 and 121 preferably use a material having a melting point higher (i.e., higher heat resistance) than the melting point of at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, the pad portions 120 and 121 use a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, titanium nitride, etc. Thus, the imaging device 1 can be manufactured using the above-described first manufacturing method.

[0470] For example, a passivation film 122 is provided on the entire front surface of the semiconductor layer 100S to cover the pad portions 120 and 121 ( Figure 75). For example, the passivation film 122 is composed of a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 via the passivation film 122. For example, the interlayer insulating film 123 is provided on the entire front surface of the semiconductor layer 100S. For example, the interlayer insulating film 123 is composed of a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. For example, the bonding film 124 is composed of a silicon nitride film.

[0471] For example, the light receiving lens 401 is opposite to the semiconductor layer 100S via the fixed charge film 112 and the insulating film 111 ( Figure 75 ). For example, each light receiving lens 401 is provided at a position opposite to the photodiode PD of each pixel 541A, 541B, 541C, and 541D.

[0472] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S is composed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. For example, the well region 211 is a p-type semiconductor region. The second substrate 200 includes a pixel circuit 210 arranged for each pixel sharing unit 539, respectively. For example, the pixel circuit 210 is provided on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 so that the back side (semiconductor layer 200S side) of the second substrate 200 is opposite to the front surface side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a face-to-back manner.

[0473] Figures 77 to 81 An example of a plane configuration of the second substrate 200 is schematically shown. Figure 77 The configuration of the pixel circuit 210 provided near the front surface of the semiconductor layer 200S is shown. Figure 78 The configurations of the wiring layer 200T (specifically, a first wiring layer W1 described below) and portions in the semiconductor layer 200S and the first substrate 100 and connected to the wiring layer 200T are schematically shown. Figures 79 to 84 Examples of the planar configuration of the wiring layer 200T are shown below. Figures 77 to 81 as well as Figure 75 The structure of the second substrate 200 is described together. Figure 77 and Figure 78In this figure, the outer shape of the photodiode PD (the boundary between the pixel isolation section 117 and the photodiode PD) is indicated by a dashed line, and the boundary between the element isolation region 213 or the insulating region 212 and the semiconductor layer 200S in the portion overlapping with the gate electrode of the transistor included in the pixel circuit 210 is indicated by a dotted dashed line. In the portion overlapping with the gate electrode of the amplifying transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 212 are provided on one side in the channel width direction.

[0474] The second substrate 200 includes the insulating region 212 that divides the semiconductor layer 200S and the element isolation region 213 provided in a part in the thickness direction of the semiconductor layer 200S ( Figure 75 ). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E connected to the two pixel sharing units 539 of the two pixel circuits 210 and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are arranged ( Figure 78 ).

[0475] The insulating region 212 has a thickness substantially the same as the thickness of the semiconductor layer 200S ( Figure 75 ). The semiconductor layer 200S is divided by the insulating region 212. The through electrodes 120E and 121E and the through electrodes TGV are arranged in the insulating region 212. For example, the insulating region 212 is made of silicon oxide.

[0476] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings of the wiring layer 200T (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4 described below). The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and their lower ends are connected to the pad portions 120 and 121 ( Figure 75 ). The through electrode 120E electrically connects the pad portion 120 and the pixel circuit 210 to each other. That is, the floating diffusion portion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E electrically connects the pad portion 121 and the reference potential line VSS of the wiring layer 200T to each other. That is, the VSS contact region 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0477] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG( Figure 75 ). Such a through electrode TGV electrically connects the transfer gates TG (transfer gates TG1, TG2, TG3, or TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring (a part of the row drive signal line 542, specifically, the wiring TRG1, TRG2, TRG3, or TRG4 in Figure 80 ) of the wiring layer 200T with each other. That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and a drive signal is transmitted to each transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR4).

[0478] The insulating region 212 is a region for providing the through electrodes 120E and 121E and the through electrode TGV for electrically connecting the first substrate 100 and the second substrate 200 to each other and insulating them from the semiconductor layer 200S. For example, in the insulating region 212 provided between two pixel circuits 210 (pixel sharing unit 539) adjacent to each other in the H direction, the through electrodes 120E and 121E and the through electrode TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel circuits 210 are arranged. For example, the insulating region 212 is provided to extend in the V direction( Figure 77 and Figure 78 ). Herein, the layout of the horizontal portion TGb of the transfer gate TG is designed such that the position of the through electrode TGV in the H direction is arranged closer to the positions of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa( Figure 76A and Figure 78)。For example, the through electrode TGV is arranged at a position substantially the same as that of the through electrodes 120E and 121E in the H direction. This enables the through electrodes 120E and 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction. In another possible arrangement example, the horizontal portion TGb is provided only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed substantially directly above the vertical portion TGa, and for example, the through electrode TGV is arranged in a substantially central portion in the H direction and the Y direction of each pixel 541. At this time, the position of the through electrode TGV in the H direction is significantly deviated from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the nearby semiconductor layer 200S. In the case where the positions of the through electrode TGV in the H direction and the through electrodes 120E and 121E in the H direction are significantly separated from each other, it is necessary to independently provide the insulating region 212 around each of the through electrodes 120E, 121E, and TGV. Therefore, the semiconductor layer 200S is subdivided. In contrast, the layout in which the through electrodes 120E and 121E and the through electrode TGV are arranged together in the insulating region 212 extending in the V direction allows the size of the semiconductor layer 200S in the H direction to increase. This enables a larger area of the semiconductor element formation region in the semiconductor layer 200S to be ensured. Therefore, for example, the size of the amplification transistor AMP can be increased and noise can be suppressed.

[0479] As described with reference to Figure 73 , each pixel sharing unit 539 has a structure in which the floating diffusion portions FD provided in a plurality of pixels 541 are electrically connected to each other and the plurality of pixels 541 share one pixel circuit 210. Then, the electrical connection between the floating diffusion portions FD is formed through the pad portion 120 provided in the first substrate 100 ( Figure 75 and Figure 76B ). The electrical connection portion (pad portion 120) provided in the first substrate 100 and the pixel circuit 210 provided in the second substrate 200 are electrically connected to each other via one through electrode 120E. In another possible structural example, the electrical connection portion between the floating diffusion portions FD is provided in the second substrate 200. In this case, each pixel sharing unit 539 is provided with four through electrodes, and each through electrode is connected to one of the floating diffusion portions FD1, FD2, FD3, and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 for insulating the peripheral portion of the through electrode becomes larger. In contrast, in the case where the first substrate 100 is provided with the pad portion 120 ( Figure 75 and Figure 76B) The structure enables reduction in the number of through electrodes and makes the insulating region 212 smaller. Therefore, a large area size can be ensured in the semiconductor element formation region in the semiconductor layer 200S. Thus, for example, the size of the amplifying transistor AMP can be increased and noise can be suppressed.

[0480] The element isolation region 213 is provided on the front surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (shallow trench isolation) structure. In the element isolation region 213, the semiconductor layer 200S has trenches extending in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the trenches. For example, the insulating film is made of silicon oxide. Each element isolation region 213 separates a plurality of transistors included in the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below (the deep part of the semiconductor layer 200S) the element isolation region 213.

[0481] Hereinafter, with reference to Figure 76A 、 Figure 76B and Figure 77 an explanation is given of the difference between the outer shape (the outer shape in the substrate plane direction) of the pixel sharing unit 539 in the first substrate 100 and the outer shape of the pixel sharing unit 539 in the second substrate 200.

[0482] In the imaging device 1, the pixel sharing unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided in the first substrate 100 and the outer shape of the pixel sharing unit 539 provided in the second substrate 200 are different from each other.

[0483] In Figure 76A and Figure 76B the outer shape lines of each pixel 541A, 541B, 541C, and 541D are indicated by dotted lines, and the outer shape line of the pixel sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to them in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four adjacent pixels 541 in two rows by two columns, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other with a two-pixel pitch (corresponding to the pitch of two pixels 541) in the H direction and a two-pixel pitch (corresponding to the pitch of two pixels 541) in the V direction.

[0484] InFigure 77 and Figure 78 In Figure 78 , the outer shape lines of each of the pixels 541A, 541B, 541C, and 541D are represented by dotted lines, and the outer shape line of the pixel sharing unit 539 is represented by a thick line. For example, the outer shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction and larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed to have a size (area) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed to have a size corresponding to adjacent pixels arranged in one row × four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0485] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in the V direction in this order ( Figure 77 ). As described above, the outer shape of each pixel circuit 210 is set to a substantially rectangular shape, which enables four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) to be arranged side by side in one direction ( Figure 10 the V direction in Figure 10 ). Accordingly, the drain of the amplification transistor AMP and the drain of the reset transistor RST can share a diffusion region (a diffusion region connected to the power supply line VDD). For example, the formation region of each pixel circuit 210 can also be set to a substantially square shape (see Figure 90 described below). Figure 90 In this case, two transistors are arranged in one direction, and it is difficult for the drain of the amplification transistor AMP and the drain of the reset transistor RST to share a diffusion region. Therefore, by setting the formation region of the pixel circuit 210 to a substantially rectangular shape, the four transistors can be easily arranged close to each other, and the formation region of the pixel circuit 210 can be made smaller. That is, the pixel can be miniaturized. In addition, when it is not necessary to make the formation region of the pixel circuit 210 smaller, the formation region of the amplification transistor AMP can be made larger, and noise can be suppressed.

[0486] For example, in addition to selecting a transistor SEL, an amplification transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG, a VSS contact region 218 connected to a reference potential line VSS is also provided near the front surface of a semiconductor layer 200S. For example, the VSS contact region 218 is formed of a p-type semiconductor region. The VSS contact region 218 is electrically connected to a VSS contact region 118 of a first substrate 100 (semiconductor layer 100S) through a wiring and a via electrode 121E of a wiring layer 200T. For example, the VSS contact region 218 is provided at a position adjacent to the source of the FD conversion gain switching transistor FDG with an element isolation region 213 interposed therebetween ( Figure 77 ).

[0487] Next, with reference to Figure 76B and Figure 77 a positional relationship between a pixel sharing unit 539 provided in a first substrate 100 and a pixel sharing unit 539 provided in a second substrate 200 will be described. For example, one of two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100 (e.g., Figure 76B the upper one in the drawing surface of Figure 77 ) is connected to one of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 (e.g., Figure 76B the left one in the drawing surface of Figure 77 ). For example, the other of two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100 (e.g., Figure 76B the lower one in the drawing surface of Figure 77 ) is connected to the other of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 (e.g., Figure 77 the right one in the drawing surface of

[0488] For example, in two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially the same as the layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and the H direction. The effects achieved by this layout will be described below.

[0489] In two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100, each pad portion 120 is arranged in the central portion of the outer shape of the pixel sharing unit 539, that is, in the central portions of the pixel sharing unit 539 in the V direction and the H direction ( Figure 76B)。On the other hand, as described above, since the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is longer in the V direction, for example, the amplification transistor AMP connected to the pad portion 120 is arranged at a position deviated upward from the center in the V direction of the pixel sharing unit 539 with respect to the paper surface. For example, when the internal layouts of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., Figure 76B the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper surface in Figure 76B ) is relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (e.g.,

[0490] the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper surface in Figure 77 ) is long. Therefore, the wiring area required for connecting the amplification transistor AMP and the pad portion 120 increases, which may complicate the wiring layout of the pixel sharing unit 539. This may affect the miniaturization of the imaging device 1.

[0490] Conversely, when the internal layouts of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 are inverted from each other at least in the V direction, the distance between each pair of the amplification transistor AMP and the pad portion 120 of both of the two pixel sharing units 539 can be shortened. Therefore, the imaging device 1 is more likely to be miniaturized compared to a configuration in which the internal layouts of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 are the same. It should be noted that the planar layout of each pixel sharing unit 539 among the plurality of pixel sharing units 539 of the second substrate 200 is symmetric about the left and right within the range shown in Figure 77 ; however, the layout including the layout of the first wiring layer W1 shown in Figure 78 is asymmetric about the left and right.

[0491] In addition, preferably, the internal layouts of each of the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 are also inverted from each other in the H direction. The reason therefor will be described below. As Figure 78As shown, two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200 are respectively connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged in the central portion in the H direction (between the two pixel sharing units 539 arranged side by side in the H direction) of the two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200. Therefore, the internal layouts of the two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200 are also reversed with respect to each other in the H direction, which makes it possible to reduce the distance between each pixel sharing unit 539 among the plurality of pixel sharing units 539 on the second substrate 200 and the pad portions 120 and 121. That is, miniaturization of the imaging device 1 becomes easy.

[0492] In addition, the position of the outer contour line of each pixel sharing unit 539 on the second substrate 200 may not be aligned with the position of the outer contour line of any one of the pixel sharing units 539 in the pixel sharing unit 539 on the first substrate 100. For example, among the two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200, one (for example, Figure 78 the one on the left side of the paper surface in Figure 78 the upper side of the paper surface in) the outer contour line of the pixel sharing unit 539 is arranged outside the outer contour line on one side in the V direction of the corresponding (for example, Figure 76B the upper side of the paper surface in) pixel sharing unit 539 on the first substrate 100. In addition, among the two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200, the other (for example, Figure 78 the one on the right side of the paper surface in) the outer contour line of the pixel sharing unit 539 on the other side in the V direction (for example, Figure 78 the lower side of the paper surface in) is arranged outside the outer contour line on the other side in the V direction of the corresponding pixel sharing unit 539 (for example, Figure 76B the pixel sharing unit 539 on the lower side of the paper surface in) on the first substrate 100. By arranging the pixel sharing units 539 on the second substrate 200 and the pixel sharing units 539 on the first substrate 100 relative to each other in this way, the distance between each pair of amplification transistors AMP and the pad portion 120 can be shortened. Therefore, miniaturization of the imaging device 1 becomes easy.

[0493] In addition, the positions of the outer contour lines of the plurality of pixel sharing units 539 on the second substrate 200 may not be aligned. For example, the positions of the outer contour lines of the two pixel sharing units 539 arranged side by side in the H direction on the second substrate 200 are arranged to be offset from each other in the V direction. Thereby, the distance between each pair of amplification transistors AMP and the pad portion 120 can be shortened. Therefore, miniaturization of the imaging device 1 becomes easy.

[0494] Refer toFigure 76B and Figure 78 The repeated arrangement of the pixel sharing unit 539 in the pixel array unit 540 will be described. The pixel sharing unit 539 on the first substrate 100 has the size of two pixels 541 in the H direction and the size of two pixels 541 in the V direction ( Figure 76B ). For example, in the pixel array unit 540 of the first substrate 100, the pixel sharing unit 539 having a size corresponding to four pixels is repeatedly arranged adjacent to each other with a two-pixel pitch (corresponding to the pitch of two pixels 541) in the H direction and a two-pixel pitch (corresponding to the pitch of two pixels 541) in the V direction. Alternatively, in the pixel array unit 540 of the first substrate 100, a pair of pixel sharing units 539 including two pixel sharing units 539 arranged adjacent to each other in the V direction may be provided. For example, in the pixel array unit 540 of the first substrate 100, the pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with a two-pixel pitch (corresponding to the pitch of two pixels 541) in the H direction and a four-pixel pitch (corresponding to the pitch of four pixels 541) in the V direction. The pixel sharing unit 539 on the second substrate 200 has the size of one pixel 541 in the H direction and the size of four pixels 541 in the V direction ( Figure 78 ). For example, in the pixel array unit 540 of the second substrate 200, a pair of pixel sharing units 539 are provided, and the pair of pixel sharing units 539 include two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and are arranged to be offset from each other in the V direction. For example, in the pixel array unit 540 of the second substrate 200, the pair of pixel sharing units 539 are repeatedly arranged adjacent to each other without a gap with a two-pixel pitch (corresponding to the pitch of two pixels 541) in the H direction and a four-pixel pitch (corresponding to the pitch of four pixels 541) in the V direction. This repeated arrangement of the pixel sharing unit 539 enables the pixel sharing unit 539 to be arranged without a gap. Therefore, miniaturization of the imaging device 1 becomes easy.

[0495] For example, preferably, the amplifying transistor AMP has a three-dimensional structure such as a Fin type structure ( Figure 75 ). Thereby, the size of the effective gate width becomes larger, and noise can be suppressed. For example, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have a planar structure. The amplifying transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0496] For example, the wiring layer 200T includes a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). For example, the passivation film 221 is in contact with the front surface of the semiconductor layer 200S and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the respective gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4) are separated by the interlayer insulating film 222. For example, the interlayer insulating film 222 is made of silicon oxide.

[0497] In the wiring layer 200T, for example, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, the fourth wiring layer W4, and the contact portions 201 and 202 are provided in this order starting from one side of the semiconductor layer 200S and are insulated from each other by the interlayer insulating film 222. The interlayer insulating film 222 includes a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layer below. The connection portion is a portion formed by embedding a conductive material into a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 includes a connection portion 218V that connects the first wiring layer W1 to the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture diameter of such a connection portion that connects the elements of the second substrate 200 is different from the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV. Specifically, preferably, the aperture diameter of the connection hole that connects the elements of the second substrate 200 is smaller than the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV. Hereinafter, the reason therefor will be described. The depth of the connection portion (such as the connection portion 218V) provided in the wiring layer 200T is shallower than the depths of the through electrodes 120E and 121E and the through electrode TGV. Therefore, compared with the through electrodes 120E and 121E and the through electrode TGV, it is easier to embed the conductive material into the connection hole of the connection portion. By making the aperture diameter of the connection portion smaller than the aperture diameters of the through electrodes 120E and 121E and the through electrode TGV, miniaturization of the imaging device 1 becomes easier.

[0498] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaching the source of the FD conversion gain switching transistor FDG). For example, the first wiring layer W1 connects the through electrode 121E to the connection portion 218V, which electrically connects the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0499] Next, the planar configuration of the wiring layer 200T will be described with reference to Figures 79 to 81 FIG. Figure 79 An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 80 An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 81 An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0500] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, and TRG4, SELL, RSTL, and FDGL that extend in the H direction (row direction) ( Figure 80 ). These wirings correspond to the multiple row driving signal lines 542 described with reference to Figure 73 . Each of the wirings TRG1, TRG2, TRG3, and TRG4 is used to send a driving signal to a corresponding one of the transfer gates TG1, TG2, TG3, and TG4. Each of the wirings TRG1, TRG2, TRG3, and TRG4 is connected to a corresponding one of the transfer gates TG1, TG2, TG3, and TG4 through the second wiring layer W2, the first wiring layer W1, and the through electrode 120E. The wiring SELL transmits a driving signal to the gate of the selection transistor SEL, the wiring RSTL transmits a driving signal to the gate of the reset transistor RST, and the wiring FDGL transmits a driving signal to the gate of the FD conversion gain switching transistor FDG. The wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG through the second wiring layer W2, the first wiring layer W1, and the connection portions, respectively.

[0501] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 that extend in the V direction (column direction) ( Figure 81 ). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact region 218 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact region 118 of the first substrate 100 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0502] The contact portions 201 and 202 may be disposed at positions overlapping with the pixel array portion 540 in a plan view (e.g., Figure 72 ), or may be disposed in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 75 ). The contact portions 201 and 202 are disposed on the front surface of the second substrate 200 (the surface on the side of the wiring layer 200T). For example, the contact portions 201 and 202 are made of a metal such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the front surface of the wiring layer 200T (the surface on the side of the third substrate 300). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and bonding between the second substrate 200 and the third substrate 300.

[0503] Figure 75 An example in which the peripheral circuit is disposed in the peripheral portion 540B of the second substrate 200 is shown. The peripheral circuit may include a part of the row driving portion 520, a part of the column signal processing portion 550, etc. In addition, as Figure 72 shown, the peripheral circuit may not be disposed in the peripheral portion 540B of the second substrate 200, and the connection hole portions H1 and H2 may be disposed near the pixel array portion 540.

[0504] For example, the third substrate 300 includes a wiring layer 300T and a semiconductor layer 300S in order starting from one side of the second substrate 200. For example, the front surface of the semiconductor layer 300S is provided on one side of the second substrate 200. The semiconductor layer 300S is formed of a silicon substrate. A circuit is provided in a part on the front surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input section 510A, the row driver section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560, and the output section 510B is provided in a part on the front surface side of the semiconductor layer 300S. For example, the wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the front surface (the surface on the side of the second substrate 200) of the wiring layer 300T. The contact portion 301 is connected to the contact portion 201 of the second substrate 200, and the contact portion 302 is connected to the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to a circuit formed in the semiconductor layer 300S (for example, at least one of the input section 510A, the row driver section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560, and the output section 510B). For example, the contact portions 301 and 302 are formed of a metal such as Cu (copper) and Al (aluminum). For example, the external terminal TA is connected to the input section 510A through the connection hole portion H1, and the external terminal TB is connected to the output section 510B through the connection hole portion H2.

[0505] Hereinafter, the characteristics of the imaging device 1 will be described.

[0506] Generally, an imaging device includes a photodiode and a pixel circuit as main components. In this article, if the area of the photodiode increases, the charge generated by photoelectric conversion increases, which thus makes it possible to improve the signal-to-noise ratio (S / N ratio) of the pixel signal, and the imaging device can output better image data (image information). On the other hand, if the size of the transistor included in the pixel circuit (specifically, the size of the amplifying transistor) increases, the noise generated in the pixel circuit decreases, so that the S / N ratio of the imaging signal can be improved, and the imaging device can output better image data (image information).

[0507] However, it can be conceived that in an imaging device in which a photodiode and a pixel circuit are provided in the same semiconductor substrate, if the area of the photodiode increases within the limited area of the semiconductor substrate, it can be conceived that the size of the transistor included in the pixel circuit will inevitably decrease. In addition, if the size of the transistor included in the pixel circuit increases, it can be conceived that the area of the photodiode will inevitably decrease.

[0508] To solve these problems, for example, the imaging device 1 according to the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. Thereby, the area of the photodiode PD can be made as large as possible within the limited area of the semiconductor substrate, and the size of the transistors included in the pixel circuit 210 can be made as large as possible. Thereby, the S / N ratio of the pixel signal can be improved, and the imaging device 1 can output better image data (image information).

[0509] When implementing a structure in which a plurality of pixels 541 share one pixel circuit 210 and the one pixel circuit 210 is arranged to overlap with the photodiode PD, a plurality of wirings connected to the one pixel circuit 210 extend from the respective floating diffusion portions FD of the plurality of pixels 541. To ensure a larger area in the semiconductor substrate 200 where the pixel circuit 210 is formed, for example, a connection wiring that connects the plurality of extended wirings into one can be formed. For the plurality of wirings extending from the VSS contact region 118, a connection wiring that connects the extended plurality of wirings into one can be formed.

[0510] For example, if a connection wiring that connects the plurality of wirings extending from the respective floating diffusion portions FD of the plurality of pixels 541 is formed in the semiconductor substrate 200 where the pixel circuit 210 is formed, it can be expected that the area of the transistors included in the pixel circuit 210 will inevitably become smaller. Similarly, if a connection wiring that connects the plurality of wirings extending from the VSS contact regions 118 of the plurality of pixels 541 into one is formed in the semiconductor layer 200S where the pixel circuit 210 is formed, it can be expected that the area of the transistors included in the pixel circuit 210 will inevitably become smaller.

[0511] To solve these problems, for example, the imaging device 1 according to the present embodiment can have a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to overlap with the photodiode PD, and a structure in which a connection wiring that connects the floating diffusion portions FD of the plurality of pixels 541 into one and a connection wiring that connects the VSS contact regions 118 included in the plurality of pixels 541 into one are provided in the first substrate 100.

[0512] In this document, if the above-described second manufacturing method is used as a manufacturing method for forming connection wirings that connect the floating diffusion portions FD of multiple pixels 541 in series and connection wirings that connect the VSS contact regions 118 of multiple pixels 541 in series in the first substrate 100, then manufacturing can be performed using an appropriate process corresponding to the configurations of the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured. Additionally, the connection wirings of the first substrate 100 and the second substrate 200 can be formed through a simple process. Specifically, in the case of using the above-described second manufacturing method, electrodes connected to the floating diffusion portion FD and electrodes connected to the VSS contact region 118 are provided on the front surfaces of the first substrate 100 and the second substrate 200 that form the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, even if displacement occurs between the electrodes provided on the front surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together, the electrodes formed on the front surfaces of the two substrates are preferably made larger so that the electrodes formed on the front surfaces of the two substrates come into contact with each other. In this case, it is considered difficult to arrange the above-described electrodes within the limited area of each pixel included in the imaging device 1.

[0513] To solve the problem of the need for large electrodes on the bonding interface between the first substrate 100 and the second substrate 200, for example, the above-described first manufacturing method can be used as a manufacturing method for the imaging device 1 according to the present embodiment in which one pixel circuit 210 is shared by multiple pixels 541 and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. Thereby, alignment of the elements in each of the first substrate 100 and the second substrate 200 can be facilitated, and a high-quality and high-performance imaging device can be manufactured. Additionally, a unique structure generated by using this manufacturing method can be provided. That is, the imaging device includes a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked on top of each other in this order, that is, a structure in which the first substrate 100 and the second substrate 200 are stacked face to back with respect to each other, and the imaging device includes through electrodes 120E and 121E that penetrate from the front surface side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 and reach the front surface of the semiconductor layer 100S of the first substrate 100.

[0514] If a structure in which connection wirings that connect the floating diffusion parts FD of a plurality of pixels 541 to each other in a line and connection wirings that connect the VSS contact regions 118 of the plurality of pixels 541 to each other in a line are provided in the first substrate 100 and the first substrate 100 and the second substrate 200 are stacked on each other using the first manufacturing method, and the pixel circuit 210 is formed in the second substrate 200, then the heating process required for forming the active elements included in the pixel circuit 210 may inevitably affect the above-described connection wirings formed in the first substrate 100.

[0515] In view of this, in order to solve the problem that the heating process for forming the above-described active elements inevitably affects the above-described connection wirings, the imaging device 1 according to the present embodiment desirably uses a conductive material having high heat resistance for the connection wirings that connect the floating diffusion parts FD of a plurality of pixels 541 to each other in a line and the connection wirings that connect the VSS contact regions 118 of the plurality of pixels 541 to each other in a line. Specifically, a material having a melting point higher than the melting point of at least some of the wiring materials included in the wiring layer 200T of the second substrate 200 can be used as the conductive material having high heat resistance.

[0516] In this way, for example, the imaging device 1 according to the present embodiment includes: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked on each other back to back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 100 are stacked on each other in this order), (2) a structure in which through electrodes 120E and 121E are provided that penetrate the semiconductor layer 200S of the second substrate 200 from the front surface side, the semiconductor layer 200S of the second substrate 200, and the wiring layer 100T of the first substrate 100 and reach the front surface of the semiconductor layer 100S of the first substrate 100, and (3) a structure in which connection wirings that connect the floating diffusion parts FD included in a plurality of pixels 541 to each other in a line and connection wirings that connect the VSS contact regions 118 included in the plurality of pixels 541 to each other in a line are formed using a conductive material having high heat resistance, which makes it possible to provide connection wirings that connect the floating diffusion parts FD included in a plurality of pixels 541 to each other in a line and connection wirings that connect the VSS contact regions 118 included in the plurality of pixels 541 to each other in a line in the first substrate 100 without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0517] [Operation of Imaging Device 1]

[0518] Next, use Figure 82 and Figure 83 to describe the operation of the imaging device 1. Compared with Figure 72 ​Figure 82 and Figure 83 An arrow indicating the path of the indication signal is additionally shown. Figure 82 The paths of the input signal, power supply potential, and reference potential input from the outside to the imaging device 1 indicated by the arrow are shown. Figure 83 The signal path of the pixel signal output from the imaging device 1 to the outside indicated by the arrow is shown. For example, the input signal (e.g., pixel clock and synchronization signal) input to the imaging device 1 through the input unit 510A is transmitted to the row driver unit 520 of the third substrate 300, and a row driving signal is generated in the row dr...

Claims

1. A semiconductor device, comprising: A first substrate, which includes a first element layer containing a first active element, a first wiring layer disposed on the first element layer, a shielding layer containing a conductive material disposed on the first wiring layer, and a photoelectric conversion portion disposed below the first element layer; And A second substrate, which includes a second element layer containing a second active element disposed on the shielding layer and a second wiring layer disposed on the second element layer, wherein The first substrate and the second substrate are stacked on top of each other such that the second element layer is closer to the first substrate than the second wiring layer, An opening is provided in the shielding layer, and The semiconductor device further includes a connection wiring, which penetrates through the opening and connects the photoelectric conversion portion or the first wiring layer to the second wiring layer.

2. The semiconductor device according to claim 1, wherein a portion of the shielding layer located at the opening extends coaxially with the connection wiring and along the longitudinal direction of the connection wiring so as to surround the outer peripheral surface of the connection wiring with an interlayer insulating film therebetween.

3. The semiconductor device according to any one of claims 1-2, wherein a third substrate is stacked on the second substrate.

4. The semiconductor device according to any one of claims 1-2, wherein the semiconductor device constitutes a solid-state imaging device.

5. A method for manufacturing a semiconductor device, comprising: Forming a first wiring layer on a first element layer containing a first active element; Forming a first substrate including the first element layer, the first wiring layer, and the shielding layer by forming a shielding layer containing a conductive material on the first wiring layer; Preparing a second substrate in which a second element layer containing a second active element is formed; Forming the second element layer on the shielding layer by bonding the second element layer side of the second substrate to the shielding layer side of the first substrate; And Forming a second wiring layer on the second element layer, wherein The first substrate further includes a photoelectric conversion portion disposed on a side of the first element layer opposite to the first wiring layer side, The first substrate and the second substrate are stacked on top of each other such that the second element layer is closer to the first substrate than the second wiring layer, An opening is provided in the shielding layer, and The semiconductor device further includes a connection wiring, which penetrates through the opening and connects the photoelectric conversion portion or the first wiring layer to the second wiring layer.

6. A semiconductor device, comprising: A first substrate, which includes a first element layer containing a first active element and a first wiring layer disposed on the first element layer; And A second substrate, which includes a second element layer containing a second active element and a second wiring layer disposed on the second element layer, wherein The first substrate and the second substrate are stacked on top of each other, and the semiconductor device further includes an electromagnetic shielding layer containing a conductive material between the first substrate and the second substrate. An opening is provided in the electromagnetic shielding layer, and a sheath portion electrically connected to the electromagnetic shielding layer is provided around the opening, and When observed in a plan view, the electromagnetic shielding layer is arranged to cover at least the first active element.

7. The semiconductor device according to claim 6, wherein the electromagnetic shielding layer is connected to a ground potential.

8. The semiconductor device according to claim 6 or 7, wherein the conductive material includes any one of tungsten, titanium, titanium nitride, carbon, and polysilicon.

9. The semiconductor device according to claim 8, wherein the electromagnetic shielding layer includes diffusion prevention layers provided on the upper and lower surfaces of the conductive material.

10. A method of manufacturing a semiconductor device, comprising: Forming a first substrate including the first element layer and the first wiring layer by forming a first wiring layer on a first element layer including a first active element; Preparing a second substrate; Forming an electromagnetic shielding layer including a conductive material on the first substrate or the second substrate; Bonding the first substrate and the second substrate together with the electromagnetic shielding layer therebetween; Forming a second element layer including a second active element on the second substrate; And Forming a second wiring layer on the second element layer, wherein An opening is provided in the electromagnetic shielding layer, and a sheath portion electrically connected to the electromagnetic shielding layer is provided around the opening, and When observed in a plan view, the electromagnetic shielding layer is arranged to cover at least the first active element.

11. A semiconductor device, comprising: A first substrate including a first element layer including a first active element, a first wiring layer disposed on the first element layer, and a photoelectric conversion portion disposed below the first element layer; And A second substrate including a second element layer including a second active element and a second wiring layer disposed on the second element layer, wherein The first substrate and the second substrate are stacked on top of each other, and the semiconductor device further includes a light attenuation portion made of a material having a refractive index higher than that of the surrounding material between the second active element and the photoelectric conversion portion, and The light attenuation portion includes a convex portion formed in the second substrate.

12. The semiconductor device according to claim 11, wherein the light attenuation portion is made of a silicon material formed in an interlayer insulating film.

13. The semiconductor device according to claim 12, wherein the light attenuation portion is made of silicon quantum dots.

14. A method of manufacturing a semiconductor device, comprising: Forming a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion portion by forming a first wiring layer on a first element layer including a first active element and forming a photoelectric conversion portion below the first element layer; Preparing a second substrate; Forming a light attenuation portion made of a material having a refractive index higher than that of the surrounding material in the second substrate; Bonding the first substrate and the second substrate together on the side of the light attenuation portion; Forming a second element layer including a second active element on the second substrate; And Forming a second wiring layer on the second element layer, wherein The light attenuation portion includes a convex portion formed in the second substrate.

15. A semiconductor device, comprising: A first substrate including a first element layer containing a first active element, a first wiring layer disposed on the first element layer, and a photoelectric conversion portion disposed below the first element layer; A second substrate including a second element layer containing a second active element and a second wiring layer disposed on the second element layer; And An antireflection portion made of a material having a refractive index lower than that of the semiconductor material included in the second substrate, wherein The first substrate and the second substrate are stacked on each other, and the antireflection portion is disposed at least between the second active element and the photoelectric conversion portion, and When observed in a plan view, the antireflection portion is further disposed in a side region of the second active element.

16. The semiconductor device according to claim 15, wherein the antireflection portion is made of silicon nitride.

17. The semiconductor device according to claim 15, further comprising: An intermediate film disposed between the antireflection portion and the second active element and made of a material different from that of the antireflection portion.

18. The semiconductor device according to claim 17, wherein the film thickness of the intermediate film is smaller than the film thickness of the antireflection portion.

19. The semiconductor device according to claim 15, wherein the antireflection portion includes a plurality of uneven portions.

20. A method for manufacturing a semiconductor device, comprising: Forming a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion portion by forming a first wiring layer on a first element layer containing a first active element and forming a photoelectric conversion portion below the first element layer; Preparing a second substrate; Forming an antireflection portion in the second substrate, the antireflection portion being made of a material having a refractive index lower than that of the semiconductor material included in the second substrate; Bonding the first substrate and the antireflection portion side of the second substrate together; Forming a second element layer containing a second active element on the second substrate; And Forming a second wiring layer on the second element layer, wherein When observed in a plan view, the antireflection portion is further disposed in a side region of the second active element.

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