Variable link, CPU link and high-speed interface connection module and test system and method

Abstract

The present invention provides a variable link module comprising a printed circuit board (PCB) and at least one set of signal lines disposed on the PCB. Each signal line is provided with a communication interface at each end, one of which is configured to communicate with a CPU, and the other is configured to communicate with a high-speed interface connector. The variable link module provided by the present invention can utilize the multiple signal lines of the module to test the electrical characteristic limits of a CPU, eliminating the need for multiple printed circuit board production, thereby reducing testing costs and improving testing efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU testing, and in particular to a variable link, a CPU link and a high-speed interface connection module, and a testing system and method. Background Art

[0002] The electrical characteristics of the CPU's high-speed interface are a key indicator of CPU performance, primarily encompassing the electrical characteristic parameter limits and link passive parameter results. This determines the compatibility of the CPU motherboard and overall system design, including the PCB trace length of the high-speed interface link, the reach of peripheral cables, the design of the relevant heat dissipation structure, and overall system stability.

[0003] To determine the electrical characteristic limits of the CPU's high-speed interface, software simulation can be used. However, the accuracy of the simulation results is highly dependent on the accuracy of the model. If the model is inaccurate, erroneous simulation results are easily obtained. To avoid this, software simulation and actual printed circuit board testing are usually used, with the simulation results verified using actual printed circuit board test results. During the testing process, the minimum limit parameters of the electrical characteristic parameter test must be determined first, and then the maximum limit parameters of the electrical characteristic parameter test must be determined through multiple tests.

[0004] In the process of realizing the present invention, the inventors discovered that the prior art has at least the following technical problems:

[0005] Since each test needs to be performed on an actual printed circuit board, multiple printed circuit boards need to be manufactured to complete the test, resulting in low test efficiency and high test costs. Summary of the Invention

[0006] The variable link, CPU link and high-speed interface connection module, as well as the test system and method provided by the present invention can use multiple groups of signal lines of the variable link module to test the electrical characteristic limit capabilities of the CPU, eliminating the need for multiple production of printed circuit boards, reducing test costs and improving test efficiency.

[0007] In a first aspect, the present invention provides a variable link module, comprising a printed circuit board and at least one group of signal lines arranged on the printed circuit board; wherein,

[0008] Communication interfaces are respectively provided at both ends of each signal line, one of which is used for communication connection with the CPU, and the other is used for communication connection with the high-speed interface connector.

[0009] Optionally, a plurality of groups of signal lines are provided on the printed circuit board, wherein each group of signal lines corresponds to a signal loss value, and the signal loss values ​​corresponding to the plurality of groups of signal lines can form a sequence that increases in increments according to a predetermined step value.

[0010] Optionally, the multiple groups of signal lines are arranged in order from low to high according to the corresponding signal loss values.

[0011] In a second aspect, the present invention provides a CPU link module, comprising:

[0012] printed circuit boards,

[0013] a processor, disposed on the printed circuit board;

[0014] A group of signal lines are arranged on the printed circuit board, one end of the signal line is communicatively connected to the processor, and the other end of the signal line is provided with a communication interface, and the communication interface is used to communicate with the variable link module.

[0015] In a third aspect, the present invention provides a high-speed interface connection module, comprising:

[0016] printed circuit boards,

[0017] A high-speed interface connector is provided on the printed circuit board;

[0018] A group of signal lines are arranged on the printed circuit board, one end of the signal line is communicatively connected to the high-speed interface connector, and the other end of the signal line is provided with a communication interface, which is used to communicate with the variable link module.

[0019] In a fourth aspect, the present invention provides a limit link testing system, comprising:

[0020] At least one variable link module as described in any one of the above, a CPU link module as described above, a high-speed interface connection module as described above, and a signal testing device;

[0021] Among them, the CPU link module and the high-speed interface connection module can be respectively communicated and connected with the two ends of one group of signal lines of the variable link module to form a high-speed signal link; the signal testing equipment is used to test the signal quality of the high-speed signal link.

[0022] Optionally, it further includes a flexible cable, wherein both ends of the flexible cable are provided with communication interfaces;

[0023] The flexible cable is used to connect the CPU link module and one of the signal lines of the variable link module, or,

[0024] The flexible cable is used to communicatively connect the high-speed interface connection module and one group of signal lines of the variable link module.

[0025] Optionally, there are multiple variable link modules, wherein the signal loss values ​​corresponding to all the signal lines of the multiple variable link modules can form a series that increases in a predetermined step value.

[0026] In a fifth aspect, the present invention provides a limit link testing method, which is performed using any of the above-mentioned limit link testing systems, comprising:

[0027] selecting a predetermined signal line from the variable link module;

[0028] Connecting the predetermined signal line to the CPU link module and the high-speed interface connection module to form a high-speed signal link;

[0029] Performing a signal test on the high-speed signal link;

[0030] When the test result is a first state, determining that the current link is a limit link;

[0031] When the test result is the second state, a predetermined signal line is reselected from the variable link module according to the signal test result.

[0032] Optionally, when selecting a predetermined signal line for the first time, the method further includes:

[0033] The link loss value of the high-speed signal interface of the CPU is evaluated, and a predetermined signal line is selected according to the evaluation result.

[0034] Optionally, after determining that the current link is a critical link, the method further includes:

[0035] A network analyzer is used to fit the link between the communication interface of the CPU link module in the extreme link and the communication interface of the high-speed interface connection module.

[0036] In the present invention, at least one set of signal lines is communicatively connected to the CPU and the high-speed interface connector to form a signal link, thereby enabling the testing results of the corresponding set of signal lines to be obtained. By testing the links formed by different signal lines in the same variable link module, or different signal lines in different variable link modules, the electrical characteristic limit capability of the CPU can be determined based on the test results. Therefore, during the testing process, the electrical characteristic limit capability of the CPU can be determined simply by connecting and testing using the variable link module, eliminating the need for multiple printed circuit board production processes. This improves testing efficiency and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1Schematic diagram of a variable link module according to an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a CPU link module according to another embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of a high-speed interface connection module according to another embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a limit link test system according to another embodiment of the present invention;

[0041] Figure 5 Schematic diagram of a limit link testing method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0043] The embodiment of the present invention provides a variable link module 100, such as Figure 1As shown, it includes a printed circuit board 110 and at least one group of signal lines 120 arranged on the printed circuit board 110; wherein, each of the signal lines 120 is provided with a communication interface 130 at both ends, one communication interface 130 is used to communicate with the CPU, and the other communication interface 130 is used to communicate with the high-speed interface connector. In some embodiments, the signal lines 120 are communication lines formed on the printed circuit board 110 by printing. A communication interface 130 is provided at both ends of each group of signal lines 120, and the communication interface 130 is communicatively connected to the signal lines 120. For multiple groups of signal lines 120, different lengths need to be set, so that different signal attenuation strengths will be generated when communicating through the multiple groups of signal lines 120. Those skilled in the art will understand that for multiple groups of signal lines 120, all can be provided on the same printed circuit board 110, or they can be provided on multiple printed circuit boards 110. When the step value of the attenuation strength of multiple groups of signal lines 120 is small, a larger number of signal lines 120 are required for the electrical characteristic limit capability test of the CPU, which can achieve a more accurate test of the electrical characteristic limit capability, but is not conducive to improving the test efficiency; when the step value of the attenuation strength of multiple groups of signal lines 120 is large, a smaller number of signal lines 120 are required for the electrical characteristic limit capability test of the CPU, which can improve the test efficiency, but it is difficult to achieve an accurate test of the electrical characteristic limit capability.

[0044] In this embodiment, by providing at least one set of signal lines 120 that are communicatively connected to the CPU and the high-speed interface connector to form a signal link, test results for the corresponding set of signal lines 120 can be obtained. By testing the links formed by different signal lines 120 within the same variable link module 100, or different signal lines 120 within different variable link modules 100, the CPU's electrical characteristic limit capability can be determined based on the test results. Therefore, during the testing process, the CPU's electrical characteristic limit capability can be determined simply by using the variable link module 100 for connection and testing, eliminating the need for multiple printed circuit board production runs. This improves testing efficiency and reduces costs.

[0045] As an optional embodiment, the printed circuit board 110 is provided with multiple groups of signal lines 120, wherein each group of signal lines 120 corresponds to a signal loss value, and the signal loss values ​​corresponding to the multiple groups of signal lines 120 can form a sequence that increases by a predetermined step value. In some embodiments, to prevent the loss of a printed circuit board 110 having partial length signal lines 120 among the multiple groups of signal lines 120, in this embodiment, multiple groups of signal lines 120 are provided on the printed circuit board 110. During use, multiple groups of signal lines 120 on a single printed circuit board 110 can be used for testing, thus avoiding difficulties in testing the electrical characteristics and capacity limits of the CPU due to the loss of a printed circuit board 110 having partial length signal lines 120.

[0046] As an optional embodiment, the multiple groups of signal lines 120 are arranged in ascending order according to their corresponding signal loss values. In some embodiments, by arranging the signal lines 120 in ascending order according to their loss values, the variable link module 100 can be moved unidirectionally during testing, avoiding reciprocating movement paths and reducing the length of the movement path during testing, thereby improving testing efficiency.

[0047] The embodiment of the present invention further provides a CPU link module 200, such as Figure 2 As shown, including:

[0048] printed circuit board 210,

[0049] The processor 240 is disposed on the printed circuit board 210. In some embodiments, the processor 240 is a CPU to be tested. During the test, the test target is the electrical characteristic limit capability of the processor 240 on the printed circuit board 210.

[0050] A set of signal lines 220 are provided on the printed circuit board 210. One end of each signal line 220 is communicatively connected to the processor 240, and the other end of each signal line 220 is provided with a communication interface 230 for communicating with the variable link module 100. In some embodiments, the signal lines 220 are communication lines printed on the printed circuit board 210; the communication signal lines 220 communicatively connect the high-speed signal interface of the processor 240 with the communication interface 230. The provision of the communication interface 230 on the CPU link module 200 allows for a detachable communication connection between the CPU link module 200 and the variable link module 100, facilitating the connection of data lines of varying lengths within the variable link module 100 to the CPU link module 200.

[0051] In this embodiment, by providing at least one set of signal lines 220 that are communicatively connected to the CPU and the high-speed interface connector to form a signal link, test results for the corresponding set of signal lines 220 can be obtained. By testing the links formed by different signal lines 220 in the same variable link module 100, or different signal lines 220 in different variable link modules 100, the electrical characteristic limit capability of the CPU can be determined based on the test results. Therefore, during the testing process, the electrical characteristic limit capability of the CPU can be determined simply by using the variable link module 100 for connection and testing, eliminating the need for multiple printed circuit board production processes. This improves testing efficiency and reduces costs.

[0052] The embodiment of the present invention further provides a high-speed interface connection module 300, such as Figure 3 As shown, including:

[0053] printed circuit board 310,

[0054] A high-speed interface connector 340 is disposed on the printed circuit board 310. In some embodiments, the high-speed interface connector 340 is a physical interface connector used for sending and receiving high-speed signals to the CPU. It typically communicates with a high-speed interface of an external device to facilitate high-speed signal communication between the CPU and the external device. Because the high-speed interface is a physical interface for communication between the CPU and the external device, it must be communicatively connected to the CPU.

[0055] A set of signal lines 320 are provided on the printed circuit board 310. One end of each signal line 320 is communicatively connected to the high-speed interface connector 340. The other end of each signal line 320 is provided with a communication interface 330 for communicating with the variable link module 100. In some embodiments, the signal lines 320 are communication lines printed on the printed circuit board 310; the communication signal lines 320 communicatively connect the high-speed interface connector 340 with the communication interface 330. The provision of the communication interface 330 on the high-speed interface connection module 300 allows for a detachable communication connection between the high-speed interface connection module 300 and the variable link module 100, facilitating the connection of data cables of varying lengths within the variable link module 100 to the high-speed interface connection module 300.

[0056] In this embodiment, by providing at least one set of signal lines 320 that are communicatively connected to the CPU and the high-speed interface connector 340 to form a signal link, test results for the corresponding set of signal lines 320 can be obtained. By testing the links formed by different signal lines 320 in the same variable link module 100, or different signal lines 320 in different variable link modules 100, the electrical characteristic limit capability of the CPU can be determined based on the test results. Therefore, during the testing process, the electrical characteristic limit capability of the CPU can be determined simply by using the variable link module 100 for connection and testing, eliminating the need for multiple printed circuit board production processes. This improves testing efficiency and reduces costs.

[0057] The embodiment of the present invention also provides a limit link test system, such as Figure 4 As shown, it includes: at least one variable link module 100 as described in any one of the above, a CPU link module 200 as described above, a high-speed interface connection module 300 as described above, and a signal testing device; wherein the CPU link module 200 and the high-speed interface connection module 300 can be respectively connected to the two ends of one group of signal lines 120 of the variable link module 100 to form a high-speed signal link; the signal testing device is used to test the signal quality of the high-speed signal link. In some embodiments, the variable link module 100, the CPU link module 200, and the high-speed interface connection module 300 are connected together to form a link in which the CPU can communicate with external devices for high-speed signals, and then the signal quality of the link is tested by a signal testing device such as an oscilloscope. The electrical characteristic limit capability of the CPU's high-speed interface can be determined by the test results of the link formed by the signal lines 120 of different lengths in the variable link module 100.

[0058] In this embodiment, by providing at least one set of signal lines 120 that are communicatively connected to the CPU and the high-speed interface connector to form a signal link, test results for the corresponding set of signal lines 120 can be obtained. By testing the links formed by different signal lines 120 within the same variable link module 100, or different signal lines 120 within different variable link modules 100, the CPU's electrical characteristic limit capability can be determined based on the test results. Therefore, during the testing process, the CPU's electrical characteristic limit capability can be determined simply by using the variable link module 100 for connection and testing, eliminating the need for multiple printed circuit board production runs. This improves testing efficiency and reduces costs.

[0059] As an optional implementation, continue as Figure 4As shown, the flexible cable 400 is further included, with communication interfaces 130 provided at both ends of the flexible cable 400. The flexible cable 400 is used to communicatively connect the CPU link module 200 with one group of signal lines 120 of the variable link module 100, or the flexible cable 400 is used to communicatively connect the high-speed interface connection module 300 with one group of signal lines 120 of the variable link module 100. In some embodiments, the CPU link module 200 and the variable link module 100 are connected via the flexible cable 400, and the high-speed interface connection module 300 and the variable link module 100 are connected via the flexible cable 400. This can improve the flexibility of the connection method, reduce the space requirement during the testing process, and allow the three modules to be placed in appropriate positions without being restricted by the connection method.

[0060] As an optional embodiment, there are multiple variable link modules 100, wherein the signal loss values ​​corresponding to all of the signal lines 120 in the multiple variable link modules 100 can form a sequence that increases in increments by a predetermined step size. In some embodiments, because the range of lengths of the signal lines 120 in a single variable link module 100 is relatively small, multiple variable link modules 100 are provided in the test system to maximize the range of signal attenuation values ​​covered by the test system and improve test accuracy.

[0061] An embodiment of the present invention further provides a limit link testing method, which is performed using any of the above-mentioned limit link testing systems, including:

[0062] A predetermined signal line 120 is selected from the variable link module 100. In some embodiments, when selecting the predetermined signal line 120, two situations need to be considered. If the current selection is the first time, the link loss value of the high-speed signal interface of the CPU needs to be evaluated first, and a signal line 120 with a loss value close to the evaluation result is selected based on the evaluation result. If it is not the first time, a judgment needs to be made based on the previous test result. The predetermined signal line 120 is connected to the CPU link module 200 and the high-speed interface connection module 300 to form a high-speed signal link. In some embodiments, forming a high-speed signal link means forming a communication connection between the three modules through a detachable connection of the communication interface.

[0063] Perform signal testing on the high-speed signal link; in some embodiments, testing the signal link refers to testing the physical signal using a signal testing device such as an oscilloscope, and the test results may be, for example, eye height and eye width parameters of a signal eye diagram.

[0064] When the test result is in the first state, the current link is determined to be a limit link; when the test result is in the second state, the predetermined signal line 120 is reselected from the variable link module 100 based on the signal test result. In some embodiments, by collecting the test results of the current link, it can be determined whether the edge threshold of the electrical characteristic limit capability is currently found. For example, when looking for the upper limit value of the electrical characteristic limit capability, the current signal line 120 is numbered X. If the previous test result meets the high-speed signal protocol standard, the signal line numbered X+1 is selected to form the corresponding link, and the eye diagram is measured to obtain the eye height and eye width parameters. The link is changed in this way until a value that does not meet the protocol standard is found. If the standard is not met, the link corresponding to the signal line numbered X-1 is selected, and the eye diagram is measured to obtain the eye height and eye width parameters. The link is changed in this way until a value that meets the protocol standard is found. Finally, the variable link that meets the protocol standard the most is found to be the limit link of the physical signal. When looking for the lower limit of the electrical characteristic capability, the process is opposite to that of finding the upper limit. If the previous test result meets the standard, X-1 is selected to form the corresponding link. If the standard is not met, the link corresponding to X+1 is selected until a value that meets the protocol standard is found. Finally, the minimum variable link that meets the protocol standard is found as the limit link of the physical signal.

[0065] In this embodiment, by providing at least one set of signal lines 120 that are communicatively connected to the CPU and the high-speed interface connector to form a signal link, test results for the corresponding set of signal lines 120 can be obtained. By testing the links formed by different signal lines 120 within the same variable link module 100, or different signal lines 120 within different variable link modules 100, the CPU's electrical characteristic limit capability can be determined based on the test results. Therefore, during the testing process, the CPU's electrical characteristic limit capability can be determined simply by using the variable link module 100 for connection and testing, eliminating the need for multiple printed circuit board production runs. This improves testing efficiency and reduces costs.

[0066] As an optional embodiment, when the predetermined signal line 120 is selected for the first time, it also includes: evaluating the link loss value of the high-speed signal interface of the CPU, and selecting the predetermined signal line 120 based on the evaluation result. Since there is no previous test result as a reference when the predetermined signal line 120 is selected for the first time, it is necessary to first determine a reference value for selecting the predetermined signal line 120. For example, the insertion loss value of the high-speed IO total link can be evaluated first, and the evaluation result is XdB. The link closest to XdB is selected from the variable link design. In this embodiment, the reference value is determined by estimation rather than random selection, which can reduce the difference between the first selection of the predetermined signal line 120 and the edge value of the electrical characteristic limit capability, reduce the number of tests, and improve test efficiency.

[0067] As an optional embodiment, after determining that the current link is a limit link, the method further includes fitting the link between the communication interface 130 of the CPU link module 200 and the communication interface 130 of the high-speed interface connection module 300 in the limit link using a network analyzer. In some embodiments, since the test link includes communication connection via the communication interface 130 and / or the flexible cable 400, the test process includes not only the attenuation value of the printed signal line 120 but also the attenuation value of the communication interface 130 and / or the flexible cable 400. To obtain an accurate PCB link design, the link needs to be fitted. For example, the fitting process can include pre-extracting the loss values ​​of the variable link board and the communication interface 130 and / or the flexible cable 400 using a network analyzer. Then, with reference to the loss values ​​of the link containing only the PCB signal line 120, the loss values ​​of the variable link board, the communication interface 130 and / or the flexible cable 400 are fitted onto a curve. Thus, based on the test results, the corresponding link containing only the PCB signal line 120 can be directly found on the curve. For example, during the curve fitting process, it was discovered that the loss value of the link formed by the signal line 120 of length a in the variable link module 100 and the flexible cable 400 was equivalent to the loss value of the signal line 120 of length b in a link consisting only of the PCB signal line 120. a and b are typically different lengths; for example, b is typically greater than a. By combining multiple a values ​​and corresponding b values, a fitted curve can be determined, facilitating subsequent link search for the PCB signal line 120.

[0068] Those skilled in the art will appreciate that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A limit link test system, characterized in that: include: at least one variable link module, a CPU link module, a high-speed interface connection module, and a signal test device; The variable link module includes a first printed circuit board and a plurality of first signal lines arranged on the first printed circuit board, wherein the first signal lines are communication lines formed on the first printed circuit board; Each of the first signal lines is provided with a first communication interface at both ends, one of the first communication interfaces being used for communication connection with the CPU, and the other of the first communication interfaces being used for communication connection with the high-speed interface connector, so that when the electrical characteristic limit capability of the CPU is tested, at least one group of the first signal lines is communicatively connected to the CPU and the high-speed interface connector to form a signal link; each group of the first signal lines corresponds to a signal loss value, and the signal loss values ​​corresponding to the multiple groups of the first signal lines can form a sequence that increases in a predetermined step value; The CPU link module includes: a second printed circuit board, A CPU is provided on the second printed circuit board; a set of second signal lines, disposed on the second printed circuit board, one end of the second signal line being communicatively connected to the CPU, and the other end of the second signal line being provided with a second communication interface, the second communication interface being used for communicating with the variable link module; The high-speed interface connection module includes: The third printed circuit board, a high-speed interface connector, disposed on the third printed circuit board; a set of third signal lines, disposed on the third printed circuit board, one end of the third signal line being communicatively connected to the high-speed interface connector, and the other end of the third signal line being provided with a third communication interface, the third communication interface being used for communicating with the variable link module; A flexible cable, the flexible cable being used to communicatively connect the CPU link module and one of the signal lines of the variable link module, and to communicatively connect the high-speed interface connection module and one of the signal lines of the variable link module; Among them, the second communication interface on the CPU link module and the third communication interface on the high-speed interface connection module can be respectively communicated and connected with the two ends of one group of first signal lines of the variable link module to form a high-speed signal link; the signal testing equipment is used to test the signal quality of the high-speed signal link.

2. The extreme link test system according to claim 1, characterized in that: Communication interfaces are provided at both ends of the flexible cable.

3. The extreme link test system according to claim 1, characterized in that: There are multiple variable link modules.

4. A limit link testing method, characterized in that: The test is performed using the extreme link test system according to any one of claims 1 to 3, comprising: selecting a predetermined signal line from the variable link module; Connecting the predetermined signal line to the CPU link module and the high-speed interface connection module to form a high-speed signal link; Performing a signal test on the high-speed signal link; When the test result is in the first state, the current link is determined to be a limit link; the test result being in the first state indicates that the link currently undergoing signal testing is the limit link that satisfies the high-speed signal protocol standard the most among all links, or is the limit link that satisfies the high-speed signal protocol standard the least among all links; When the test result is in the second state, a predetermined signal line is reselected from the variable link module based on the test result; the test result being in the second state indicates that it is uncertain based on all current test results whether the link currently undergoing signal testing is the limit link that satisfies the high-speed signal protocol standard the most among all links, or is the limit link that satisfies the high-speed signal protocol standard the least among all links; After determining that the current link is a limit link, the method further includes: using a network analyzer to fit the link between the second communication interface of the CPU link module in the limit link and the third communication interface of the high-speed interface connection module to extract loss values ​​of the variable link board and the first communication interface and / or the flexible cable, and referencing the loss values ​​of the link with only the first signal line to fit the loss values ​​of the variable link board and the first communication interface and / or the flexible cable onto a curve.

5. The extreme link testing method according to claim 4, characterized in that: When selecting a predetermined signal line for the first time, it also includes: The link loss value of the high-speed signal interface of the CPU is evaluated, and a predetermined signal line is selected according to the evaluation result.

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