Voltage glitch detection in integrated circuits

Abstract

An integrated circuit for hardware security includes a voltage glitch detection processing system including an oscillator circuit that generates and outputs a local oscillator clock that is a function of a supply voltage, and a counter that is clocked by the oscillator circuit to generate at least one count value, and a capture section that synchronizes the at least one count value into a system clock domain for detecting voltage glitches in the supply voltage.

Description

Technical Field

[0001] This disclosure generally relates to security protection in data processing systems, and more specifically, to power supply voltage glitches detection techniques for preventing fault attacks in devices including integrated circuits. Background Technology

[0002] Data processing systems, such as automotive controller chips, set-top box systems, chip cards, and other system-on-a-chip (SoC) circuits, are increasingly vulnerable to power supply voltage glitches. These glitches can include positive or negative voltage spikes that reach or process stored data. A prominent hacking technique is the so-called glitch attack, in which voltage spikes are applied. This can cause transistors in a chip's integrated circuit (IC) to switch states unnecessarily and unpredictably. For example, a voltage glitch applied to the power supply voltage can temporarily change the threshold voltage of a transistor or logic gate, causing the logic of the embedded central processing unit (CPU) to "skip" instructions and subsequently cause the CPU to ignore specific security checks in the software executed by the CPU. This allows a hacker to control parts of the logic, hijack the data before encryption, gain information about the device architecture, and so on.

[0003] A common method for detecting voltage glitches is to connect an analog detector, such as a voltage sensor, to the chip's voltage supply line. However, such voltage supply lines are not easily ported to other process nodes, such as the 16nm FinFET process, which makes the integration of analog sensor systems more difficult. Summary of the Invention

[0004] As will be understood, the disclosed embodiments include at least the following embodiments. In one embodiment, an integrated circuit for hardware security includes a voltage glitch detection processing system, the voltage glitch detection processing system comprising: an oscillator circuit that generates and outputs a local oscillator clock as a function of a power supply voltage; a counter that is timed by the ring oscillator to generate at least one count value; and a capture segment that synchronizes the at least one count value to a system clock domain for detecting voltage glitch in the power supply voltage.

[0005] Alternative embodiments of the integrated circuit for hardware security include one or any combination of the following features.

[0006] The voltage glitch detection and processing system further includes a clock pulse gate, which generates a gated clock from the local oscillator clock to control the ripple counter to receive the local oscillator clock.

[0007] The capture segment synchronizes the count value to the system clock domain after the count value has stabilized in response to the gated clock.

[0008] The local oscillator clock is stopped to allow the count value to stabilize within the stabilization period.

[0009] The ripple counter has a reset input for clearing the at least one count value to zero.

[0010] After each cycle, the current value of at least one count value of the counter is captured, and the counter is reset to establish a new cycle.

[0011] The counter increments by at least one count value on the clock edge of the gated clock, and the gated clock output from the clock pulse gate is provided at the rising edge of the counting pulse and applied to the counting pulse.

[0012] The value of the at least one counter is directly dependent on the power supply voltage during the measurement period when the clock pulse gate is open and the local oscillator clock passes through the clock pulse gate to reach the counter, and the resolution of the voltage glitch detection processing system is determined by the number of ring oscillator clocks in the measurement period.

[0013] The integrated circuit further includes an error detection system, wherein at least one count value is output from the counter to the error detection system, and the error detection system generates an error signal when the at least one count value differs from a reference value by a predetermined margin.

[0014] The integrated circuit further includes a reference adaptation function, wherein the reference value is adapted at regular time intervals to the average value of the count value received in the previous time interval.

[0015] The integrated circuit further includes a plurality of clock pulse gates, each of which generates a gated clock for a plurality of counters connected in parallel with the clock pulse gate, the plurality of counters generating continuous glitch detection in each clock cycle of the system clock.

[0016] The integrated circuit further includes a clock and capture control module that outputs a clock enable signal to the clock pulse gate, such that the gated clock, in response to the local oscillator clock, is applied to only one of the counters at a time.

[0017] The clock pulse gate is a logic AND gate, each of which has a first input for receiving the local oscillator clock from the ring oscillator and a second input for receiving the clock enable signal from the clock and capture control module.

[0018] The integrated circuit further includes a selector that controls the output of the counter such that a count value is captured by the capture segment at a time.

[0019] In one embodiment, a voltage glitch detection processing system for a system-on-a-chip (SOC) includes: an oscillator circuit that generates and outputs a local oscillator clock as a function of a power supply voltage; and a counter that is timed by the ring oscillator to generate at least one count value synchronized with the system clock to detect voltage glitch in the power supply voltage.

[0020] Alternative embodiments of the voltage glitch detection and processing system include one or any combination of the following features.

[0021] The voltage glitch detection and processing system further includes a clock pulse gate (204) that controls the local oscillator clock to allow the at least one count value output from the counter to stabilize before being captured into the domain of the system clock, such that the clock value is directly related to the power supply voltage.

[0022] The at least one count value of the counter is timed by the local oscillator clock, sampled in a fixed time frame defined by the system clock, and compared with subsequent count values.

[0023] The voltage glitch detection and processing system further includes multiple clock pulse gates, each of which generates a gated clock for a counter in a plurality of counters connected in parallel with the clock pulse gate, the plurality of counters generating continuous glitch detection in each clock cycle of the system clock.

[0024] The system is constructed and arranged to function as a frequency monitor.

[0025] In one embodiment, a method for detecting power supply voltage glitches at a hardware security integrated circuit includes: generating a first clock based on a power supply voltage; generating a count value in response to the first clock; and synchronizing the count value to a second clock domain to detect voltage glitches in the power supply voltage.

[0026] Alternative embodiments of the voltage glitch detection and processing system include one or any combination of the following features.

[0027] The first clock is the local oscillator clock, and the second clock is the system clock. Attached Figure Description

[0028] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0029] Figure 1 This is a block diagram of a computer chip according to a selected embodiment of the present disclosure.

[0030] Figure 2 This is a block diagram of a voltage glitch detector according to a selected embodiment of the present disclosure.

[0031] Figure 3 This illustrates a selected embodiment according to the present disclosure. Figure 1 and 2 A set of timing waveforms representing different stages of the synchronization process performed by the voltage glitch detector.

[0032] Figure 4 This is a block diagram of another voltage glitch detection and processing system according to a selected embodiment of the present disclosure.

[0033] Figure 5 This illustrates a selected embodiment according to the present disclosure. Figure 4 A set of timing waveforms for different stages of the synchronization process of a voltage glitch detector.

[0034] Figure 6 This is a block diagram of an automotive microcontroller including a voltage glitch detector according to a selected embodiment of the present disclosure.

[0035] Figure 7 This is a flowchart illustrating a method for detecting and preventing glitch attacks on a data processing system according to a selected embodiment of the present disclosure. Detailed Implementation

[0036] To address the aforementioned shortcomings and other drawbacks of modern glitch detectors known to those skilled in the art, embodiments of the present invention include security detection systems, devices, and methods utilizing standard cells in the digital core of a computer chip or integrated circuit (IC), etc., to provide continuous protection against voltage glitch or associated electrical glitch or power supply glitch. The glitch detection mechanism overcomes the portability problems encountered by conventional analog glitch sensors by providing a synthesizable detector composed entirely of various electronic logic functions available from any standard cell library. This synthesizable detector can be applied to digital designs of different chip types for embedding in logic blocks.

[0037] Furthermore, the security detection system, apparatus, and method of the present invention offer greater scalability and higher resolution than conventional glitch detection systems because the ripple counter is configured to receive a direct clock. On the other hand, conventional glitch detection systems typically rely on delay lines, formed by inverters or buffers or associated fixed-delay logic elements that output the result to a capture trigger, and arranged to compensate for unstable input signals. However, this consumes valuable circuit level areas of the integrated circuit (IC). For example, a delay line can be used to determine whether there is a difference between the time when a signal should stabilize and the time when the signal is actually captured, specifically by measuring the delay of the signal passing through the logic gates of the delay line. The delay line must be long enough to cover at least one clock cycle of the applied clock, requiring a considerable physical area for the detector. Additionally, conventional delay-line-based glitch detectors require a corresponding increase in the length of the delay line to perform glitch detection at a smaller clock frequency. For example, reducing the clock from 96 MHz to 12 MHz requires an eightfold increase in the size of the delay device, which is undesirable in modern chip designs that emphasize minimizing logic elements. The additional logic required by the delay line consumes valuable chip resources. These resources limit the chip in terms of additional scaling, clock rate increases, or other required chip improvements.

[0038] Furthermore, the safety detection system, apparatus, and method of the present invention provide automatic adaptation to changing environmental conditions by maintaining a detection margin as small as possible and detecting glitch that is invisible compared to conventional analog and digital glitch detection systems, using programmable margin settings. Specifically, a typical analog glitch detection mechanism is constructed and arranged to detect voltages above or below a threshold voltage level. The voltage level is defined by a maximum and minimum permissible power supply voltage level (margin). Here, glitches with voltages below this level cannot be detected. The safety detection system, apparatus, and method of the present invention can detect glitches that exceed the current reference margin. The relevant voltage level can be lower / higher than the level at which the analog sensor would normally trigger. In some embodiments, the safety detection system, apparatus, and method of the present invention automatically adapts to temperature and voltage changes and maintains the measurement range in an optimal position to improve the sensitivity of glitch detection.

[0039] Considering the degradation caused by voltage spikes passing through computer chips due to the capacity of the power supply network, the system of the present invention requires fewer spike detectors to protect the specific safety-critical IC areas of concern.

[0040] Therefore, the voltage glitch detector according to embodiments of the present invention can be constructed and arranged for various automotive, government and industrial applications requiring security features, such as chip-based automotive hardware security engines or related security subsystems that require on-chip security features to prevent unauthorized access by hackers who may attempt to control the operation of the vehicle via the chip.

[0041] Figure 1 This is a block diagram of a computer chip 10 according to some embodiments. Chip 10 may include a set of electronic circuits, such as transistors or other combinations of components formed of metal, oxide, silicon, etc. Chip 10 may include a processor core, memory, input / output (I / O), and peripheral components (not shown) that receive direct power supply voltage from, for example, the power supply of another IC, and may be implemented, for example, as described herein. Figure 6 The various automotive, industrial, and consumer applications described.

[0042] Chip 10 may include at least one power supply voltage glitch detection processing system 100 and at least one digital circuit 12. According to selected embodiments of this disclosure, the voltage glitch detection processing system 100, also referred to as a voltage glitch detector, may be implemented as part of a system-on-a-chip (SoC) device or an associated computer chip via the digital circuit 12. The digital circuit 12 may include various electronic components, such as combinations of logic gates (e.g., AND gates, OR gates, and XOR gates), flip-flops, etc., available in standard cell libraries. In some embodiments, the digital circuit 12 may include a post-processing section comprising an error detection system for generating an alarm, event, or error signal when an unwanted glitch is detected.

[0043] The voltage glitch detection processing system 100 can also be formed from components of a standard cell library. The voltage glitch detection processing system 100 is constructed and arranged to perform glitch detection functions, including filtering and removing unwanted voltage glitch relative to the input signal received by the digital circuitry 12, but in a manner that allows for easier scaling of the system clock frequency compared to conventional glitch detectors. Specifically, the voltage glitch detection processing system 100 requires fewer digital logic units forming delay lines than a conventional glitch detector, while reducing the overall area of ​​the hardware components of the voltage glitch detection processing system 100. Additionally, the region dependence on clock frequency is reduced. On the other hand, the delay lines provided by conventional glitch detectors require scaling the delay line length, and thus the detector size increases linearly with the clock cycle. The glitch detection processing system 100 of the present invention only requires scaling the ring oscillator depending on the resolution of the detector. Since it is a direct-timing counter and does not require an initial delay line, the region size is also reduced.

[0044] This reduction also improves the resolution of glitch detection and automatically adapts to environmental conditions such as temperature variations and noise conditions, as glitch will experience less degradation as it passes through chip 10 due to the power grid. The voltage glitch detection processing system 100 relies on a counter instead of a delay line and captured values ​​for glitch detection, thus requiring fewer logic components, such as delay elements, and providing additional advantages over conventional glitch detection systems as described herein. In some embodiments, a count value output from a ripple counter is output to a post-processing section of an IC including an error detection system (not shown), which compares the captured count value with a calculated reference value to generate an error signal if the difference between the result (i.e., the count value) and the reference value exceeds a programmable and predetermined margin value. The reference is calculated based on the highest and lowest results (i.e., the count value during a given time period, as determined by the programmable counter). Thus, the reference can be adapted to acceptable variations in environmental conditions, as long as the variations are within acceptable limits, such as temperature increases. In some embodiments, the integrated circuit 10 includes a reference adaptation function, wherein the reference value is adapted at regular time intervals to the average of the count values ​​received in the previous time interval.

[0045] The aforementioned scalable resolution is achieved because the glitch detector 100 includes a ripple counter configured to receive a direct clock. Adding a single bit to the ripple counter and post-processing logic doubles the resolution of the glitch detector. For example, adding a single flip-flop would require doubling the detector's resolution. On the other hand, a conventional detector would require doubling the number of flip-flops to achieve a similar increase in resolution. Therefore, the resolution provided by the glitch detector 100 of this invention can be enhanced by ensuring that all process variations in the integrated circuit's manufacturing parameters have sufficient measurement range to avoid erroneous affirmations.

[0046] Figure 2 yes Figure 1 A block diagram of a voltage glitch detection and processing system 100 is shown. As illustrated, in some embodiments, the voltage glitch detection and processing system 100 includes a local clock generation circuit 202, a clock pulse gate 204, a multi-bit counter 206, and one or more capture triggers of a capture segment 208. Although the voltage glitch detection and processing system 100 is described as a particular embodiment... Figure 1 The above is shown and described, but other configurations and implementations may also be applied.

[0047] In some embodiments, the local clock generation circuit 202 includes an oscillator circuit, such as a ring oscillator for timing the counter 206. Although Figure 2Ripple counter 206 is shown, but other counter types can be applied similarly. The local oscillator clock OCK is generated by a ring oscillator based on the power supply voltage (V) provided to the various electrical components of the computer chip 10 on the bus or other pipes, lines, etc. DD The frequency of the ring oscillator is generated based on the frequency of the supply voltage, which may have voltage transients, with glitches detected by system 10. Therefore, the output OCK of the ring oscillator can be used to time the ripple counter 206 for a period defined by the applied system clock. The ring oscillator frequency is determined by the oscillator's construction, and consequently by the length of the ring oscillator delay chain. The propagation delay in the ring oscillator circuit 202 is expressed as the supply voltage (V... DD The function output of ).

[0048] Clock pulse gate 204 is constructed and arranged to stop or gate the local oscillator clock OCK to allow the count value output from ripple counter 206 to stabilize or synchronize before being captured into the clock domain of an external system, as the value may not stabilize to a stable value within a single clock cycle. This value is directly related to the supply voltage, especially when considered in a regular manner according to fixed time frames defined by the system clock. In some embodiments, clock pulse gate 204 includes an enable input (CLK enable) provided by clock enable logic input to an AND gate, etc., that controls the clock, for example, by gating the output so that no clock is output during a predetermined period of the synchronization process, and thereby controlling when counter 206 increments its value. The foregoing illustrates one possible synchronization technique, but is not limited thereto.

[0049] In addition, the clock pulse gate 204 reduces the power consumption of the device and also allows the count value output from the ripple counter 206 to stabilize.

[0050] Ripple counter 206 is constructed and arranged to receive a gated clock signal directly from clock pulse gate 204. As previously mentioned, ripple counter 206 is timed by ring oscillator 202, etc. Due to the dependence of ring oscillator 202 on the supply voltage, when the oscillator clock OCK clocks ripple counter 206 for a predetermined time period defined by the system clock, the count value in ripple counter 206 will be related to the supply voltage (V). DD The count value is directly related to the voltage glitch detection and processing system 100, and is subsequently generated in a regular manner based on a fixed time frame, i.e., defined by the period of the clock used in the system to which the system is designed to be protected. The ripple counter 206 has a reset input for clearing the count value. More specifically, a ring oscillator output is used to time the ripple counter 206 for a period of time defined by the applied system clock having a static clock frequency. After each cycle, the current value of the counter 206 is captured, and the counter 206 is reset to establish a new cycle.

[0051] The capture section 208 includes one or more capture triggers configured and arranged to synchronize bit-level signals, and more specifically, as part of the synchronization process, to capture the count value output from the ripple counter 206 into the system clock domain. The output of the capture section 208 can be provided to a post-processing section of the IC, or to an external error correction device communicating with chip 10, etc.

[0052] The basic concept of this invention is to use subsequent values ​​of one or more counters, timed by a voltage-dependent clock source such as a ring oscillator clock, to sample these values ​​within fixed time frames defined by a system clock, and to compare these subsequent values ​​with each other by generating a reference value from the count values. As described herein, the concept of the invention is characterized by comparing voltage-dependent count values ​​captured at regular time intervals defined by the system clock. A reference is calculated from the count values. If the count value exceeds the reference plus a specific margin, an error signal is generated. The use of two clock sources for timing the counters and generating the time reference requires a so-called cross-clock domain between the clock sources. One such concept is described below.

[0053] In order to improve Figure 1 and 2 For an understanding of the operation of the voltage glitch detector described in [the document], please refer to [the document]. Figure 3 The Figure 3 A timing diagram 300 showing the relevant input and output signals from the voltage glitch detector 100 is provided.

[0054] like Figure 3As shown, a system clock with a predetermined fixed frequency is provided. As previously described, the result or output of counter 206 depends directly on the supply voltage during the previous measurement cycle, which is defined by the period during which the clock pulse gate 204 is open and the clock from the ring oscillator is passed to the ripple counter. The measurement cycle is defined by the system clock. Depending on the frequency relationship between the ring oscillator and the system clock, some embodiments may use a measurement cycle of one system clock cycle, while other embodiments may use more system clock cycles. The number of ring oscillator clock cycles in the selected measurement cycle defines the possible resolution of the detector. Ripple counter 206 increments the stored count value on the clock edge of the gated clock signal. In some embodiments, the gated clock output from clock pulse gate 204 is provided at the rising edge of the counting pulse and is applied to the counting pulse to synchronize the counter value to the system clock domain. The clock from ring oscillator 202 passing through clock pulse gate 204 is applied to counter 206. This counts the duration for which clock pulse gate 204 is open. The stabilization, capture, and result phases of the synchronization process follow the counting phase, but unlike the counting pulses, they are independent of the supply voltage and therefore less susceptible to glitches in the supply voltage. Specifically, during synchronization, the clock of the ripple counter 206 must stop to allow the count value to stabilize. After the stabilization period, the count value is captured into the system clock domain. Subsequently, the ripple counter 206 is reset, for example, as... Figure 3 The asynchronous reset is shown in the figure.

[0055] Since glitch detection is not performed separately for the clock pulses of the stabilization, capture, and reset phases, it is concluded that glitch detection does not occur in every system clock cycle. However, turning to Figure 4 and 5 Multiple ripple counters can be constructed and arranged to allow the voltage glitch detection processing system to generate continuous glitch detection in each clock cycle and to maintain the count value at each stage of the counting and synchronization process.

[0056] See Figure 4 The circuit diagram of the voltage glitch detection and processing system 400 according to the selected embodiment is described below. At least some components of the voltage glitch detector 400 are the same as or similar to those described with respect to the voltage glitch detection and processing system 100, and therefore will not be repeated for the sake of brevity.

[0057] Clock pulse gates 404A-404D (typically 404) comprise multiple logic gates, such as AND gates. Each clock pulse gate 404 has an output coupled to a ripple counter 406. Each clock pulse gate 404 has a first input configured and arranged to receive a local oscillator clock OCK from a ring oscillator 402 and a second input for receiving a relevant clock enable signal from a clock and capture control module 410.

[0058] The clock and capture control module 510 is configured and arranged to communicate with the clock pulse gate 404 and the selection circuit 412, such as a multiplexer. By means of a clock enable and capture selection signal, the selection circuit 412 controls the clock pulse gate in such a way that the clock from the ring oscillator 402 is applied to only one ripple counter in the ripple counter 406 at a time, and in the case of each system clock, captures the count value from one ripple counter 406. Figure 5 The relevant timing diagram 500 is shown. Specifically, timing diagram 500 illustrates the shift behavior of four parallel pairs of clock pulse gates 404 and ripple counters 406, with shift measurement phases, stable capture phases, and reset phases. The values ​​shown in the diagram are example values ​​408, referred to herein as "results," used to aid in understanding which count value will take over to the capture trigger. A capture selection value defines counter 406, from which the value is taken over to the "result" on the next rising clock edge; for example, if the "capture selection" is 1, the value from counter 1 will take over to the "result."

[0059] As described above, the output of the voltage glitch detection and processing system can be provided to a post-processing section of chip 10, such as the post-processing section of digital circuit 12, or to an external error correction device communicating with chip 10. The post-processing section evaluates this output by comparing a ripple counter value with a reference value. Specifically, a synchronized count value is compared with a reference value, which is calculated from a previous count value. In some embodiments, the reference value may be a fixed value. In other embodiments, as described below, the reference value may be a variable value.

[0060] An error occurs if the difference between the reference value and the result is greater than the programmable positive margin or less than the programmable negative margin. The programmable margin setting allows the voltage glitch detection processing system to adapt to different noise distributions on different chips and applications, ensuring optimal glitch detection rate while avoiding false positives or false negatives. In some embodiments, this is achieved through the security detection system, apparatus, and method of the present invention, which allows continuous glitch detection operations to be performed in each system clock cycle, for example... Figure 4 and 5 As shown in the image.

[0061] Additionally, digital post-processing can be performed to remove the effects of temperature and slow power supply voltage variations on the results, ensuring that the reference value is consistently applied to the measured results. The update rate can be programmed via a timer setting. An update timer (not shown) can be provided to generate a periodic timing reference signal for updating the reference value.

[0062] For each timer cycle, the highest and lowest measurement results (minimum / maximum) are determined. The average of the maximum and minimum measurement results can be used as a reference value. At the end of the timer cycle, these values ​​are averaged against the reference with programmable weights. Programmable weights for the reference allow suppression of large variations in the reference value due to changes in power supply noise attributable to application variations. Therefore, the system can provide automatic adaptation to changing environmental conditions by using programmable margin settings to maintain the detection margin as small as possible and detect glitch that is invisible compared to conventional analog and digital glitch detection systems. Additionally, the safety detection system, apparatus, and method of the present invention can automatically compensate for temperature variations.

[0063] As described herein, embodiments of the present invention detect voltage glitches by comparing successive counts, timed by a ring oscillator and dependent on the supply voltage. The subsequently generated counts may also depend on the frequency of the system clock, as this determines the length of the measurement period. Therefore, in some embodiments, the system is constructed and arranged to function as a frequency monitor without additional structural requirements or changes.

[0064] Figure 6 This is a block diagram of an automotive microcontroller 600 including a voltage glitch detector 620 according to a selected embodiment of this disclosure. The automotive microcontroller 600 can be implemented for various automotive functions, including but not limited to automotive radar systems, braking and stability control, electric power steering (EPS), hybrid and electric vehicle power converters, powertrains, converters, and chargers. Although in Figure 6 The diagram shows a portion of an automotive chip, but the voltage spike detector 620 can be applied to any chip that needs to prevent power supply voltage spikes and contains synthetic digital logic segments. Generally, all security-related chips, integrated circuits, etc., may include features of this invention, such as quantum technology or other protective mechanisms implemented in radio chips provided by the Institute for Defense Analyses (IDA).

[0065] Voltage glitch detector 620 can be respectively with Figures 1 to 5 The voltage glitch detectors 100 and 400 described herein are identical or similar. Voltage glitch detector 620 may be part of security system 608 and communicates with other components of the on-chip automotive microcontroller 600, including but not limited to memory 602, CPU 604, motor control system 606, security system 608, serial communication 610, and input / output (I / O). Specifically, security system 608 is configured and arranged to provide security functions and fault recovery for detecting, isolating, and differentiating computer faults without shutting down the system. Security system 608 implementing voltage glitch detector 620 can provide protection against malicious hacking attacks.

[0066] Figure 7This is a flowchart illustrating a method 700 for detecting and preventing glitch attacks on a data processing system according to a selected embodiment of the present disclosure. Some or all of method 700 may be executed in a computer chip described in the embodiments herein, for example, by a glitch detector hardware engine appropriately connected to a power line.

[0067] At block 702, an oscillator clock signal is generated, the oscillator clock signal having a frequency that depends on the power supply voltage of the circuit of interest.

[0068] At block 704, an oscillator clock signal is used to time a counter for a predetermined amount of time defined by an applied system clock. In some embodiments, the counter is a ripple counter. Other embodiments may include other counter types.

[0069] At box 706, the counter generates a counter value. Due to the dependence of the ring oscillator frequency on the supply voltage, the value in the ripple counter is directly related to the voltage when evaluated in a regular manner based on a fixed time frame. The fixed time frame is defined by the period of the clock used in the system that the detector should protect.

[0070] At box 708, the ripple counter value is synchronized to the system clock domain. In doing so, the oscillator clock can be stopped to allow the value to stabilize. Once stabilized, the value can be captured into the system clock domain.

[0071] At box 710, the aforementioned value is provided to the post-processing computer, for example, Figure 1 Digital circuit 12.

[0072] While the invention has been described herein with reference to specific embodiments, various modifications and variations may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any advantage, benefit, or solution to the problem described herein with reference to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0073] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of such elements.

Claims

1. An integrated circuit for hardware security, characterized in that, include: A voltage glitch detection and processing system, comprising: An oscillator circuit that generates and outputs a local oscillator clock as a function of the power supply voltage; A counter, which is timed by the oscillator circuit to generate at least one count value; A capture segment that synchronizes the at least one count value to the system clock domain for detecting voltage glitches in the power supply voltage; and A selector controls the output of the counter so that a count value is captured by the capture segment at a time.

2. The integrated circuit according to claim 1, characterized in that, The voltage glitch detection and processing system further includes: A clock pulse gate that generates a gated clock from the local oscillator clock to control the counter to receive the local oscillator clock.

3. The integrated circuit according to claim 2, characterized in that, The counter increments by at least one count value on the clock edge of the gated clock, and the gated clock output from the clock pulse gate is provided at the rising edge of the counting pulse.

4. The integrated circuit according to claim 2, characterized in that, The at least one counter value is directly dependent on the power supply voltage during the measurement period when the clock pulse gate is open and the local oscillator clock passes through the clock pulse gate to reach the counter, and the resolution of the voltage glitch detection processing system is determined by the number of oscillator clocks in the measurement period.

5. The integrated circuit according to claim 1, characterized in that, The system also includes an error detection system, wherein at least one count value is output from the counter to the error detection system, and the error detection system generates an error signal when the at least one count value differs from a reference value by a predetermined margin.

6. The integrated circuit according to claim 1, characterized in that, Additionally, it includes multiple clock pulse gates, each of which generates a gated clock for a counter in a plurality of counters connected in parallel with the clock pulse gate, the plurality of counters generating continuous glitch detection in each clock cycle of the system clock.

7. A voltage glitch detection and processing system for a system-on-a-chip device, characterized in that, include: An oscillator circuit that generates and outputs a local oscillator clock as a function of the power supply voltage; A counter, which is timed by the oscillator circuit to generate at least one count value; as well as The selection logic circuit is configured to receive at least one count value from the counter and output a specific count value of the at least one count value associated with the counter; wherein the specific count value is synchronized with the system clock to detect voltage glitches in the power supply voltage.

8. The voltage glitch detection and processing system according to claim 7, characterized in that, Additionally, a clock pulse gate is included, which controls the local oscillator clock to allow the at least one count value output from the counter to stabilize before being captured into the domain of the system clock, such that the clock value is directly related to the power supply voltage.

9. The voltage glitch detection and processing system according to claim 7, characterized in that, Additionally, it includes multiple clock pulse gates, each of which generates a gated clock for a counter in a plurality of counters connected in parallel with the clock pulse gate, the plurality of counters generating continuous glitch detection in each clock cycle of the system clock.

10. A method for detecting power supply voltage glitches at a hardware security integrated circuit, characterized in that, include: The first clock is generated based on the power supply voltage; A count value is generated in response to the first clock; A specific count value is selected from the count values ​​by the selection logic circuit; as well as The specific count value is synchronized to the second clock domain to detect voltage glitches in the power supply voltage.

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