Memory system, memory controller, and method of operating a memory system

Abstract

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the memory system. According to the embodiments of the present disclosure, when a sudden power off (SPO) signal is transmitted from a power management core to a flash memory interface layer core, the memory system can search for a target command to be processed before entering a power-off state in multiple command queues that queue commands to be input to a memory device, queue the target command in a highest-priority command queue having the highest priority among the multiple command queues, and input the target command queued in the highest-priority command queue into the memory device before entering a power-off state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0075461, filed on June 22, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. Background Art

[0004] A memory system (e.g., a storage device) stores data based on a request from a host such as a computer, a mobile terminal (e.g., a smartphone or tablet), or any of various other electronic devices. The memory system may be a device that stores data on a magnetic disk, such as a hard disk drive (HDD), or a device that stores data in a non-volatile memory, such as a solid-state drive (SDD), a universal flash storage (UFS) device, or an embedded MMC (eMMC) device.

[0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive commands from a host and, based on the received commands, may execute or control operations for reading, writing, or erasing data in a volatile memory or nonvolatile memory included in the memory system. The memory controller may drive firmware to execute logic operations for controlling these operations.

[0006] When a sudden power outage (SPO) occurs, the memory system may dump data in the volatile memory to the memory device. The memory system can then perform a recovery operation using the data dumped at power-on to restore the data to the state before the SPO occurred. To minimize the time required to dump data in the volatile memory to the memory device, the memory system may allow the currently executing operation to continue, requiring completion, and may suspend the remaining operations. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a memory system, a memory controller, and a method of operating the memory system that may reduce the time required to dump data to a memory device when a sudden power outage (SPO) occurs.

[0008] In addition, embodiments of the present disclosure may provide a memory system, a memory controller, and a method of operating the memory system that may reduce the time required for a recovery process after an SPO occurs.

[0009] In one aspect, embodiments of the present disclosure may provide a memory system including a memory device and a memory controller for controlling the memory device.

[0010] When the SPO signal is transmitted from the power management core to the flash interface layer core, the memory controller may search for a target command to be processed before entering the power-off state in a plurality of command queues that queue commands to be input to the memory device.

[0011] The memory controller may queue the target command in a highest priority command queue having the highest priority among the plurality of command queues.

[0012] The memory controller may input a target command queued in a highest priority command queue to the memory device before entering the power-off state.

[0013] Before an SPO occurs, the highest priority command queue can be empty.

[0014] The target command may be a command for requesting an operation of writing metadata.

[0015] The plurality of command queues may further include a first priority command queue and a second priority command queue. The memory controller may process commands in the first priority command queue at a higher priority than commands in the second priority command queue. After an SPO occurs, the memory controller may queue a command requesting an internal read operation in the first priority command queue.

[0016] The memory controller may queue the target command in a highest priority command queue until a command for requesting to abort the corresponding operation is transmitted to the flash interface layer core.

[0017] The SPO signal can be directly transmitted from the power management core to the flash interface layer core.

[0018] On the other hand, an embodiment of the present disclosure may provide a memory controller including a memory interface configured to communicate with a memory device, and the memory controller is configured to include a control circuit for controlling the memory device.

[0019] When the SPO signal is transmitted from the power management core to the flash interface layer core, the control circuit may search for a target command to be processed before entering the power-off state in a plurality of command queues that queue commands to be input to the memory device.

[0020] The control circuit may queue the target command in a highest priority command queue having the highest priority among the plurality of command queues.

[0021] The control circuitry may input a target command queued in a highest priority command queue to the memory device before entering the power-down state.

[0022] Before an SPO occurs, the highest priority command queue can be empty.

[0023] The target command may be a command for requesting an operation of writing metadata.

[0024] The plurality of command queues may further include a first priority command queue and a second priority command queue. The control circuit may process commands in the first priority command queue at a higher priority than commands in the second priority command queue. After an SPO occurs, the control circuit may queue a command for requesting an internal read operation into the first priority command queue.

[0025] The control circuit may queue the target command in a highest priority command queue until a command for requesting to abort the corresponding operation is transmitted to the flash interface layer core.

[0026] The SPO signal can be directly transmitted from the power management core to the flash interface layer core.

[0027] On the other hand, embodiments of the present disclosure may provide a method of operating a memory system including a memory device and a memory controller configured to control the memory device.

[0028] The method of operating a memory system may include transmitting an SPO signal from a power management core to a flash interface layer core.

[0029] The method of operating a memory system may include searching a plurality of command queues that queue commands to be input to a memory device for a target command to be processed before entering a power-off state.

[0030] The method of operating a memory system may include queuing the target command in a highest priority command queue having a highest priority among a plurality of command queues.

[0031] The target command may be a command for requesting an operation of writing metadata.

[0032] The plurality of command queues may further include a first priority command queue and a second priority command queue. Commands included in the first priority command queue may be processed with a higher priority than commands in the second priority command queue.

[0033] The method of operating a memory system may include inputting a target command queued into a highest priority command queue to a memory device before entering a power-off state.

[0034] On the other hand, an embodiment of the present disclosure may provide a memory system including a memory device and a memory controller including a first command queue having a first priority, and second and third command queues.

[0035] The memory controller may queue a plurality of commands for the memory device in the second command queue and the third command queue.

[0036] The memory controller may identify a priority of each of the plurality of commands in response to a sudden power off (SPO) signal.

[0037] The memory controller may move a target command having a first priority from at least one of the second command queue and the third command queue to the first command queue.

[0038] The memory controller may move the command having the second priority from the third command queue to the second command queue.

[0039] The memory controller may provide the target command from the first command queue to the memory device.

[0040] According to an embodiment of the present disclosure, the time required to dump data to a memory device when an SPO occurs can be reduced.

[0041] In addition, according to the embodiments of the present disclosure, the time required in the recovery process after the occurrence of SPO can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0043] Figure 1 is a schematic diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0044] Figure 2 is a block diagram schematically illustrating a memory device according to an embodiment of the present disclosure.

[0045] Figure 3 is a diagram illustrating a structure of word lines and bit lines of a memory device according to an embodiment of the present disclosure.

[0046] Figure 4 The operation flow of the memory system according to an embodiment of the present disclosure is shown.

[0047] Figure 5 is a diagram illustrating a highest priority command queue according to an embodiment of the present disclosure.

[0048] Figure 6 is a diagram illustrating an example of states of a plurality of command queues before a sudden power outage (SPO) occurs according to an embodiment of the present disclosure.

[0049] Figure 7 is a diagram illustrating an example of an operation of searching for a target command in a command queue after an SPO occurs according to an embodiment of the present disclosure.

[0050] Figure 8 is a diagram illustrating an example of an operation of queuing a target command in a highest priority command queue after an SPO occurs according to an embodiment of the present disclosure.

[0051] Figure 9 is a diagram illustrating an example of an operation of queuing a command queued in a second-priority command queue into a first-priority command queue after SPO occurs according to an embodiment of the present disclosure.

[0052] Figure 10 is a diagram illustrating a comparison between examples of types of commands queued in a command queue before and after an SPO occurs according to an embodiment of the present disclosure.

[0053] Figure 11 The operation flow of the memory system according to an embodiment of the present disclosure is shown.

[0054] Figure 12 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present disclosure.

[0055] Figure 13 is a diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "an embodiment" or the like do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term "an embodiment" when used herein does not necessarily refer to all embodiments.

[0057] Figure 1 is a schematic diagram showing the configuration of a memory system 100 according to an embodiment of the present disclosure.

[0058] Reference Figure 1 , the memory system 100 may include a memory device 110 configured to store data and a memory controller 120 configured to control the memory device 110 .

[0059] Memory device 110 may include a plurality of memory blocks. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. Operations of memory device 110 may include, for example, read operations, program operations (also referred to as "write operations"), erase operations, etc.

[0060] The memory device 110 may include a memory cell array including a plurality of memory cells (also simply referred to as “cells”) configured to store data. The memory cell array may exist inside a memory block.

[0061] For example, the memory device 110 may be implemented as any of various types such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, perpendicular NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0062] The memory device 110 may be implemented in a three-dimensional array structure. The embodiments of the present disclosure are applicable not only to flash memory devices having a charge storage layer configured as a conductive floating gate, but also to flash memory devices having a charge trap flash memory (CTF) having a charge storage layer configured as an insulating film.

[0063] The memory device 110 may be configured to receive a command and an address from the memory controller 120 and access a region of the memory cell array selected using the address. That is, the memory device 110 may perform an operation corresponding to the received command in a region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0064] For example, the memory device 110 may perform a program operation, a read operation, an erase operation, etc. During a program operation, the memory device 110 may program data in an area selected by an address. During a read operation, the memory device 110 may read data from an area selected by an address. During an erase operation, the memory device 110 may erase data stored in an area selected by an address.

[0065] Memory controller 120 may control write (or program) operations, read operations, erase operations, and background operations for memory device 110. Background operations may include, for example, garbage collection (GC) operations, wear leveling (WL) operations, and / or bad block management (BBM) operations.

[0066] Memory controller 120 may control the operation of memory device 110 at the request of the host. Alternatively, memory controller 120 may control the operation of memory device 110 without a corresponding request from the host, for example, when memory controller 120 performs one or more background operations of the memory device.

[0067] The memory controller 120 and the host may be separate devices. In some cases, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, the memory controller 120 and the host are separate devices.

[0068] The memory controller 120 may include a host interface (I / F) 121 , a memory interface 122 , and a control circuit 123 .

[0069] The host interface 121 may be configured to provide an interface for communicating with a host.

[0070] When receiving a command from a host (HOST), the control circuit 123 may receive the command through the host interface 121 and may perform an operation of processing the received command.

[0071] The memory interface 122 may be connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 may be configured to provide an interface to the memory device 110 and the memory controller 120 in response to the control of the control circuit 123.

[0072] The control circuit 123 may be configured to control the operation of the memory device 110 by performing operations to exercise overall control over the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may also include an error detection and correction (detection / correction) circuit (i.e., an ECC circuit) 126.

[0073] The processor 124 may control the overall operation of the memory controller 120 . The processor 124 may perform logical operations. The processor 124 may communicate with the host through the host interface 121 . The processor 124 may communicate with the memory device 110 through the memory interface 122 .

[0074] The processor 124 may perform the function of a flash translation layer (FTL). The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA by using a mapping table.

[0075] There are various address mapping methods that the FTL can adopt according to the mapping unit. Typical address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0076] The processor 124 may be configured to randomize data received from the host. For example, the processor 124 may randomize the data received from the host using a randomization seed. The randomized data is provided to the memory device 110 as data to be stored and is programmed into the memory cell array.

[0077] During a read operation, the processor 124 may be configured to derandomize data received from the memory device 110. For example, the processor 124 may derandomize the data received from the memory device 110 by using a derandomization seed. The derandomized data may be output to the host.

[0078] The processor 124 may execute firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 may control the overall operation of the memory controller 120 and, in order to perform logical operations, may execute (or drive) the firmware loaded into the working memory 125 during booting.

[0079] Firmware refers to a program running inside the memory system 100 and may include various functional layers.

[0080] For example, the firmware may include a flash translation layer (FTL), a host interface layer (HIL), and / or a flash interface layer (FIL). The FTL is configured to convert between a logical address provided by the host to the memory system 100 and a physical address of the memory device 110. The HIL is configured to interpret commands issued by the host to the memory system 100 (or storage device) and pass the commands to the FTL. The FIL is configured to pass commands issued by the FTL to the memory device 110.

[0081] For example, firmware may be stored in the memory device 110 and then loaded into the working memory 125 .

[0082] The working memory 125 may store firmware, program codes, commands, or data that drive the memory controller 120. For example, the working memory 125 may include static RAM (SRAM), dynamic RAM (DRAM), and / or synchronous DRAM (SDRAM) as volatile memory.

[0083] The error detection / correction circuit 126 may be configured to detect error bits of target data by using an error correction code and correct the detected error bits. For example, the target data may be data stored in the working memory 125, data retrieved from the memory device 110, etc.

[0084] Error detection / correction circuit 126 can be implemented to decode data using error correction codes. Error detection / correction circuit 126 can be implemented using various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0085] For example, the error detection / correction circuit 126 can detect error bits sector by sector for each read data. That is, each read data may include multiple sectors. As used herein, a sector may refer to a data unit that is smaller than a read unit (page) of a flash memory. The sectors that constitute each read data may correspond to each other via addresses.

[0086] The error detection / correction circuit 126 can calculate the bit error rate (BER) and determine whether correction is possible on a sector-by-sector basis. For example, if the BER is greater than a reference value, the error detection / correction circuit 126 can determine that the corresponding sector is uncorrectable or "failed." If the BER is less than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable or "passed."

[0087] The error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data strips. When a sector in the read data is correctable, the error detection / correction circuit 126 can omit the error detection and correction operations associated with the corresponding sector for the next read data strip. After completing the error detection and correction operations on all read data strips in this manner, the error detection / correction circuit 126 can detect sectors that are ultimately considered uncorrectable. There may be one or more sectors that are considered uncorrectable. The error detection / correction circuit 126 can transmit information (e.g., address information) about the sectors that are considered uncorrectable to the processor 124.

[0088] The bus 127 may be configured to provide a channel between the constituent elements of the memory controller 120, namely, the host interface 121, the memory interface 122, the processor 124, the working memory 125, and the error detection / correction circuit 126. For example, the bus 127 may include a control bus for transmitting various types of control signals and commands and a data bus for transmitting various types of data.

[0089] The above-described components of the memory controller 120 are provided as examples only. Note that some of the above-described components of the memory controller 120 may be omitted, or some of the above-described components of the memory controller 120 may be integrated into a single component. In addition, in some cases, one or more other components may be added to the memory controller 120.

[0090] In the following, reference is made to Figure 2 The memory device 110 is described in more detail.

[0091] Figure 2 is a block diagram schematically illustrating a memory device 110 according to an embodiment of the present disclosure.

[0092] Reference Figure 2 , the memory device 110 may include a memory cell array 210 , an address decoder 220 , a read and write (read / write) circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0093] The memory cell array 210 may include a plurality of memory blocks BLK1 -BLKz, where z is a natural number greater than or equal to 2.

[0094] In the plurality of memory blocks BLK1 -BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided to form a grid-like structure, and a plurality of memory cells MC may be arranged at intersections.

[0095] The plurality of memory blocks BLK1-BLKz may be connected to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1-BLKz may be connected to the read / write circuit 230 through a plurality of bit lines BL.

[0096] Each of the plurality of memory blocks BLK1 -BLKz may include a plurality of memory cells, for example, nonvolatile memory cells having a vertical channel structure.

[0097] The memory cell array 210 may be configured in a two-dimensional structure, and in some cases, may be configured in a three-dimensional structure.

[0098] Each of the plurality of memory cells in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data, a multi-level cell (MLC) configured to store two bits of data, a triple-level cell (TLC) configured to store three bits of data, or a quad-level cell (QLC) configured to store four bits of data. As another example, the memory cell array 210 can include a plurality of memory cells each configured to store five or more bits of data.

[0099] The address decoder 220 , the read / write circuit 230 , the control logic 240 , and the voltage generation circuit 250 may operate as peripheral circuits configured to drive the memory cell array 210 .

[0100] The address decoder 220 may be connected to the memory cell array 210 through a plurality of word lines WL.

[0101] The address coder 220 may be configured to operate in response to the control of the control logic 240 .

[0102] The address decoder 220 may receive an address through an input / output buffer (not shown) within the memory device 110. The address decoder 220 may be configured to decode a block address from the received address. The address decoder 220 may select at least one memory block based on the decoded block address.

[0103] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0104] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL inside a selected memory block and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0105] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL inside a selected memory block and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0106] The address decoder 220 may be configured to decode a column address among the received addresses and may transmit the decoded column address to the read / write circuit 230 .

[0107] The memory device 110 may perform a read operation and a program operation on a page-by-page basis. An address received when requesting a read operation and a program operation may include at least one of a block address, a row address, and a column address.

[0108] The address decoder 220 may select a memory block and a word line according to the block address and the row address. The column address may be decoded by the address decoder 220 and may be provided to the read / write circuit 230.

[0109] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0110] The read / write circuit 230 may include a plurality of page buffers PB. The read / write circuit 230 may operate as a “read circuit” when the memory cell array 210 performs a read operation, and may operate as a “write circuit” when the memory cell array 210 performs a write operation.

[0111] The above-mentioned read / write circuit 230 is also called a page buffer circuit including a plurality of page buffers PB, or a data register circuit. The read / write circuit 230 may include a data buffer participating in a data processing function, and in some cases, may further include a cache buffer operating in a cache function.

[0112] A plurality of page buffers PB may be connected to the memory cell array 210 through a plurality of bit lines BL. In order to sense the threshold voltage Vth of the memory cells during a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cells, may sense a change in the amount of current flowing through the sensing nodes according to a program state of the corresponding memory cells, and may latch the sensed change as sensing data.

[0113] The read / write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0114] During a read operation, the read / write circuit 230 senses data in the memory cells, temporarily stores the retrieved data, and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, the read / write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0115] The control logic 240 may be connected to the address decoder 220, the read / write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory device 110.

[0116] The control logic 240 may be configured to control overall operations of the memory device 100 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting precharge potential levels of sensing nodes of the plurality of page buffers PB.

[0117] Control logic 240 may control read / write circuit 230 to perform a read operation in memory cell array 210. Voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from control logic 240.

[0118] A memory block BLK in the memory device 110 may be composed of a plurality of pages PG and a plurality of strings. The plurality of pages PG corresponds to a plurality of word lines WL, and the plurality of strings STR corresponds to a plurality of bit lines BL.

[0119] In a memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to intersect. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. For another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0120] A plurality of word lines WL and a plurality of bit lines BL may intersect each other, thereby defining a plurality of memory cells MC. Each memory cell MC may have a transistor TR disposed therein.

[0121] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to a source line (which may be grounded) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0122] In each of the multiple memory blocks BLK1-BLKz, a first selection line (also called a source selection line or a drain selection line) can be additionally arranged outside a first outermost word line among the two outermost word lines that is closer to the read / write circuit 230, and a second selection line (also called a drain selection line or a source selection line) can be additionally arranged outside the other second outermost word line.

[0123] In some cases, at least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally disposed between the second outermost word line and the second selection line.

[0124] A read operation and a program operation (ie, a write operation) of a memory block may be performed on a page-by-page basis, and an erase operation may be performed on a memory block-by-memory block basis.

[0125] Figure 3 is a diagram illustrating the structure of word lines WL and bit lines BL of a memory device 110 according to an embodiment of the present disclosure.

[0126] Reference Figure 3 The memory device 110 includes a core region where memory cells MC are concentrated and an auxiliary region corresponding to the remaining region except the core region. The auxiliary region supports the operation of the memory cell array 210.

[0127] The core region may include a page PG and a string STR. In the core region, a plurality of word lines WL1-WL9 and a plurality of bit lines BL are arranged to intersect.

[0128] The word lines WL1-WL9 may be connected to the row decoder 310. The bit lines BL may be connected to the column decoder 320. Figure 2 The data register 330 of the read / write circuit 230 may be provided between the plurality of bit lines BL and the column decoder 320 .

[0129] The plurality of word lines WL1 - WL9 may correspond to a plurality of pages PG.

[0130] For example, Figure 3 As shown, each of the plurality of word lines WL1-WL9 may correspond to one page PG. When the size of each of the plurality of word lines WL1-WL9 is large, each of the plurality of word lines WL1-WL9 may correspond to at least two (e.g., two or four) page PGs. Each page PG is the minimum unit associated with performing programming and reading operations, and when performing programming and reading operations, all memory cells MC within the same page PG may perform operations simultaneously.

[0131] The plurality of bit lines BL may be connected to the column decoder 320 alternately between odd-numbered bit lines BL and even-numbered bit lines BL.

[0132] To access a memory cell MC, an address may be input to the core region first through an input / output terminal and then through the row decoder 310 and the column decoder 320, thereby designating a corresponding target memory cell. As used herein, designating a target memory cell refers to accessing one of the memory cells MC at the intersection between one of the word lines WL1-WL9 connected to the row decoder 310 and one of the bit lines BL connected to the column decoder 320 to program data in one of the memory cells MC or read programmed data from one of the memory cells MC.

[0133] The first direction (e.g., Figure 3 The pages PG in the horizontal direction (shown) are defined by a common line called a word line WL, and the pages PG in the second direction (eg, Figure 3 The strings STR (in the vertical direction shown) are defined (i.e., connected) by a common line called a bit line BL. As used herein, "commonly defined" means being structurally connected through the same material and simultaneously receiving the same voltage during voltage application. Due to the voltage drop across the preceding memory cell MC among the series-connected memory cells MC, the voltage applied to the memory cell MC located downstream of the series line among the memory cells MC may be slightly different from the voltage applied to the memory cell MC upstream of the series line.

[0134] Data register 330 plays an important role because all data processing performed by memory device 110, including programming and reading operations, occurs through data register 330. If data processing performed by data register 330 is delayed, all other regions need to wait until data register 330 completes data processing. In addition, performance degradation of data register 330 can degrade the overall performance of memory device 110.

[0135] exist Figure 3 In the example shown, in one string STR, a plurality of transistors TR1-TR9 may be connected to a plurality of word lines WL1-WL9, respectively. The plurality of transistors TR1-TR9 correspond to memory cells MC. In this example, each of the plurality of transistors TR1-TR9 includes a control gate CG and a floating gate FG.

[0136] The plurality of word lines WL1-WL9 include two outermost word lines WL1 and WL9. A first select line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register 330 in terms of a signal path, among the two outermost word lines WL1 and WL9. A second select line SSL may be additionally arranged outside the other second outermost word line WL9.

[0137] The first selection transistor D-TR, whose turn-on / off is controlled by the first selection line DSL, has a gate electrode connected to the first selection line DSL but does not include a floating gate FG. The second selection transistor S-TR, whose turn-on / off is controlled by the second selection line SSL, has a gate electrode connected to the second selection line SSL but does not include a floating gate FG.

[0138] The first selection transistor D-TR functions as a switch that turns on or off the connection between the corresponding string STR and the data register 330. The second selection transistor S-TR functions as a switch that turns on or off the connection between the corresponding string STR and the source line SL. In other words, the first selection transistor D-TR and the second selection transistor S-TR function as gatekeepers located at opposite ends of the corresponding string STR to pass or block signals.

[0139] During a programming operation, the memory system 100 fills the target memory cell MC of the bit line BL to be programmed with electrons. Therefore, the memory system 100 applies a turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0140] During a read operation or a verify operation, the memory system 100 turns on both the first select transistor D-TR and the second select transistor S-TR. Therefore, during a read operation or a verify operation, current can flow through the corresponding string STR and to the source line SL corresponding to ground, thereby enabling measurement of the voltage level of the bit line BL. However, during a read operation, there may be a time difference between the on / off timing of the first select transistor D-TR and the second select transistor S-TR.

[0141] During an erase operation, the memory system 100 can supply a voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 floats both the first select transistor D-TR and the second select transistor S-TR, thereby generating infinite resistance. Therefore, the effects of the first select transistor D-TR and the second select transistor S-TR are eliminated, and electrons can only flow between the floating gate FG and the substrate due to the potential difference.

[0142] Figure 4 The operation flow of the memory system 100 according to an embodiment of the present disclosure is shown.

[0143] Reference Figure 4 When a sudden power off (SPO) occurs, the power management core (PMC) of the memory controller 120 may transmit an SPO signal indicating the occurrence of the SPO to the flash interface layer core FIL_CORE.

[0144] The PMC is a core for controlling operations related to power supplied to the memory system 100 and may be Figure 1The flash interface layer core FIL_CORE is a core that executes the functions of the flash interface layer FIL and may be one of the multiple cores in the processor 124 .

[0145] In some embodiments, the PMC may recognize the occurrence of SPO through a signal (eg, a GPIO interrupt) generated outside the memory system 100. Upon recognizing the occurrence of SPO, the PMC may transmit an SPO signal indicating the occurrence of SPO to other cores of the memory controller 120.

[0146] The SPO signal generated by the PMC may be transmitted to other cores of the memory controller 120 in the form of an electrical signal of a certain level (ie, a signal having a low level or a high level), a message indicating the occurrence of SPO, or the like.

[0147] When SPO occurs, the memory system 100 may perform an operation of dumping a portion of data loaded in a volatile memory (e.g., the working memory 125) into the memory device 110. At this time, since power is not normally supplied to the memory system 100 from an external power supply, the memory system 100 may perform the operation of dumping a portion of data loaded in the volatile memory into the memory device 110 using power supplied from an emergency power supply device such as a capacitor.

[0148] However, since the amount of power supplied from the emergency power supply device is limited, the memory system 100 may only perform an operation to restore the memory system 100 to a state before the SPO occurs when powered on after the SPO occurs, and may suspend the remaining operations.

[0149] To this end, after receiving the SPO signal from the PMC, the flash interface layer core FIL_CORE of the memory controller 120 may search for a target command in a plurality of command queues.

[0150] Multiple command queues can queue commands to be input to the memory device 110. Before inputting a command to the memory device 110 to perform a specific operation, the memory controller 120 can queue the corresponding command in the command queue. This is to allow the memory controller 120 to manage the order in which each of the multiple commands is input to the memory device 110 when there are multiple commands to be input to the memory device 110.

[0151] The command queue enqueues a command, which means that the command queue stores the corresponding command therein. Conversely, the command queue dequeues a command, which means that the command queue deletes or otherwise removes the corresponding command.

[0152] The target command ensures that the memory system 100 is processed as needed before entering the power-off state after SPO occurs. That is, even when SPO occurs, the memory system 100 can ensure that the target command is not aborted but processed before entering the power-off state.

[0153] To this end, the memory controller 120 may reorder the execution order of commands queued in the command queue so that the target command can be processed before other commands. In this case, the memory controller 120 may reorder the execution order of the commands by dequeuing the target command and then queuing the dequeued target command to the command queue with the highest priority.

[0154] Specifically, the flash interface layer core FIL_CORE of the memory controller 120 may queue the target command found in the search in the highest priority command queue among the multiple command queues, that is, the command queue with the highest priority. The target command queued in the highest priority command queue may be input to the memory device 110 before the commands queued in other command queues. Even if the flash interface layer core FIL_CORE of the memory controller 120 receives a command requesting the abort of the corresponding operation, the flash interface layer core FIL_CORE may process the target command without aborting the target command before entering the power-off state. On the other hand, when the flash interface layer core FIL_CORE of the memory controller 120 receives a command requesting the abort of the corresponding operation, it will not process the command queued in another command queue before entering the power-off state.

[0155] To process the target command before entering the power-off state, the memory system 100 may control the target command to be processed before other commands by queuing the target command in a highest priority command queue.

[0156] The flash interface layer core FIL_CORE of the memory controller 120 may input a target command queued in the highest priority command queue to the memory device 110 before entering the power-off state.

[0157] Figure 5 is a diagram illustrating a top priority command queue CMD_Q_TOP according to an embodiment of the present disclosure.

[0158] In some embodiments of the present disclosure, before an SPO occurs, the highest priority command queue CMD_Q_TOP is in an empty state. That is, before an SPO occurs, the memory controller 120 may not queue any commands in the highest priority command queue CMD_Q_TOP, but may queue commands in any other command queue (i.e., excluding the highest priority command queue CMD_Q_TOP). In this way, the memory controller 120 may keep the highest priority command queue CMD_Q_TOP in an empty state before an SPO occurs.

[0159] After an SPO occurs, the target command TGT_CMD may be queued in the highest priority command queue CMD_Q_TOP. The memory controller 120 may queue the target command TGT_CMD in the highest priority command queue CMD_Q_TOP after an SPO occurs, and then may input the target command TGT_CMD to the memory device 110 to control the pending operation requested by the target command TGT_CMD. In other words, the highest priority command queue CMD_Q_TOP may be used after an SPO occurs.

[0160] The type of the target command TGT_CMD queued in the highest priority command queue CMD_Q_TOP may vary depending on the situation and / or operating conditions. For example, the target command TGT_CMD may be used to request an operation to write metadata. The memory controller 120 may generate metadata to manage data stored in the memory system 100. For example, the metadata may include mapping information between logical addresses in the host and physical addresses in the memory device 110, or information for managing the storage space of the memory device 110.

[0161] The reason why a command requesting an operation for writing metadata upon occurrence of SPO is processed with higher priority upon occurrence of SPO is as follows.

[0162] When the SPO occurs and the memory system 100 is powered off and cannot write metadata to the memory device 110, the memory system 100 needs to scan for metadata that has not yet been written. This is because if the metadata has not been written to the memory device 110, the data associated with the metadata cannot be normally accessed.

[0163] Therefore, when the operation of writing metadata is completed before entering the power-off state after SPO occurs, the memory system 100 does not need to perform the operation of scanning metadata during the subsequent power-on process, thereby reducing the time required for the recovery process after SPO occurs.

[0164] Figure 6is a diagram illustrating an example of states of a plurality of command queues before SPO occurs according to an embodiment of the present disclosure.

[0165] The plurality of command queues may include a first priority command queue CMD_Q_1 and a second priority command queue CMD_Q_2 as well as the aforementioned highest priority command queue CMD_Q_TOP.

[0166] The memory controller 120 may process commands queued in the first priority command queue CMD_Q_1 at a higher priority than commands queued in the second priority command queue CMD_Q_2. That is, commands queued in the first priority command queue CMD_Q_1 are processed before commands queued in the second priority command queue CMD_Q_2.

[0167] exist Figure 6 In the example shown in FIG, among the plurality of command queues, the highest priority command queue CMD_Q_TOP has the highest priority, the first priority command queue CMD_Q_1 has the second highest priority, and the second priority command queue CMD_Q_2 has the lowest priority. Figure 5 As described above, before SPO occurs, the highest priority command queue CMD_Q_TOP is in a blank state.

[0168] Figure 7 is a diagram illustrating an example of an operation of searching for a target command in a command queue after an SPO occurs according to an embodiment of the present disclosure.

[0169] Reference Figure 7 After SPO occurs, the flash interface layer core FIL_CORE of the memory controller 120 may search for the target command TGT_CMD among the commands queued in the first priority command queue CMD_Q_1 and the commands queued in the second priority command queue CMD_Q_2.

[0170] As described above, for example, the target command TGT_CMD may be a command for requesting an operation of writing metadata.

[0171] Because the time required to process a command requesting an operation to write metadata is longer than the time required to process a command requesting an operation to read data, the target command may be queued only in the second-priority command queue CMD_Q_2 before SPO occurs. In this case, when the flash interface layer core FIL_CORE of the memory controller 120 searches for the target command TGT_CMD after SPO occurs, the process of searching for the target command TGT_CMD in the first-priority command queue CMD_Q_1 may be omitted.

[0172] Figure 8 is a diagram illustrating an example of an operation of queuing a target command TGT_CMD in a top priority command queue CMD_Q_TOP after an SPO occurs according to an embodiment of the present disclosure.

[0173] Reference Figure 8 , the flash interface layer core FIL_CORE of the memory controller 120 may queue the target command TGT_CMD identified from the search of the first priority command queue CMD_Q_1 and the second priority command queue CMD_Q_2 to the highest priority command queue CMD_Q_TOP.

[0174] Figure 9 is a diagram illustrating an example of an operation of queuing a command currently queued in a second-priority command queue in a first-priority command queue after an SPO occurs according to an embodiment of the present disclosure.

[0175] Reference Figure 9 , the flash interface layer core FIL_CORE of the memory controller 120 may queue a command processed with a higher priority among the commands queued in the second priority command queue CMD_Q_2 from the second priority command queue CMD_Q_2 to the first priority command queue CMD_Q_1.

[0176] Among the commands queued in the second-priority command queue CMD_Q_2, the command queued in the first-priority command queue CMD_Q_1 may be a command for requesting an internal read operation. Unlike a host read operation in response to a read request from the host, a command for requesting an internal read operation is a command generated by the memory controller 120 itself for performing operations such as garbage collection (GC), wear leveling (WL), and read reclamation (RR). Before an SPO occurs, in order to more quickly process the read operation requested by the host, the flash interface layer core FIL_CORE of the memory controller 120 may queue the command for requesting a host read operation in the first-priority command queue CMD_Q_1 and may queue the command for requesting an internal read operation in the second-priority command queue CMD_Q_2.

[0177] As such, the reason why the memory controller 120 processes the command for requesting the internal read operation with a higher priority after the occurrence of the SPO is that the time required to process the internal read operation is relatively short compared to the program operation or the erase operation.

[0178] The flash interface layer core FIL_CORE of the memory controller 120 may queue commands processed with a lower priority when SPO occurs, among commands queued in the first priority command queue CMD_Q_1 , from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 .

[0179] The flash interface layer core FIL_CORE of the memory controller 120 can delete from the first priority command queue CMD_Q_1 a command that is processed with a lower priority when SPO occurs among the commands queued in the first priority command queue CMD_Q_1, thereby minimizing the possibility that another command queued in the first priority command queue CMD_Q_1 (for example, a command for requesting an internal read operation) will not be executed when power is off.

[0180] The memory controller 120 may determine commands that may be processed with a lower priority when an SPO occurs in various ways.

[0181] In an embodiment, the flash interface layer core FIL_CORE of the memory controller 120 may queue a specific type of command from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 among the commands queued in the first priority command queue CMD_Q_1 when SPO occurs. For example, the flash interface layer core FIL_CORE of the memory controller 120 may queue a command for requesting a host read operation from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 when SPO occurs.

[0182] In another embodiment, the flash interface layer core FIL_CORE of the memory controller 120 may queue commands that access a specific area of the memory device 110 from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 when an SPO occurs. For example, the flash interface layer core FIL_CORE of the memory controller 120 may queue commands that access a cold data area of the memory device 110 from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 when an SPO occurs. The cold data area may be defined as an area where the number of times the host reads data per unit time is less than or equal to a threshold number.

[0183] In another embodiment, the flash interface layer core FIL_CORE of the memory controller 120 may queue commands for reading a large amount of data from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 when an SPO occurs. For example, the flash interface layer core FIL_CORE of the memory controller 120 may queue 1) a command for reading a threshold amount of data or more, or 2) a command for reading the maximum amount of data, from the first priority command queue CMD_Q_1 to the second priority command queue CMD_Q_2 when an SPO occurs. In this way, when an SPO occurs, the flash interface layer core FIL_CORE of the memory controller 120 can process more commands for reading a small amount of data that can be processed quickly.

[0184] Figure 10 is a diagram illustrating a comparison between examples of types of commands queued into a command queue before and after an SPO occurs according to an embodiment of the present disclosure.

[0185] Reference Figure 10 Before SPO occurs, the highest priority command queue CMD_Q_TOP is empty, and commands requesting host read operations can be queued in the first priority command queue CMD_Q_1. Commands requesting internal read operations, commands requesting program operations, commands requesting erase operations, and commands requesting metadata write operations can be queued in the second priority command queue CMD_Q_2. In this case, commands requesting host read operations can be processed first.

[0186] However, after SPO occurs, commands requesting metadata write operations may be queued in the highest-priority command queue CMD_Q_TOP, and commands requesting host read operations and commands requesting internal read operations may be queued in the first-priority command queue CMD_Q_1. Additionally, commands requesting program operations and commands requesting erase operations may remain queued in the second-priority command queue CMD_Q_2. In this case, commands requesting metadata write operations may be processed first, followed by commands requesting host read operations and commands requesting internal read operations.

[0187] Figure 11 The flow of the operation of the memory system 100 according to an embodiment of the present disclosure is shown.

[0188] Reference Figure 11When SPO occurs, the power management core (PMC) of the memory controller 120 may directly transmit an SPO signal indicating the occurrence of SPO to the flash interface layer core FIL_CORE. That is, the SPO signal generated by the PMC may be directly transmitted to the flash interface layer core FIL_COREPMC without passing through a core that performs the functions of another layer (e.g., the host interface layer (HIL) or the flash translation layer (FTL)).

[0189] The flash interface layer core FIL_CORE that directly receives the SPO signal generated by the PMC can search for the target command in multiple command queues, as shown above. Figure 4 In addition, the flash interface layer core FIL_CORE may input the target command found in the search into the highest priority command queue among the multiple command queues, that is, the command queue with the highest priority.

[0190] In some embodiments, another core of the memory controller 120 may also receive information indicating that an SPO has occurred from the PMC. For example, a flash translation layer (FTL) core FTL_CORE that performs a flash translation layer (FTL) function may receive an SPO signal directly from the PMC, or may receive information indicating that an SPO has occurred through another core. The flash translation layer core FTL_CORE may be one of the multiple cores included in the processor 124, similar to the PMC and the flash interface layer core FIL_CORE.

[0191] The flash translation layer core FTL_CORE may transmit a command for requesting to suspend the corresponding operation to the flash interface layer core FIL_CORE. After receiving the command for requesting to suspend the corresponding operation, the flash interface layer core FIL_CORE may suspend processing the commands queued in other command queues (excluding the highest priority command queue).

[0192] The flash interface layer core FIL_CORE may input the target command queued in the highest priority command queue to the memory device 110. Figure 11 , describes a case where a target command is input to the memory device 110 after the flash interface layer core FIL_CORE receives a command for requesting to suspend the corresponding operation. However, before the flash interface layer core FIL_CORE receives the command for requesting to suspend the corresponding operation, a target command that has been queued in the highest priority command queue may be input to the memory device 110.

[0193] Figure 12 is a flowchart illustrating a method of operating the memory system 100 according to an embodiment of the present disclosure.

[0194] Reference Figure 12, in operation S1210 , the method of operating the memory system 100 may include transmitting an SOP signal from the PMC to the flash interface layer core FIL_CORE.

[0195] Then, in operation S1220, the method of operating the memory system 100 may include searching the plurality of command queues for a target command TGT_CMD to be processed before entering the power-off state. In some embodiments, the target command TGT_CMD may be a command for requesting an operation of writing metadata.

[0196] Then, in operation S1230 , the method of operating the memory system 100 may include queuing the target command TGT_CMD found in the search operation S1220 in a top-priority command queue CMD_Q_TOP having the highest priority among the plurality of command queues.

[0197] In some embodiments, in addition to the top priority command queue CMD_Q_TOP, the plurality of command queues may further include a first priority command queue CMD_Q_1 and a second priority command queue CMD_Q_2. Commands in the first priority command queue CMD_Q_1 may be processed with a higher priority than commands in the second priority command queue CMD_Q_2.

[0198] Then, in operation S1240 , the method of operating the memory system 110 may include inputting a target command TGT_CMD queued in the highest priority command queue CMD_Q_TOP to the memory device 110 before entering the power-off state.

[0199] The above-described operations of the memory controller 120 may be controlled by the control circuit 123 , and the processor 124 may be controlled in such a manner that various operations of the memory controller 120 run (ie, drive) programmed firmware.

[0200] Figure 13 is a diagram illustrating a configuration of a computing system 1300 according to an embodiment of the present disclosure.

[0201] Reference Figure 13The computing system 1300 may include: a memory system 100 electrically connected to a system bus 1360; a central processing unit (CPU) 1310 configured to control the overall operation of the computing system 1300; a random access memory (RAM) 1320 configured to store data and information related to the operation of the computing system 1300; a user interface / user experience (UI / UX) module 1330 configured to provide a user environment to a user; a communication module 1340 configured to communicate with an external device via a wired connection and / or wirelessly; and a power management module 1350 configured to manage the power used by the computing system 1300.

[0202] The computing system 1300 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, a tablet computer, or any of various other electronic devices.

[0203] The computing system 1300 may further include a battery for supplying operating voltage, an application chipset, a graphics-related module, a camera image processor, and a DRAM. As understood by those skilled in the art, the computing system 1300 may include one or more other elements.

[0204] The memory system 100 may include not only a device configured to store data on a magnetic disk, such as a hard disk drive (HDD), but also a device configured to store data in a non-volatile memory, such as a solid-state drive (SDD), a universal flash memory device, or an embedded MMC (eMMC) device. Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. In addition, the memory system 100 may be implemented as any of various storage devices that can be installed in any of various electronic devices.

[0205] According to the embodiments of the present disclosure described above, the operation delay time of the memory system can be minimized. In addition, according to the embodiments of the present disclosure, the overhead incurred in the process of calling a specific function can be minimized. Although various embodiments of the present disclosure have been shown and described, it will be understood by those skilled in the art that various modifications, additions and substitutions can be made without departing from the scope and spirit of the present invention as set forth in the appended claims. Although the embodiments of the present disclosure have been described for the sake of brevity and clarity, the scope of the present invention covers all variations that fall within the scope of the claims including their equivalents.

Claims

1. A memory system comprising: memory device; as well as a memory controller that controls the memory device, wherein the memory controller: When a sudden power-off signal (SPO) is transmitted from the power management core to the flash memory interface layer core, a plurality of command queues are searched for target commands to be processed before entering a power-off state, the plurality of command queues queuing commands to be input to the memory device. enqueueing the target command in a highest priority command queue having the highest priority among the plurality of command queues, and Prior to entering the power-off state, the target command queued in the highest priority command queue is input to the memory device. 2 . The memory system of claim 1 , wherein before an SPO occurs, the highest priority command queue is in an empty state. 3 . The memory system according to claim 1 , wherein the target command is a command requesting an operation of writing metadata.

4. The memory system of claim 1 , wherein the plurality of command queues further include a first priority command queue and a second priority command queue, and the memory controller processes commands in the first priority command queue with a higher priority than commands in the second priority command queue. 5 . The memory system of claim 4 , wherein after an SPO occurs, the memory controller queues a command requesting an internal read operation in the first priority command queue. 6 . The memory system of claim 4 , wherein the memory controller queues commands among the first priority command queue that are processed with a lower priority when SPO occurs, into the second priority command queue. 7 . The memory system of claim 1 , wherein the memory controller queues the target command in the highest priority command queue until a command requesting abort of a corresponding operation is transmitted to the flash interface layer core.

8. The memory system of claim 1, wherein the SPO signal is transmitted directly from the power management core to the flash interface layer core.

9. A memory controller comprising: a memory interface for communicating with a memory device; as well as a control circuit that controls the memory device, The control circuit: When a sudden power-off signal (SPO) is transmitted from the power management core to the flash memory interface layer core, searching for a target command to be processed before entering a power-off state in a plurality of command queues, the plurality of command queues queuing commands to be input to the memory device; enqueueing the target command in a highest priority command queue having the highest priority among the plurality of command queues, and Prior to entering the power-off state, the target command queued in the highest priority command queue is input to the memory device. 10 . The memory controller of claim 9 , wherein before the SPO occurs, the highest priority command queue is in an empty state. 11 . The memory controller according to claim 9 , wherein the target command is a command requesting an operation of writing metadata.

12. The memory controller of claim 9, wherein the plurality of command queues further include a first priority command queue and a second priority command queue, and the control circuit processes commands in the first priority command queue with a higher priority than commands in the second priority command queue. 13 . The memory controller of claim 12 , wherein after an SPO occurs, the control circuit queues a command requesting an internal read operation in the first priority command queue. 14 . The memory controller of claim 12 , wherein the control circuit queues commands among the first priority command queue that are processed with a lower priority when SPO occurs, into the second priority command queue. 15 . The memory controller of claim 9 , wherein the control circuit queues the target command in the highest priority command queue until a command requesting abort of a corresponding operation is transmitted to the flash interface layer core.

16. The memory controller of claim 9, wherein the SPO signal is transmitted directly from the power management core to the flash interface layer core.

17. A method of operating a memory system, the memory system comprising a memory device, the method comprising: Transmitting a sudden power-off signal, namely an SPO signal, from the power management core to the flash memory interface layer core; searching a plurality of command queues for a target command to be processed before entering a power-off state, the plurality of command queues queuing commands to be input to the memory device; queuing the target command in a highest priority command queue having the highest priority among the plurality of command queues; and Prior to entering the power-off state, the target command queued in the highest priority command queue is input to the memory device. The method according to claim 17 , wherein the target command is a command requesting an operation of writing metadata.

19. The method of claim 17, wherein the plurality of command queues further include a first priority command queue and a second priority command queue, and commands in the first priority command queue are processed with a higher priority than commands in the second priority command queue.

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