Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device that can be suitably manufactured. The semiconductor memory device of the embodiment includes: two memory blocks arranged in a first direction and extending in a second direction intersecting the first direction; a plurality of first extending bodies respectively provided between two memory blocks adjacent in the first direction and extending in the second direction; and a second extending body spaced apart from the two memory blocks in the second direction and extending in the first direction. The two memory blocks include a plurality of first conductive layers arranged in a third direction intersecting the surface of the substrate. The first extending body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than the first conductive layer closest to the substrate among the plurality of first conductive layers. The second extending body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers. The other end of the first extending body and the other end of the second extending body are farther from the substrate than the first conductive layer farthest from the substrate among the plurality of first conductive layers and closer to the substrate than the plurality of bit lines. The second extending body is spaced apart from the first extending body in the second direction.

Description

[0001] [Related Application(s)]

[0002] This application claims priority based on Japanese Patent Application No. 2020-116116 (filing date: July 6, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device is known that includes a plurality of memory blocks arranged in a first direction and extending in a second direction intersecting the first direction, and the plurality of memory blocks include a plurality of conductive layers arranged in a third direction intersecting the surface of the substrate. Summary of the Invention

[0005] An embodiment provides a semiconductor memory device that can be suitably manufactured.

[0006] A semiconductor memory device according to an embodiment includes: a plurality of memory blocks arranged in a first direction and extending in a second direction intersecting the first direction; a plurality of first extending bodies respectively provided between two adjacent memory blocks in the first direction and extending in the second direction; a second extending body spaced apart from the plurality of memory blocks in the second direction and extending in the first direction; and a plurality of bit lines arranged in the second direction and extending in the first direction and connected to the plurality of memory blocks. The plurality of memory blocks include a plurality of first conductive layers arranged in a third direction intersecting the surface of the substrate. The first extending body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than the first conductive layer closest to the substrate among the plurality of first conductive layers. The second extending body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers. The other end of the first extending body and the other end of the second extending body are farther from the substrate than the first conductive layer farthest from the substrate among the plurality of first conductive layers, and are closer to the substrate than the plurality of bit lines. The second extending body is spaced apart from the first extending body in the second direction. Brief Description of the Drawings

[0007] Figure 1 is a schematic plan view of a semiconductor memory device according to a first embodiment.

[0008] Figure 2 is a schematic perspective view of a memory cell array region RMCA.

[0009] Figure 3 is cut along A-A' Figure 1The schematic cross-sectional view when observing the shown structure along the Y direction.

[0010] Figure 4 is Figure 1 The schematic enlarged view of a part of

[0011] Figure 5 is the schematic cross-sectional view when cutting along the C-C' line Figure 4 the shown structure and observing along the X direction.

[0012] Figure 6 is Figure 5 The schematic enlarged view of the part indicated by D of

[0013] Figure 7 The schematic cross-sectional view showing the structure of the transistor Tr provided in the row decoder region RRD.

[0014] Figure 8 is Figure 3 The schematic enlarged view of the part indicated by E of

[0015] Figure 9 is including Figure 8 The schematic enlarged view of the part indicated by F of

[0016] Figure 10 The schematic cross-sectional view showing a part of the wiring region RHU.

[0017] Figures 11 - 16 The schematic cross-sectional view for explaining the manufacturing method of the semiconductor memory device of the first embodiment.

[0018] Figure 17 The schematic perspective view for explaining the manufacturing method of the semiconductor memory device of the first embodiment.

[0019] Figures 18 - 21 The schematic cross-sectional view for explaining the manufacturing method of the semiconductor memory device of the first embodiment.

[0020] Figure 22 The schematic perspective view of the semiconductor memory device of the comparative example.

[0021] Figure 23 The schematic perspective view showing the manufacturing method of the semiconductor memory device of the comparative example.

[0022] Figure 24 The schematic cross-sectional view for explaining the manufacturing method.

[0023] Figure 25 The schematic cross-sectional view for explaining the manufacturing method of the semiconductor memory device of the first embodiment.

[0024] Figure 26 It is a schematic perspective view of the semiconductor memory device of the second embodiment.

[0025] Figure 27 It is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of the second embodiment.

[0026] Figure 28 It is a schematic perspective view of the semiconductor memory device of the third embodiment.

[0027] Figure 29 It is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of the third embodiment.

[0028] Figure 30 It is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of the fourth embodiment.

[0029] Figure 31 It is a schematic top view showing a part of the configuration of the semiconductor memory device of the fifth embodiment.

[0030] Figure 32 It is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of the fifth embodiment.

[0031] Figure 33 It is a schematic cross-sectional view showing a part of the configuration of another configuration example of the semiconductor memory device of the fifth embodiment.

[0032] Figure 34 It is a schematic top view showing a part of the configuration of the semiconductor memory device of the sixth embodiment.

[0033] Figure 35 It is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of the sixth embodiment.

[0034] Figure 36 It is a schematic top view showing the configuration of the semiconductor memory device of other embodiments.

[0035] Figure 37 It is a schematic top view showing a part of the configuration of the semiconductor memory device of other embodiments. Specific embodiments

[0036] Next, with reference to the drawings, the semiconductor memory device of the embodiment will be described in detail. In addition, the following embodiments are only examples and are not intended to limit the present invention. In addition, the following drawings are schematic views, and in order to facilitate the description, some configurations may be omitted. In addition, for multiple embodiments, the same reference numerals may be added to common parts and the description may be omitted.

[0037] In addition, in this specification, when referring to a "semiconductor memory device", it sometimes refers to a memory die, and sometimes also refers to a storage system including a controller die such as a storage chip, a memory card, or an SSD (Solid State Drive). Furthermore, it sometimes refers to a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0038] In addition, in this specification, when it is said that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0039] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0040] In addition, in this specification, sometimes the direction along a specific plane is referred to as the first direction, the direction along the specific plane and intersecting the first direction is referred to as the second direction, and the direction intersecting the specific plane is referred to as the third direction. These first direction, second direction, and third direction may correspond to any one of the X direction, Y direction, and Z direction, or may not correspond to these directions.

[0041] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as upper, and the direction approaching the substrate along the Z direction is referred to as lower. In addition, when referring to the lower surface or lower end of a certain configuration, it means the surface or end on the substrate side of the configuration, and when referring to the upper surface or upper end, it means the surface or end on the side opposite to the substrate of the configuration. In addition, a plane intersecting the X direction or Y direction is referred to as a side surface, etc.

[0042] In addition, in this specification, when referring to the "width", "length", or "thickness", etc. of a specific direction of a configuration, component, etc., it sometimes refers to the width, length, or thickness, etc. in a cross-section obtained by observation using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc. In addition, sometimes the length in a specific direction is expressed as the width or thickness.

[0043] [First Embodiment]

[0044] [Structure]

[0045] Figure 1 is a schematic top view of the semiconductor memory device of the present embodiment. As Figure 1 shown, the semiconductor memory device of the present embodiment includes a semiconductor substrate 100. In the illustrated example, in the semiconductor substrate 100, two memory cell array regions R arranged in the X direction are provided MCA . In addition, in the memory cell array region R MCA , a memory hole region R MH , and a wiring region R provided at a position arranged in the X direction with respect to the memory hole region R MH are provided. The wiring region R HU extends in the Y direction along both end portions in the X direction of the memory hole region R HU . In addition, a row decoder region R MH is provided at a position arranged in the X direction with respect to the memory cell array region R MCA . The row decoder region R RD extends in the Y direction along both end portions in the X direction of the memory cell array region R RD . In addition, a peripheral circuit region R extending in the X direction is provided at the end portion in the Y direction of the semiconductor substrate 100 MCA . PC .

[0046] Figure 2 is a schematic perspective view of the memory cell array region R MCA . As Figure 2 shown, in the memory cell array region R MCA , the following are provided: a plurality of memory blocks BLK arranged in the Y direction; an inter-block structure ST X1 , which is an extension body provided between two memory blocks BLK adjacent in the Y direction and extending in the X direction; and a plurality of bit lines BL arranged above the memory blocks BLK and extending in the Y direction. In addition, a block-side structure ST MCA serving as an extension body extending in the Y direction is provided in a region between the memory cell array region R RD and the row decoder region R Y1 .

[0047] Next, with reference to Figures 3 - 10 , each component included in the semiconductor memory device of the present embodiment will be described. Figure 3 is a schematic cross-sectional view when cutting along A-A' Figure 1 of the structure shown and observing in the Y direction. Figure 4 is Figure 1 a schematic enlarged view of a part of Figure 5 is a cut along the line C-C' Figure 4The structure shown and a schematic cross-sectional view when observed along the X direction. Figure 6 is Figure 5 a schematic enlarged view of the part indicated by D. Figure 7 is a schematic cross-sectional view showing the structure of the transistor Tr provided in the row decoder region R RD . Figure 8 is a schematic enlarged view of the part indicated by E in the figure. Figure 9 is Figure 8 a schematic enlarged view of the part indicated by F including Figure 10 is a schematic cross-sectional view showing a part of the wiring region R HU .

[0048] [Structure of the semiconductor substrate 100]

[0049] The semiconductor substrate 100 ( Figure 3 ) is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). For example, as Figure 3 shown, on the surface of the semiconductor substrate 100, an N-type well region 100N containing N-type impurities such as phosphorus (P), a P-type well region 100P containing P-type impurities such as boron (B), a semiconductor substrate region 100S where neither the N-type well region 100N nor the P-type well region 100P is provided, and an insulating region 100I are provided, for example. In addition, in the illustrated example, a P-type well region 100P (hereinafter referred to as "P-type well region 100P1") is provided in the memory cell array region R MCA , and an N-type well region 100N is provided between the P-type well region 100P1 and the semiconductor substrate region 100S. In addition, the semiconductor substrate region 100S is provided in the row decoder region RRD.

[0050] [Structure in the memory hole region R of the memory block BLK MH

[0051] In the memory hole region R of the memory block BLK MH , a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 ( Figure 5 ) provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120 are provided, respectively.

[0052] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), or the like. Additionally, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction. A part of the plurality of conductive layers 110 functions as word lines and gate electrodes of a plurality of memory cells connected to the word lines. Additionally, a part of the plurality of conductive layers 110 functions as selection gate lines and gate electrodes of selection gate transistors connected to the selection gate lines.

[0053] A conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), or the like. Additionally, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110. The conductive layer 111 functions as a selection gate line and a gate electrode of a selection gate transistor connected to the selection gate line.

[0054] For example, as Figure 4 shown, the semiconductor layer 120 is arranged in a specific pattern in the X direction and the Y direction. The semiconductor layer 120 functions as a channel region of a plurality of memory cells and selection gate transistors arranged in the Z direction. The semiconductor layer 120 is, for example, a semiconductor layer such as polysilicon (Si). For example, as Figure 5 shown, the semiconductor layer 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central part. Additionally, the outer peripheral surfaces of the semiconductor layer 120 are respectively surrounded by the conductive layer 110 and face the conductive layer 110.

[0055] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor layer 120. The impurity region 121 is connected to a plurality of bit lines BL arranged in the X direction via contact C h and contact C b , respectively (refer to Figure 4 ).

[0056] The lower end portion of the semiconductor layer 120 is connected to the P-type well region 100P1 of the semiconductor substrate 100 via a semiconductor layer 122 including single-crystalline silicon (Si) or the like. The semiconductor layer 122 functions as a channel region of a selection gate transistor. The outer peripheral surface of the semiconductor layer 122 is surrounded by the conductive layer 111 and faces the conductive layer 111. An insulating layer 123 such as silicon oxide is provided between the semiconductor layer 122 and the conductive layer 111.

[0057] The gate insulating film 130 has a substantially cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120.

[0058] For example, as Figure 6 shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge accumulation film 132, and a blocking insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 are insulating films such as silicon oxide (SiO2), for example. The charge accumulation film 132 is a film capable of accumulating charges such as silicon nitride (Si3N4), for example. The tunnel insulating film 131, the charge accumulation film 132, and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0059] In addition, in Figure 6 an example is shown in which the gate insulating film 130 includes a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may also include, for example, a floating gate such as polysilicon containing N-type or P-type impurities.

[0060] [Structure in the wiring area R of the memory block BLK HU

[0061] For example, as Figure 3 shown, in the wiring area R of the memory block BLK HU the ends in the X direction of a plurality of conductive layers 110 are provided. Regarding these plurality of ends, the positions in the X direction or the Y direction are different from each other. As a result, a substantially stepped structure is formed at the ends in the X direction of the memory block BLK.

[0062] In addition, for example, as Figure 4 shown, a plurality of contacts CC arranged in a matrix in the X direction and the Y direction are provided in the wiring area R HU . As Figure 3 shown, these plurality of contacts CC extend in the Z direction and are connected to the conductive layer 110 at the lower ends. In addition, these plurality of contacts CC are connected at the upper ends to a plurality of wirings m0, m1 provided above ( Figure 3 ). The contact CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0063] In addition, as Figure 4 shown, a support structure HR provided near the contact CC is provided in the wiring area R HU . The outer peripheral surfaces of the support structure HR are respectively surrounded by the conductive layer 110 and are connected to the conductive layer 110. For example, as Figure 10 ​As shown, the support structure HR may include a semiconductor layer 120, an insulating layer 125, and a gate insulating film 130. Additionally, the support structure HR may also include an insulating layer such as silicon oxide (SiO2) configured to be substantially cylindrical instead of these structures. Additionally, the support structure HR of the present embodiment may also extend toward the row decoder region R RD side. That is, the position of the upper end of the support structure HR in the X direction may be located closer to the row decoder region R than the position of the lower end of the support structure HR in the X direction RD side position. Additionally, the magnitude of this inclination (the difference in the X direction between the upper end position and the lower end position) may be greater than that of the semiconductor layer 120 provided in the memory hole region R MH ( Figure 3 ) and the contact CC( Figure 3 ).

[0064] [Inter-block structure ST X1 structure]

[0065] For example, as Figure 4 and Figure 5 shown, the inter-block structure ST X1 includes a conductive layer LI extending in the Z direction and the X direction X1 , and insulating layers SW such as silicon oxide (SiO2) provided on both side surfaces of the conductive layer LI in the Y direction X1 . The lower end of the conductive layer LI X1 is located at a position lower than that of the plurality of conductive layers 110 and the conductive layer 111, and is connected to an N-type impurity region 100n provided in the P-type well region 100P1 of the semiconductor substrate 100 X1 . The impurity region 100n X1 extends in the X direction along the inter-block structure ST X1 , and contains N-type impurities such as phosphorus (P). The upper end of the conductive layer LI X1 is located at a position higher than that of the plurality of conductive layers 110 and lower than that of the plurality of bit lines BL, and is connected to a wiring m0 extending in the Y direction. The conductive layer LI X1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), may also include a laminated film of this kind and a semiconductor layer such as polysilicon, may also include a semiconductor layer such as polysilicon and a silicide, etc. The conductive layer LI X1 functions as a part of the source line, for example. That is, when a voltage is supplied to the conductive layer 111, an electron channel (inversion layer) is formed in the P-type well region 100P1, whereby the semiconductor layer 120 and the conductive layer LI X1 are conducted. Additionally, the length of the inter-block structure ST in the X direction may be greater than the length of the memory block BLK in the X direction X1 . X1 ​

[0066] [In the row decoder region R RD and the peripheral circuit region R PC the structure]

[0067] In the row decoder region R RD ( Figure 1 ) there is provided a row decoder that transmits voltages to the conductive layer 110 and the conductive layer 111. In the peripheral circuit region R PC ( Figure 1 ) there are provided other circuits that supply voltages to the memory block BLK and the like.

[0068] For example, as Figure 7 shown, in the row decoder region R of the semiconductor substrate 100 RD and the peripheral circuit region R PC there are provided a gate insulating film 210, a gate electrode 220, and a contact CS that connects to the semiconductor substrate 100 and the gate electrode 220.

[0069] In the row decoder region R RD the semiconductor substrate region 100S of the semiconductor substrate 100 functions as a channel region or the like of a plurality of transistors Tr that constitute the peripheral circuit PC. Further, in the peripheral circuit region R PC the N-type well region 100N, the P-type well region 100P, and the semiconductor substrate region 100S of the semiconductor substrate 100 respectively function as a channel region or the like of a plurality of transistors Tr that constitute the peripheral circuit PC.

[0070] The gate insulating film 210 is provided on the N-type well region 100N, the P-type well region 100P, and the semiconductor substrate region 100S of the semiconductor substrate 100. The gate insulating film 210 contains, for example, silicon oxide (SiO2) or the like.

[0071] The gate electrode 220 includes, for example, semiconductor layers 221, 222 such as polysilicon containing impurities such as phosphorus (P) or boron (B), and a conductive layer 223 such as tungsten (W). Further, on the upper surface of the gate electrode 220, an insulating layer 225 such as silicon nitride (SiN) is provided, for example.

[0072] The contact CS extends in the Z direction and is connected at the lower end to the upper surface of the semiconductor substrate 100 or the gate electrode 220. Further, as Figure 3 shown, the contact CS is connected at the upper end to a plurality of wirings m0, m1 provided above. The contact CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0073] [Memory cell array region R MCA and the row decoder region R RDThe structure in the region between

[0074] As Figure 8 shown, in the region between the memory cell array region R MCA and the row decoder region R RD starting from the memory cell array region R MCA side, a guard ring region R GR1 , an insulating region 100I1, a guard ring region R GR2 , an insulating region 100I2, a guard ring region R GR3 , and an insulating region 100I3 are provided in sequence.

[0075] The guard ring region R GR1 is provided in a P-type well region 100P1 common to the memory cell array region R MCA and is formed so as to surround the memory cell array region R MCA on the surface of the semiconductor substrate 100. The insulating region 100I1 is provided between the guard ring region R GR1 and the guard ring region R GR2 and is formed so as to surround the guard ring region R GR1 on the surface of the semiconductor substrate 100.

[0076] The guard ring region R GR2 is provided in an N-type well region 100N between the P-type well region 100P1 and the semiconductor substrate region 100S and is formed so as to surround the insulating region 100I1 on the surface of the semiconductor substrate 100. In addition, in the guard ring region R GR2 , an impurity region 100n2 containing N-type impurities such as phosphorus (P) is provided on the surface of the semiconductor substrate 100. In addition, in the guard ring region R GR2 , a plurality of contacts CS are provided along the impurity region 100n2. These plurality of contacts CS supply a well voltage to the N-type well region 100N. The insulating region 100I2 is provided between the guard ring region R GR2 and the guard ring region R GR3 and is formed so as to surround the guard ring region R GR2 on the surface of the semiconductor substrate 100.

[0077] The guard ring region R GR3 is provided in a P-type well region 100P2 separately provided from the P-type well region 100P1 and is formed so as to surround the insulating region 100I2 on the surface of the semiconductor substrate 100. In addition, in the guard ring region R GR3 , an impurity region 100p2 containing P-type impurities such as boron (B) is provided on the surface of the semiconductor substrate 100. In addition, in the guard ring region R GR3A plurality of contacts CS are provided along the impurity region 100p2. These plurality of contacts CS supply a well voltage to the P-type well region 100P2.

[0078] In addition, in the guard ring area R GR1 and the memory cell array region R MCA Between them, a dummy transistor structure DTr and a block side structure ST are set. Y1 The dummy transistor structure DTr includes the gate insulating film 210, the gate electrode 220, and the insulating layer 225 included in the transistor Tr. However, these structures do not function as the transistor Tr. Block side structure ST Y1 It is provided closer to the memory cell array region R than the dummy transistor structure DTr. MCA side.

[0079] [Block side structure ST Y1 [Structure of

[0080] For example, Figure 4 and Figure 9 As shown, the block side structure ST Y1 A conductive layer LI extending in the Z direction and the Y direction is provided. Y1 , and arranged in the conductive layer LI Y1 The insulating layer SW of silicon oxide (SiO2) on both sides of the X direction Y1 Conductive layer LI Y1 The lower end of the semiconductor substrate 100 is located below the plurality of conductive layers 110 and 111 and is connected to the P-type impurity region 100p provided in the P-type well region 100P1. Y1 . Impurity region 100p Y1 Construct ST along the block side Y1 The conductive layer LI extends in the Y direction and contains P-type impurities such as boron (B). Y1 The upper end of the conductive layer LI is located above the plurality of conductive layers 110 and below the plurality of bit lines BL, and is connected to the wiring m0. Y1 For example, it may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), or it may include such a laminated film and a semiconductor layer such as polysilicon, or it may include a semiconductor layer such as polysilicon and silicide. Y1 For example, the conductive layer LI can function as a wiring for supplying a ground voltage to the P-type well region 100P1. Y1 It can be electrically connected to an external terminal (not shown) of the semiconductor memory device to which a ground voltage is supplied. Y1 Set in the X direction with the memory block BLK and the inter-block structure ST X1 Separate locations. In addition,Figure 1 In the example of Y1 , the length in the Y direction of the block side structure ST MCA is the same as the width in the Y direction of the memory cell array region R Y1 . However, the length in the Y direction of the block side structure ST MCA may also be greater than or less than the width in the Y direction of the memory cell array region R Figure 4 . In the example of Y1 , the width in the X direction of the block side structure ST X1 is the same as the width in the Y direction of the inter-block structure ST Y1 . However, the width in the X direction of the block side structure ST X1 may also be greater than or less than the width in the Y direction of the inter-block structure ST

[0081] [Manufacturing Method]

[0082] Next, with reference to Figures 11 - 21 , the manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figure 11 , Figures 13 - 15 , Figures 18 - 20 are schematic cross-sectional views for explaining this manufacturing method, and show the corresponding configurations to Figure 5 . Figure 12 is a schematic cross-sectional view for explaining this manufacturing method, and shows the corresponding cross-section to Figure 8 . Figure 16 and Figure 21 are schematic cross-sectional views for explaining this manufacturing method, and show the corresponding cross-sections to Figure 9 . Figure 17 is a schematic perspective view for explaining this manufacturing method, and shows the corresponding configurations to Figure 2 .

[0083] When manufacturing the semiconductor memory device of this embodiment, first, a plurality of transistors Tr ( Figure 3 ) constituting the peripheral circuit PC are formed in the row decoder region R RD and the peripheral circuit region R PC of the semiconductor substrate 100.

[0084] Next, for example, as shown in Figure 11 , a plurality of sacrificial layers 110A and an insulating layer 101 are formed on the semiconductor substrate 100. The sacrificial layer 110A contains, for example, silicon nitride (SiN) or the like. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition). In addition, the plurality of sacrificial layers 110A and the insulating layer 101 are formed in the memory cell array region R described with reference to Figure 1 ​MCA .

[0085] Next, for example, as Figure 12 shown, a plurality of sacrificial layers 110A and a part of the insulating layer 101 are removed in the wiring region R HU to form a substantially stepped structure. This step is performed, for example, by repeating the following steps: forming a resist on the upper surface of the structure described with reference to Figure 11 , removing the insulating layer 101 by RIE (Reactive Ion Etching), removing the sacrificial layer 110A by RIE, etc., and isotropically removing the resist.

[0086] Next, an insulating layer 102 covering the stepped structure is formed (refer to Figure 9 ). This step is performed, for example, by a method such as CVD.

[0087] Next, for example, as Figure 13 shown, a plurality of memory holes MH are formed at positions corresponding to the semiconductor layer 120 and at positions corresponding to the support structure HR. The memory holes MH extend in the Z direction, penetrate the insulating layer 101 and the sacrificial layer 110A, and expose the upper surface of the semiconductor substrate 100. This step is performed, for example, by a method such as RIE.

[0088] Next, for example, as Figure 14 shown, a semiconductor layer 122, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed inside the memory holes MH. This step is performed, for example, by methods such as epitaxial growth, CVD, and RIE.

[0089] >Next, for example, as Figures 15 - 17 shown, a groove STA X1 is formed at a position corresponding to the inter-block structure ST X1 , and a groove STA Y1 is formed at a position corresponding to the block-side structure ST Y1 . The groove STA X1 extends in the Z direction and the X direction, cuts off the insulating layer 101 and the sacrificial layer 110A in the Y direction, and exposes the upper surface of the semiconductor substrate 100. The groove STA Y1 extends in the Z direction and the Y direction and exposes the upper surface of the semiconductor substrate iced 100. This step is performed, for example, as follows: an insulating layer 103 such as SiO2 is formed on the upper surface of the structure described with reference to Figure 14 , and RIE, etc. is performed using this insulating layer 103 as a mask.

[0090] Next, for example, as Figure 18As shown, via the groove STA X1 The sacrificial layer 110A is removed. Thus, a structure including a plurality of insulating layers 101 arranged in the Z direction, a structure (semiconductor layer 120, gate insulating film 130, and insulating layer 125) within the memory holes MH that support the insulating layer 101, and a hollow structure that supports the structure HR is formed. This step is performed by a method such as wet etching, for example.

[0091] Next, for example, as Figure 19 shown, the insulating layer 123 is formed. This step is performed by a method such as an oxidation process, for example. In addition, the conductive layer 110 and the conductive layer 111 are formed. This step is performed by a method such as CVD, for example.

[0092] Next, for example, as Figure 20 shown, in the groove STA X1 the inter-block structure ST X1 is formed, and as Figure 21 shown, in the groove STA Y1 the block-side structure ST Y1 is formed. In this step, for example, by a method such as CVD, an insulating layer such as silicon oxide (SiO2) is formed thinly on the sidewalls of the groove STA X1 , the groove STA Y1 so as not to fill the groove STA X1 , the groove STA Y1 , thereby forming the insulating layers SW X1 , SW Y1 . In addition, for example, by a method such as RIE, the portions of the insulating layers SW X1 , SW Y1 covering the upper surface of the semiconductor substrate 100 are removed to expose the upper surface of the semiconductor substrate 100. In addition, for example, ions are implanted into the upper surface of the semiconductor substrate 100 to form the impurity regions 100n X1 , 100p Y1 . In addition, for example, by a method such as CVD, conductive layers LI X1 , the groove STA Y1 are formed inside the groove STA X1 , LI Y1 .

[0093] Then, by forming the contacts CC, CS, wirings m0, m1, etc., the semiconductor memory device of the first embodiment is formed.

[0094] [Comparative Example]

[0095] Next, refer to Figure 22, a semiconductor memory device of a comparative example will be described. The semiconductor memory device of the comparative example is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the comparative example does not have the block-side structure ST Y1 .

[0096] Next, with reference to Figure 23 , a manufacturing method of the semiconductor memory device of the comparative example will be described. The semiconductor memory device of the comparative example is basically manufactured in the same manner as the semiconductor memory device of the first embodiment. However, in the manufacturing method of the comparative example, as Figure 23 shown, in the steps described with reference to Figures 15 - 17 , only the groove STA X1 is formed, and the groove STA Y1 is not formed.

[0097] [Effects of the First Embodiment]

[0098] When manufacturing the semiconductor memory device of the comparative example, in the steps described with reference to Figure 18 , for example, as Figure 24 shown, there is a case where a hollow structure including a plurality of insulating layers 101 is deformed. It is considered that the reason is that the insulating layer 101 is squeezed toward the center side in the X direction due to the compressive stress in the X direction of the insulating layer 102 provided in the wiring region R HU .

[0099] Here, when manufacturing the semiconductor memory device of the first embodiment, in the steps described with reference to Figure 17 and the like, not only the groove STA X1 is formed, but also the groove STA Y1 is formed. Therefore, as Figure 25 shown, the compressive stress in the X direction of the insulating layer 102 can be dissipated toward the row decoder region R RD side, thereby appropriately suppressing the deformation of the hollow structure as described above.

[0100] In addition, for example, when the groove STA X1 intersects with the groove STA Y1 , in the steps described with reference to Figure 17 and the like, there is a case where the gas of RIE is concentrated in the intersecting portion of these grooves STA X1 and the groove STA Y1 , resulting in damage to the semiconductor substrate 100 in this portion. Therefore, in the manufacturing method of the first embodiment, the groove STA Y1 is separated from the groove STA X1 . Thus, the semiconductor memory device can be appropriately manufactured.

[0101] In addition, for example, in the groove STAX1 When intersecting with the groove STA Y1 in the case, in the steps described with reference to Figure 17 etc., the structure provided on the semiconductor substrate 100 is completely truncated in the Y direction. In this case, due to the compressive stress etc., deformation occurs in each structure, resulting in unevenness in the distance in the Y direction between these structures (the width in the Y direction of the groove STA X1 ). Therefore, in the manufacturing method of the first embodiment, the groove STA Y1 is separated from the groove STA X1 . According to this method, each structure truncated by the groove STA X1 becomes a state of being interconnected via the insulating layers 102 and 103. Therefore, the positional relationship between each structure can be fixed via the insulating layers 102 and 103, thereby suppressing the generation of unevenness as described above. Thus, a semiconductor memory device can be suitably manufactured.

[0102] In addition, as described above, when it is desired to dissipate the compressive stress in the X direction of the insulating layer 102 to the row decoder region R Y1 side through the groove STA RD , it is ideal that the groove STA Y1 is provided near the memory cell array region R MCA . The reason is that the closer the groove STA Y1 is to the memory cell array region R MCA , the smaller the width of the insulating layer 102 in the X direction, and the easier it is for the insulating layer 102 to deform in the X direction. Therefore, as described with reference to Figure 8 , in the first embodiment, the groove STA Y1 is arranged closer to the inside than the guard ring region R GR1 . Thereby, the deformation of the hollow structure as described above can be suitably suppressed.

[0103] In addition, as described with reference to Figure 9 etc., the conductive layer LI Y1 of the present embodiment extends in the Y direction along a plurality of memory blocks BLK arranged in the Y direction and is supplied with a ground voltage. In this configuration, since the conductive layer LI Y1 functions as a shielding electrode, it can protect the memory blocks BLK from external electromagnetic wave interference.

[0104] [Second Embodiment]

[0105] Next, referring to Figure 26 and Figure 27The semiconductor memory device of the second embodiment will be described. The semiconductor memory device of the second embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, Figure 2 As shown in FIG. 1 , in the semiconductor memory device of the first embodiment, in the memory cell array region R MCA There is a block structure ST on each side of the X direction. Y1 On the other hand, Figure 26 As shown, in the second embodiment, in the memory cell array region R MCA There are two block side structures ST on each side of the X direction Y1 In addition, if Figure 27 As shown, these 2 block side structures ST Y1 Both are arranged closer to the memory cell array region R than the dummy transistor structure DTr. MCA side.

[0106] In this configuration, the memory cell array region R is provided. MCA Two nearby conductive layers LI Y1 Both function as shielding electrodes, thereby better protecting the memory block BLK from interference from external electromagnetic waves.

[0107] [Third embodiment]

[0108] Secondly, refer to Figure 28 and Figure 29 The semiconductor memory device of the third embodiment will be described. The semiconductor memory device of the third embodiment is basically configured in the same manner as the semiconductor memory device of the second embodiment. However, Figure 26 As shown, in the semiconductor memory device of the second embodiment, in the memory cell array region R MCA There are two block side structures ST on each side of the X direction Y1 On the other hand, Figure 28 As shown, in the third embodiment, in the memory cell array region R MCA On both sides of the X direction, except for the 2 block side structures ST Y1 In addition, a block side structure ST is also provided as an extension extending in the Y direction. Y3 In addition, if Figure 29 As shown, the block side structure ST Y3 Set in the guard ring area R GR2 .

[0109] Block side structure ST Y3 Basically with block side structure ST Y1 The same structure. However, the block side structure ST Y1 The conductive layer LI contained Y1Via the P-type impurity region 100p Y1 is connected to the P-type well region 100P1. On the other hand, the block-side structure ST Y3 contains the conductive layer LI Y3 is connected to the N-type well region 100N via the impurity region 100n2.

[0110] In this configuration, the two conductive layers LI MCA near the storage cell array region R Y1 and the conductive layer LI Y3 both act as shielding electrodes, so that the storage block BLK can be better protected from external electromagnetic waves.

[0111] [Fourth Embodiment]

[0112] Next, with reference to Figure 30 , the semiconductor memory device of the fourth embodiment will be described. The semiconductor memory device of the fourth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. On both sides in the X direction of the storage cell array region R MCA one block-side structure ST is provided respectively. Y1 . Furthermore, on both sides of the block-side structure ST Y1 one block-side structure ST as an extension extending in the Y direction is also provided respectively. Y4 . The block-side structure ST Y4 is provided between the dummy transistor structure DTr and the block-side structure ST Y1 .

[0113] The block-side structure ST Y4 is basically configured in the same manner as the block-side structure ST Y1 . However, a dummy transistor structure DTr' is provided below the block-side structure STY4. The dummy transistor structure DTr' is configured in the same manner as the dummy transistor structure DTr. In addition, the lower end of the conductive layer LI Y4 contained in the block-side structure ST Y4 is connected to the upper surface of the conductive layer 223 contained in the dummy transistor structure DTr'.

[0114] In this configuration, the conductive layer LI MCA near the storage cell array region R Y1 and the conductive layer LI Y4 also both act as shielding electrodes, so that the storage block BLK can be better protected from external electromagnetic waves.

[0115] [Fifth Embodiment]

[0116] Next, with reference to Figure 31 andFigure 32 , the semiconductor memory device of the fifth embodiment will be described. The semiconductor memory device of the fifth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the fifth embodiment includes a block-side structure ST as an extension extending in the Y direction Y5 to replace the block-side structure ST Y1 .

[0117] The block-side structure ST Y5 is basically configured in the same manner as the block-side structure ST Y1 . However, as described with reference to Figure 4 , Figure 10 etc., the block-side structure ST of the first embodiment Y1 includes a conductive layer LI Y1 . On the other hand, as shown in Figure 31 and Figure 32 , the block-side structure ST of the fifth embodiment Y5 does not include the conductive layer LI Y1 , but is formed of an insulating layer such as silicon oxide (SiO2). In addition, as shown in Figure 31 , the width W in the X direction of the block-side structure ST Y4 has a size of twice the width W in the Y direction of the insulating layer SW STY5 included in the inter-block structure ST X1 i.e., 2W X1 or less. SWX1 SWX1

[0118] The semiconductor memory device of the fifth embodiment is basically manufactured in the same manner as the semiconductor memory device of the first embodiment. However, in the manufacturing method of the fifth embodiment, in the steps described with reference to Figures 15 - 17 , the width in the X direction of the groove STA Y1 is made smaller than the width in the Y direction of the groove STA X1 . In addition, in the steps described with reference to Figure 20 , when forming the insulating layer SW X1 , the insulating layer SW X1 is not used to fill the groove STA X1 , and an insulating layer such as silicon oxide (SiO2) is formed with a film thickness sufficient to fill the groove STA Y1 .

[0119] According to this configuration, deformation of the hollow structure as described above can be suppressed with a smaller area.

[0120] In addition, in the example of Figure 32 , the block-side structure ST Y5 ​An example where the lower end reaches the upper surface of the semiconductor substrate 100. However, for example, as Figure 33 shown, the block-side structure ST Y5 The lower end of can also be located at a position higher than the upper surface of the semiconductor substrate 100, the conductive layer 111, and a part of the conductive layer 110.

[0121] [Sixth Embodiment]

[0122] Next, with reference to Figure 34 and Figure 35 , a semiconductor memory device according to the sixth embodiment will be described. The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0123] However, the semiconductor memory device according to the sixth embodiment includes an inter-block structure ST X6 as an extended body extending in the X direction, instead of the inter-block structure ST X1 . The inter-block structure ST X6 is basically configured in the same manner as the inter-block structure ST X1 . However, as described with reference to Figure 5 and so on, the inter-block structure ST X1 of the first embodiment includes a conductive layer LI X1 . On the other hand, as Figure 34 and Figure 35 shown, the inter-block structure ST X6 of the sixth embodiment does not include a conductive layer LI X1 , but is made of silicon oxide (SiO2) or the like. In addition, as Figure 34 shown, the width W X6 in the Y direction of the inter-block structure ST STX6 has a size of twice the width W Y1 in the X direction of the insulating layer SW SWY1 included in the block-side structure STY1, that is, 2W SWY1 or less.

[0124] In addition, as Figure 35 shown, the semiconductor memory device according to the sixth embodiment includes a semiconductor layer 140 and a conductive layer 141 provided above the semiconductor substrate 100 and separated from the semiconductor substrate 100. The semiconductor layer 140 is a semiconductor layer such as polysilicon containing N-type impurities such as phosphorus (P). The conductive layer 141 is connected to the lower surface of the semiconductor layer 140. The conductive layer 141 can be, for example, a metal such as tungsten (W), or tungsten silicide, or other conductive layers. In addition, the semiconductor layer 120' in this embodiment is basically configured in the same manner as the semiconductor layer 120, but is not connected to the P-type well region 100P of the semiconductor substrate 100, but is connected to the N-type well region 100N.

[0125] In addition, in the semiconductor memory device of the sixth embodiment, the block-side structure ST Y1 is provided at a position overlapping with the conductive layer 141 when viewed from the Z direction. In addition, the block-side structure ST Y1 has its lower end connected to the semiconductor layer 140.

[0126] [Other Embodiments]

[0127] The semiconductor memory devices of the first to sixth embodiments have been illustrated above. However, the above configurations and manufacturing methods are merely illustrative, and the specific configurations and the like can be adjusted as appropriate.

[0128] For example, in the first to fifth embodiments, the lower end of the semiconductor layer 120 is connected to the P-type well region 100P1 of the semiconductor substrate 100. However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the lower end of the semiconductor layer 120 may also be connected to the N-type well region 100N. For example, as illustrated in the sixth embodiment, a semiconductor layer such as polysilicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) may be provided above the semiconductor substrate 100, and the lower end of the semiconductor layer 120 may be connected to this semiconductor layer. In this case, the block-side structures ST Y1 、ST Y3 、ST Y4 、ST Y5 may be provided at positions overlapping with the semiconductor layer when viewed from the Z direction, rather than at positions overlapping with the P-type well region 100P1 when viewed from the Z direction. In addition, in this case, the lower ends of the inter-block structures ST X1 、ST X6 , and the lower ends of the block-side structures ST Y1 、ST Y3 、ST Y4 、ST Y5 may be connected to this semiconductor layer, rather than to the surface of the semiconductor substrate 100.

[0129] In addition, the semiconductor memory device of each embodiment only needs to include at least one of the block-side structures ST Y1 、ST Y3 、ST Y4 、ST Y5 . For example, the semiconductor memory device of the first embodiment may include the block-side structure ST Y3 or the block-side structure ST Y4 to replace the block-side structure ST Y1 . In addition, for example, the semiconductor memory device of the sixth embodiment may include, in addition to the block-side structure ST Y1 , also the block-side structure ST Y5, or may have a block-side structure ST Y5 to replace the block-side structure ST Y1 . Additionally, in this case, the width of the block-side structure ST Y5 in the X direction may be the same as the width W X6 of the block-interval structure ST STX6 in the Y direction, or may be smaller than the width W STX6 .

[0130] Additionally, in the example of Figure 1 , the length of the block-side structure ST Y1 in the Y direction is the same as the length of the memory cell array region R MCA in the Y direction. However, this configuration is only an example, and the specific configuration can be adjusted as appropriate. For example, as Figure 36 shows, the length of the block-side structure ST Y1 in the Y direction can be made smaller than the length of the memory cell array region R MCA in the Y direction, so that multiple block-side structures ST Y1 are provided in the Y direction. In this case, for example, the length of the block-side structure ST Y1 in the Y direction can be the same as the width of one or more memory blocks BLK in the Y direction, or can be larger than this width. The block-side structures ST Y3 、ST Y4 、ST Y5 of other embodiments are the same as well.

[0131] Additionally, in the said example, the block-side structures ST Y1 、ST Y3 、ST Y4 、ST Y5 have a substantially plate-like shape extending in the Z direction and the Y direction. However, for example, these block-side structures can also be formed into a substantially cylindrical shape as Figure 37 shows. In this case, in the region between the memory cell array region R MCA and the row decoder region R RD , multiple block-side structures ST Y1' arranged in the Y direction are provided. Additionally, Figure 37 the block-side structure ST Y1' shown has a conductive layer LI Y1' and an insulating layer SW Y1' . The conductive layer LI Y1' is basically configured in the same way as the conductive layer LI Y1 , but is configured as a substantially cylindrical shape extending in the Z direction. The insulating layer SW Y1' is basically configured in the same way as the insulating layer SW Y1 , but is configured to cover the conductive layer LIY1' substantially cylindrical on the outer peripheral surface. Additionally, in Figure 37 , an example is shown in which the block-side structure ST Y1 is configured to be substantially cylindrical. However, for example, the block-side structures ST Y3 , ST Y4 , ST Y5 of other embodiments may also be configured to be substantially cylindrical.

[0132] [Other]

[0133] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention and are included in the invention described in the claims and its equivalents.

[0134] [Description of Reference Numerals]

[0135] 100 Semiconductor substrate

[0136] 110 Conductive layer

[0137] 120 Semiconductor layer

[0138] 130 Gate insulating film

[0139] BLK Memory block

[0140] STX1 Inter-block structure

[0141] STY1 Block-side structure

[0142] BL Bit line.

Claims

1. A semiconductor memory device, characterized in that Comprising: A substrate; Two memory blocks arranged in a first direction parallel to the surface of the substrate and extending in a second direction parallel to the surface of the substrate and intersecting the first direction and different from the first direction; A first extension body disposed between two adjacent memory blocks in the first direction and extending in the second direction; A second extension body separated from the two memory blocks in the second direction and extending in the first direction; And A plurality of bit lines arranged in the second direction and extending in the first direction and connected to the two memory blocks; and The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged in a third direction intersecting the surface of the substrate and different from the first direction and the second direction, The first extension body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than the first conductive layer closest to the substrate among the plurality of first conductive layers, The second extension body has one end and the other end in the third direction, the one end is closer to the substrate than the other end, and the one end is closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, The other end of the first extension body and the other end of the second extension body are farther from the substrate than the first conductive layer farthest from the substrate among the plurality of first conductive layers and closer to the substrate than the plurality of bit lines, The second extension body is separated from the first extension body in the second direction.

2. The semiconductor memory device according to claim 1, wherein The length of the second extension body in the first direction is greater than the length of at least one of the two memory blocks in the first direction.

3. The semiconductor memory device according to claim 1, wherein The length of the second extension body in the second direction is less than the length of the first extension body in the first direction.

4. The semiconductor memory device according to claim 3, wherein The one end of the second extension body is farther from the substrate than the first conductive layer closest to the substrate among the plurality of first conductive layers.

5. The semiconductor memory device according to claim 1 or 2, wherein The length of the second extension body in the second direction is greater than the length of the first extension body in the first direction.

6. The semiconductor memory device according to claim 1, 2 or 4, characterized in that The second extension body includes a second conductive layer, the second conductive layer has one end and the other end in the third direction, the one end is closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, and the other end is farther from the substrate than the first conductive layer farthest from the substrate among the plurality of first conductive layers.

7. The semiconductor memory device according to claim 6, wherein The second conductive layer is electrically connected to an external terminal to which a ground voltage can be supplied.

8. The semiconductor memory device according to claim 1 or 2, wherein The substrate includes a first well region, The two memory blocks are disposed on the first well region, The second extension body is disposed at a position overlapping the first well region when viewed from the third direction.

9. The semiconductor memory device according to claim 8, wherein The second extension body includes a second conductive layer, the second conductive layer has one end and the other end in the third direction, the one end is closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, and the other end is farther from the substrate than the first conductive layer farthest from the substrate among the plurality of first conductive layers. The second conductive layer is connected to the first well region.

10. The semiconductor memory device according to claim 1, wherein The second extension includes a second conductive layer having one end and the other end in the third direction, the one end being closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, and the other end being farther from the substrate than the first conductive layer among the plurality of first conductive layers that is farthest from the substrate. The semiconductor memory device further includes: a second insulating layer provided on the surface of the substrate; a first semiconductor layer provided on the surface of the first insulating layer; and a third conductive layer provided on the surface of the first semiconductor layer; and the second conductive layer is connected to the third conductive layer.

11. The semiconductor memory device according to claim 1, wherein A third extension is further provided, the third extension being separated from the two memory blocks in the second direction and extending in the first direction. The third extension includes a fourth conductive layer having one end and the other end in the third direction, the one end being closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, and the other end being farther from the substrate than the first conductive layer among the plurality of first conductive layers that is farthest from the substrate. The substrate includes a first well region and a second well region. The first well region is provided in the second well region. The fourth conductive layer is connected to the second well region.

12. The semiconductor memory device according to claim 1 or 2, wherein A second semiconductor layer provided between the substrate and the two memory blocks is further provided, and the second extension is provided at a position overlapping the second semiconductor layer when viewed in the third direction.

13. The semiconductor memory device according to claim 12, wherein The second extension includes a second conductive layer having one end and the other end in the third direction, the one end being closer to the substrate than at least a part of the first conductive layers among the plurality of first conductive layers, and the other end being farther from the substrate than the first conductive layer among the plurality of first conductive layers that is farthest from the substrate. The second conductive layer is connected to the second semiconductor layer.

14. The semiconductor memory device according to claim 1, wherein A third insulating layer is further provided, and the third insulating layer covers at least a part of the side surface of the second extension in the second direction.

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