Method for checking an erase phase of a memory device

Abstract

The present disclosure relates to a non-volatile memory device comprising at least an array of memory cells and associated decoding and sensing circuitry and a memory controller, and a method for checking an erase phase of said non-volatile device; said method comprising: performing a dynamic erase operation of at least a block of memory; storing at least an internal block variable and / or a known pattern of said dynamic erase operation in a dummy row.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to methods for setting operating parameters of integrated memory circuits.

[0002] More specifically, this disclosure relates to methods for self-adjusting operating parameters of a memory device and for checking the erase phase of a memory device. Background Technology

[0003] Memory devices are well known in the electronics field for storing and accessing digital information. Generally, different types of semiconductor memory devices can be incorporated into more complex systems that include non-volatile memory components as well as volatile memory components, such as so-called system-on-a-chip (SoCs) in which the aforementioned memory components are embedded.

[0004] However, today's automotive applications demand that SoCs continuously improve their performance and efficiency for real-time operating systems, and known solutions can no longer meet these needs.

[0005] Non-volatile memory provides permanent data by retaining the stored data even when not powered and can include NAND flash memory or NOR flash memory, among others. NAND flash also features fewer erase and write cycles and requires less chip area per cell, thus allowing for greater storage density and lower cost per bit compared to NOR flash.

[0006] A key characteristic of flash memory is that it can be erased in blocks, rather than one byte at a time. However, a critical drawback of flash memory is that it can only undergo a relatively small number of write and erase cycles within a given block.

[0007] Flash memory devices may comprise large arrays of memory cells, typically organized into rows and columns, for storing data. Individual memory cells and / or ranges of memory cells can be addressed by their rows and columns. When the memory array is addressed, one or more address translation layers may exist to translate, for example, the logical addresses used by the host device (i.e., the SoC) between physical addresses corresponding to locations within the memory array.

[0008] Although uncommon, the address information provided to the memory device on its command / address bus may still be corrupted due to errors, making it possible to perform internal operations of the memory device (e.g., read operations, write operations, erase operations, etc.) on a physical address that is different from the physical address targeted by the controller of the host device or the memory device.

[0009] Therefore, there is a need for a method to verify that memory operations have been performed at the expected address, and this disclosure focuses on a method for checking the correctness of the read phase. Summary of the Invention

[0010] In one aspect, this disclosure relates to a non-volatile memory device comprising at least one memory cell array and associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises: a plurality of memory blocks; and at least one dummy line for each block, the dummy line being located outside the address space of each block for storing at least internal block variables and at least one known pattern during an erase phase.

[0011] In one aspect, this disclosure relates to a system comprising: a host device; a non-volatile memory device coupled to the host device and including at least one memory cell array with associated decoding and sensing circuitry and a memory controller; a plurality of memory blocks in the memory cell array; and at least one dummy line for each block, the dummy line being located outside the address space of each block for storing at least internal block variables and at least one known pattern during an erase phase.

[0012] In another aspect, this disclosure relates to a method for inspecting an erase operation of a non-volatile memory device comprising at least one memory cell array and associated decoding and sensing circuitry and a memory controller, the method comprising: performing an erase phase of a memory block; storing at least internal block variables and at least one known pattern of the erase phase in a dummy line associated with the memory block.

[0013] In another aspect, this disclosure relates to a method for erasing a non-volatile memory device comprising at least one memory cell array and associated decoding and sensing circuitry and a memory controller, the method comprising: performing a dynamic erase operation on at least one memory block; storing at least internal block variables of the dynamic erase operation in a dummy row; and storing at least one known pattern in the dummy row. Attached Figure Description

[0014] Figure 1 shows a schematic diagram of a system including a memory component and a controller that exchanges data, addresses and control signals with the memory device.

[0015] Figure 2 This is a schematic diagram of a memory component according to the present disclosure;

[0016] Figure 3 This is a schematic layout diagram of an example of a memory component according to an embodiment of the present disclosure;

[0017] Figure 4This is a schematic diagram of a memory block formed by multiple rows of a memory array according to an embodiment of the present disclosure;

[0018] Figure 5 This is a schematic diagram of the address register group for memory pages in the memory components of this disclosure;

[0019] Figure 6 A schematic diagram showing the distribution of good erase / programming units (1 bit / unit);

[0020] Figure 7 Showing the corresponding Figure 6 The diagram, which reports an expanded distribution that is attributed to the shift toward the depletion state (negative Vth) caused by aging, temperature, and stress;

[0021] Figure 8 A block diagram illustrating an example of the method steps of this disclosure. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments. Throughout the drawings, the same reference numerals describe substantially similar components. Other embodiments may be disclosed without departing from the scope of this disclosure, and structural, logical, and electrical changes may be made. Therefore, the following detailed description should not be viewed in a limiting sense.

[0023] Several embodiments of this disclosure are directed to memory devices, systems including memory devices, and methods of operating memory devices for the purpose of avoiding potential problems of aging, temperature, and process drift during memory operation.

[0024] In one embodiment of this disclosure, a novel memory architecture is provided to improve the security and performance of the data erasure phase in a non-volatile memory device.

[0025] More specifically, this disclosure relates to a non-volatile memory device comprising at least one memory cell array and associated decoding and sensing circuitry and a memory controller, wherein the memory array includes:

[0026] - Multiple memory blocks;

[0027] - At least one dummy line for each block, the dummy line being located outside the address space of each block to store at least internal block variables and at least one known pattern for the read phase.

[0028] The aforementioned internal block variables are parameters used during the erase phase of a memory block.

[0029] More specifically, internal block variables are parameters such as the erase pulses and / or target voltages applied to the memory block during the erase phase.

[0030] Furthermore, before starting the erase algorithm on the memory block, the internal block variables from the previous erase phase are retrieved from the dummy row.

[0031] To better understand this disclosure, it should be noted that flash memory has become a common source of non-volatile memory for a wide range of electronic applications.

[0032] Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data state of each cell can be determined by changing the threshold voltage of the cell through programming charge storage structures (such as floating gates or trap layers or other physical phenomena). Single-level cells (SLCs) store binary digits (e.g., logic 0 or logic 1); multi-level cells (MLCs) store more bits in the same physical cell; for example, triple-level cells (TLCs) use eight threshold voltage levels to store three information bits.

[0033] When a memory array is addressed, one or more address translation layers may exist, such as the translation between logical addresses used by the host device and physical addresses corresponding to locations within the memory array. This type of mechanism is well-suited for implementing advanced features such as block wear leveling and / or factory / field block redundancy.

[0034] Although uncommon, it is still possible for incomplete erasure to occur during an erase operation. In such situations, it is crucial to have a mechanism that allows the detection of blocks that have not been properly erased or have not been completely erased. Since blocks that have not been properly erased cannot be read or programmed, it is extremely important to avoid any unexplained failures during the read or programming phase on blocks where incomplete erasure has occurred.

[0035] In some embodiments, at each power-on and / or reset phase and / or as required by the user, all blocks in the array are verified to determine whether some of the blocks are in an incomplete erasure state. This verification can be accomplished by verifying the presence of patterns in the dummy rows described above.

[0036] Without completing the erasure detection:

[0037] - Provide a warning message to the host device; and / or

[0038] - Perform an erase on this type of block to restore the block. This can happen automatically or upon a host command.

[0039] For example, a warning and / or recovery can be triggered by detecting an incorrectly completed erase operation in a block.

[0040] In addition, the following situation may occur: temperature variations within the same device can produce read offsets known as the ghost temperature problem.

[0041] The drawbacks associated with such temperature variations affect the true bit distribution detected by the sensing amplifier, causing a shift relative to its programmed ideal center value. In some cases, such offsets and / or amplified threshold voltage distributions can cause the same problems during read operations as with incomplete erase operations, as will be presented in the following description.

[0042] To illustrate this simply, if the programming phase is performed at -40°C, the following scenario may occur: at 120°C, the read results will contain multiple errors. This is a real problem for all chips integrated into automotive systems, where temperature rise during vehicle operation must be taken into account.

[0043] Therefore, the memory device read phase is never performed in an environment similar to that of the original programming phase; the same is true for the erase phase.

[0044] A memory device can be defined as a kind of "real-time" device in the sense that it must publish reliable data in all environmental operating conditions (regardless of whether it has been tested in the factory and reported for approval due to positive test results).

[0045] Furthermore, the increased device aging is attributed to temperature-induced drift, and memory devices integrated into the on-chip system of autonomous vehicles are particularly sensitive to this issue.

[0046] Figure 1 illustrates a schematic example of a system 10 incorporating a flash memory device or component 100. The system also includes a memory controller 101 coupled to the memory device 100.

[0047] The controller 101 is shown coupled to the memory device 100 on a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus may be a 64-bit and / or 128-bit wide double data rate (DDR) bus.

[0048] The system device 10 shown in Figure 1 may be a host device or a system-on-a-chip coupled to the memory component 100, as presented in the description of other embodiments with reference to other figures in this disclosure. In any case, the system-on-a-chip 10 and the memory device 100 are implemented on respective dies obtained through different lithography techniques and manufacturing processes.

[0049] Figure 2This is a schematic diagram of a memory component according to the present disclosure. The memory component 100 is a standalone structure but is closely associated with a host device or a System-on-a-Chip (SoC) structure. More specifically, the memory device 100 is associated with and linked to an SoC structure that partially overlaps with such a structure, and the corresponding semiconductor regions of the SoC structure are used for other logic circuits and for providing support to the standalone memory device 100 on the partially overlapping structure, for example, through multiple pillars or other similar alternative connections (e.g., convex balls) or through a flip-chip-like technique.

[0050] More specifically, this non-volatile memory component 100 includes an array 90 of flash memory cells and a circuit system surrounding the memory array. Coupling between the SoC structure 10 and the memory component 100 is achieved by interconnecting multiple corresponding pads or pin terminals that face each other in the circuit layout, in which pad alignment is maintained even if the size of the memory component is modified.

[0051] In one embodiment of this disclosure, the pads of the memory components are arranged on the surface of the memory component 100, specifically on top of the array. More specifically, the pads are arranged above the array such that when the memory component 100 is inverted, its pads face the corresponding pads of the host or SoC architecture 10. Signals for data (105), command (106), and address (107) buses are transmitted through the pads described above; the pads can also be used for power supply voltages and other signals and / or voltages.

[0052] Finally, a memory device 100 is manufactured according to user requirements, ranging from at least 128 megabits to 512 megabits or even greater. More specifically, the proposed external architecture allows for exceeding the current limits of eFlash (i.e., embedded flash technology) to allow for the integration of larger memories, which can be 512 megabits and / or 1 gigabit and / or even larger, depending on the memory technology and technology node.

[0053] For more specific reference Figure 2 An example will be provided to disclose the main structure of the memory component 100 according to an embodiment of the present disclosure.

[0054] The memory component 100 includes at least: I / O circuitry 5, micro sequencer 3, memory cell array 90, voltage and current reference generator 7, charge pump 2 located on or below the array periphery and decoding circuitry 8, sensing amplifier 9 and corresponding latch, and command user interface, such as CUI block 4.

[0055] The memory cell array 90 includes non-volatile flash memory cells. These cells can be erased in blocks, rather than one byte at a time. Each erasable memory block comprises multiple non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating voltages and timings on the access and data lines.

[0056] For writing to and erasing the memory cells of array 90, a dedicated logic circuit section is provided, which includes a simplified reduced instruction set computer (RISC) controller or a modified finite state machine or logic circuitry for handling programming and erasing algorithms.

[0057] To read memory cells from array 90, a dedicated circuit section is provided, which includes an optimized read finite state machine to ensure high read performance, such as branch prediction, fetch / prefetch, interrupt management, etc. Error correction is left as an operation to SoC 10; additional bits are provided to controller 101 to store any possible ECC correctors associated with the page. The ECC cell allows the host controller to understand whether corruption is occurring on the data-addressed content.

[0058] Errors affecting the address information provided to the memory device on the command or address bus can cause memory operations to be performed at a memory address that is different from the intended address.

[0059] In this respect, the controller is configured to receive a data word at an address to be stored in the memory cell array. The controller is further configured to command the array to read the data word from the address, receive response data from the array, and verify that the orientation marker of the response data corresponds to the desired address.

[0060] If the orientation marker does not correspond to the address, the controller is configured to indicate an error. This error is detected in the metadata containing ECC information.

[0061] ECC information is stored adjacent to the data that provides error correction capabilities.

[0062] Now, examining the internal structure of memory component 100 more closely, it should be noted that the architecture of array 90 is constructed as a series of subarrays 120, as shown in... Figure 3 The diagram is shown schematically.

[0063] The sense amplifier SA at the output of each subarray 120 is directly connected to the modified JTAG cell 140 to integrate the JTAG structure and sense amplifier into a single circuit section. This allows for minimizing the latency when propagating the output of the memory array to the SoC.

[0064] Each subarray contains 120, which will be referenced later. Figure 4 The disclosed memory blocks 160.

[0065] In this way, smaller sectors significantly reduce access time and increase the overall throughput of the memory component compared to known solutions.

[0066] Each subarray 120 can be independently addressed within the memory device 100. Furthermore, the memory array 90 is configured to have, for example, at least four memory subarrays 120, one for each communication channel with a corresponding core of the host device or SoC 10. Different numbers of cores and / or subarrays can be used. The host device or system-on-a-chip 10 typically contains more than one core, each core coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 100.

[0067] Therefore, in the embodiments of the present invention, each subarray 120 can access a corresponding channel to communicate with the corresponding core of the system-on-chip 10.

[0068] Additionally, it should be noted that each subarray 120 contains an address register connected to a data buffer register, similar to the architecture used in DRAM memory devices.

[0069] Furthermore, according to one embodiment of this disclosure, at least one dummy row 300 is associated with each block 160 of the memory subarray 120.

[0070] This dummy row 300 is located within the address space of memory array 90 and is used for optimizing read, write, and erase parameters.

[0071] In addition, this dummy line is used to erase robustness checks, to ensure the smooth completion of modification operations, and for other purposes.

[0072] According to another embodiment, the dummy rows of block 160 are located in another block of memory subarray 120; this allows a single dummy row to remain updated for multiple memory blocks that may experience the same environmental changes.

[0073] As will be understood by those skilled in the art, such dummy rows can also reside in a dedicated portion of the memory array (e.g., a subarray not coupled to the SoC). Furthermore, if the contents of this "external" row become invalid, it must be updated, for example, rewritten, and therefore erased, but such an operation would mean erasing the entire block of NAND memory in which this "external" row resides.

[0074] The dummy line 300 may contain the following information: suitable for tracking parameters that may be used during the read and erase phases of the memory component 100 and / or for storing some parameters for detecting possible incomplete erases.

[0075] The dummy row 300 contains a known mode of controller 101 of memory device 100.

[0076] Suppose a known pattern value, such as 0x55 or 0xAA, is recorded in dummy row 300 in hexadecimal form. This value is well-suited because it contains the same amount of "0" and "1" logic values ​​stored in two distinct flash memory cells within the array with two different thresholds.

[0077] In another embodiment, the well-known patterns described above are not limited to values ​​in hexadecimal form such as 0x55 or 0xAA, but also include updates to erase parameters, such as the amplitude / number of step pulses and / or the erase / depletion check level.

[0078] In any case, since those values ​​are also known a priori to the memory controller, the system will execute several read cycles that change the read trimming parameters until the value is correctly read. The correctly read modified trimming parameters will correspond to the set temperature value recorded in the programmable register. In the case of a multi-level cell memory (N-level), the value to be stored can be selected to overwrite all N levels present in the memory array. For example, the known pattern can include programmed cells in all available levels of the multi-level cell memory device.

[0079] The read phase of other memory blocks of subarray 120 may be performed only if the trimming parameters set for the read phase are fully capable of retrieving the correct known values.

[0080] In one embodiment of this disclosure, the output of the general subarray 120 is formed by extended pages combining data units, address units, and ECC units. In this example, the total number of bits will involve 168 pads per channel, such as... Figure 5 As shown.

[0081] The combination of data unit, address unit, and ECC unit allows for complete security coverage of the bus according to the standard requirements of ISO 26262, because ECC covers the entire bus communication (data unit + address unit), while the presence of the address unit provides confidence that the data is accurately coming from the addressable location of the controller.

[0082] Furthermore, each memory subarray 120 is constructed within a memory block 160. The memory block architecture, including each location of the memory array, can be defined as an extended page 150. An extended page is the 128-bit I / O required by the SoC and involves 16-bit ECC with 24-bit addressing (up to 2GB of available space).

[0083] exist Figure 5 The diagram shows a schematic of the output of the sense amplifier SA through a modified JTAG unit 140, where it can be understood that, as a non-limiting example, the extended page 150 has a composition of 168 bits.

[0084] In other words, the 128-bit atomic pages used to fill the communication channels with the SoC device 10 in each subarray 120 have been expanded in this embodiment of the invention to contain the stored address and form an ECC for the 168-bit extended page. The two extended pages 150 form a “superpage”.

[0085] Each memory block 160 contains 256 rows, and each row 135 contains sixteen extended pages of the above size. Each superpage contains two 168-bit combinations of data bits, address bits, and ECC bits. Therefore, each row 135 of the memory array 90 can contain up to sixteen double pages, each 128 bits, plus an address and ECC corrector spare bit for each page.

[0086] For the sake of providing numerical values, an extended page is formed by 128 + 16 + 24 = 168 bits, and each row of 135 has sixteen extended pages, which together comprise 168 * 16 = 2688 bits.

[0087] Therefore, each row 150 of memory block 160 contains at least sixteen pages, which include a memory word plus corresponding address bits and corresponding ECC bits. Obviously, another size can be chosen, and the reported values ​​are only for illustrative purposes of a non-limiting example. This allows the final result of the block to be directly driven to the host device or SoC 10 without using a high-power output buffer and without optimizing the path.

[0088] The concept based on this disclosure begins with consideration of the memory component 100 itself using a stored reference that can detect temperature and aging drift affecting the memory array 90.

[0089] By using drift information of the well-known stored pattern, it is possible to set the optimal parameters to be used in the next erase operation. This information can be used to properly adjust all voltage values ​​and timing (i.e., signal shapes) that will be used in each stage of the erase algorithm.

[0090] Generally, the correct voltage levels and timing to be used in each erase stage must follow technical guidelines. These guidelines, provided by flash cell technicians, map the degree of aging to the associated voltage / timing values ​​to be used. According to these guidelines, several well-known or predefined parameters are defined a priori for a given technology. For example, these parameters can be further adjusted during electrical testing of the die to account for process variations.

[0091] In another embodiment of this disclosure, adjusted or unadjusted parameters and / or known patterns may be stored in dummy row 300 during wafer sorting or electrical testing in some embodiments, and / or updated during the field operating lifetime, such as after a properly performed erase operation.

[0092] Now see the erasure procedure according to this method:

[0093] The well-known pattern is read from virtual line 300 and processed by the internal controller to determine the optimal parameters to be used in the following steps. The erasure algorithm can then begin.

[0094] If the parameter is not present in dummy line 300, this means an incomplete erase has occurred. This event must be recovered by erasing the entire block. Otherwise, the block cannot be programmed or read correctly. The absence of a parameter in the dummy line can be confirmed by a mismatch between the pattern (which is also normally present in dummy line 300, as will be explained in more detail below) and the expected known pattern.

[0095] Under normal operating conditions, a pre-programming stage, also known as programming all0, is typically provided for erasing this type of memory device.

[0096] Normally, before the erasure phase begins, the threshold of the cell to be erased moves toward the programming state. This is accomplished by emitting some blind (i.e., unverified) programming pulses.

[0097] This procedure uses the number of pre-programmed pulses to be issued and / or the voltage to be used, based on the previous read step of the dummy line.

[0098] During the erase pulse phase, the voltage and pulse duration can be set to quickly and safely erase cells in the block (based on the previous erase phase).

[0099] If the block is cycled (multiple program-erase cycles estimated using drift information), then some appropriate strong voltage and pulse duration are used. Normally, the block is erased by applying several different erase pulses (for a negative gate voltage and / or a positive body source). This sequence can be referred to as a ladder.

[0100] Once an erase pulse is issued (as described above), the erase cell state is verified by applying the appropriate cell gate voltage value that will be used to perform the erase verification, thereby ensuring a good erased cell distribution with sufficient margin.

[0101] In other words, step #1 is based on the erase pulse in the ladder, while step #2 is based on erase verification. Drift information can be used to select the correct erase verification value.

[0102] For example, Figure 6 This diagram illustrates the distribution of correctly erased / programmed cells (1 bit / cell). All cell threshold groups are correctly bounded within the assigned boundaries (i.e., programmed '0' or erased '1'). Repeat steps #1 and #2 (erase pulse and erase verification) until all cells meet the erase verification criteria.

[0103] Once all cells have been correctly (erase) verified, also check for cells with excessively low thresholds. Figure 6 This is illustrated by the annotation depletion verification DV.

[0104] In the case of attenuation, soft programming operations are issued on the required cells. The parameters used to perform soft drift on the cells can be selected based on the degree of cell aging so that the threshold is correctly placed within the erase cell distribution.

[0105] Incorrect selection of such parameters can lead to poor placement of the cell threshold outside the erase distribution (above the erase verification value), which would imply that the block must be erased again starting from step #1 above, which provides the erase pulse (this is time-consuming).

[0106] Once erasure is complete (as per the previous stages), the well-known mode or even erasure parameters (i.e., step pulse amplitude / number and / or erase / depletion check level, etc.) are written into line 300, which will be used for the next erasure cycle. Specifically, the mode selected by storing settings (0x55, 0xAA, etc.) is programmed and verified using appropriate programming pulses (the voltage and timing of which depend on the current aging of the block). Figure 6 (PV stage).

[0107] By using the drift information and the number of erase pulses provided in the erase phase (step #1 above), it is possible to infer that the block is nearing the end of its lifespan.

[0108] This information can be used as a warning to customers or as a flag for internal algorithms to trigger possible block wear leveling or On-Field Block Redundancy (OFBR) operations when implemented. OFBR involves replacing a block with a spare block.

[0109] Figure 7 Showing the corresponding Figure 6 The diagram shows an increased distribution, but reports attribute this to aging, temperature, and / or stress. Threshold voltage distributions tend to widen under aging, temperature, and / or stress. According to the method of this disclosure, it is possible to track the distribution widening and cell degradation and use this information to correct subsequent erase pulses. This allows for improved reliability and performance during the erase phase.

[0110] The trimming sequence used to perform the read phase of the memory array under different temperatures or aging conditions of the memory device can be detected in the laboratory during the technology development phase and / or product testing and stored in the programmable register of the memory controller 101.

[0111] Similarly, the parameters used during the erasure phase can be adjusted in the same manner during field operations.

[0112] For the content of the correct read phase, the actual temperature value during the read phase is not important. This temperature can be higher (even much higher) or lower than the temperature level during the programming phase when the known values ​​are executed.

[0113] The system is automatically protected against any thermal drift because the trimming parameter is selected only after a correct read of the known sequence stored in dummy line 300 has been performed and the trimming parameter has been set accordingly to correctly read that known value.

[0114] The procedure allows for the identification of more suitable read trimming parameters for a correct read phase at a specific temperature value. This type of procedure does not need to be repeated at every read phase or access point. Instead, it can be performed periodically or in a more appropriate manner (e.g., by abnormally incrementing the ECC bit) when a potential problem is detected.

[0115] An increase in the number of ECC bits can lead to reports of excessive erroneous reads from the memory device. In such cases, the system can automatically begin detecting potential thermal drift and then proceed with a procedure to adjust trimming parameters.

[0116] Dummy line 300 can also be used as an indication of possible failure of the erase operation.

[0117] The method disclosed herein allows for proper inspection of the erase phase of memory component 1, or more preferably, proper inspection of the erase phase of memory block 160.

[0118] A method for erasing a non-volatile memory device comprising at least one memory cell array and associated decoding and sensing circuitry and a memory controller includes at least the following steps:

[0119] -Execute the erase operation on memory block 160;

[0120] - Store at least the internal block variables and at least one known pattern of the erase phase in the dummy line 300 of the memory block 160.

[0121] exist Figure 8 The above method stages are illustrated in the examples. Figure 8 This is a flowchart 800 illustrating a dynamic erase operation of at least one memory block 160 as the first stage 810.

[0122] Subsequently, in the next stage 820, at least the internal block variables of the erase operation are stored in dummy line 300.

[0123] Finally, in stage 830, at least the known patterns are also stored in the dummy row 300.

[0124] The first step of the erasure algorithm is to invalidate the contents of the dummy row so that the new erased variable can be stored in dummy row 300 at the end of the erasure phase. For example, to invalidate the contents of dummy row 300, a programmable fallback or invalidation mode can be used, or the entire row can be overwritten.

[0125] The content of dummy row 300 includes at least internal block variables, which refer to parameters used during the erase phase of the block, such as erase pulse, target voltage, etc.

[0126] Furthermore, the content of dummy row 300 should also contain at least a known pattern, which refers to the previously mentioned known hexadecimal value. Alternatively, examples of known patterns include: 0x0, 0x1, 0x2, ..., 0xF, or any other sequence of bits that are set to zero and one in a similar manner, such as: 0x55, 0xAA, 0x33, etc. As previously mentioned, in cases where multi-level cells store more than a single bit in a single physical cell, the corresponding known pattern should be selected to account for correct detection of all possible threshold voltage levels.

[0127] The method disclosed herein enables the execution of an erasure algorithm using specific parameters. In other words, before starting the erasure algorithm on memory block 160, the internal block variables from the previous erasure phase are retrieved from the dummy line 300.

[0128] The completion of the erasure algorithm is manifested by storing the key erasure parameters and the known pattern.

[0129] The storage of key parameters provides feedback on block health and also determines how wear leveling must be applied to block 160 of subarray 220.

[0130] The existence of a known pattern at the end of the dummy row ensures the correctness of the operation.

[0131] Block recovery is triggered when block variables and / or known patterns cannot be correctly read when accessing dummy row 300, for example, in cases of unsuccessful retrieval (such as in cases where an incomplete erase event could occur during a previous erase operation before the erase procedure has been correctly completed). Block recovery may include an erase procedure based on predefined (e.g., factory-defined) parameters. Therefore, a blind pre-programming phase is performed (to set all bits to All0 before the actual erase pulse sequence). Subsequently, a ladder is applied to the bits of the block of interest, increasing the applied voltage steps interleaved with the erase verification step (using a predefined erase check level), and finally, verification against a predefined depletion check level is performed, possibly followed by programming of the depletion bits. The recovery erase procedure is completed by programming the known pattern into the dummy row 300 of the block for future use. Erase parameters may also be stored in dummy row 300.

[0132] The method disclosed herein allows for dynamic erase verification during the erase phase because it is possible to obtain security feedback on the correctness of the erase operation even under different operating environment conditions.

Claims

1. A non-volatile memory device, comprising: Memory cell array, comprising: Multiple memory blocks; and Multiple dummy rows corresponding to each corresponding memory block of the plurality of memory blocks, wherein each dummy row: Associated with a first address space, which is located outside the second address space of the corresponding memory block; and Configured to store internal block variables and specific patterns associated with the erase phase; and A controller, coupled to the memory cell array, is configured for each of the plurality of dummy rows to: In response to power-on of the memory cell array, determine whether the specific pattern is stored in the dummy row, wherein determining that the specific pattern is not stored in the dummy row indicates an incomplete erase of the corresponding memory block; and In response to determining that the specific pattern is not stored in the dummy row, the erase phase is performed on the corresponding memory block.

2. The non-volatile memory device of claim 1, wherein the internal block variable indicates parameters for performing the erase phase on the respective memory block.

3. The non-volatile memory device of claim 2, wherein the parameters of the erase phase include an erase pulse and a target voltage applied to the respective memory block associated with the erase phase.

4. The non-volatile memory device of claim 1, wherein the plurality of memory blocks comprises a subarray of the memory cell array.

5. A system comprising: Main unit; A non-volatile memory device coupled to the host device and including a memory cell array and a controller coupled to the memory cell array, wherein the memory cell array includes: Multiple memory blocks; Multiple dummy rows corresponding to each corresponding memory block of the plurality of memory blocks, wherein each dummy row: Associated with a first address space, which is located outside the second address space of the corresponding memory block; and Configured to store internal block variables and specific patterns associated with the erase phase; and The controller is configured for each of the plurality of dummy rows to: In response to power-on of the memory cell array, determine whether the specific pattern is stored in the dummy row, wherein determining that the specific pattern is not stored in the dummy row indicates an incomplete erase of the corresponding memory block; and In response to determining that the specific pattern is not stored in the dummy row, the erase phase is performed on the corresponding memory block.

6. The system of claim 5, wherein the controller is further configured to retrieve the internal block variable from the dummy row, wherein the internal block variable is associated with the erase phase previously performed on the respective memory block.

7. The system of claim 6, wherein the controller is further configured to initiate the execution of the erase phase on the respective memory block in response to the retrieval of the internal block variable.

8. The system of claim 5, wherein the dummy row is disposed in another block of the plurality of memory blocks or in a dedicated memory portion of the memory cell array.

9. The system of claim 5, wherein the internal block variable indicates parameters for performing the erase phase on the corresponding memory block.

10. The system of claim 9, wherein the parameters of the erasure phase include an erasure pulse and a target voltage applied to the respective memory block associated with the erasure phase.

11. The system of claim 5, wherein the plurality of memory blocks comprises a subarray of the memory cell array.

12. A method comprising: Perform the erase phase on the memory blocks of the memory cell array of the non-volatile memory device; Before the memory cell array is powered on, the internal block variables and specific patterns associated with the erase phase are stored in dummy rows corresponding to the memory blocks, wherein the dummy rows are associated with a first address space, which is located outside the second address space of the corresponding memory block; After the memory cell array is powered on, it is determined whether the specific pattern is stored in the dummy row, wherein determining that the specific pattern is not stored in the dummy row indicates an incomplete erase of the corresponding memory block; and In response to determining that the specific pattern is not stored in the dummy row, the erase phase is performed on the corresponding memory block.

13. The method of claim 12, wherein performing the erase phase includes performing a dynamic erase operation on the respective memory block.

14. The method of claim 13, further comprising invalidating the contents of the dummy line before performing the dynamic erase operation.

15. The method of claim 12, wherein storing the internal block variable includes storing parameters on the corresponding memory block for performing the erase phase.

16. The method of claim 12, wherein storing the internal block variable includes storing data indicating erase pulses and target voltages applied to the respective memory block associated with performing the erase phase.

17. The method of claim 12, further comprising retrieving the internal block variable from the dummy row, wherein the internal block variable is associated with the erase phase previously performed on the respective memory block.

18. The method of claim 17, further comprising initiating the erase phase on the respective memory block in response to retrieving the internal block variable.

19. The method of claim 18, wherein initiating the erase phase includes restoring the corresponding memory block.

20. A method for erasing a non-volatile memory device, the method comprising: Perform dynamic erase operations on memory blocks of the memory cell array; Before the memory cell array is powered on, the internal block variables of the dynamic erase operation are stored in dummy rows, wherein the dummy rows are associated with a first address space, which is located outside the second address space of the memory block; Before the memory cell array is powered on, the known patterns are stored in the dummy rows; After the memory cell array is powered on, it is determined whether the known pattern is stored in the dummy row, wherein determining that the known pattern is not stored in the dummy row indicates that the memory block has not been completely erased; and In response to determining that the known pattern is not stored in the dummy row, the dynamic erase operation is performed on the memory block.

21. The method of claim 20, further comprising invalidating the contents of the dummy line before performing the dynamic erase operation.

22. The method of claim 20, wherein the internal block variable includes an erase pulse and / or a target voltage applied to the memory block during the erase operation.

23. The method of claim 20, further comprising retrieving the previously stored internal block variables and / or the known patterns from the dummy row prior to performing another dynamic erase operation.

24. The method of claim 23, wherein performing another dynamic erasure operation includes restoring the block if the retrieval is unsuccessful.

25. The method of claim 24, wherein restoring the block comprises erasing the block according to predefined parameters.

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