A semiconductor device and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method, which comprises a wafer and a conducting structure, wherein a ring-shaped blind hole is arranged on the wafer, a metal conductor is filled in the ring-shaped blind hole, the conducting structure is formed, and the width of the ring-shaped blind hole is related to the thermal expansion coefficient of the metal conductor. The semiconductor device greatly reduces the residual stress of the wafer after silicon through hole, increases the thickness of the wafer after silicon through hole, saves the manufacturing cost, optimizes the silicon through hole structure of the wafer, and improves the performance of the wafer after silicon through hole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Through-Silicon Via (TSV) technology is a core technology for 2.5D / 3D semiconductor integration, primarily used in high-sensitivity MEMS (Micro-Electro-Mechanical Systems) sensor fabrication. TSV technology is mostly fabricated using bulk silicon processes, and its key technologies include via etching, via thin film deposition, via filling, and chemical mechanical polishing (CMP).

[0003] Typically, through-silicon via (TSV) technology involves forming vias on a wafer and then filling these vias with metal conductors to create solid metal pillars. However, because the coefficient of thermal expansion of the metal inside the solid metal pillar is greater than that of the wafer, the metal expansion under environmental factors such as high temperatures can easily cause the wafer to crack. In other words, the thermal expansion coefficients of the metal and the wafer are not well matched, which affects the reliability and usability of the wafer and results in a thinner wafer. Summary of the Invention

[0004] This application provides a semiconductor device and manufacturing method that solves the technical problem in the prior art where the thermal expansion coefficient of the internal metal of a semiconductor based on through-silicon vias is poorly matched with the thermal expansion coefficient of the wafer, resulting in poor semiconductor reliability and usability. It achieves an optimized matching strategy between the thermal expansion coefficient of the internal metal of the semiconductor and the thermal expansion coefficient of the wafer, thereby improving the reliability and usability of the semiconductor and increasing the thickness of the semiconductor.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising:

[0006] A wafer and a conductive structure, wherein an annular blind via is provided on the wafer, and a metal conductor is filled in the annular blind via to form the conductive structure, wherein the width of the annular blind via is related to the coefficient of thermal expansion of the metal conductor.

[0007] Preferably, the width of the annular blind via is determined with the goal of matching the thermal expansion coefficient of the wafer with that of the metal conductor.

[0008] Preferred options also include:

[0009] An insulating layer is located between the conductive structure and the annular wall of the annular blind hole.

[0010] Preferred options also include:

[0011] A barrier layer is located between the conductive structure and the insulating layer.

[0012] Preferably, the material of the barrier layer includes titanium or titanium nitride.

[0013] Preferably, the material of the conductive structure includes gold, silver, aluminum, tungsten, or copper.

[0014] Based on the same inventive concept, in a second aspect, the present invention also provides a method for manufacturing a semiconductor device, comprising:

[0015] Etch annular blind vias on the wafer;

[0016] A metal conductor is filled into the annular blind hole to form the conductive structure, wherein the width of the annular blind hole is determined according to the coefficient of thermal expansion of the metal conductor.

[0017] Preferably, the width of the annular blind via is determined based on the thermal expansion coefficient of the metal conductor, including: determining the width of the annular blind via based on the thermal expansion coefficient of the wafer and the thermal expansion coefficient of the metal conductor.

[0018] Preferably, before filling the annular blind hole with the metal conductor, the method further includes:

[0019] An insulating layer is formed on the annular wall of the annular blind hole.

[0020] Preferably, after forming an insulating layer on the annular wall of the annular blind hole, the method further includes:

[0021] A barrier layer is formed on the insulating layer.

[0022] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0023] The semiconductor device of this invention includes a wafer and a conductive structure. The conductive structure is formed by etching annular blind vias on the wafer and filling the annular blind vias with a metal conductor. The width of the annular blind vias is subject to specific requirements and is determined based on the thermal expansion coefficient of the metal conductor. By optimizing the width of the annular blind vias, the aim is to achieve the best match between the thermal expansion coefficients of the silicon wafer and the metal conductor. This involves finding a balance between the ease of metal filling in the Through Silicon Via (TSV) technology and the control of stress in the TSV structure. This significantly reduces the residual stress on the wafer after TSV, increases the wafer thickness, saves manufacturing costs, optimizes the TSV structure, and improves the performance of the wafer after TSV. Attached Figure Description

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0025] Figure 1 A top view of the semiconductor device in an embodiment of the present invention is shown;

[0026] Figure 2 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is shown;

[0027] Figure 3 A schematic flowchart of the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0029] Example 1

[0030] The first embodiment of the present invention provides a semiconductor device, such as... Figure 1 and Figure 2 As shown, it includes:

[0031] The wafer 101 and the conductive structure 102 are provided, wherein an annular blind via 103 is provided on the wafer 101, and a metal conductor is filled in the annular blind via 103 to form the conductive structure 102. The width of the annular blind via 103 is related to the thermal expansion coefficient of the metal conductor.

[0032] It should also be noted that the material of the conductive structure 102 includes, but is not limited to, gold, silver, aluminum, tungsten, or copper. The conductive structure 102 extends through the wafer 101. The material of the wafer 101 includes, but is not limited to, silicon or silicon carbide. The annular blind via can be a circular annular blind via or an irregular annular blind via; no limitation is made here. The width of the annular blind via refers to the distance between the walls of the annular blind via.

[0033] The width of the annular blind via 103 is determined based on the thermal expansion coefficient of the metal conductor. The determination process is as follows: by establishing a model, or software simulation, or by looking up the thermal expansion coefficients of the wafer and the metal conductor in a table, the width of the annular blind via is determined with the goal of optimally matching the thermal expansion coefficients of the wafer and the metal conductor.

[0034] The semiconductor device in this embodiment includes a wafer 101 and a conductive structure 102. The conductive structure 102 is formed by etching an annular blind via 103 on the wafer 101 and filling the annular blind via 103 with a metal conductor. The width of the annular blind via 103 is subject to specific requirements and is determined based on the thermal expansion coefficient of the metal conductor. By optimizing the width of the annular blind via 103 and the conductive structure 102 formed by filling the annular blind via 103 with a metal conductor, the optimal match between the thermal expansion coefficients of the silicon wafer and the metal conductor is achieved. This involves finding a balance between the ease of metal filling in the Through-Silicon Via (TSV) technology and the control of TSV structural stress, thereby significantly reducing the residual stress on the wafer after TSV. By reducing the residual stress on the wafer after silicon through-hole (STB) treatment, the thickness of the wafer after STB treatment can be increased, enabling wafer processing with a thickness of not less than 700µm. At the same time, it improves the reliability and usability of the wafer, saves manufacturing costs, optimizes the STB structure of the wafer, and improves the performance of the wafer after STB treatment.

[0035] The semiconductor device further includes an insulating layer 104, which is located between the conductive structure 102 and the annular wall of the annular blind via. The insulating layer 104 is made of, but is not limited to, silicon dioxide or silicon nitride.

[0036] The semiconductor device also includes a barrier layer 105, which is located between the conductive structure 102 and the insulating layer 104. The barrier layer 105 is made of materials including, but not limited to, titanium or titanium nitride. The functions of the barrier layer 105 are: firstly, to bond the metal conductor to the barrier layer 105 and the insulating layer 104, thereby constructing a stable conductive structure 102; and secondly, to prevent signal loss transmitted on the metal conductor, reducing signal transmission loss.

[0037] The specific fabrication method of the semiconductor device in this embodiment is as follows: A ring-shaped blind via 103 is etched on wafer 101 using deep reactive ion etching (DRIE). The width of the ring-shaped blind via 103 is determined based on the coefficient of thermal expansion of the metal conductor filling the ring-shaped blind via 103. Next, an insulating layer 104 is deposited on the ring wall of the ring-shaped blind via 103 using chemical vapor deposition (CVD). Then, a barrier layer 105 is formed on the insulating layer 104 using physical vapor deposition (PVD). Next, a metal conductor is filled into the ring-shaped blind via 103 using electroplating to form a conductive structure 102. Finally, both sides of wafer 101 are polished, planed, and thinned using chemical mechanical polishing (CMP) to expose the conductive structure 102 on both sides of wafer 101, forming a semiconductor device with an electroplated metal pillar in a blind via.

[0038] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0039] The semiconductor device in this embodiment includes a wafer and a conductive structure. The conductive structure is formed by etching annular blind vias on the wafer and filling the annular blind vias with a metal conductor. The width of the annular blind vias is subject to specific requirements and is determined based on the thermal expansion coefficient of the metal conductor. By optimizing the width of the annular blind vias, the aim is to achieve the best match between the thermal expansion coefficients of the silicon wafer and the metal conductor. This involves finding a balance between the ease of metal filling in the Through Silicon Via (TSV) technology and the control of stress in the TSV structure. This significantly reduces the residual stress on the wafer after TSV, increases the wafer thickness, saves manufacturing costs, optimizes the TSV structure, and improves the performance of the wafer after TSV.

[0040] Example 2

[0041] Based on the same inventive concept, the second embodiment of the present invention also provides a method for fabricating a semiconductor device, such as... Figure 3 As shown, it includes:

[0042] S201, etching annular blind vias on the wafer;

[0043] S202, a metal conductor is filled into the annular blind hole to form the conductive structure, wherein the width of the annular blind hole is determined according to the coefficient of thermal expansion of the metal conductor.

[0044] As an optional embodiment, the width of the annular blind via is determined based on the thermal expansion coefficient of the metal conductor, including: determining the width of the annular blind via based on the thermal expansion coefficient of the wafer and the thermal expansion coefficient of the metal conductor.

[0045] As an optional embodiment, before filling the annular blind hole with a metal conductor, the method further includes forming an insulating layer on the annular wall of the annular blind hole.

[0046] As an optional embodiment, after forming an insulating layer on the annular wall of the annular blind hole, the method further includes forming a barrier layer on the insulating layer.

[0047] Since the semiconductor device fabrication method described in this embodiment is the method used to implement the semiconductor device in Embodiment 1 of this application, those skilled in the art can understand the specific implementation method and various variations of the semiconductor device fabrication method in this embodiment based on the semiconductor device described in Embodiment 1 of this application. Therefore, how the semiconductor device fabrication method implements the method in Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the method used to implement the semiconductor device in Embodiment 1 of this application, it falls within the scope of protection of this application.

[0048] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0049] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A wafer and a conductive structure, wherein an annular blind via is provided on the wafer, and a metal conductor is filled in the annular blind via to form the conductive structure, the width of the annular blind via being related to the coefficient of thermal expansion of the metal conductor; an insulating layer is located between the conductive structure and the annular wall of the annular blind via; The goal is to match the thermal expansion coefficients of the wafer and the metal conductor, that is, to find a balance between the ease of the metal filling process in the through-silicon via (TSV) technology and the control of the stress of the TSV structure, and to determine the width of the annular blind via.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A barrier layer is located between the conductive structure and the insulating layer.

3. The semiconductor device as described in claim 2, characterized in that, The barrier layer is made of titanium or titanium nitride.

4. The semiconductor device as claimed in claim 1, characterized in that, The conductive structure is made of materials including gold, silver, aluminum, tungsten, or copper.

5. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to claims 1-4, characterized in that, include: Etch annular blind vias on the wafer; A metal conductor is filled into the annular blind hole to form a conductive structure, wherein the width of the annular blind hole is determined according to the coefficient of thermal expansion of the metal conductor; Before filling the annular blind hole with a metal conductor, the method further includes: An insulating layer is formed on the annular wall of the annular blind hole; The width of the annular blind hole is determined based on the coefficient of thermal expansion of the metallic conductor, including: The width of the annular blind via is determined by finding a balance between the ease of metal filling process in the through-silicon via (TSV) technology and the control of TSV structural stress, based on the thermal expansion coefficients of the wafer and the metal conductor.

6. The manufacturing method as described in claim 5, characterized in that, After forming an insulating layer on the annular wall of the annular blind hole, the method further includes: A barrier layer is formed on the insulating layer.

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