Display device

Abstract

A display device includes: a display panel including a front portion, a first side portion extending from a first side of the front portion, a second side portion extending from a second side of the front portion, and a corner portion between the first side portion and the second side portion. The display panel includes: a first display area at the front portion and including a plurality of first pixels; and a second display area at the corner portion and including a plurality of second pixels. The second display area includes a first encapsulation separator between adjacent second pixels among the plurality of second pixels.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With the development of the information-oriented society, the demand for display devices is constantly increasing. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays. Light-emitting displays include: organic light-emitting displays that include organic light-emitting elements; inorganic light-emitting displays that include inorganic light-emitting elements such as inorganic semiconductors; and micro light-emitting displays that include ultra-miniature light-emitting elements.

[0004] Because display devices are used in a variety of suitable electronic devices, they are required to have a variety of suitable designs. For example, when the display device is a light-emitting display device, the image can be displayed not only on the front but also on the sides that are bent at the four edges of the front. Such a display device may include corner portions disposed between a first side portion bent at a first side edge of the front and a second side portion bent at a second side edge of the front. Summary of the Invention

[0005] Aspects of some exemplary embodiments of this disclosure relate to a display device that can prevent or reduce the occurrence of pixels located at the corners of the display device being perceived as dark spots due to moisture penetration caused by particles.

[0006] However, aspects of the exemplary embodiments of this disclosure are not limited to those set forth herein. These and other aspects of the exemplary embodiments of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains from the following detailed description of the disclosure.

[0007] According to some example embodiments of this disclosure, a display device is provided, including: a display panel including a front portion, a first side portion extending from a first side of the front portion, a second side portion extending from a second side of the front portion, and a corner portion between the first side portion and the second side portion. The display panel includes: a first display area at the front portion and including a plurality of first pixels; and a second display area at the corner portion and including a plurality of second pixels. The second display area includes a first encapsulation separator between adjacent second pixels among the plurality of second pixels.

[0008] According to some example embodiments of this disclosure, a display device is provided, comprising: a display panel including a front portion, a first side portion extending from a first side of the front portion, a second side portion extending from a second side of the front portion, and a corner portion between the first side portion and the second side portion. The corner portion includes a plurality of cut patterns separated by cutting grooves. Each of the plurality of cut patterns includes a display area having a plurality of pixels for displaying an image. Each of the plurality of pixels includes a plurality of emission areas for emitting different lights. Each of the plurality of emission areas includes a plurality of sub-emission areas for emitting light of the same color.

[0009] According to the foregoing and other exemplary embodiments of this disclosure, because each pixel in the cutout pattern is surrounded by encapsulation separators and dams, they can be individually encapsulated. Therefore, even if one pixel in the cutout pattern appears as a dark spot due to moisture penetration caused by particles, the occurrence of other pixels in the cutout pattern being damaged and correspondingly appearing as dark spots can be prevented or reduced.

[0010] According to the foregoing and other exemplary embodiments of this disclosure, because each of the emission regions of the pixels in the cutout pattern is surrounded by encapsulation separators and dams, they can be individually encapsulated. Therefore, even if one of the emission regions of the pixels in the cutout pattern appears as a dark spot due to moisture penetration caused by particles, the occurrence of damage to other emission regions of the pixels in the cutout pattern and correspondingly appearing as dark spots can be prevented or reduced.

[0011] According to the foregoing and other exemplary embodiments of this disclosure, each of the emission regions of a pixel in the notch pattern includes a sub-emission region for emitting light of the same color, and each sub-emission region is surrounded and can be individually encapsulated. Therefore, even if some sub-emission regions of the notch pattern appear as dark spots due to moisture penetration caused by particles, the occurrence of damage to other sub-emission regions of the notch pattern and their corresponding dark spot appearance can be prevented or reduced. Thus, even if some sub-emission regions of a pixel appear as dark spots due to moisture penetration caused by particles, the image can still be displayed normally through the other sub-emission regions of the pixel. Attached Figure Description

[0012] The above and other exemplary embodiments and features of this disclosure will become more apparent from the description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a perspective view of a display device according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0015] Figure 3 This is an unfolded view showing a display device according to an exemplary embodiment of the present disclosure;

[0016] Figure 4 This is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 5 This is a layout diagram showing the first display area to the third display area and the non-display area of ​​a display panel according to an example embodiment of the present disclosure;

[0018] Figure 6 This is a layout diagram showing the first to third display areas and the non-display area of ​​a display panel according to another exemplary embodiment of the present disclosure;

[0019] Figure 7 It is shown Figure 5 A layout diagram of an example of the first display area;

[0020] Figure 8 It shows along Figure 7 A cross-sectional view of an example display panel taken by line II-II';

[0021] Figure 9 It is shown Figure 5 A layout diagram of an example of the third display area;

[0022] Figure 10 It shows along Figure 9 A cross-sectional view of an example display panel taken by line III-III';

[0023] Figure 11 It is shown Figure 5 A layout diagram of an example of the second display area;

[0024] Figure 12 It shows along Figure 11 A cross-sectional view of an example display panel taken by line IV-IV';

[0025] Figure 13 It shows along Figure 11 A cross-sectional view of an example display panel taken by line V-V';

[0026] Figure 14 It is shown Figure 5 Another example of the layout diagram for the second display area;

[0027] Figure 15 It shows along Figure 14 A cross-sectional view of an example display panel taken by line VI-VI';

[0028] Figure 16 It is shown Figure 5 Another example of the layout diagram for the second display area;

[0029] Figure 17 It shows along Figure 16 A cross-sectional view of an example display panel taken by line VII-VII';

[0030] Figure 18 It is shown Figure 5 Another example of the layout diagram for the second display area;

[0031] Figure 19 It shows along Figure 18 A cross-sectional view of an example display panel taken by line VIII-VIII';

[0032] Figure 20 It is shown Figure 5 Another example of the layout diagram for the second display area;

[0033] Figure 21 It shows along Figure 20 A cross-sectional view of an example display panel taken by line X-X';

[0034] Figure 22 It is shown Figure 5 Another example of the layout diagram for the second display area;

[0035] Figure 23 It shows along Figure 22 A cross-sectional view of an example display panel taken by line B-B';

[0036] Figure 24 It is shown Figure 5 Another example of the layout diagram for the second display area; and

[0037] Figure 25 It is shown Figure 5 Another example of the layout diagram for the second display area. Detailed Implementation

[0038] This disclosure will now be described more fully below with reference to the accompanying drawings, in which some embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various suitable forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0039] In this document, when describing embodiments of the present disclosure, the term “may” is used to mean “one or more embodiments of the present disclosure.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. As used herein, when following a list of elements, expressions such as “at least one of,” “one of,” and “selected from” modify the entire list of elements and do not modify individual elements of the list.

[0040] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," "coupled to," or "adjacent to" another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or one or more intermediary elements or intermediary layers may be present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there is no intermediary element or intermediary layer. As used herein, the terms "substantially," "approximately," and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases in measurements or calculations that will be recognized by those skilled in the art.

[0041] As used herein, phrases such as “plan view” can refer to a view from the top or from a direction orthogonal to the display area of ​​the display device.

[0042] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “bottom,” and “top” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element or feature described as “below” or “under” other elements or features will subsequently be oriented “above” or “on” other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0043] Any numerical range listed herein is intended to include all subranges with the same numerical precision contained within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and including) the listed minimum value of 1.0 and the listed maximum value of 10.0, that is, all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit listed herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification, including the claims, to expressly list any subranges contained within the ranges expressly listed herein.

[0044] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or in this disclosure, and shall not be interpreted in an idealized or overly formalized sense.

[0045] In the following, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0046] Figure 1 This is a perspective view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0047] Reference Figure 1 and Figure 2The display device 10 according to exemplary embodiments of this disclosure can be employed by portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In some embodiments, the display device 10 can be utilized (e.g., used) as a display unit of a television, laptop computer, monitor, electronic billboard, or Internet of Things (IoT) device. In some embodiments, the display device 10 can be applied to wearable devices such as smartwatches, watch phones, glasses-type displays (e.g., displays integrated into or with glasses), and head-mounted display (HMD) devices. In some embodiments, the display device 10 can be utilized (e.g., used) as a central information display (CID) disposed, for example, on a vehicle's dashboard, center instrument panel, or dashboard; as an interior mirror display representing a vehicle's rearview mirror; or as a display placed on the back of each of the front seats as an entertainment system for passengers in the rear seats of the vehicle.

[0048] As used herein, the first direction (X-axis direction) may be parallel (e.g., substantially parallel) to the shorter side of the display device 10, such as the horizontal direction of the display device 10 when viewed from above (e.g., in a plan view). The second direction (Y-axis direction) may be parallel (e.g., substantially parallel) to the longer side of the display device 10, such as the vertical direction of the display device 10 when viewed from above. The third direction (Z-axis direction) may refer to the thickness direction of the display device 10.

[0049] The display device 10 according to an example embodiment may include a display panel 300. For example... Figure 1 and Figure 2 As shown, the display panel 300 may include a front portion FS, a first side portion SS1, a second side portion SS2, a third side portion SS3, a fourth side portion SS4, a first corner portion CS1, a second corner portion CS2, a third corner portion CS3, and a fourth corner portion CS4.

[0050] The display panel 300 may include a suitably flexible substrate capable of being bent, folded, and / or rolled. For example, the substrate SUB may include (e.g., made of materials such as) polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylated or polyaryl ester (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. In some embodiments, the substrate SUB may include a metallic material (e.g., it may be a metallic material). Additionally, only a portion of the substrate SUB may be flexible, or the entire area of ​​the substrate SUB may be flexible.

[0051] When viewed from above, the front portion FS can have, but is not limited to, a rectangular shape having a shorter side in the first direction (X-axis direction) and a longer side in the second direction (Y-axis direction). When viewed from above, the front portion FS can also have other suitable shapes such as polygonal, circular, or elliptical shapes. Although in Figure 1 and Figure 2 In the example shown, the front portion FS is flat, but this disclosure is not limited thereto. For example, in some embodiments, the front portion FS may include a curved surface.

[0052] The first side portion SS1 may extend from the first side of the front portion FS (e.g., it may extend from the first side of the front portion FS). At the first side of the front portion FS (e.g., on the first side of the front portion FS), the first side portion SS1 may extend along the first bend line BL1 (see...). Figure 3 ) bend (for example, along the first bend line BL1 (see Figure 3 (The extended axis is bent or flexed), and therefore can have a first curvature. For example... Figure 1 and Figure 2 As shown, the first side of the front FS can be the left side of the front FS.

[0053] The second side portion SS2 can extend from the second side of the front portion FS (e.g., it can extend from the second side of the front portion FS). At the second side of the front portion FS (e.g., on the second side of the front portion FS), the second side portion SS2 can extend along the second bend line BL2 (see...). Figure 3 The bend can thus have a second curvature. The second curvature may differ from the first curvature, but this disclosure is not limited thereto. In some embodiments, the second curvature may be the same as the first curvature. Figure 1 and Figure 2 As shown, the second side of the front FS can be the lower side of the front FS.

[0054] The third side portion SS3 can extend from the third side of the front portion FS (e.g., it can extend from the third side of the front portion FS). At the third side of the front portion FS (e.g., on the third side of the front portion FS), the third side portion SS3 can be along the third bend line BL3 (see...). Figure 3 The curvature is bent, and therefore can have a third curvature. The third curvature can be equal to the second curvature, but this disclosure is not limited thereto. In some embodiments, the third curvature can be different from the second curvature. Figure 1 and Figure 2 As shown, the third side of the front FS can be the right side of the front FS.

[0055] The fourth side portion SS4 can extend from the fourth side of the front portion FS (e.g., it can extend from the fourth side of the front portion FS). At the fourth side of the front portion FS (e.g., on the fourth side of the front portion FS), the fourth side portion SS4 can extend along the fourth bend line BL4 (see...). Figure 3 The bend can therefore have a fourth curvature. The fourth curvature can be equal to the first curvature, but this disclosure is not limited thereto. In some embodiments, the fourth curvature can be different from the first curvature. Figure 1 and Figure 2 As shown, the fourth side of the front FS can be the upper side of the front FS.

[0056] A first corner portion CS1 can be positioned between a first side portion SS1 and a second side portion SS2. For example, the first corner portion CS1 can contact the lower side of the first side portion SS1 and the left side of the second side portion SS2 (e.g., direct contact or physical contact). The first corner portion CS1 can have a double curvature due to the first curvature of the first side portion SS1 and the second curvature of the second side portion SS2. Therefore, strain can be applied to the first corner portion CS1 by the bending force caused by the first curvature of the first side portion SS1 and by the bending force caused by the second curvature of the second side portion SS2.

[0057] The second corner portion CS2 can be positioned between the second side portion SS2 and the third side portion SS3. For example, the second corner portion CS2 can contact the right side of the second side portion SS2 and the lower side of the third side portion SS3 (e.g., direct contact or physical contact). Due to the second curvature of the second side portion SS2 and the third curvature of the third side portion SS3, the second corner portion CS2 can have a hyperbola. Therefore, strain can be applied to the second corner portion CS2 by the bending force caused by the second curvature of the second side portion SS2 and by the bending force caused by the third curvature of the third side portion SS3.

[0058] The third corner portion CS3 can be positioned between the third side portion SS3 and the fourth side portion SS4. For example, the third corner portion CS3 can contact the upper side of the third side portion SS3 and the right side of the fourth side portion SS4 (e.g., direct contact or physical contact). Due to the third curvature of the third side portion SS3 and the fourth curvature of the fourth side portion SS4, the third corner portion CS3 can have a double curvature. Therefore, strain can be applied to the third corner portion CS3 by the bending force caused by the third curvature of the third side portion SS3 and by the bending force caused by the fourth curvature of the fourth side portion SS4.

[0059] The fourth corner portion CS4 can be positioned between the first side portion SS1 and the fourth side portion SS4. For example, the fourth corner portion CS4 can contact the upper side of the first side portion SS1 and the left side of the fourth side portion SS4 (e.g., direct or physical contact). Due to the first curvature of the first side portion SS1 and the fourth curvature of the fourth side portion SS4, the fourth corner portion CS4 can have a double curvature. Therefore, strain can be applied to the fourth corner portion CS4 by the bending force caused by the first curvature of the first side portion SS1 and by the bending force caused by the fourth curvature of the fourth side portion SS4.

[0060] like Figure 5 As shown, each of the first corner portion CS1, the second corner portion CS2, the third corner portion CS3, and the fourth corner portion CS4 may include a cut pattern separated by a cutting groove in order to reduce strain due to hypercurvature. (See below for further details.) Figure 5 Describe the cut pattern.

[0061] Figure 3 This is an unfolded view showing a display device according to an example embodiment of the present disclosure.

[0062] Reference Figure 3 The display panel 300 may also include a bending area BA and a pad area PA. The display panel 300 may include a first display area DA1 to a third display area DA3, a non-display area NDA, a bending area BA, and a pad area PA.

[0063] The first display area DA1 to the third display area DA3 include pixels or emission areas to display images. The non-display area NDA does not include pixels or emission areas and does not display images. In the non-display area NDA, signal lines or driver circuits embedded in the panel for driving the pixels or emission areas can be set.

[0064] The first display area DA1 may be the main display area of ​​the display panel 300, and may include a front portion FS, a portion of a first side portion SS1, a portion of a second side portion SS2, a portion of a third side portion SS3, and a portion of a fourth side portion SS4. A portion of the first side portion SS1 extends from the first side of the front portion FS, and a portion of the second side portion SS2 extends from the second side of the front portion FS. A portion of the third side portion SS3 extends from the third side of the front portion FS, and a portion of the fourth side portion SS4 extends from the fourth side of the front portion FS. Each corner of the first display area DA1 may be rounded with a predetermined or set curvature.

[0065] Each of the second display areas DA2 can be a second auxiliary display area that assists the first display area DA1, such as the main display area. The resolution of each of the second display areas DA2 can be different from the resolution of the first display area DA1. For example, because each of the second display areas DA2 is used to assist the first display area DA1, the resolution of each of the second display areas DA2 can be lower than the resolution of the first display area DA1. For example, the number of emission areas per unit area in each of the second display areas DA2 can be less than the number of emission areas per unit area in the first display area DA1. However, it should be understood that this disclosure is not limited thereto. The resolution of each of the second display areas DA2 can be substantially equal to the resolution of the first display area DA1.

[0066] The second display area DA2 can be disposed on the outer side of the third display area DA3. Therefore, the third display area DA3 can be disposed between the first display area DA1 and the second display area DA2. At least a portion of each of the second display areas DA2 can be disposed at a corresponding location among the corners CS1 to CS4. In addition, at least a portion of each of the second display areas DA2 can be disposed at two of the first side portions SS1 to the fourth side portions SS4.

[0067] For example, at least a portion of the second display area DA2 located on the outer side of the corner where the lower and left sides of the first display area DA1 intersect can be located at the first corner CS1, the first side SS1, and the second side SS2. At least a portion of the second display area DA2 located on the outer side of the corner where the lower and right sides of the first display area DA1 intersect can be located at the second corner CS2, the second side SS2, and the third side SS3. At least a portion of the second display area DA2 located on the outer side of the corner where the upper and right sides of the first display area DA1 intersect can be located at the third corner CS3, the third side SS3, and the fourth side SS4. At least a portion of the second display area DA2 located on the outer side of the corner where the upper and left sides of the first display area DA1 intersect can be located at the fourth corner CS4, the first side SS1, and the fourth side SS4.

[0068] Each of the third display areas DA3 can be a second auxiliary display area that assists the first display area DA1, such as the main display area. The resolution of each of the third display areas DA3 can be different from the resolution of the first display area DA1. For example, because each of the third display areas DA3 is used to assist the first display area DA1, the resolution of each of the third display areas DA3 can be lower than the resolution of the first display area DA1. For example, the number of emission areas per unit area in each of the third display areas DA3 can be less than the number of emission areas per unit area in the first display area DA1. However, it should be understood that this disclosure is not limited thereto. The resolution of each of the third display areas DA3 can be substantially equal to the resolution of the first display area DA1.

[0069] Each of the third display areas DA3 can be disposed on the outer side of a corresponding corner of the first display area DA1. At least a portion of each of the third display areas DA3 can be disposed at a corresponding corner CS1 to CS4. In addition, at least a portion of each of the third display areas DA3 can be disposed on the front FS. Furthermore, at least a portion of each of the third display areas DA3 can be disposed at two of the first side SS1 to the fourth side SS4.

[0070] For example, at least a portion of the third display area DA3 located on the outer side of the corner where the lower and left sides of the first display area DA1 intersect can be located at the front FS, the first corner CS1, the first side SS1, and the second side SS2. At least a portion of the third display area DA3 located on the outer side of the corner where the lower and right sides of the first display area DA1 intersect can be located at the front FS, the second corner CS2, the second side SS2, and the third side SS3. At least a portion of the third display area DA3 located on the outer side of the corner where the upper and right sides of the first display area DA1 intersect can be located at the front FS, the third corner CS3, the third side SS3, and the fourth side SS4. At least a portion of the third display area DA3 located on the outer side of the corner where the upper and left sides of the first display area DA1 intersect can be located at the front FS, the fourth corner CS4, the first side SS1, and the fourth side SS4.

[0071] The non-display area NDA may include a portion of the first side SS1, a portion of the second side SS2, a portion of the third side SS3, a portion of the fourth side SS4, a portion of the first corner CS1, a portion of the second corner CS2, a portion of the third corner CS3, and a portion of the fourth corner CS4. The non-display area NDA may be located on the outer side of the first display area DA1 at the sides SS1, SS2, SS3, and SS4. For example, the non-display area NDA may be located at the left edge of the first side SS1, the lower edge of the second side SS2, the right edge of the third side SS3, and the upper edge of the fourth side SS4.

[0072] The non-display area NDA can be located on the outer side of the second display area DA2 at corners CS1, CS2, CS3, and CS4. For example, the non-display area NDA can be located at the edge of the corner where the lower and left sides of the first corner CS1 intersect, at the edge of the corner where the lower and right sides of the second corner CS2 intersect, at the edge of the corner where the upper and right sides of the third corner CS3 intersect, and at the edge of the corner where the upper and left sides of the fourth corner CS4 intersect.

[0073] The bending region BA can extend from the underside of the second side SS2 (e.g., it can extend from the underside of the second side SS2). The bending region BA can be located between the second side SS2 and the pad region PA. The length of the bending region BA in the first direction (X-axis direction) can be less than the length of the second side SS2 in the first direction (X-axis direction). The bending region BA can be bent along the fifth bending line BL5 on the underside of the second side SS2.

[0074] The pad region PA can extend from the underside of the bent region BA (e.g., it can extend from the underside of the bent region BA). The length of the pad region PA in the first direction (X-axis direction) can be greater than the length of the bent region BA in the first direction (X-axis direction). However, it should be understood that this disclosure is not limited thereto. The length of the pad region PA in the first direction (X-axis direction) can be substantially equal to the length of the bent region BA in the first direction (X-axis direction). The pad region PA can be bent along the sixth bend line BL6 on the underside of the bent region BA. The pad region PA can be located on the underside of the front FS.

[0075] An integrated driver circuit IDC and pads PAD can be disposed in the pad area PA. The integrated driver circuit IDC can be implemented as an integrated circuit (IC). The integrated driver circuit IDC can be coupled (e.g., attached) in the pad area PA using glass flip-chip (COG) technology, plastic flip-chip (COP) technology, or ultrasonic bonding. In some embodiments, the integrated driver circuit IDC can be disposed on a circuit board, which is disposed on the pads PAD of the pad area PA.

[0076] The integrated driver circuit IDC can be electrically coupled (e.g., electrically connected) to the pads PAD of the pad area PA. The integrated driver circuit IDC can receive digital video data and timing signals through the pads PAD of the pad area PA. The integrated driver circuit IDC can convert the digital video data into analog data voltage and output the analog data voltage to the data lines of display areas DA1, DA2, and DA3.

[0077] The circuit board can be coupled (e.g., attached) to the pads PAD of the pad region PA using an anisotropic conductive film. For this reason, the pads PAD of the pad region PA can be electrically coupled (e.g., electrically connected) to the circuit board.

[0078] like Figure 3 As shown, display areas DA1, DA2, and DA3 can be located at the front FS, the first side SS1, the second side SS2, the third side SS3, the fourth side SS4, the first corner CS1, the second corner CS2, the third corner CS3, and the fourth corner CS4. Therefore, the image can be displayed not only on the front (e.g., front side) FS, the first side SS1, the second side SS2, the third side SS3, and the fourth side SS4, but also on the first corner CS1, the second corner CS2, the third corner CS3, and the fourth corner CS4.

[0079] Figure 4 This is a cross-sectional view showing a display device according to an example embodiment of the present disclosure. Figure 4 It shows along Figure 2An example of a display device 10 cut off by line I-I'.

[0080] Reference Figure 4 The display panel 300 may include a substrate SUB, a display layer DISL, a sensor electrode layer SENL, a polarizing film PF, and / or a cover window CW.

[0081] The display layer DISL can be set on the base SUB. The display layer DISL can include display areas DA1, DA2, and DA3 (see...). Figure 3 ) and the non-display area NDA (see Figure 3 In addition to the emission area, scan lines, data lines, power lines, etc., used to drive the light-emitting elements can also be set in the display areas DA1, DA2, and DA3 of the display layer DISL (see...). Figure 3 In the non-display area NDA of the display layer DISL, scan driver circuits for outputting scan signals to scan lines, fan-out lines for coupling (e.g., connecting) data lines to the integrated driver circuit IDC, etc., can be provided.

[0082] like Figure 8 As shown, the display layer DISL may include a thin-film transistor layer TFTL in which thin-film transistors are formed, an emissive material layer EML in which light-emitting elements for emitting light are disposed in the emitting region, and an encapsulation layer TFEL for encapsulating the emissive material layer EML. In some embodiments, the encapsulation layer TFEL may be a thin-film encapsulation layer.

[0083] A sensor electrode layer (SENL) can be disposed on a display layer (DISL). The sensor electrode layer (SENL) may include sensor electrodes. The sensor electrode layer (SENL) can utilize (e.g., by using) sensor electrodes to sense the presence of a person and / or object touch.

[0084] A polarizing film PF can be disposed on the sensor electrode layer SENL. The polarizing film PF may include a first substrate member, a linear polarizer, a delay film including a λ / 4 (quarter-wave) plate and / or a λ / 2 (half-wave) plate, and a second substrate member. For example, the first substrate member, the linear polarizer, the λ / 4 plate, the λ / 2 plate, and the second substrate member may be sequentially stacked on the sensor electrode layer SENL.

[0085] The cover window (CW) can be disposed on the polarizing film (PF). The cover window (CW) can be coupled (e.g., attached) to the polarizing film (PF) by a transparent adhesive member such as an optically transparent adhesive (OCA) film and / or an optically transparent resin (OCR). The cover window (CW) can comprise inorganic materials such as glass or organic materials such as plastics and / or polymers (e.g., it can be an inorganic material such as glass or an organic material such as plastics and / or polymers).

[0086] The bending area BA can be bent along the fifth bending line BL5 and can be disposed on the lower surface of the second side SS2. The pad area PA can be bent along the sixth bending line BL6 and can be disposed on the lower surface of the front FS. The pad area PA can be coupled (e.g., attached) to the lower surface of the front FS by an adhesive member ADH. The adhesive member ADH can be a pressure-sensitive adhesive.

[0087] Figure 5 This is a layout diagram showing the first to third display areas and non-display areas of a display panel according to an example embodiment of the present disclosure. Figure 5 yes Figure 3 A magnified view of region A. Figure 5 The setting is shown Figure 3 The display areas DA1, DA2, and DA3 around the first corner CS1, and the non-display area NDA.

[0088] Reference Figure 5 The intersection point CRP of the first bend line BL1 and the second bend line BL2 can be located in the first display area DA1. In this case, the first display area DA1 can be set on the front FS, the first side SS1, the second side SS2, and the first corner CS1. The third display area DA3 can be set on the first side SS1, the second side SS2, and the first corner CS1. The second display area DA2 can be set on the first side SS1, the second side SS2, and the first corner CS1. The non-display area NDA can be set on the first side SS1, the second side SS2, and the first corner CS1.

[0089] The location of the intersection point CRP of the first bend line BL1 and the second bend line BL2 is not limited to... Figure 5 The location shown in the image can be positioned in the second display area DA2 or as shown in the image. Figure 3 The location shown is in the third display area DA3.

[0090] The first display area DA1 may include a first pixel PX1 for displaying an image (see...). Figure 7 Additionally, the first display area DA1 may include sensor electrodes SE for sensing the user's touch (see...). Figure 7 The sensor electrode SE may include a driving electrode TE and a sensing electrode RE (see...). Figure 7 (Refer to) Figure 7 and Figure 8 A more detailed description of the first pixel PX1, driving electrode TE, and sensing electrode RE of the first display area DA1 (see...) Figure 7 ).

[0091] The third display area DA3 can be located outside the first display area DA1. The third display area DA3 may include a third pixel PX3 and a touch drive line TL (see...). Figure 9 Touch drive line TL (see) Figure 9 It can be coupled (e.g., connected) to the drive electrode TE (see...) Figure 7 The third display area DA3 can include not only the touch drive line TL (see...) Figure 9 Furthermore, it may include coupling (e.g., connection) to the sensing electrode RE (see...). Figure 7 ) touch sensing line.

[0092] If a non-display area where no image is displayed is located between the first display area DA1 and the second display area DA2, the user can identify the non-display area between the first display area DA1 and the second display area DA2. For example, the user can identify the gap between the image displayed by the first display area DA1 and the image displayed by the second display area DA2. Conversely, when the third pixel PX3 (see...) is included... Figure 9 When the third display area DA3 is formed between the first display area DA1 and the second display area DA2 (e.g., immediately between the first display area DA1 and the second display area DA2), it can prevent or reduce the following situation: the gap between the image displayed by the first display area DA1 and the image displayed by the second display area DA2 is seen (e.g., recognized) by the user.

[0093] The second display area DA2 can be located outside the third display area DA3. The non-display area NDA can be located outside the second display area DA2. The second display area DA2 may include a cut pattern CP and a cut connection pattern CBP spaced apart from each other by a cutting groove CG. The second display area DA2 may include a second pixel PX2 (see...) located in the cut pattern CP. Figure 11 ).

[0094] The cut pattern CP and the cut connection pattern CBP can be obtained by laser cutting the display panel 300 (see...). Figure 3 Therefore, the cutting groove CG can exist between adjacent cutting patterns CP and between adjacent cutting connection patterns CBP.

[0095] One end of each of the cutout patterns CP can be coupled (e.g., connected) to a third display area DA3, and the other end of each of the cutout patterns CP (e.g., the end opposite to said one end) can be coupled (e.g., connected) to a cutout connection pattern CBP. When viewed from above, each of the cutout patterns CP can be formed in a shape resembling a trapezoid. In this case, the width of the cutout pattern CP can become narrower from the third display area DA3 toward the cutout connection pattern CBP. However, this disclosure is not limited thereto. In some embodiments, the cutout pattern CP can be formed in a rectangular shape. In this case, the width of the cutout pattern CP coupled (e.g., connected) to the third display area DA3 can be substantially equal to the width of the cutout pattern CP coupled (e.g., connected) to the cutout connection pattern CBP.

[0096] Furthermore, the length of the cut pattern CP at the center of the second display area DA2 can be greater than the length of the cut pattern CP at the edge. Therefore, adjacent cut patterns CP in the second display area DA2 can have different sizes. For example, in some embodiments, the size of the cut pattern CP at the center of the second display area DA2 (e.g., planar area in a plan view) can be greater than the size of the cut pattern CP at the edge of the second display area DA2 (e.g., planar area in a plan view). However, this disclosure is not limited thereto. For example, in some embodiments, the size of the cut pattern CP at the center of the second display area DA2 can be smaller than the size of the cut pattern CP at the edge.

[0097] A cut-and-connect pattern (CBP) can be positioned between each cut-and-connect pattern (CP) and the non-display area (NDA). One end of each of the cut-and-connect patterns (CBP) can be coupled (e.g., connected) to the respective cut-and-connect pattern (CP), and the other end of each of the cut-and-connect patterns (CBP) can be coupled (e.g., connected) to the non-display area (NDA).

[0098] The cut-and-connect pattern CBP can be formed into a serpentine shape including multiple bends. For example, the cut-and-connect pattern CBP can be designed to allow the cut-and-connect pattern CP of the second display area DA2 to easily expand and / or contract. Therefore, the strain and stress applied to the second display area DA2 due to hypercurvature can be reduced.

[0099] Settings Figure 3 The display areas DA1, DA2, and DA3 at the second corner CS2, the third corner CS3, and the fourth corner CS4, as well as the non-display area NDA, shown in the figure, can be similar to those referenced above. Figure 5The description describes the display areas DA1, DA2, and DA3 and the non-display area NDA located at the first corner CS1 (e.g., they may have a structure and / or configuration similar to those of the display areas DA1, DA2, and DA3 and the non-display area NDA located at the first corner CS1). Therefore, the second corner CS2, the third corner CS3, and the fourth corner CS4 may not be described.

[0100] Figure 6 This is a layout diagram showing the first display area to the third display area and the non-display area of ​​a display panel according to another example embodiment of the present disclosure.

[0101] In addition to the elimination of the cut-and-connect pattern CBP and the coupling (e.g., connection) of the cut-and-connect pattern CP to the non-display area NDA, Figure 6 The example embodiments shown are similar to Figure 5 The example embodiments are essentially the same. Therefore, redundant descriptions of them are not necessary.

[0102] Figure 7 It is shown Figure 5 A layout diagram of an example of the first display area.

[0103] Figure 7 The first pixel PX1 of the first display area DA1 and the sensor electrode layer SENL are shown (see Figure 4 The driving electrode TE and the sensing electrode RE. Figure 7 In the example shown, the user's touch is sensed by mutual capacitance sensing using two sensor electrodes, such as a drive electrode TE and a sensing electrode RE. For ease of illustration, Figure 7 Only two sensing electrodes RE that are adjacent to each other in the first direction (X-axis direction) and two driving electrodes TE that are adjacent to each other in the second direction (Y-axis direction) are shown.

[0104] Reference Figure 7 The driving electrode TE can be electrically separated from the sensing electrode RE. The driving electrode TE and the sensing electrode RE are formed on the same layer, and therefore the driving electrode TE and the sensing electrode RE can be spaced apart from each other. A gap may exist between the driving electrode TE and the sensing electrode RE.

[0105] The sensing electrodes RE can be electrically coupled (e.g., electrically connected) to each other in a first direction (X-axis direction). The driving electrodes TE can be electrically coupled (e.g., electrically connected) to each other in a second direction (Y-axis direction). In order to electrically decouple the sensing electrodes RE and the driving electrodes TE at their intersection or intersection, the driving electrodes TE adjacent to each other in the second direction (Y-axis direction) can be coupled (e.g., connected) by connecting electrodes BE1 (e.g., multiple connecting electrodes BE1).

[0106] The connecting electrode BE1 can be formed on a different layer than the driving electrode TE and the sensing electrode RE, and the connecting electrode BE1 can be coupled (e.g., connected) to the driving electrode TE through the first touch contact hole TCNT1. One end of each of the connecting electrodes BE1 can be coupled (e.g., connected) to one of the driving electrodes TE that are adjacent to each other in the second direction (Y-axis direction) through the first touch contact hole TCNT1. The other end of each of the connecting electrodes BE1 can be coupled (e.g., connected) to the other of the driving electrodes TE that are adjacent to each other in the second direction (Y-axis direction) through the first touch contact hole TCNT1. The connecting electrode BE1 can overlap with the sensing electrode RE in the third third direction (Z-axis direction) (e.g., in a plan view). Because the connecting electrode BE1 is formed on a different layer than the driving electrode TE and the sensing electrode RE, the connecting electrode BE1 can be electrically decoupled from the sensing electrode RE even if the connecting electrode BE1 overlaps with the sensing electrode RE in the third third direction (Z-axis direction).

[0107] Each of the connecting electrodes BE1 can be bent at least once. Although in Figure 7 In the example shown, the connecting electrode BE1 is bent into the shape of angle brackets "<" or ">", but the shape of the connecting electrode BE1 is not limited to this. In some embodiments, because the drive electrodes TE that are adjacent to each other in the second direction (Y-axis direction) are coupled (e.g., connected) through a plurality of connecting electrodes BE1, the drive electrodes TE that are adjacent to each other in the second direction (Y-axis direction) can still be electrically coupled (e.g., electrically connected) to each other even if any one of the connecting electrodes BE1 is uncoupled (e.g., disconnected).

[0108] When viewed from above (e.g., in a plan view), each of the driving electrode TE and the sensing electrode RE can have a mesh structure. This is because the driving electrode TE and the sensing electrode RE are formed within the encapsulation layer TFEL (see...). Figure 8 Therefore, from the common electrode 173 (see...) Figure 8 The distance to the driving electrode TE and / or sensing electrode RE is small. Therefore, at the common electrode 173 (see...) Figure 8 Parasitic capacitances can form between the common electrode 173 and the driving electrode TE and / or the sensing electrode RE. The parasitic capacitances between the common electrode 173 and the driving electrode TE or the sensing electrode RE are respectively related to the common electrode 173 (see...). Figure 8 The area of ​​the driving electrode TE or sensing electrode RE overlapping each other is proportional to the area of ​​the driving electrode TE or sensing electrode RE. To reduce this parasitic capacitance, the driving electrode TE and sensing electrode RE can have a grid structure when viewed from above (e.g., in a planar view).

[0109] The first display area DA1 may include a first pixel PX1 for displaying an image. Each of the first pixels PX1 may include multiple emission areas EA1, EA2, EA3, and EA4. For example, each of the first pixels PX1 may include a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4. The first emission area EA1 refers to the emission area of ​​a first sub-pixel for emitting a first light, and the second emission area EA2 refers to the emission area of ​​a second sub-pixel for emitting a second light. The third emission area EA3 refers to the emission area of ​​a third sub-pixel for emitting a third light, and the fourth emission area EA4 refers to the emission area of ​​a fourth sub-pixel for emitting a fourth light.

[0110] The first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 can emit light of different colors. In some embodiments, two of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 can emit light of the same color. For example, the first emission region EA1 can emit red light, the second emission region EA2 and the fourth emission region EA4 can emit green light, and the third emission region EA3 can emit blue light.

[0111] When viewed from above (e.g., in a plan view), each of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 may have, but is not limited to, a quadrilateral shape such as a rhombus. For example, when viewed from above (e.g., in a plan view), the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 may have other suitable polygonal shapes, circular shapes, or elliptical shapes besides quadrilateral shapes. Figure 7 In the example shown, the third transmission region EA3 has the largest area, the first transmission region EA1 has the second largest area, and the second transmission region EA2 and the fourth transmission region EA4 have the smallest areas. However, it should be understood that this disclosure is not limited thereto.

[0112] Because the driving electrode TE, sensing electrode RE, and connecting electrode BE1 form a grid structure when viewed from above (e.g., in a plan view), the emitting regions EA1, EA2, EA3, and EA4 do not overlap with the driving electrode TE, sensing electrode RE, and connecting electrode BE1 in the third direction (Z-axis direction) (e.g., in a plan view). Therefore, the light emitted from the emitting regions EA1, EA2, EA3, and EA4 is not blocked by the driving electrode TE, sensing electrode RE, and connecting electrode BE1, or is blocked less by them, and thus, the reduction in light illuminance due to the electrodes can be avoided or reduced.

[0113] Figure 8 It shows along Figure 7 A cross-sectional view of an example display panel taken by line II-II'.

[0114] Reference Figure 8 The display layer DISL, including the thin film transistor layer TFTL, the emitter material layer EML, and the encapsulation layer TFEL, can be disposed on the substrate SUB, and the sensor electrode layer SENL, including the driving electrode TE, the sensing electrode RE, and the connection electrode BE1, can be disposed on the display layer DISL.

[0115] The substrate SUB can be made of an insulating material such as a polymer resin and / or glass. For example, the substrate SUB may include polyimide (e.g., it may be polyimide). In this case, the substrate SUB can be a suitably flexible substrate that can be bent, folded, and / or rolled up.

[0116] A thin-film transistor layer (TFTL), including a first thin-film transistor (ST1), can be disposed on a substrate (SUB). The TFTL may include the first thin-film transistor (ST1), a first connection electrode (ANDE1), a first buffer layer (BF1), a gate insulating layer (130), a first interlayer dielectric layer (141), a second interlayer dielectric layer (142), a first planarization layer (150), a second planarization layer (160), and a first inorganic layer (161).

[0117] The first buffer layer BF1 can be disposed on the substrate SUB. The first buffer layer BF1 can be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0118] The first thin-film transistor ST1 may be disposed on the first buffer layer BF1. The first thin-film transistor ST1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0119] The first active layer ACT1 of the first thin-film transistor ST1 may be disposed on the first buffer layer BF1. The first active layer ACT1 may comprise a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, and / or amorphous silicon (e.g., it may be a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, and / or amorphous silicon). The portion of the first active layer ACT1 that overlaps with the first gate electrode G1 in the third direction (Z-axis direction) (e.g., in a plan view) may define a channel region. The other portions of the first active layer ACT1 that do not overlap with the first gate electrode G1 in the third direction (Z-axis direction) may define a conductive region. The conductive region of the first active layer ACT1 may be made conductive by doping the silicon semiconductor with ions and / or impurities.

[0120] The gate insulating layer 130 may be formed on the first active layer ACT1 of the first thin film transistor ST1. The gate insulating layer 130 may be formed of inorganic layers such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and / or aluminum oxide.

[0121] The first gate electrode G1 and the first capacitor electrode CAE1 of the first thin-film transistor ST1 can be disposed on the gate insulating layer 130. The first gate electrode G1 of the first thin-film transistor ST1 can overlap with the first active layer ACT1 in the third direction (Z-axis direction) (e.g., in a planar view). The first capacitor electrode CAE1 can overlap with the second capacitor electrode CAE2 in the third direction (Z-axis direction) (e.g., in a planar view). The first gate electrode G1 and the first capacitor electrode CAE1 can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0122] The first interlayer dielectric layer 141 may be disposed on the first gate electrode G1 and the first capacitor electrode CAE1. The first interlayer dielectric layer 141 may be formed of inorganic layers such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide. The first interlayer dielectric layer 141 may include multiple inorganic layers.

[0123] The second capacitor electrode CAE2 can be disposed on the first interlayer dielectric layer 141. The second capacitor electrode CAE2 can overlap with the first capacitor electrode CAE1 in a third direction (Z-axis direction) (e.g., in a plan view). Because the first interlayer dielectric layer 141 has a predetermined or set dielectric constant, the capacitor can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the first interlayer dielectric layer 141. The second capacitor electrode CAE2 can be composed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0124] The second interlayer dielectric layer 142 can be disposed above the second capacitor electrode CAE2. The second interlayer dielectric layer 142 can be formed of inorganic layers such as silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and / or aluminum oxide layer.

[0125] The first source electrode S1 and the first drain electrode D1 of the first thin-film transistor ST1 can be disposed on the second interlayer dielectric layer 142. The first source electrode S1 and the first drain electrode D1 can be composed of a single layer of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or a multilayer of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0126] The first source electrode S1 of the first thin-film transistor ST1 can be coupled (e.g., connected) to a conductive region located on the first side of the channel region of the first active layer ACT1 through contact holes penetrating the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The first drain electrode D1 of the first thin-film transistor ST1 can be coupled (e.g., connected) to a conductive region located on the opposite side of the channel region of the first active layer ACT1, opposite to the first side of the channel region, through contact holes penetrating the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142.

[0127] A first planarization layer 150 may be disposed on the first source electrode S1 and the first drain electrode D1 to provide a flat surface over thin-film transistors with different levels. The first planarization layer 150 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0128] The first connection electrode ANDE1 can be disposed on the first planarization layer 150. The first connection electrode ANDE1 can be coupled (e.g., connected) to the first source electrode S1 or the first drain electrode D1 of the first thin-film transistor ST1 through a contact hole penetrating the first planarization layer 150. The first connection electrode ANDE1 can consist of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0129] The second planarization layer 160 may be disposed on the first connecting electrode ANDE1. The second planarization layer 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0130] The first inorganic layer 161 may be disposed on the second planarization layer 160. The first inorganic layer 161 may be composed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0131] An emissive material layer (EML) is disposed on a thin-film transistor layer (TFTL). The emissive material layer (EML) may include a light-emitting element and a 180° diaphragm.

[0132] Each of the light-emitting elements may include a pixel electrode 171, an emitting layer 172, and a common electrode 173. In each of the emitting regions EA1, EA2, EA3, and EA4, the pixel electrode 171, the emitting layer 172, and the common electrode 173 are sequentially stacked on top of each other, such that holes from the pixel electrode 171 and electrons from the common electrode 173 combine with each other in the emitting layer 172 to emit light. In this case, the pixel electrode 171 may be an anode electrode, and the common electrode 173 may be a cathode electrode. Although in Figure 8 The diagram shows the third launch area EA3, but the first launch area EA1, the second launch area EA2, and the fourth launch area EA4 can be connected to it. Figure 8 The third emission region EA3 shown in the figure is essentially the same (e.g., it may have the same characteristics as the third emission region EA3 shown in the figure). Figure 8 The third launch area EA3 shown in the figure has essentially the same structure and / or configuration.

[0133] Pixel electrode 171 may be formed on the first inorganic layer 161. Pixel electrode 171 may be coupled (e.g., connected) to the first connection electrode ANDE1 through contact holes penetrating the first inorganic layer 161 and the second planarization layer 160.

[0134] In the top emitting structure in which light is emitted from the emitting layer 172 toward the common electrode 173, the pixel electrode 171 may be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), and / or aluminum (Al), or may be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and / or a stacked structure of APC alloy and ITO (ITO / APC / ITO) to improve reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0135] A dam 180 is used to define each of the emission regions EA1, EA2, EA3, and EA4 of the display pixel. For this purpose, the dam 180 can be formed on the first inorganic layer 161 to expose a portion of the pixel electrode 171. The dam 180 can cover the edge of the pixel electrode 171. The pixel electrode 171 can be disposed in contact holes penetrating the first inorganic layer 161 and the second planarization layer 160. Therefore, the contact holes penetrating the first inorganic layer 161 and the second planarization layer 160 can be filled by the pixel electrode 171. The dam 180 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0136] An emission layer 172 is formed on the pixel electrode 171. The emission layer 172 may include an organic material (e.g., it may be an organic material) and may emit light of a certain color. For example, the emission layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant (e.g., it may be a host and a dopant). The organic material layer may include (e.g., it may be) a material for emitting predetermined or set light (e.g., light having a predetermined or set color or wavelength), and may be formed using (e.g., using) phosphors and / or fluorescent materials.

[0137] A common electrode 173 is formed on the emitter layer 172. The common electrode 173 may be formed to cover the emitter layer 172. The common electrode 173 may be a common layer formed across display pixels. A cover layer may be formed on the common electrode 173.

[0138] In the top-emitting structure, the common electrode 173 can be formed of a transparent conductive material (TCP) such as ITO and / or IZO that transmits light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 is formed of a semi-transmissive metallic material, the light extraction efficiency can be improved by utilizing (e.g., using) a microcavity.

[0139] The encapsulation layer TFEL can be formed on the emissive material layer EML. The encapsulation layer TFEL may include at least one inorganic layer to prevent or block oxygen and / or moisture from penetrating into the emissive material layer EML. In addition, the encapsulation layer TFEL may include at least one organic layer to protect the emissive material layer EML from the effects of particles.

[0140] For example, the encapsulation layer TFEL may include a first inorganic encapsulation layer 191 disposed on the common electrode 173, an organic encapsulation layer 192 disposed on the first inorganic encapsulation layer 191, and a second inorganic encapsulation layer 193 disposed on the organic encapsulation layer 192. The first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 may each be a multilayer composition in which one or more inorganic layers of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked. The organic encapsulation layer may be an acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0141] The sensor electrode layer SENL is disposed on the encapsulation layer TFEL. The sensor electrode layer SENL may include a driving electrode TE, a sensing electrode RE, and a connection electrode BE1.

[0142] The second buffer layer BF2 may be disposed on the encapsulation layer TFEL. The second buffer layer BF2 may include at least one inorganic layer. For example, the second buffer layer BF2 may consist of a multilayer in which one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately.

[0143] The connecting electrode BE1 can be disposed on the second buffer layer BF2. The connecting electrode BE1 can be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) and / or aluminum (Al), or it can be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and / or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0144] The first sensor insulating layer TINS1 can be disposed on the connecting electrode BE1. The first sensor insulating layer TINS1 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0145] The driving electrode TE and the sensing electrode RE can be disposed on the first sensor insulating layer TINS1. To prevent or reduce the reduction of light intensity caused by the driving electrode TE and / or the sensing electrode RE blocking light emitted from the emission regions EA1, EA2, EA3, and EA4, the driving electrode TE and the sensing electrode RE do not overlap with the emission regions EA1, EA2, EA3, and EA4. The driving electrode TE and the sensing electrode RE can consist of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or can consist of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0146] The second sensor insulating layer TINS2 can be disposed on the driving electrode TE and the sensing electrode RE. The second sensor insulating layer TINS2 may include an inorganic layer and / or an organic layer. The inorganic layer may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0147] Figure 9 It is shown Figure 5 A layout diagram of an example of the third display area. Figure 9 yes Figure 5 A magnified view of region B.

[0148] Reference Figure 9 The touch drive line TL can be extended along the A-direction DRA (e.g., it can be extended along the A-direction DRA). The A-direction DRA can be tilted 135 degrees relative to the first direction (X-axis direction) and 45 degrees relative to the second direction (Y-axis direction). The touch drive line TL can be arranged along the B-direction DRB, which intersects the A-direction DRA. The B-direction DRB can be tilted 45 degrees relative to the first direction (X-axis direction) and 45 degrees relative to the second direction (Y-axis direction).

[0149] The third pixel PX3 can be disposed between adjacent touch driving lines TL. The third pixel PX3 disposed between adjacent touch driving lines TL can be arranged on the DRA in direction A. At least one touch driving line TL can be disposed between adjacent second emission regions EA2" on the DRB in direction B. The spacing between touch driving lines TL on the DRB in direction B and the spacing between third pixels PX3 on the DRB in direction B can be approximately tens of μm. As used herein, the term μm can mean equal to 10. -6 A distance of meters.

[0150] Each of the third pixels PX3 may include multiple emission regions EA1", EA2", and EA3". The number of emission regions EA1", EA2", and EA3" in each of the third pixels PX3 may differ from the number of emission regions EA1, EA2, EA3, and EA4 in each of the first pixels PX1.

[0151] For example, each of the third pixels PX3 may include a first emission region EA1", a second emission region EA2", and a third emission region EA3". The first emission region EA1" refers to the emission region of the first sub-pixel used to emit the first light, the second emission region EA2" refers to the emission region of the second sub-pixel used to emit the second light, and the third emission region EA3" refers to the emission region of the third sub-pixel used to emit the third light.

[0152] The first emission region EA1", the second emission region EA2", and the third emission region EA3" can emit light of different colors. For example, the first emission region EA1" can emit red light, the second emission region EA2" can emit green light, and the third emission region EA3" can emit blue light.

[0153] The first transmission region EA1", the second transmission region EA2", and the third transmission region EA3" can be arranged in the first direction (X-axis direction). In some embodiments, the first transmission region EA1", the second transmission region EA2", and the third transmission region EA3" can be arranged in the B direction DRB.

[0154] When viewed from above (e.g., in a planar view), the shape of each of the emission regions EA1", EA2", and EA3" of the third pixel PX3 may differ from the shape of each of the emission regions EA1", EA2", EA3", and EA4 of the first pixel PX1. For example, when viewed from above (e.g., in a planar view), each of the first emission region EA1", the second emission region EA2", and the third emission region EA3" may have a rectangular shape. When viewed from above (e.g., in a planar view), each of the first emission region EA1", the second emission region EA2", and the third emission region EA3" may have a rectangular shape having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction).

[0155] However, it should be understood that, when viewed from above (e.g., in a plan view), the shape of each of the first emission region EA1", the second emission region EA2", and the third emission region EA3" is not limited thereto. When viewed from above (e.g., in a plan view), each of the first emission region EA1", the second emission region EA2", and the third emission region EA3" may have other suitable polygonal shapes besides quadrilateral, circular, or elliptical shapes. Although in Figure 9 In the example shown, the first emission region EA1", the second emission region EA2", and the third emission region EA3" have substantially the same area (e.g., planar area in a plan view), but this disclosure is not limited thereto. At least one of the first emission region EA1", the second emission region EA2", and the third emission region EA3" may have an area different from that of the other emission regions among the first emission region EA1", the second emission region EA2", and the third emission region EA3".

[0156] The first dam DAM1 can be disposed at the edge of the third display area DA3 adjacent to the second display area DA2. The first dam DAM1 can be disposed between the touch drive line TL and the cutout pattern CP of the second display area DA2. The first dam DAM1 can be an organic encapsulation layer 192 (see [link to encapsulation layer]) used to prevent or block the encapsulation layer TFEL. Figure 10 The characteristics of overflow. The first dam DAM1 can be extended in the A direction DRA (e.g., it can be extended in the A direction DRA).

[0157] like Figure 9 As shown, a third display area DA3, including a third pixel PX3 for displaying an image, is disposed between the first display area DA1 and the second display area DA2. Therefore, it is possible to prevent or reduce the occurrence of a gap between the image displayed on the first display area DA1 and the image displayed on the second display area DA2, which is perceived by the user.

[0158] Figure 10 It shows along Figure 9 A cross-sectional view of an example display panel taken by line III-III'.

[0159] Figure 10 The second thin-film transistor ST2, the first emitter region EA1", the second emitter region EA2", and the third emitter region EA3" of the thin-film transistor layer TFTL can be substantially the same as the first thin-film transistor ST1 and the third emitter region EA3 of the thin-film transistor layer TFTL; and therefore, redundant descriptions are not required.

[0160] To prevent or reduce the reduction in illuminance caused by the light emitted from emission regions EA1", EA2", and EA3" being blocked by the driving electrode TE and the sensing electrode RE, the touch driving line TL does not overlap with the first emission region EA1", the second emission region EA2", or the third emission region EA3". The touch driving line TL can be disposed on the second buffer layer BF2. The touch driving line TL can be... Figure 8 The connecting electrodes BE1 are made of the same material on the same layer.

[0161] The scan driver transistor SDT of the scan driver circuit may include a scan active layer SACT, a scan gate electrode SG, a scan source electrode SS, and a scan drain electrode SD. The scan active layer SACT, scan gate electrode SG, scan source electrode SS, and scan drain electrode SD of the scan driver transistor SDT can be respectively referenced above. Figure 8 The first active layer ACT1, first gate electrode G1, first source electrode S1, and first drain electrode D1 of the first thin-film transistor ST1 are substantially the same. Therefore, redundant descriptions are not required.

[0162] The scan driving transistor SDT is disposed together in the thin-film transistor layer TFTL with the second thin-film transistor ST2, which is used to drive the first emission region EA1", the second emission region EA2", and the third emission region EA3" of the third pixel PX3. Therefore, in order to avoid the second thin-film transistor ST2, the scan driving transistor SDT can be disposed in a position where the second thin-film transistor ST2 is not disposed. For example, in a plan view, the scan driving transistor SDT can be spaced apart from the second thin-film transistor ST2 so that the scan driving transistor SDT and the second thin-film transistor ST2 do not interfere with each other. Because the touch driving line TL is set not to overlap with the first emission region EA1", the second emission region EA2", and the third emission region EA3", the scan driving transistor SDT can overlap with the touch driving line TL in the third direction (Z-axis direction) (e.g., in a plan view).

[0163] The first voltage connection line VSEL can be disposed on the second interlayer dielectric layer 142. The first voltage connection line VSEL can be made of the same material as the first source electrode S1 and first drain electrode D1 of the first thin film transistor ST1, the second source electrode S2 and second drain electrode D2 of the second thin film transistor ST2, and the scan source electrode SS and scan drain electrode SD of the scan drive transistor SDT.

[0164] A first voltage line VSL may be disposed on the first planarization layer 150. In some embodiments, the first voltage line VSL may be a first supply voltage line. The first voltage line VSL may be formed of the same material as the first connection electrode ANDE1. The first voltage line VSL may be coupled (e.g., connected) to a first voltage connection line VSEL through a contact hole penetrating the first planarization layer 150. A first supply voltage may be applied to the first voltage line VSL.

[0165] Each of the light-emitting elements may include a pixel electrode 171", an emitting layer 172", and a common electrode 173". The common electrode 173" may be coupled (e.g., connected) to a first voltage line VSL through a contact hole through the second planarization layer 160. A first supply voltage of the first voltage line VSL may be applied to the common electrode 173".

[0166] A first dam DAM1 may be disposed in the third display area DA3 to prevent or block the overflow of the organic encapsulation layer 192 of the thin-film encapsulation layer TFEL. The first dam DAM1 may include a first sub-dam SDAM1 made of the same material as the first planarization layer 150, a second sub-dam SDAM2 made of the same material as the second planarization layer 160, and a third sub-dam SDAM3 made of the same material as the dam 180. Due to the first dam DAM1, the end of the organic encapsulation layer 192 may be disposed between the outermost first emission area EA1" and the first dam DAM1. A first inorganic encapsulation layer 191 and a second inorganic encapsulation layer 193 may be disposed on the first dam DAM1. The first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 may be in contact with each other on the first dam DAM1.

[0167] Another dam for restricting flow across the organic encapsulation layer 192 of the first dam DAM1 may be disposed on the outside of the first dam DAM1. The other dam may have a substantially identical structure to the first dam DAM1. In some embodiments, the other dam may include at least one selected from the first sub-dam SDAM1, the second sub-dam SDAM2, and the third sub-dam SDAM3 of the first dam DAM1.

[0168] like Figure 10 As shown, the scan driver transistor SDT of the scan driver circuit can be positioned where the second thin-film transistor ST2 is not located, so as to avoid the second thin-film transistor ST2 used to drive the first emission region EA1", the second emission region EA2", and the third emission region EA3" of the third pixel PX3. In this case, because the touch drive line TL is set not to overlap with the first emission region EA1", the second emission region EA2", and the third emission region EA3", the scan driver transistor SDT can overlap with the touch drive line TL in the third direction (Z-axis direction) (e.g., in the plan view).

[0169] Figure 11 It is shown Figure 5 A layout diagram of an example of the second display area.

[0170] Reference Figure 11 The second display area DA2 may include a notch pattern CP and a cutting groove CG. The notch pattern CP can be obtained by laser cutting the display panel 300 (see...). Figure 3 Therefore, the cutting groove CG can be formed between adjacent cutting patterns CP.

[0171] One end of each of the cutout patterns CP may be coupled (e.g., connected) to a third display area DA3, and the other end of each of the cutout patterns CP may be coupled (e.g., connected) to a cutout connection pattern CBP or a non-display area NDA. When viewed from above (e.g., in a plan view), the cutout patterns CP may be formed in a trapezoidal shape. The width of the cutout patterns CP may be wider or narrower from the third display area DA3 toward the cutout connection pattern CBP or the non-display area NDA. In some embodiments, the width of the cutout patterns CP at the third display area DA3 may be greater than the width of the cutout patterns CP at the cutout connection pattern CBP. For example, the width of the cutout patterns CP may vary continuously or discontinuously from the third display area DA3 toward (e.g., to) the cutout connection pattern CBP. For example, the width of the cutout patterns CP may vary along the length of the cutout patterns CP from the third display area DA3 to the cutout connection pattern CBP. Additionally, when viewed from above (e.g., in a plan view), the cut pattern CP can be formed as a rectangular shape, a rhombus shape, or any suitable polygonal shape other than a quadrilateral shape.

[0172] The second pixel PX2, the second dam DAM2, and the power contact hole PCT can be set in each of the cut pattern CP.

[0173] The second pixel PX2 can be arranged on the DRC in the C direction (e.g., along the DRC in the C direction). The second dam DAM2 can be set around the second pixel PX2 (e.g., around the second pixel PX2). The second dam DAM2 can be set at the edge of each of the cut patterns CP. For example, the second dam DAM2 can extend along the boundary of the corresponding cut pattern CP to surround the second pixel PX2 of the corresponding cut pattern CP.

[0174] Each of the second pixel PX2 may include multiple emission regions EA1', EA2', and EA3'. The number of emission regions EA1', EA2', and EA3' for each of the second pixel PX2 can be [missing information]. Figure 7The number of emission regions EA1, EA2, EA3, and EA4 in each of the first pixels PX1 shown is different. The number of emission regions EA1', EA2', and EA3' in each of the second pixels PX2 can be equal to, but is not limited to, equal to, the number of emission regions EA1', EA2', and EA3'. Figure 9 The number of emission regions EA1", EA2", and EA3" for each of the third pixel PX3 shown. The number of emission regions EA1', EA2', and EA3' for each of the second pixel PX2 can be related to... Figure 9 The number of emission regions EA1", EA2", and EA3" in each of the third pixels PX3 shown is different.

[0175] For example, each of the second pixels PX2 may include a first emission region EA1', a second emission region EA2', and a third emission region EA3'. The first emission region EA1' refers to the emission region of the first sub-pixel used to emit the first light, the second emission region EA2' refers to the emission region of the second sub-pixel used to emit the second light, and the third emission region EA3' refers to the emission region of the third sub-pixel used to emit the third light.

[0176] The first emission region EA1', the second emission region EA2', and the third emission region EA3' can emit light of different colors. For example, the first emission region EA1' can emit red light, the second emission region EA2' can emit green light, and the third emission region EA3' can emit blue light.

[0177] The first emission region EA1', the second emission region EA2', and the third emission region EA3' can be arranged on the DRC in the C direction. When viewed from above (e.g., in a plan view), each of the first emission region EA1', the second emission region EA2', and the third emission region EA3' can have a rectangular shape. For example, when viewed from above (e.g., in a plan view), each of the first emission region EA1', the second emission region EA2', and the third emission region EA3' can have a rectangular shape having a shorter side on the DRC in the C direction and a longer side on the DRD in the D direction. However, it should be understood that this disclosure is not limited thereto. When viewed from above (e.g., in a plan view), each of the first emission region EA1', the second emission region EA2', and the third emission region EA3' can have other suitable polygonal shapes besides quadrilateral, circular, or elliptical shapes. Although in Figure 11In the example shown, the first transmission region EA1', the second transmission region EA2', and the third transmission region EA3' have substantially the same area, but this disclosure is not limited thereto. At least one of the first transmission region EA1', the second transmission region EA2', and the third transmission region EA3' may have an area different from that of the other transmission regions among the first transmission region EA1', the second transmission region EA2', and the third transmission region EA3'.

[0178] A first encapsulation separator ED1 can be disposed between adjacent second pixels PX2. When the first encapsulation separator ED1 is disposed between adjacent second pixels PX2 in the C direction DRC, the first encapsulation separator ED1 can be extended in the D direction DRD (e.g., it can be extended in the D direction DRD). The first encapsulation separator ED1 can be coupled (e.g., connected) to a second dam DAM2. For example, the first encapsulation separator ED1 can extend from one part of the second dam DAM2 to another part of the second dam DAM2 between two adjacent second pixels PX2. For example, the first encapsulation separator ED1 can divide the area surrounded by the second dam DAM2 with the cut pattern CP.

[0179] like Figure 12 As shown, in the first encapsulation separator ED1, the first inorganic layer 161 can contact the common electrode 173', the first inorganic encapsulation layer 191 can contact the common electrode 173', and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. In the second dam DAM2, the first inorganic encapsulation layer 191 can contact the first inorganic layer 161, and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. Multiple inorganic layers can be stacked in the first encapsulation separator ED1 and the second dam DAM2. Therefore, the area defined by the first encapsulation separator ED1 and the second dam DAM2 can be individually encapsulated. For example, a separate encapsulation region IEA can be defined by the first encapsulation separator ED1 and the second dam DAM2. For example, each of the separate encapsulation regions IEA can be surrounded by the first encapsulation separator ED1 and the second dam DAM2.

[0180] The second pixel PX2 can be disposed in each of the individual encapsulation areas IEA. For example, because each of the second pixel PX2 is surrounded by the first encapsulation separator ED1 and the second dam DAM2, they can be encapsulated individually. Therefore, even if one of the second pixel PX2 of the cutout pattern CP appears as a dark spot due to moisture penetration caused by particles, damage to the other second pixel PX2 of the cutout pattern CP can be prevented or reduced. For example, even if one of the second pixel PX2 of the cutout pattern CP appears as a dark spot due to moisture penetration caused by particles, the occurrence of all second pixel PX2 of the cutout pattern CP being considered as dark spots can be prevented or reduced.

[0181] The power contact hole (PCT) can be located in the area surrounded by the second dam (DAM2). The power contact hole (PCT) can also be located within a separate package area (IEA). For example, the power contact hole (PCT) can be located between the second dam (DAM2) and a second pixel (PX2) located at one edge of the notch pattern (CP). The edge of the notch pattern (CP) can be an edge adjacent to the non-display area (NDA) or the notch connection pattern (CBP). The power contact hole (PCT) can be a first voltage line (VSL) (see...). Figure 13 ) and common electrode 173' (see Figure 13 A power connection hole coupled (e.g., connected) here (e.g., to here). Therefore, the first voltage line VSL (see...) Figure 13 The first supply voltage can be applied to the common electrode 173' (see Figure 13 ).

[0182] Figure 12 It shows along Figure 11 A cross-sectional view of an example display panel taken by line IV-IV'. Figure 13 It shows along Figure 11 A cross-sectional view of an example display panel taken by line V-V'.

[0183] The third thin-film transistor ST3, the first emitter region EA1', and the third emitter region EA3' of the thin-film transistor layer (TFTL) can be respectively compared with the above reference. Figure 8 The first thin-film transistor ST1, the first emitter region EA1, and the third emitter region EA3 of the described thin-film transistor layer (TFTL) are essentially the same. Therefore, redundant descriptions are unnecessary. Although in Figure 12 The diagram shows the first launch area EA1' and the third launch area EA3', but the second launch area EA2' can be connected to... Figure 12 The first launch area EA1' and the third launch area EA3' shown are essentially the same.

[0184] The second display area DA2 includes a display panel 300 cut with a laser (see...). Figure 3 The cut pattern CP and cut groove CG are formed. The organic encapsulation layer 192 of the TFEL (see...) Figure 8 and Figure 10 The notch pattern CP can be formed via an inkjet process. If the length or width of the notch pattern CP in the D direction DRD is in the range of tens of μm, it is difficult to form the organic encapsulation layer 192 within the second dam DAM2 of the notch pattern CP. If the organic encapsulation layer 192 is formed in the notch groove CG, the notch pattern CP is coupled (e.g., connected) through the organic encapsulation layer 192. Therefore, the strain and stress applied to the second display area DA2 due to the hypercurvature may not be sufficiently reduced. Therefore, the encapsulation layer TFEL in the first display area DA1 and the third display area DA3 includes a first inorganic encapsulation layer 191, an organic encapsulation layer 192, and a second inorganic encapsulation layer 193, while the encapsulation layer TFEL in the second display area DA2 includes a first inorganic encapsulation layer 191 and a second inorganic encapsulation layer 193, but does not include the organic encapsulation layer 192.

[0185] Because the organic encapsulation layer 192 of the encapsulation layer TFEL is higher than the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193, the organic encapsulation layer 192 of the encapsulation layer TFEL acts as a particle covering layer to cover the particles. When the encapsulation layer TFEL does not include the organic encapsulation layer 192 in the second display area DA2, a portion of the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 may be damaged by the particles. Therefore, moisture and / or oxygen may be introduced, and thus the emitter layer 172' may be damaged. When this happens, all second pixels PX2 disposed on the notch pattern CP may appear as dark spots.

[0186] The first encapsulation separator ED1 may include a first aperture DH1. The first aperture DH1 may be a hole penetrating the second planarization layer 160 and the dam 180. The first aperture DH1 may include a first sub-aperture SDH1 penetrating the second planarization layer 160 and a second sub-aperture SDH2 penetrating the dam 180. The size of the first sub-aperture SDH1 (e.g., planar area in a planar view) may be smaller than the size of the second sub-aperture SDH2 (e.g., planar area in a planar view). For example, the length of the first sub-aperture SDH1 in the C-direction DRC may be smaller than the length of the second sub-aperture SDH2 in the C-direction DRC.

[0187] Because the size of the first sub-hole SDH1 can be smaller than the size of the second sub-hole SDH2, a portion of the upper surface of the first inorganic layer 161 can be left uncovered by the dam 180. A portion of the upper surface of the first inorganic layer 161 can contact the common electrode 173'.

[0188] The second dam DAM2 may include a first subdam SDAM1' made of the same material as the second planarization layer 160, a second subdam SDAM2' made of the same material as the first inorganic layer 161, and a third subdam SDAM3' made of the same material as the dike 180. The second dam DAM2 may also include a fourth subdam disposed on the third subdam SDAM3'.

[0189] The second dam DAM2 can be formed in an undercut shape in the cross-sectional view. For example, the maximum length of the second sub-dam SDAM2' in one direction can be greater than the maximum length of the first sub-dam SDAM1' in that direction. For example, in the plan view, a portion of the second sub-dam SDAM2' can extend beyond the edge of the first sub-dam SDAM1', such that in the cross-sectional view, the second sub-dam SDAM2' hangs above the first sub-dam SDAM1'. Therefore, even if the emitter layer 172' or the common electrode 173' is formed to the second dam DAM2, the emitter layer 172' or the common electrode 173' can be separated (e.g., disconnected) due to the undercut shape of the second dam DAM2 in the cross-sectional view.

[0190] The first inorganic layer 161, the common electrode 173', the first inorganic encapsulation layer 191, and the second inorganic encapsulation layer 193 can be disposed in the first aperture DH1. A dam aperture DMH penetrating the second planarization layer 160 can be formed on the inner side of the second dam DAM2. The first inorganic layer 161, the first inorganic encapsulation layer 191, and the second inorganic encapsulation layer 193 can be disposed in the dam aperture DMH. Therefore, each of the second pixels PX2 can be surrounded by the first aperture DH1 and the dam aperture DMH of the first encapsulation separator ED1. Therefore, because the inorganic layers are in contact with each other in the dam aperture DMH of the first aperture DH1 and the second dam DAM2, each of the second pixels PX2 can be individually encapsulated. Therefore, even if one of the second pixels PX2 of the cut pattern CP appears as a dark spot due to moisture penetration caused by particles, damage to the other second pixels PX2 of the cut pattern CP can be prevented or reduced. For example, even if one of the second pixels PX2 of the cut pattern CP appears as a dark spot due to moisture penetration caused by particles, it is possible to prevent or reduce the occurrence of all second pixels PX2 of the cut pattern CP being regarded as dark spots.

[0191] Furthermore, the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be disposed on the cut surface or side of the notch pattern CP. For example, the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be disposed on the cut surface or side of the substrate SUB, the first buffer layer BF1, the gate insulating layer 130, the first interlayer dielectric layer 141, the second interlayer dielectric layer 142, and the first planarization layer 150 of the notch pattern CP. Therefore, damage to the emitter layer 172' that may occur when moisture and / or oxygen are introduced through the cut surface or side of the notch pattern CP can be prevented or reduced.

[0192] A power contact hole (PCT) extends through the second planarization layer 160 to expose the first voltage line (VSL). A common electrode (173') can be coupled (e.g., connected) to the first voltage line (VSL) through the power contact hole (PCT).

[0193] Figure 14 It is shown Figure 5 Another example of the layout diagram for the second display area. Figure 15 It shows along Figure 14 A cross-sectional view of an example display panel taken by line VI-VI'.

[0194] Figure 14 and Figure 15 Example embodiments and Figure 11 and Figure 12 The difference in the example embodiment is that the first hole DH1' of the first package separator ED1 has an undercut shape and the power contact hole PCT is disposed in each of the separate package areas IEA. The differences will be described in detail.

[0195] Reference Figure 14 and Figure 15 The first hole DH1' may include the first sub-hole SDH1' and the second sub-hole SDH2'.

[0196] The first sub-via SDH1' can penetrate the second planarization layer 160 to expose the second inorganic layer 162 disposed on the first planarization layer 150. The first sub-via SDH1' can be formed in an undercut shape in a cross-sectional view. An undercut shape refers to a hole in which the inlet is smaller than the bottom or a hole in which the inlet is smaller than the area between the inlet and the bottom. A hole with an undercut shape in a cross-sectional view can resemble the eaves of a tank or a roof in a cross-sectional view. For example, the inlet of the first sub-via SDH1' can be defined by the first inorganic layer 161. The lower surface of the first inorganic layer 161 may not be covered by the second planarization layer 160. For this reason, the size of the inlet of the first sub-via SDH1' can be smaller than the size of the area between the inlet and the bottom of the first sub-via SDH1'. In some embodiments, a portion of the first inorganic layer 161 in a plan view may extend beyond the side surface of the second planarization layer 160 forming the first sub-via SDH1', such that in a cross-sectional view the first inorganic layer 161 is suspended above the second planarization layer 160, and the length of the opening in the first inorganic layer 161 that overlaps with the first sub-via SDH1' in the plan view is less than the length of the first sub-via SDH1' at the lower surface of the first inorganic layer 161.

[0197] In the first sub-via SDH1', the first floating pattern FP1, the second floating pattern FP2, the first inorganic encapsulation layer 191, and the second inorganic encapsulation layer 193 can be disposed (e.g., stacked sequentially) on the second inorganic layer 162. Because the emitter layer 172' and the common electrode 173' have poor step coverage, the emitter layer 172' and the common electrode 173' may not be disposed on the sidewall of the first sub-via SDH1'. Therefore, the emitter layer 172' and the common electrode 173' can be separated (e.g., disconnected) at the first encapsulation separator ED1. Step coverage refers to the ability of subsequent layers to uniformly cover layers ("steps") already present on the substrate without being separated (e.g., disconnected).

[0198] The first floating pattern FP1 may be disposed in the first sub-via SDH1' on the second inorganic layer 162. The first floating pattern FP1 may be a residual layer of the emitter layer 172', which is not coupled (e.g., not connected) to the emitter layer 172' but is separate from the emitter layer 172' (e.g., disconnected). The first floating pattern FP1 may be made of the same material as the emitter layer 172'.

[0199] Additionally, a second floating pattern FP2 may be disposed in the first sub-via SDH1 on the second inorganic layer 162 (e.g., above the first floating pattern FP1). The second floating pattern FP2 may be a residual layer of the common electrode 173', which is not coupled (e.g., not connected) to the common electrode 173' but is separate from (e.g., disconnected) from the common electrode 173'. The second floating pattern FP2 may be made of the same material as the common electrode 173'.

[0200] Because the common electrode 173' is separated (e.g., disconnected) at the first package separator ED1 due to the undercut shape of the first hole DH1' in the cross-sectional view, the common electrode 173' of a single package region IEA is separated (e.g., disconnected) from the common electrode 173' of another separate package region IEA adjacent to that single package region IEA, with the first package separator ED1 between the single package region IEA and the other separate package region IEA. Therefore, a power contact hole PCT for applying a first supply voltage to the common electrode 173' can be provided in each of the single package regions IEA.

[0201] The second sub-hole SDH2' can penetrate the dam 180. The first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be disposed in the second sub-hole SDH2'.

[0202] Figure 16 It is shown Figure 5 Another example of the layout diagram for the second display area. Figure 17 It shows along Figure 16 A cross-sectional view of an example display panel taken by line VII-VII'.

[0203] Figure 16 and Figure 17 Example embodiments and Figure 11 and Figure 12 The difference in the example embodiment is that the second encapsulation separator ED2 is disposed between the first emission region EA1' and the second emission region EA2' of each of the second pixels PX2, and between the second emission region EA2' and the third emission region EA3'. The description will focus on the differences.

[0204] The second encapsulation separator ED2 can be disposed between the first emission region EA1' and the second emission region EA2' in each of the second pixels PX2, and between the second emission region EA2' and the third emission region EA3'. When the second encapsulation separator ED2 is disposed between adjacent emission regions EA1', EA2', and EA3' in the C direction DRC, the second encapsulation separator ED2 can be extended in the D direction DRD (e.g., it can be extended in the D direction DRD). The second encapsulation separator ED2 can be coupled (e.g., connected) to the second dam DAM2. For example, the second encapsulation separator ED2 can extend from one part of the second dam DAM2 to another part of the second dam DAM2 to delineate the area of ​​the cut pattern CP surrounded by the second dam DAM2.

[0205] The second encapsulation separator ED2 may include a second aperture DH2. The second aperture DH2 may penetrate the second planarization layer 160 and the dam 180. The second aperture DH2 may be connected to... Figure 12The first hole DH1 of the first encapsulation separator ED1 shown is substantially the same. Therefore, redundant descriptions are not required.

[0206] In the first encapsulation separator ED1 and the second encapsulation separator ED2, the first inorganic layer 161 can contact the common electrode 173', the first inorganic encapsulation layer 191 can contact the common electrode 173', and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. In the second dam DAM2, the first inorganic encapsulation layer 191 can contact the first inorganic layer 161, and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. In some embodiments, in the dam aperture DMH, the first inorganic encapsulation layer 191 can contact the first inorganic layer 161, and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. Multiple inorganic layers can be stacked in the first encapsulation separator ED1, the second encapsulation separator ED2, and the second dam DAM2. In some embodiments, multiple inorganic layers can be stacked in the dam aperture DMH. Therefore, the area defined by the first encapsulation separator ED1, the second encapsulation separator ED2, and the second dam DAM2 can be individually encapsulated. For example, each of the individual package regions IEA can be defined by a first package separator ED1, a second package separator ED2, and a second dam DAM2.

[0207] The emission regions EA1', EA2', and EA3' of the second pixel PX2 can each be disposed in a separate encapsulation region IEA. For example, each of the emission regions EA1', EA2', and EA3' of the second pixel PX2 is surrounded by a first encapsulation separator ED1, a second encapsulation separator ED2, and / or a second dam DAM2, and therefore they can be encapsulated individually. In some embodiments, each of the emission regions EA1', EA2', and EA3' of the second pixel PX2 can be surrounded by one or both of the first encapsulation separator ED1 and the second encapsulation separator ED2, as well as the second dam DAM2. Therefore, even if one of the emission regions EA1', EA2', and EA3' of the second pixel PX2 in the cutout pattern CP appears as a dark spot due to moisture penetration caused by particles, damage to the other emission regions EA1', EA2', and EA3' of the second pixel PX2 in the cutout pattern CP can be prevented or reduced. Therefore, even if one of the emission regions EA1', EA2', and EA3' of the second pixel PX2 of the cut pattern CP appears as a dark spot due to moisture penetration caused by particles, the occurrence of all emission regions EA1', EA2', and EA3' of the second pixel PX2 of the cut pattern CP appearing as dark spots can be prevented or reduced.

[0208] Figure 18 It is shown Figure 5 Another example of the layout diagram for the second display area. Figure 19 It shows along Figure 18 A cross-sectional view of an example display panel taken by line VIII-VIII'.

[0209] Figure 18 and Figure 19 Example embodiments and Figure 16 and Figure 17 The difference in the example embodiment is that the first hole DH1' of the first package separator ED1 has an undercut shape and the power contact hole PCT is provided in each of the separate package areas IEA.

[0210] according to Figure 18 and Figure 19 The exemplary embodiment of the first hole DH1' in the cross-sectional view and the power contact hole PCT in each of the individual package areas IEA are referenced above. Figure 14 and Figure 15 The undercut shape of the first hole DH1' described in the cross-sectional view is substantially the same as the power contact hole PCT in each of the individual package areas IEA. Therefore, redundant descriptions are not required.

[0211] Figure 20 It is shown Figure 5 Another example of the layout diagram for the second display area. Figure 21 It shows along Figure 20 A cross-sectional view of an example display panel taken by line X-X'.

[0212] Figure 20 and Figure 21 Example embodiments and Figure 11 and Figure 12 The difference in the example embodiment is that the first transmission region EA1' includes a first sub-transmission region EA11 and a second sub-transmission region EA12, the second transmission region EA2' includes a third sub-transmission region EA21 and a fourth sub-transmission region EA22, the third transmission region EA3' includes a fifth sub-transmission region EA31 and a sixth sub-transmission region EA32, and a third encapsulation separator ED3 is further provided. The description will focus on the differences. Figure 20 A cross-sectional view of the display panel taken along line IX-IX' and Figure 12 The cross-sectional views are basically the same. Therefore, redundant descriptions are unnecessary. Figure 21 It can be applied to the first sub-transmission area EA11 and the second sub-transmission area EA12 of the first transmission area EA1', the third sub-transmission area EA21 and the fourth sub-transmission area EA22 of the second transmission area EA2', and the fifth sub-transmission area EA31 and the sixth sub-transmission area EA32 of the third transmission area EA3'.

[0213] Reference Figure 20 and Figure 21 The pixel electrode 171' of the first sub-emitting region EA11 and the pixel electrode 171' of the second sub-emitting region EA12 can be coupled (e.g., connected) to the same first connection electrode ANDE1. Therefore, the pixel electrode 171' of the first sub-emitting region EA11 and the pixel electrode 171' of the second sub-emitting region EA12 can be electrically coupled (e.g., connected) to the third source electrode S3 or the third drain electrode D3 of the same third thin-film transistor ST3. Therefore, the same voltage can be applied to the pixel electrode 171' of the first sub-emitting region EA11 and the pixel electrode 171' of the second sub-emitting region EA12. Therefore, the first sub-emitting region EA11 and the second sub-emitting region EA12 of the first emitting region EA1' can emit the same light with the same brightness. For example, the first sub-emitting region EA11 and the second sub-emitting region EA12 can emit red light with the same brightness.

[0214] The pixel electrode 171' of the third sub-emission region EA21 and the pixel electrode 171' of the fourth sub-emission region EA22 can be coupled (e.g., connected) to the same first connection electrode ANDE1. Therefore, the pixel electrodes 171' of the third sub-emission region EA21 and the pixel electrode 171' of the fourth sub-emission region EA22 can be electrically coupled (e.g., connected) to the third source electrode S3 or the third drain electrode D3 of the same third thin-film transistor ST3. Therefore, the same voltage can be applied to the pixel electrodes 171' of the third sub-emission region EA21 and the pixel electrode 171' of the fourth sub-emission region EA22. Therefore, the third sub-emission region EA21 and the fourth sub-emission region EA22 of the second emission region EA2' can emit the same light with the same brightness. For example, the third sub-emission region EA21 and the fourth sub-emission region EA22 can emit green light with the same brightness.

[0215] The pixel electrode 171' of the fifth sub-emission region EA31 and the pixel electrode 171' of the sixth sub-emission region EA32 can be coupled (e.g., connected) to the same first connection electrode ANDE1. Therefore, the pixel electrodes 171' of the fifth sub-emission region EA31 and the pixel electrode 171' of the sixth sub-emission region EA32 can be electrically coupled (e.g., connected) to the third source electrode S3 or the third drain electrode D3 of the same third thin-film transistor ST3. Therefore, the same voltage can be applied to the pixel electrodes 171' of the fifth sub-emission region EA31 and the pixel electrode 171' of the sixth sub-emission region EA32. Therefore, the fifth sub-emission region EA31 and the sixth sub-emission region EA32 of the third emission region EA3' can emit the same light with the same brightness. For example, the fifth sub-emission region EA31 and the sixth sub-emission region EA32 can emit blue light with the same brightness.

[0216] Despite Figure 20 In the example shown, when viewed from above (e.g., in a plan view), each of the first sub-emission region EA11, the second sub-emission region EA12, the third sub-emission region EA21, the fourth sub-emission region EA22, the fifth sub-emission region EA31, and the sixth sub-emission region EA32 has a rectangular shape, having a shorter side in the C direction DRC and a longer side in the D direction DRD, but this disclosure is not limited thereto. When viewed from above (e.g., in a plan view), each of the first sub-emission region EA11, the second sub-emission region EA12, the third sub-emission region EA21, the fourth sub-emission region EA22, the fifth sub-emission region EA31, and the sixth sub-emission region EA32 may have a suitable polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape. Additionally, although in Figure 20 In the example shown, the first sub-emission region EA11, the second sub-emission region EA12, the third sub-emission region EA21, the fourth sub-emission region EA22, the fifth sub-emission region EA31, and the sixth sub-emission region EA32 have substantially the same area (e.g., planar area in a plan view), but this disclosure is not limited thereto. At least one selected from the first sub-emission region EA11, the second sub-emission region EA12, the third sub-emission region EA21, the fourth sub-emission region EA22, the fifth sub-emission region EA31, and the sixth sub-emission region EA32 may have an area different from that of the other emission regions among the first sub-emission region EA11, the second sub-emission region EA12, the third sub-emission region EA21, the fourth sub-emission region EA22, the fifth sub-emission region EA31, and the sixth sub-emission region EA32.

[0217] The first sub-transmitter region EA11 and the second sub-transmitter region EA12 can be spaced apart from each other in the D direction DRD. The third sub-transmitter region EA21 and the fourth sub-transmitter region EA22 can be spaced apart from each other in the D direction DRD. The fifth sub-transmitter region EA31 and the sixth sub-transmitter region EA32 can be spaced apart from each other in the D direction DRD.

[0218] A third encapsulation separator ED3 may be disposed between the first sub-emitting region EA11 and the second sub-emitting region EA12, between the third sub-emitting region EA21 and the fourth sub-emitting region EA22, and between the fifth sub-emitting region EA31 and the sixth sub-emitting region EA32. The third encapsulation separator ED3 may be extended along the C-direction DRC (e.g., it may extend along the C-direction DRC). The third encapsulation separator ED3 may be coupled (e.g., connected) to the second dam DAM2. For example, one end of the third encapsulation separator ED3 may be coupled (e.g., connected) to a portion of the second dam DAM2, and the other end of the third encapsulation separator ED3 may be coupled to another portion of the second dam DAM2 to delineate the area of ​​the cutout pattern CP surrounded by the second dam DAM2.

[0219] The third encapsulation separator ED3 may include a third aperture DH3. The third aperture DH3 may penetrate the dam 180 to expose the first inorganic layer 161. The third aperture DH3 may be positioned between the pixel electrode 171' of the first sub-emitting region EA11 and the pixel electrode 171' of the second sub-emitting region EA12. The third aperture DH3 may be positioned between the pixel electrode 171' of the third sub-emitting region EA21 and the pixel electrode 171' of the fourth sub-emitting region EA22. The third aperture DH3 may be positioned between the pixel electrode 171' of the fifth sub-emitting region EA31 and the pixel electrode 171' of the sixth sub-emitting region EA32.

[0220] A common electrode 173', a first inorganic encapsulation layer 191, and a second inorganic encapsulation layer 193 can be disposed in a third aperture DH3. Therefore, in the third encapsulation separator ED3, the first inorganic layer 161 can contact the common electrode 173', the first inorganic encapsulation layer 191 can contact the common electrode 173', and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. Therefore, the movement of moisture and / or oxygen can be blocked by the third encapsulation separator ED3. Therefore, the area defined by the first encapsulation separator ED1, the third encapsulation separator ED3, and the second dam DAM2 can be individually encapsulated. For example, the first sub-emission region EA11, the third sub-emission region EA21, and the fifth sub-emission region EA31 can be individually encapsulated, and the second sub-emission region EA12, the fourth sub-emission region EA22, and the sixth sub-emission region EA32 can be individually encapsulated. For example, the first sub-emission region EA11, the third sub-emission region EA21 and the fifth sub-emission region EA31 can be surrounded by the first encapsulation separator ED1, the third encapsulation separator ED3 and the second dam DAM2.

[0221] Therefore, even if one of the first sub-emission region EA11, the third sub-emission region EA21, and the fifth sub-emission region EA31 becomes a dark spot due to moisture penetration caused by particles, the occurrence of damage to the second sub-emission region EA12, the fourth sub-emission region EA22, and the sixth sub-emission region EA32, resulting in a corresponding dark spot, can be prevented or reduced. Furthermore, even if one of the second sub-emission region EA12, the fourth sub-emission region EA22, and the sixth sub-emission region EA32 becomes a dark spot due to moisture penetration caused by particles, the occurrence of damage to the first sub-emission region EA11, the third sub-emission region EA21, and the fifth sub-emission region EA31, resulting in a corresponding dark spot, can be prevented or reduced.

[0222] For example, even if one of the first sub-emission regions EA11 and EA12 of the first emission region EA1', which emits the same light with the same brightness, appears as a dark spot due to moisture penetration caused by particles, the other of the first sub-emission regions EA11 and EA12 may not appear as a dark spot. Similarly, even if one of the third sub-emission regions EA21 and EA22 of the second emission region EA2', which emits the same light with the same brightness, appears as a dark spot due to moisture penetration caused by particles, the other of the third sub-emission regions EA21 and EA22 may not appear as a dark spot. Furthermore, even if one of the fifth sub-emission regions EA31 and EA32 of the third emission region EA3', which emits the same light with the same brightness, appears as a dark spot due to moisture penetration caused by particles, the other of the fifth sub-emission regions EA31 and EA32 may not appear as a dark spot. Therefore, even if some of the sub-emission regions EA11, EA12, EA21, EA22, EA31, and EA32 of the second pixel PX2 (e.g., the first sub-emission region EA11, the third sub-emission region EA21, and the fifth sub-emission region EA31) appear as dark spots due to moisture penetration caused by particles, the image can still be displayed normally by utilizing (e.g., using) other sub-emission regions (e.g., the second sub-emission region EA12, the fourth sub-emission region EA22, and the sixth sub-emission region EA32).

[0223] Figure 22 It is shown Figure 5 Another example of the layout diagram for the second display area. Figure 23 It shows along Figure 22 A cross-sectional view of an example display panel taken by line B-B'.

[0224] Figure 22 and Figure 23 Example embodiments and Figure 20 and Figure 21 The difference in the example embodiment is that the third hole DH3' of the third package separator ED3 has an undercut shape and the power contact hole PCT is provided in each of the separate package areas IEA.

[0225] according to Figure 22 and Figure 23 In the example embodiment, the power contact hole PCT in each of the separate package areas (IEA) is referenced above. Figure 14 and Figure 15 The power contact holes (PCTs) in each of the individual package areas (IEAs) are substantially the same. Therefore, redundant descriptions are unnecessary. Figure 22A cross-sectional view of the display panel taken along line A-A' and Figure 12 The cross-sectional views are basically the same. Therefore, redundant descriptions are unnecessary. Figure 23 It can be applied to the first sub-transmission area EA11 and the second sub-transmission area EA12 of the first transmission area EA1', the third sub-transmission area EA21 and the fourth sub-transmission area EA22 of the second transmission area EA2', and the fifth sub-transmission area EA31 and the sixth sub-transmission area EA32 of the third transmission area EA3'.

[0226] Reference Figure 22 and Figure 23 The third encapsulation separator ED3 may include a third aperture DH3'. The third aperture DH3' may penetrate the second planarization layer 160, the first inorganic layer 161, and the dam 180. The third aperture DH3' may be positioned between the pixel electrode 171' of the first sub-emission region EA11 and the pixel electrode 171' of the second sub-emission region EA12. The third aperture DH3' may be positioned between the pixel electrode 171' of the third sub-emission region EA21 and the pixel electrode 171' of the fourth sub-emission region EA22. The third aperture DH3' may be positioned between the pixel electrode 171' of the fifth sub-emission region EA31 and the pixel electrode 171' of the sixth sub-emission region EA32.

[0227] The third hole DH3' may include the first sub-hole SDH1" and the second sub-hole SDH2".

[0228] The first sub-via SDH1" can penetrate the second planarization layer 160 to expose the first connection electrode ANDE1. The first sub-via SDH1" can be formed in an undercut shape in a cross-sectional view. An undercut shape refers to a hole in which the inlet is smaller than the bottom or a hole in which the inlet is smaller than the area between the inlet and the bottom. A hole with an undercut shape in a cross-sectional view can resemble the eaves of a can or a roof in a cross-sectional view. For example, the inlet of the first sub-via SDH1" can be defined by the first inorganic layer 161. The lower surface of the first inorganic layer 161 may not be covered by the second planarization layer 160. For this reason, the size of the inlet of the first sub-via SDH1" can be smaller than the size of the area between the inlet and the bottom of the first sub-via SDH1".

[0229] On the first connecting electrode ANDE1, a first inorganic encapsulation layer 191 and a second inorganic encapsulation layer 193 can be disposed within the first sub-via SDH1". Because the emitter layer 172' and the common electrode 173' have poor step coverage, the emitter layer 172' and the common electrode 173' may not be disposed on the sidewall of the first sub-via SDH1". Therefore, the emitter layer 172' and the common electrode 173' can be separated (e.g., disconnected) at the third encapsulation separator ED3. Step coverage refers to the ability of subsequent layers to uniformly cover layers ("steps") already present on the substrate without being separated (e.g., disconnected).

[0230] The second sub-hole SDH2” can penetrate the dam 180. The first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be disposed in the second sub-hole SDH2”.

[0231] Despite Figure 23 In the example shown, no floating pattern is set in the first sub-hole SDH1", but a pattern such as can be set in the first sub-hole SDH1". Figure 15 The first floating pattern FP1 and the second floating pattern FP2 are shown in the figure.

[0232] like Figure 23 As shown, the first connecting electrode ANDE1 can contact the first inorganic encapsulation layer 191, and the second inorganic encapsulation layer 193 can contact the first inorganic encapsulation layer 191. Therefore, the movement of moisture and / or oxygen can be blocked by the third encapsulation separator ED3. Thus, the area defined by the first encapsulation separator ED1, the third encapsulation separator ED3, and the second dam DAM2 can be individually encapsulated.

[0233] Incidentally, because the common electrode 173' is separated (e.g., disconnected) at the third package separator ED3 due to the undercut shape of the third hole DH3' in the cross-sectional view, the common electrode 173' of a single package region IEA is separated (e.g., disconnected) from the common electrode 173' of another separate package region IEA adjacent to that single package region IEA, with the third package separator ED3 located between the single package region IEA and the other separate package region IEA. Therefore, a power contact hole PCT for applying the first supply voltage to the common electrode 173' can be provided in each of the single package regions IEA.

[0234] Figure 24 It is shown Figure 5 Another example of the layout diagram for the second display area.

[0235] Figure 24 Example embodiments and Figure 20 and Figure 21The difference in the example embodiment is that the second encapsulation separator ED2 is disposed between the first emission region EA1' and the second emission region EA2' of each of the second pixels PX2 and between the second emission region EA2' and the third emission region EA3'.

[0236] The second encapsulation separator ED2 is referenced above. Figure 16 and Figure 17 The second encapsulation separator ED2 is essentially the same as described. Therefore, redundant descriptions are unnecessary. Figure 24 A cross-sectional view of the display panel taken along line C-C' and Figure 17 The cross-sectional views are basically the same. Therefore, redundant descriptions are unnecessary. Figure 24 A cross-sectional view of the display panel taken along line D-D' and Figure 21 The cross-sectional views are essentially the same except for the third encapsulation separator ED3. Therefore, redundant descriptions are unnecessary.

[0237] Figure 25 It is shown Figure 5 Another example of the layout diagram for the second display area.

[0238] Figure 25 Example embodiments and Figure 22 and Figure 23 The difference in the example embodiment is that the second encapsulation separator ED2 is disposed between the first emission region EA1' and the second emission region EA2' of each of the second pixels PX2 and between the second emission region EA2' and the third emission region EA3'.

[0239] The second encapsulation separator ED2 is referenced above. Figure 16 and Figure 17 The second encapsulation separator ED2 is essentially the same as described. Therefore, redundant descriptions are unnecessary. Figure 25 A cross-sectional view of the display panel taken along line E-E' and Figure 17 The cross-sectional views are basically the same. Therefore, redundant descriptions are unnecessary. Figure 25 A cross-sectional view of the display panel taken along line F-F' and Figure 23 The cross-sectional views are basically the same. Therefore, redundant descriptions are unnecessary.

[0240] Although some embodiments of this disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various suitable modifications, additions and substitutions are possible without departing from the scope and spirit of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes a front portion, a first side portion extending from a first side of the front portion, a second side portion extending from a second side of the front portion, and a corner portion between the first side portion and the second side portion. The display panel includes: A first display area is located at the front portion and includes a plurality of first pixels; and A second display area is located at the corner and includes a plurality of second pixels. The second display area includes a first encapsulation separator between adjacent second pixels among the plurality of second pixels.

2. The display device according to claim 1, wherein, Each of the first pixel and the second pixel includes multiple emission regions, and The emission region of each of the plurality of first pixels is different in number from the emission region of each of the plurality of second pixels.

3. The display device according to claim 1, wherein, The second display area includes: The dam is located around the plurality of second pixels; and Multiple separate encapsulation regions are defined by the first encapsulation separator and the dam, and Each of the plurality of individual encapsulation regions includes at least one of the plurality of second pixels.

4. The display device according to claim 3, wherein, The second display area also includes a power connection hole, located in one of the plurality of separate package areas.

5. The display device according to claim 3, wherein, The second display area also includes a power connection hole in each of the plurality of separate package areas.

6. The display device according to claim 3, wherein, Each of the plurality of second pixels includes: A thin-film transistor includes a gate electrode, a source electrode, and a drain electrode; The pixel electrode is coupled to the source electrode or the drain electrode of the thin film transistor through a contact hole penetrating the planarization layer on the thin film transistor. An emission layer is located on the pixel electrode; Common electrode, on the emitter layer; and The first inorganic encapsulation layer is on the common electrode.

7. The display device according to claim 6, wherein, The first encapsulation separator includes a first hole penetrating the planarization layer.

8. The display device according to claim 7, wherein, The common electrode and the first inorganic encapsulation layer are located in the first hole.

9. The display device according to claim 7, wherein, The second display area further includes a first inorganic layer between the planarization layer and the pixel electrode.

10. The display device according to claim 9, wherein, The first inorganic layer is in the first hole and is in contact with the common electrode in the first hole.

11. The display device according to claim 9, wherein, The second display area further includes a second inorganic encapsulation layer in the first hole.

12. The display device according to claim 11, wherein, The second inorganic encapsulation layer contacts the first inorganic encapsulation layer in the first hole.

13. The display device according to claim 11, wherein, The first hole is undercut.

14. The display device according to claim 6, wherein, Each of the plurality of second pixels includes a plurality of emission regions, and wherein the second display region includes a second encapsulation separator between adjacent emission regions among the plurality of emission regions.

15. The display device according to claim 14, wherein, Each of the plurality of individual packaging regions is defined by the first packaging separator, the second packaging separator, and the dam, and Each of the plurality of individual encapsulation regions includes one of the plurality of emission regions.

16. The display device according to claim 15, wherein, The second encapsulation separator includes a second hole penetrating the planarization layer.

17. The display device according to claim 16, wherein, The common electrode and the first inorganic encapsulation layer are located in the second hole.

18. The display device according to claim 17, wherein, The second display area further includes: a first inorganic layer, located between the planarization layer and the pixel electrode, and The first inorganic layer is located in the second hole and is in contact with the common electrode in the second hole.

19. A display device, comprising: The display panel includes a front portion, a first side portion extending from a first side of the front portion, a second side portion extending from a second side of the front portion, and a corner portion between the first side portion and the second side portion. The corner portion includes multiple cut patterns separated by cutting grooves. Each of the plurality of cut patterns includes a display area with multiple pixels for displaying an image. Each of the plurality of pixels includes multiple emission regions to emit different light, and Each of the plurality of emission regions includes a plurality of sub-emission regions to emit light of the same color.

20. The display device according to claim 19, wherein, The display area further includes a first encapsulation separator between adjacent pixels among the plurality of pixels.

21. The display device according to claim 19, wherein, The display area further includes a second encapsulation separator between adjacent emission areas in the plurality of emission areas.

22. The display device according to claim 19, wherein, The display area further includes a third encapsulation separator between adjacent sub-emission areas in the plurality of sub-emission areas.

23. The display device according to claim 22, wherein, Each of the plurality of pixels includes: A thin-film transistor includes a gate electrode, a source electrode, and a drain electrode; The connecting electrode is coupled to the source electrode or the drain electrode of the thin film transistor through a first connecting contact hole penetrating the first planarization layer on the thin film transistor. A pixel electrode is coupled to the connection electrode in the first emission region and through a first contact hole in the second planarization layer that extends through the connection electrode. The pixel electrode is located in the second emission region and is coupled to the connection electrode through a second contact hole penetrating the second planarization layer; An emission layer is provided on the pixel electrode in the first emission region and the pixel electrode in the second emission region. Common electrode, on the emitter layer; and The first inorganic encapsulation layer is on the common electrode.

24. The display device according to claim 23, wherein, The third encapsulation separator is located between the pixel electrode of the first sub-emission region and the pixel electrode of the second sub-emission region in the sub-emission region, and includes a third hole penetrating the second planarization layer.

25. The display device according to claim 24, wherein, In the cross-sectional view, the third hole is undercut.

Images