A table lookup circuit, memory and method based on aes decode-in-place

Abstract

The embodiment of the present application provides a table lookup circuit based on in-memory decoding of AES, a memory and a method, the circuit comprises: a voltage / time difference conversion circuit, a data output circuit and a decoding circuit; the voltage / time difference conversion circuit is used for applying different voltages to word lines connected with two storage units to make the two storage units discharge in turn, and forming an enabling signal with different voltage rising times according to different resistance states of the two storage units and different discharge speeds of bit lines; the data output circuit is used for making the two in-memory decoding units output logic signals respectively according to the rising time of the enabling signal; and the decoding circuit is used for generating a table lookup address according to the logic signals output by the two in-memory decoding units respectively, so that the time and power consumption of the table lookup circuit can be effectively reduced without limiting the bandwidth of data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of table lookup circuit, and particularly relates to a table lookup circuit based on AES in-memory decoding, a memory and a method. BACKGROUND

[0002] In the related art, the table lookup circuit for the advanced encryption standard (AES) is separated from data storage, and the logic unit for processing lookup and the memory are separated. In the execution stage, data is obtained from the memory according to an instruction and input into the decoding circuit for decoding, and then the result is obtained to perform lookup in the substitution box (S-box). Although this structure improves the computing capability of the computing system, it limits the bandwidth of data transmission, and also causes long delay and power consumption in the computing process. SUMMARY

[0003] An object of the present application is to provide a table lookup circuit based on AES in-memory decoding, which can effectively reduce the time and power consumption of the table lookup circuit without limiting the bandwidth of data transmission. Another object of the present application is to provide a memory. Another object of the present application is to provide a table lookup method based on AES in-memory decoding.

[0004] To achieve the above objects, the present application discloses a table lookup circuit based on AES in-memory decoding, comprising:

[0005] a voltage / time difference conversion circuit, a data output circuit and a decoding circuit.

[0006] The voltage / time difference conversion circuit is used to apply different voltages to the word lines connected to the two storage units to make the two storage units discharge in turn, and form an enable signal with different voltage rising times according to the resistance states of the two storage units and the discharge speeds of the bit lines.

[0007] The data output circuit is used to make the two in-memory decoding units output logic signals respectively according to the rising times of the enable signals.

[0008] The decoding circuit is used to generate a table lookup address according to the logic signals output by the two in-memory decoding units respectively.

[0009] Preferably, the voltage / time difference conversion circuit comprises a discharge control unit and an inverter.

[0010] The discharge control unit is used to apply different voltages to the word lines connected to the two storage units to make the two storage units discharge at different discharge speeds, and form discharge voltages corresponding to the resistance states of the two storage units and the discharge speeds.

[0011] The inverter is used to output an enable signal corresponding to a rising time when a discharge voltage reaches a preset voltage threshold.

[0012] Preferably, the discharge control unit comprises two discharge sub-units.

[0013] Each of the discharge sub-units comprises a first discharge circuit, a second discharge circuit and a voltage output circuit.

[0014] The first discharge circuit comprises a first power terminal, a first switch element, at least one first storage unit and a second switch element.

[0015] The second discharge circuit comprises a second power terminal, a third switch element, at least one second storage unit and a fourth switch element.

[0016] The voltage output circuit comprises a fifth switch element and a sixth switch element.

[0017] The control terminal of the first switch element is connected with a bit line inputting a first pre-charge signal, the first terminal is connected with the first power terminal, and the second terminal is connected with the first terminal of the second switch element.

[0018] The control terminal of the second switch element is connected with a word line inputting a first discharge signal, and the second terminal is connected with a signal input terminal of the first storage unit.

[0019] The signal output terminal of the at least one first storage unit is connected with the voltage output circuit.

[0020] The control terminal of the third switch element is connected with a bit line inputting a second pre-charge signal, the first terminal is connected with the second power terminal, and the second terminal is connected with the first terminal of the fourth switch element.

[0021] The control terminal of the fourth switch element is connected with a word line inputting a second discharge signal, and the second terminal is connected with a signal input terminal of the second storage unit.

[0022] The signal output terminal of the at least one second storage unit is connected with the voltage output circuit.

[0023] The control terminals of the fifth switch element and the sixth switch element are connected with a third power terminal.

[0024] The first terminal of the fifth switch element is connected with the signal output terminal of the first storage unit, and the second terminal is connected with a voltage output terminal outputting an enable signal.

[0025] The first terminal of the sixth switch element is connected with the signal output terminal of the second storage unit, and the second terminal is connected with the voltage output terminal outputting the enable signal.

[0026] The first switch element is turned on in response to a first pre-charge signal to make the first end of the second switch element conductive with the first power supply end, and the second switch element is turned on in response to a first discharge signal to make the first storage unit discharge under the action of the first power supply end;

[0027] The third switch element is turned on in response to a second pre-charge signal to make the first end of the fourth switch element conductive with the second power supply end, and the fourth switch element is turned on in response to a second discharge signal to make the second storage unit discharge under the action of the second power supply end.

[0028] Preferably, the voltage / time difference conversion circuit further comprises a buffer;

[0029] The first end of the buffer is connected with the inverter, and the second end is connected with the data output circuit;

[0030] The buffer is used to enhance the enable signal output by the inverter.

[0031] Preferably, the data output circuit comprises a first in-memory decoding unit and a second in-memory decoding unit;

[0032] The first in-memory decoding unit and the second in-memory decoding unit comprise a first signal input end, a second signal input end, a third signal input end and a fourth signal input end, and a first signal output end, a second signal output end, a third signal output end and a fourth signal output end;

[0033] The first signal input ends of the first in-memory decoding unit and the second in-memory decoding unit are respectively connected with the voltage output ends of the two discharge units;

[0034] The second signal input ends, the third signal input ends and the fourth signal input ends of the first in-memory decoding unit and the second in-memory decoding unit are respectively used to receive a first pulse signal corresponding to a first voltage rise time, a second pulse signal corresponding to a second voltage rise time and a third pulse signal corresponding to a third voltage rise time;

[0035] The first signal output ends, the second signal output ends, the third signal output ends and the fourth signal output ends of the first in-memory decoding unit and the second in-memory decoding unit are used to output logic signals corresponding to the rise time of the enable signal, and the rise time of the enable signal is the first voltage rise time, the second voltage rise time, the third voltage rise time or a fourth voltage rise time which is not the first voltage rise time, not the second voltage rise time and not the third voltage rise time.

[0036] Preferably, the decoding circuit is configured to perform an AND operation between a logic signal outputted by each of the first signal output terminal, the second signal output terminal, the third signal output terminal and the fourth signal output terminal of the first in-memory decoding unit and a logic signal outputted by each of the first signal output terminal, the second signal output terminal, the third signal output terminal and the fourth signal output terminal of the second in-memory decoding unit, to obtain the lookup table address.

[0037] The application further discloses a memory comprising a plurality of memory cells and an AES in-memory decoding based lookup table circuit as described above.

[0038] The application further discloses an AES in-memory decoding based lookup table method, comprising:

[0039] applying different voltages to word lines connected to the two memory cells to make the two memory cells discharge in sequence;

[0040] forming an enable signal with different voltage rising times corresponding to different resistance states of the two memory cells and different discharging speeds of the bit lines;

[0041] outputting logic signals by the two in-memory decoding units according to the rising time of the enable signal;

[0042] generating a lookup table address according to the logic signals outputted by the two in-memory decoding units.

[0043] Preferably, the memory cells comprise a first memory cell and a second memory cell.

[0044] Before the step of applying different voltages to word lines connected to the two memory cells to make the two memory cells discharge in sequence, the method further comprises:

[0045] controlling the first switch element to be turned on in response to a first pre-charging signal to make the first end of the second switch element be connected to the first power supply terminal, and controlling the second switch element to be turned on in response to a first discharging signal to make the first memory cell discharge under the action of the first power supply terminal;

[0046] controlling the third switch element to be turned on in response to a second pre-charging signal to make the first end of the fourth switch element be connected to the second power supply terminal, and controlling the fourth switch element to be turned on in response to a second discharging signal to make the second memory cell discharge under the action of the second power supply terminal.

[0047] Preferably, the step of forming an enable signal with different voltage rising times corresponding to different resistance states of the two memory cells and different discharging speeds of the bit lines comprises:

[0048] applying different voltages to word lines connected to the two memory cells to make the two memory cells discharge at different discharging speeds, to form a discharging voltage corresponding to the resistance states and the discharging speeds of the two memory cells;

[0049] When the discharge voltage reaches the preset voltage threshold, an enable signal corresponding to the rising time is output.

[0050] Preferably, the in-memory decoding unit comprises a first in-memory decoding unit and a second in-memory decoding unit.

[0051] According to the rising time of the enable signal, the two in-memory decoding units respectively output logic signals, including:

[0052] The first signal input end, the second signal input end, the third signal input end and the fourth signal input end of the first in-memory decoding unit and the second in-memory decoding unit respectively receive a first pulse signal corresponding to the first voltage rising time, a second pulse signal corresponding to the second voltage rising time and a third pulse signal corresponding to the third voltage rising time.

[0053] The first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first in-memory decoding unit and the second in-memory decoding unit output logic signals corresponding to the enable signal, and the rising time of the enable signal is the first voltage rising time, the second voltage rising time, the third voltage rising time or a fourth voltage rising time which is not the first voltage rising time, not the second voltage rising time and not the third voltage rising time.

[0054] Preferably, the in-memory decoding unit comprises a first in-memory decoding unit and a second in-memory decoding unit, and the first in-memory decoding unit and the second in-memory decoding unit comprise a first signal output end, a second signal output end, a third signal output end and a fourth signal output end.

[0055] According to the logic signals respectively output by the two in-memory decoding units, a lookup table address is generated, including:

[0056] The logic signals output by each of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first in-memory decoding unit are respectively ANDed with the logic signals output by the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the second in-memory decoding unit, to obtain the lookup table address.

[0057] The application provides a table lookup circuit based on AES in-memory decoding, which comprises a voltage / time difference conversion circuit, a data output circuit and a decoding circuit. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0059] Figure 1 A module schematic diagram of the table lookup circuit based on AES in-memory decoding provided by the embodiment of the present application;

[0060] Figure 2 A circuit structure diagram of the table lookup circuit based on AES in-memory decoding provided by the embodiment of the present application;

[0061] Figure 3 A circuit structure diagram of the data output circuit part of the in-memory decoding unit provided by the embodiment of the present application;

[0062] Figure 4 A timing waveform diagram of the table lookup circuit provided by the embodiment of the present application;

[0063] Figure 5 A circuit structure diagram of another table lookup circuit based on AES in-memory decoding provided by the embodiment of the present application;

[0064] Figure 6 A flowchart of a table lookup method based on AES in-memory decoding provided by the embodiment of the present application;

[0065] Figure 7 A flowchart of another table lookup method based on AES in-memory decoding provided by the embodiment of the present application. DETAILED DESCRIPTION

[0066] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0067] With the rapid development of modern communication technology and information technology, information systems have become the infrastructure of human society, supporting various aspects of human life. At the same time, since information is often stored, transmitted and processed in an open communication system, it is vulnerable to security threats such as theft and tampering, and information security problems have become increasingly serious. Encryption of information through cryptographic algorithms can improve information security to some extent. Cryptographic algorithms can be implemented through hardware or software. Software encryption has the advantages of high flexibility and good portability, but the disadvantage is low encryption speed. Since the running environment is open, encrypted information is easy to be stolen. Compared with software encryption, hardware encryption technology has higher physical security and encryption speed, and has a broader application prospect. The Advanced Encryption Standard (AES) circuit has been widely used in many fields. However, implementing the AES algorithm on a low-cost, low-power, resource-constrained hardware platform poses new challenges to circuit design. In related technologies, two schemes are proposed, one is a design scheme based on a combination of substitution boxes (S-boxes), and the other is a look-up table (LUT) lookup table circuit.

[0068] The two schemes proposed in related technologies will be analyzed as follows:

[0069] For a design scheme of a S-box based on combination logic, a byte transformation is involved. The byte transformation is a nonlinear and reversible sub-byte substitution process, which uses each byte of the data substitution state matrix in the S-box. The S-box is used to blur the relationship between the key and the ciphertext, and the combination logic structure of the 8-b input and 8-b output of the byte transformation process is realized by the S-box. For the whole implementation process, each byte of the data matrix is obtained from the organization of eight distributed data structures respectively and input to the S-box, so that the final output result is obtained. However, this structure only realizes a small overhead in the combination logic implementation process of the 8-b input and 8-b output, and because only 1B can be input to the S-box at a time, the process of sub-byte conversion can only be carried out sequentially, which takes a long time. In order to speed up the sub-byte conversion, more S-box combination logic needs to be added to support parallel sub-byte execution. However, when adding this structure, the hardware overhead introduced by multiple S-boxes needs to be considered; in addition, data input and decoding in the S-box need to be completed in two clock cycles, which will cause a long delay.

[0070] For a LUT lookup table circuit, the lookup table circuit can be used for the implementation of the S-box. The LUT circuit with m inputs has a 2 m ×1 storage block, in which the truth table of the m-input Boolean logic function is stored, where m is a positive integer. The storage block in the LUT circuit stores the output corresponding to the input of the Boolean logic function. However, this structure mainly consists of a storage unit, a decoding multiplexer and a peripheral circuit to realize the function of the LUT circuit lookup table. Although the implementation is simple, the time and power consumption of circuit addressing are relatively increased. When the LUT structure is used for the implementation of the S-box in the AES algorithm, the data needs to be read from the peripheral circuit and then decoded, so that the data storage and data use are separated. When the data is input, the reading and decoding need to be completed in two clock cycles, which increases the time of circuit addressing.

[0071] In summary, the current lookup table circuit used for AES is separated from the processor, and this structure improves the computing ability of the computing system, but limits the bandwidth of data transmission, and also causes a long delay and power consumption in the computing process.

[0072] Therefore, the present application proposes a method of in-memory computing (IMC) to solve the above problems, that is, a hardware design of logic is performed in a memory array. IMC can effectively reduce data transmission and realize more energy-efficient information processing. The principle of memory computing is to activate multiple storage units at the same time, detect the current or voltage formed on the bit line by multiple storage units, and perform corresponding logic calculation according to the current or voltage to obtain a logic result; and the corresponding data is obtained by processing the logic result. The structure of in-memory computing reduces data movement, reduces power consumption and time delay.

[0073] Figure 1 A module schematic diagram of a table lookup circuit based on in-memory decoding of AES provided by the embodiment of the present application is shown in Figure 1 The circuit includes a voltage / time difference conversion circuit 1, a data output circuit 2 and a decoding circuit 3. The voltage / time difference conversion circuit 1 is connected with the data output circuit 2, and the data output circuit 2 is connected with the decoding circuit 3.

[0074] The voltage / time difference conversion circuit 1 is used to apply different voltages to the word lines connected with two memory cells to make the two memory cells discharge in turn, form enable signals with different rising times of corresponding voltages according to the resistance states of the two memory cells and the different discharge speeds of the bit lines, and input the enable signals to the data output circuit 2.

[0075] It is worth mentioning that the memory cell in the embodiment of the present application is a non-volatile memory cell.

[0076] The data output circuit 2 is used to make the two in-memory decoding units output logic signals respectively according to the rising time of the enable signal, and input the logic signals to the decoding circuit 3.

[0077] The decoding circuit 3 is used to generate a table lookup address according to the logic signals output by the two in-memory decoding units respectively.

[0078] Figure 2 A circuit structure diagram of a table lookup circuit based on in-memory decoding of AES provided by the embodiment of the present application is shown in Figure 2

[0079] The voltage / time difference conversion circuit 1 includes a discharge control unit 100 and an inverter 200, and the discharge control unit 100 is connected with the inverter 200. The discharge control unit 100 is used to apply different voltages to the word lines connected with two memory cells to make the two memory cells discharge at different speeds, and form discharge voltages corresponding to the resistance states of the two memory cells and the discharge speeds. The inverter 200 is used to output enable signals with corresponding rising times when the discharge voltages reach a preset voltage threshold. The voltage threshold can be set according to actual needs, and the embodiment of the present application does not limit this.

[0080] Figure 3 A circuit structure diagram of a discharge unit and a data output circuit part provided by the embodiment of the present application is shown in Figure 3 ​As shown, the discharge control unit 100 includes two discharge sub-units, each of which includes a first discharge circuit 110, a second discharge circuit 120 and a voltage output circuit 130. The first discharge circuit 110 includes a first power supply end (VDD) 111, a first switching element T1, at least one first storage unit 112 and a second switching element T2. The second discharge circuit 120 includes a second power supply end (VDD) 121, a third switching element T3, at least one second storage unit 122 and a fourth switching element T4. The voltage output circuit 130 includes a fifth switching element T5 and a sixth switching element T6.

[0081] The control end of the first switching element T1 is connected to a bit line P01 inputting a first pre-charge signal, the first end is connected to the first power supply end 111, and the second end is connected to the first end of the second switching element T2. The control end of the second switching element T2 is connected to a word line inputting a first discharge signal, and the second end is connected to the signal input end of the first storage unit 112. The signal output end of the at least one first storage unit 112 is connected to the voltage output circuit 130. The control end of the third switching element T3 is connected to a bit line P11 inputting a second pre-charge signal, the first end is connected to the second power supply end 121, and the second end is connected to the first end of the fourth switching element T4. The control end of the fourth switching element T4 is connected to a word line inputting a second discharge signal, and the second end is connected to the signal input end of the second storage unit 122. The signal output end of the at least one second storage unit 122 is connected to the voltage output circuit 130. The control ends of the fifth switching element T5 and the sixth switching element T6 are connected to a third power supply end 131. The first end of the fifth switching element T5 is connected to the signal output end of the first storage unit 112, and the second end is connected to a voltage output end 132 outputting an enable signal. The first end of the sixth switching element T6 is connected to the signal output end of the second storage unit 122, and the second end is connected to the voltage output end 132 outputting the enable signal.

[0082] The first switching element T1 is turned on in response to the first pre-charge signal to turn on the first end of the second switching element T1 and the first power supply end 111; the second switching element T2 is turned on in response to the first discharge signal to discharge the first storage unit 112 under the action of the first power supply end 111; the third switching element T3 is turned on in response to the second pre-charge signal to turn on the first end of the fourth switching element T4 and the second power supply end 121, and the fourth switching element T4 is turned on in response to the second discharge signal to discharge the second storage unit 122 under the action of the second power supply end 121.

[0083] Specifically, the first switch element T1 turns on in response to the first pre-charge signal and the third switch element T3 turns on in response to the second pre-charge signal, which respectively pre-charge the right side bit lines BLB0 and BLB1 of the first discharge circuit 110 and the second discharge circuit 120 to a high level; different voltages are applied to the two word lines WL0 and WL00 to make the turn-on time of the second switch element T2 and the fourth switch element T4 different, so that the voltage speed flowing through it is different, thereby making the first storage unit 112 and the second storage unit 122 have different discharge speeds under the action of the first power supply end 111 and the second power supply end 121 respectively. Taking the example that a higher voltage is applied to the word line WL0 and a lower voltage is applied to the word line WL00, the first storage unit 112 and the second storage unit 122 are activated to discharge at different times under the action of the first power supply end 111 and the second power supply end 121 respectively. Since the data in the first storage unit 112 and the second storage unit 122 can be 1 or 0, the voltage drop amplitude of the voltage output end 132 is also different under different storage states of the first storage unit 112 and the second storage unit 122.

[0084] As shown in Figure 3 , the first storage unit 112 and the second storage unit 122 are connected in parallel. Since different voltages are applied to the two word lines WL0 and WL00, there are four possible states of the effective resistance formed, that is, the four possible states of two low resistance states in parallel (00), two high resistance states in parallel (11), one low resistance state and one high resistance state in parallel (01), and one high resistance state and one low resistance state in parallel (10). Correspondingly, the voltage output end 132 will appear four possible states.

[0085] It should be noted that the low resistance state and the high resistance state correspond to different logic signals respectively, for example, in the embodiment, the low resistance state corresponds to the logic signal "0" and the high resistance state corresponds to the logic signal "1".

[0086] As shown in Figure 3 , the inverter 200 is connected with the voltage output end 132, and the inverter 200 outputs a low voltage until the discharge voltage output by the voltage output end 132 is greater than the preset voltage threshold of the inverter 200, and the inverter 200 only flips to output a high voltage. Different voltage changes of the discharge voltage output by the voltage output end 132 will cause the output voltage of the inverter 200 to flip at different times, that is, the voltage / time difference conversion circuit 1 converts the amplitude difference of the voltage drop into the sequence of time before and after. Compared with the detection and differentiation of the sensitive amplifier, this structure does not need a reference voltage, so the circuit structure proposed by the present application is more efficient and simple.

[0087] In the preferred embodiment, to ensure the stability of the circuit structure, the seventh switch element T7 is also mirror arranged with the first switch element T1, the control end of the seventh switch element T7 is connected with the bit line P00 inputting the third pre-charge signal, the first end is connected with the first power supply end 111, and the second end is connected with the signal output end of the first storage unit 112.

[0088] In the preferred embodiment, to ensure the stability of the circuit structure, the eighth switch element T8 is also mirror arranged with the third switch element T3, the control end of the eighth switch element T8 is connected with the bit line P10 inputting the fourth pre-charge signal, the first end is connected with the second power supply end 121, and the second end is connected with the signal output end of the second storage unit 122.

[0089] In the preferred embodiment, to ensure the stability of the circuit structure, the ninth switch element T9 is also mirror arranged with the fifth switch element T5, the control end of the ninth switch element T9 is connected with the fourth power supply end 133, the first end is connected with the signal output end of the first storage unit 112, and the second end is connected with the voltage output end 132 outputting the enable signal.

[0090] In the preferred embodiment, to ensure the stability of the circuit structure, the tenth switch element T10 is also mirror arranged with the sixth switch element T6, the control end of the tenth switch element T10 is connected with the fourth power supply end 133, the first end is connected with the signal output end of the second storage unit 122, and the second end is connected with the voltage output end 132 outputting the enable signal.

[0091] In the preferred embodiment, the first discharge circuit 110 is also provided with the eleventh switch element T11, the control end of the eleventh switch element T11 is connected with the first signal line N00, the first end is connected with the signal output end of the first storage unit 112, and the second end is connected with the ground end. The eleventh switch element T11 can be used for circuit reset of the first discharge circuit 110.

[0092] In the preferred embodiment, to ensure the stability of the circuit structure, the twelfth switch element T12 is also mirror arranged with the eleventh switch element T11, the control end of the twelfth switch element T12 is connected with the second signal line N01, the first end is connected with the signal input end of the first storage unit 112, and the second end is connected with the ground end.

[0093] In the preferred embodiment, the second discharge circuit 120 is also provided with the thirteenth switch element T13, the control end of the thirteenth switch element T13 is connected with the third signal line N10, the first end is connected with the signal output end of the second storage unit 122, and the second end is connected with the ground end. The thirteenth switch element T13 can be used for circuit reset of the second discharge circuit 120.

[0094] In a preferred embodiment, to ensure the stability of the circuit structure, a fourteenth switch element T14 is also provided in mirror with the thirteenth switch element T13, the control end of the fourteenth switch element T14 is connected with the fourth signal line N11, the first end is connected with the signal input end of the second storage unit 122, and the second end is connected with the ground end.

[0095] As shown in Figure 2 , the voltage / time difference conversion circuit 1 further comprises a buffer 300, the first end of the buffer 300 is connected with the inverter 200, and the second end is connected with the data output circuit 2. The buffer 300 is used to enhance the enable signal output by the inverter.

[0096] The data output circuit 2 corresponds to a 2-4 storage decoding unit, and the data output circuit 2 comprises a first storage decoding unit 400 and a second storage decoding unit 500, and the data output circuit 2 can convert the enable signals input at different times into different logic signals.

[0097] The first storage decoding unit 400 and the second storage decoding unit 500 comprise a first signal input end, a second signal input end, a third signal input end, a fourth signal input end, a first signal output end, a second signal output end, a third signal output end and a fourth signal output end. As shown in Figure 1 , the input of the first signal input end of the first storage decoding unit 400 and the second storage decoding unit 500 is the enable signal corresponding to the rising time output by the voltage output end 132, the input of the second signal input end is the first pulse signal sig1 corresponding to the first voltage rising time, the input of the third signal input end is the second pulse signal sig2 corresponding to the second voltage rising time, and the input of the fourth signal input end is the third pulse signal sig3 corresponding to the third voltage rising time. The rising time of the enable signal is the first voltage rising time, the second voltage rising time, the third voltage rising time or the fourth voltage rising time which is not the first voltage rising time, not the second voltage rising time and not the third voltage rising time; the first signal output end of the first storage decoding unit 400 outputs the logic signal D0 corresponding to the first voltage rising time, the second signal output end outputs the logic signal D1 corresponding to the second voltage rising time, the third signal output end outputs the logic signal D2 corresponding to the third voltage rising time, and the fourth signal output end outputs the logic signal D3 corresponding to the fourth voltage rising time; the first signal output end of the second storage decoding unit 500 outputs the logic signal E0 corresponding to the first voltage rising time, the second signal output end outputs the logic signal E1 corresponding to the second voltage rising time, the third signal output end outputs the logic signal E2 corresponding to the third voltage rising time, and the fourth signal output end outputs the logic signal E3 corresponding to the fourth voltage rising time.

[0098] The first signal input terminals of the first and second in-memory decoding units 400 and 500 are connected to the voltage output terminals 132 of the two discharge sub-units; the second, third and fourth signal input terminals of the first and second in-memory decoding units 400 and 500 are used to receive the first, second and third pulse signals sig1, sig2 and sig3 corresponding to the first, second and third voltage rise times, respectively.

[0099] The first, second, third and fourth signal output terminals of the first and second in-memory decoding units 400 and 500 are used to output logic signals corresponding to the enable signals with the rise times of the first, second, third or fourth voltage rise times, which are the first, second, third, or fourth voltage rise times, respectively.

[0100] The data output circuit 2 distinguishes the four different enable signals with different rise times by the pulse signals sig1, sig2 and sig3, and converts them into different logic signals for representation. After detecting the input of the voltage / time difference conversion circuit 1 at different times, the data output circuit 2 inputs the obtained logic signals into the decoding circuit 3.

[0101] Figure 4 The timing waveform diagram of the look-up table circuit provided by the embodiment of the present application is shown in FIG. 6, in which the horizontal axis represents time and the vertical axis represents level. Figure 4 The timing waveform diagram of the third pulse signal sig3 corresponding to the third voltage rise time is shown in FIG. 6a. Figure 4 The timing waveform diagram of the second pulse signal sig2 corresponding to the second voltage rise time is shown in FIG. 6b. Figure 4 The timing waveform diagram of the first pulse signal sig1 corresponding to the first voltage rise time is shown in FIG. 6c. Figure 4 The timing waveform diagram of the enable signal with the value of 00 is shown in FIG. 6d. Figure 4 The timing waveform diagram of the enable signal with the value of 01 is shown in FIG. 6e. Figure 4 The timing waveform diagram of the enable signal with the value of 10 is shown in FIG. 6f. Figure 4 The timing waveform diagram of the enable signal with the value of 11 is shown in FIG. 6g. Figure 4 The timing waveform diagram of the data output circuit with the enable signal with the value of 00 is shown in FIG. 6h. Figure 4 The timing waveform diagram of the data output circuit with the enable signal with the value of 01 is shown in FIG. 6i. Figure 4 The timing waveform diagram of the data output circuit with the enable signal with the value of 10 is shown in FIG. 6j. Figure 3The k in the figure represents the timing waveform diagram of each signal output end of the data output circuit when the enable signal is 11. Specifically, the output of different logic signals can be identified by the pulse signals, for example: in the first pulse signal sig1, the inverter flips to generate the enable signal, it is identified that the enable signal is 00, the output D0 is 1, and the outputs D1, D2 and D3 are all 0; in the second pulse signal sig2, the inverter flips to generate the enable signal, it is identified that the enable signal is 01, the output D1 is 1, and the outputs D0, D2 and D3 are all 0; in the third pulse signal sig3, the inverter flips to generate the enable signal, it is identified that the enable signal is 01, the output D2 is 1, and the outputs D0, D1 and D3 are all 0; in the first pulse signal sig1, the second pulse signal sig2 and the third pulse signal sig3, the inverter does not flip, it is identified that the enable signal is 11, the output D3 is 1, and the outputs D0, D1 and D2 are all 0.

[0102] The output results of each signal output end of the data output circuit 2 are shown in Table 1:

[0103] Table 1

[0104]

[0105] Among them, the effective resistance is different resistance state corresponding to the logic signal, for example: the enable signal is 00, the effective resistance R P / / R P represents two high resistance states in parallel, the first output end D0 outputs 1, and the second output end D1, the third output end D2 and the fourth output end D3 all output 0; the enable signal is 01, the effective resistance R P / / R AP represents one high resistance state and one low resistance state in parallel, the second output end D1 outputs 1, and the first output end D0, the third output end D2 and the fourth output end D3 all output 0.

[0106] The data output circuit 2 includes a first in-memory decoding unit 400 and a second in-memory decoding unit 500, the internal structures of the first in-memory decoding unit 400 and the second in-memory decoding unit 500 are the same, and the internal structure of the in-memory decoding unit will be introduced below by taking the first in-memory decoding unit 400 as an example:

[0107] As Figure 5As shown, the data output circuit 2 comprises a first structure, a second structure, a third structure and a fourth structure. The first structure comprises a fifteenth switch element T15, a sixteenth switch element T16, a seventeenth switch element T17, an eighteenth switch element T18 and a nineteenth switch element T19. The control end of the fifteenth switch element T15 is connected with the buffer 300, the first end is connected with the fifth power end, and the second end is connected with the first end of the sixteenth switch element T16; the control end of the sixteenth switch element T16 is connected with the buffer 300, and the second end is connected with the first end of the seventeenth switch element T17; the control end of the seventeenth switch element T17 is connected with the input end of the first pulse signal, and the second end is connected with the ground end; the control end of the eighteenth switch element T18 is connected with the control end of the nineteenth switch element T19, the first end is connected with the fifth power end, and the second end is connected with the first output end; the control end of the nineteenth switch element T19 is connected with the control end of the eighteenth switch element T18, the first end is connected with the first output end, and the second end is connected with the ground end.

[0108] The second structure comprises a twenty-sixth switch element T26, a twenty-seventh switch element T27, a twenty-eighth switch element T28, a twenty-ninth switch element T29, a thirtieth switch element T30, a thirty-first switch element T31 and a thirty-second switch element T32. The control end of the twenty-sixth switch element T26 is connected with the control end of the thirtieth switch element T30, the first end is connected with the buffer 300, and the second end is connected with the first end of the thirtieth switch element T30; the control end of the twenty-seventh switch element T27 is connected with the control end of the twenty-eighth switch element T28, the first end is connected with the sixth power end, and the second end is connected with the first end of the twenty-eighth switch element T28; the second end of the twenty-eighth switch element T28 is connected with the first end of the thirty-first switch element T31; the control end of the twenty-ninth switch element T29 is connected with the control end of the thirty-second switch element T32, the first end is connected with the sixth power end, and the second end is connected with the second output end; the second end of the thirtieth switch element T30 is connected with the ground end; the control end of the thirty-first switch element T31 is connected with the input end of the second pulse signal, and the second end is connected with the ground end; the first end of the thirty-second switch element T32 is connected with the input end of the second pulse signal, and the second end is connected with the ground end.

[0109] The third structure comprises a thirty-third switch element T33, a thirty-fourth switch element T34, a thirty-fifth switch element T35, a thirty-sixth switch element T36, a thirty-seventh switch element T37, a thirty-eighth switch element T38, a thirty-ninth switch element T39, a fortieth switch element T40, and a forty-first switch element T41. The control end of the thirty-third switch element T33 is connected with the control end of the thirty-fifth switch element T35, the first end is connected with the buffer 300, and the second end is connected with the first end of the thirty-fourth switch element T34; the control end of the thirty-fourth switch element T34 is connected with the control end of the thirty-sixth switch element T36, and the second end is connected with the control end of the thirty-eighth switch element T38; the first end of the thirty-fifth switch element T35 is connected with the first end of the thirty-sixth switch element T36, and the second end is connected with the ground end; the second end of the thirty-sixth switch element T36 is connected with the ground end; the control end of the thirty-seventh switch element T37 is connected with the input end of the third pulse signal, the first end is connected with the second end of the thirty-ninth switch element T39, and the second end is connected with the ground end; the first end of the thirty-eighth switch element T38 is connected with the seventh power supply end, and the second end is connected with the first end of the thirty-ninth switch element T39; the control end of the thirty-ninth switch element T39 is connected with the control end of the thirty-eighth switch element T38; the control end of the fortieth switch element T40 is connected with the first end of the thirty-eighth switch element T38, the first end is connected with the seventh power supply end, and the second end is connected with the third output end; the control end of the forty-first switch element T41 is connected with the first end of the thirty-ninth switch element T39, the first end is connected with the third output end, and the second end is connected with the ground end.

[0110] The fourth structure includes the forty-second switching element T42, the forty-third switching element T43, the forty-fourth switching element T44, the forty-fifth switching element T45, the forty-sixth switching element T46, the forty-seventh switching element T47, the forty-eighth switching element T48, and the forty-ninth switching element T49. The control terminal of the forty-second switching element T42 is connected to the buffer 300, its first terminal is connected to the eighth power supply terminal, and its second terminal is connected to the first terminal of the forty-third switching element T43; the control terminal of the forty-third switching element T43 is connected to the first output terminal, and its second terminal is connected to the first terminal of the forty-fourth switching element T44; the control terminal of the forty-fourth switching element T44 is connected to the second output terminal, and its second terminal is connected to the first terminal of the forty-fifth switching element T45; the control terminal of the forty-fifth switching element T45 is connected to the third output terminal, and its second terminal is connected to the fourth output terminal; the control terminal of the forty-sixth switching element T46 is connected to the third output terminal, its first terminal is connected to the fourth output terminal, and its second terminal is connected to the ground terminal; the control terminal of the forty-seventh switching element T47 is connected to the second output terminal, its first terminal is connected to the fourth output terminal, and its second terminal is connected to the ground terminal; the control terminal of the forty-eighth switching element T48 is connected to the first output terminal, its first terminal is connected to the fourth output terminal, and its second terminal is connected to the ground terminal; the control terminal of the forty-ninth switching element T49 is connected to the buffer 300, its first terminal is connected to the fourth output terminal, and its second terminal is connected to the ground terminal.

[0111] Based on the logic signals output by data output circuit 2 at different times, a decoding circuit was designed to perform the decoding operation. In this embodiment of the invention, the decoding circuit consists of 16 AND gates. These 16 AND gates combine the two 4-bit logic signals output by data output circuit 2 pairwise to obtain a 16-bit lookup table address, thereby completing the decoding operation. For example, performing an AND operation between the logic signal D0 output from the first output terminal of the first in-memory decoding unit 400 and the logic signal E0 output from the first output terminal of the second in-memory decoding unit 500 yields a result A0, which can be directly used as part of the S-box lookup address.

[0112] Figure 5 A circuit diagram of another lookup table circuit based on AES in-memory decoding provided in an embodiment of the present invention is shown below. Figure 5 As shown, the lookup table circuit also includes a decoding circuit 3. The decoding circuit 3 is used to perform an AND operation between the logic signals output from the first, second, third, and fourth signal output terminals of the first in-memory decoding unit and the logic signals output from the first, second, third, and fourth signal output terminals of the second in-memory decoding unit to obtain the lookup table address.

[0113] Decoding circuit 3 includes 16 decoding sub-circuits. Figure 5Two decoding sub-circuits are shown for illustration, as shown in Figure 6 The structure of each decoding sub-circuit is the same, and the first decoding sub-circuit 31 is taken as an example. The first decoding sub-circuit 31 comprises a twentieth switch element T20, a twenty-first switch element T21, a twenty-second switch element T22, a twenty-third switch element T23, a twenty-fourth switch element T24, and a twenty-fifth switch element T25. The control end of the twentieth switch element T20 is connected with the data output circuit 2, the first end is connected with the first end of the twenty-fourth switch element T24, and the second end is connected with the control end of the twenty-fifth switch element T25. The control end of the twenty-first switch element T21 is connected with the data output circuit 2, the first end is connected with the control end of the twenty-fifth switch element T25, and the second end is connected with the first end of the twenty-second switch element T22. The control end of the twenty-second switch element T22 is connected with the data output circuit 2, and the second end is connected with the second end of the twenty-fifth switch element T25. The control end of the twenty-third switch element T23 is connected with the data output circuit 2, the first end is connected with the first end of the twenty-fourth switch element T24, and the second end is connected with the control end of the twenty-fifth switch element T25. The control end of the twenty-fourth switch element T24 is connected with the first end of the twenty-first switch element T21, and the second end is connected with the output end of the first decoding sub-circuit 31. The first end of the twenty-fifth switch element T25 is connected with the output end of the first decoding sub-circuit 31.

[0114] The table lookup circuit based on the in-memory decoding of the AES provided by the example of the present application can directly read data in the storage array and be used for the input of the table lookup operation in the S-box. Compared with the S-box circuit realized by the LUT and the S-box circuit realized by the general logic structure, the circuit structure of the table lookup circuit of the present application can effectively reduce the time and power consumption of the table lookup circuit without limiting the bandwidth of data transmission. Table 2 is the performance data of the table lookup circuit provided by the present application.

[0115] Table 2

[0116]

[0117] The example of the present application uses the in-memory decoding circuit, and after reading data from the storage structure, the decoding operation can be directly performed, and the operation process is completed in one clock. In the case of not limiting the bandwidth of data transmission, the time and power consumption of the table lookup circuit can be effectively reduced.

[0118] The application provides a table lookup circuit based on AES in-memory decoding, which comprises a voltage / time difference conversion circuit, a data output circuit and a decoding circuit.

[0119] Based on the same principle, the application further discloses a memory comprising a plurality of memory units and the table lookup circuit based on AES in-memory decoding.

[0120] The following takes the table lookup circuit based on AES in-memory decoding as an example to illustrate the implementation process of the table lookup method based on AES in-memory decoding.

[0121] Figure 6 The table lookup method based on AES in-memory decoding provided by the application has the flow chart as shown in Figure 7 The method comprises the following steps.

[0122] In step 101, different voltages are applied to the word lines connected to the two memory units to make the two memory units discharge in turn.

[0123] In the application, the memory unit comprises a first memory unit and a second memory unit.

[0124] In step 102, the enable signals with different voltage rising times are formed according to the different resistance states of the two memory units and the different discharge speeds of the bit lines.

[0125] In the application, the memory unit comprises a first memory unit and a second memory unit.

[0126] In step 103, the two in-memory decoding units output logic signals respectively according to the rising time of the enable signals.

[0127] In step 104, the table lookup address is generated according to the logic signals output by the two in-memory decoding units respectively.

[0128] In the application, the in-memory decoding unit comprises a first in-memory decoding unit and a second in-memory decoding unit, and the first in-memory decoding unit and the second in-memory decoding unit comprise a first signal output end, a second signal output end, a third signal output end and a fourth signal output end.

[0129] The technical scheme provided by the embodiment of the present application comprises the following steps: different voltages are applied to the word lines connected to the two storage units to make the two storage units discharge in turn; different enable signals with different voltage rising time are formed according to the resistance states of the two storage units and the discharging speed of the bit line; the two storage decode units output logic signals respectively according to the rising time of the enable signals; and a lookup table address is generated according to the logic signals output by the two storage decode units, so that the time and power consumption of the lookup table circuit can be effectively reduced without limiting the bandwidth of data transmission.

[0130] Figure 7 The flow chart of another lookup table method based on the AES storage decode provided by the embodiment of the present application is shown in FIG. 4, which comprises the following steps: ​

[0131] In step 201, the first switch element is controlled to be turned on in response to the first pre-charge signal to make the first end of the second switch element conductive with the first power supply end, and the second switch element is controlled to be turned on in response to the first discharging signal to make the first storage unit discharge under the action of the first power supply end.

[0132] In step 202, the third switch element is controlled to be turned on in response to the second pre-charge signal to make the first end of the fourth switch element conductive with the second power supply end, and the fourth switch element is controlled to be turned on in response to the second discharging signal to make the second storage unit discharge under the action of the second power supply end.

[0133] Specifically, the first switch element is turned on in response to the first pre-charge signal and the third switch element is turned on in response to the second pre-charge signal to pre-charge the right bit lines BLB0 and BLB1 of the first discharging circuit and the second discharging circuit to high level respectively; different voltages are applied to the two word lines WL0 and WL00 to make the turn-on time of the second switch element and the fourth switch element different, and the voltage speed flowing through it different, so that the first storage unit and the second storage unit have different discharging speeds under the action of the first power supply end and the second power supply end respectively. Taking the example that a higher voltage is applied to the word line WL0 and a lower voltage is applied to the word line WL00, the first storage unit and the second storage unit are activated to discharge at different times under the action of the first power supply end and the second power supply end respectively. Since the data in the first storage unit and the second storage unit can be 1 or 0, the voltage drop amplitude of the discharging voltage of the voltage output end is also different under the different storage states of the first storage unit and the second storage unit. The first storage unit and the second storage unit are connected in parallel. Since different voltages are applied to the two word lines WL0 and WL00, there are four possible states of the effective resistance, i.e. two low resistance states in parallel (00), two high resistance states in parallel (11), one low resistance state and one high resistance state in parallel (01) and one high resistance state and one low resistance state in parallel (10).

[0134] ​Step 203, when the discharge voltage reaches the preset voltage threshold, the inverter is controlled to flip and output an enable signal corresponding to the rising time.

[0135] In the embodiment of the present application, the voltage threshold can be set according to actual needs, and the embodiment of the present application does not limit this.

[0136] Specifically, the inverter is connected with the voltage output end, and the inverter output is low voltage until the discharge voltage output by the voltage output end is greater than the preset voltage threshold of the inverter, and the inverter only flips to output high voltage. Different voltage changes of the discharge voltage output by the voltage output end will cause the output voltage of the inverter to flip at different times, that is, the voltage / time difference conversion circuit converts the amplitude difference of the voltage drop to the front and rear order of time.

[0137] Step 204, the first signal input end, the third signal input end and the fourth signal input end of the first and second in-memory decoding units respectively receive a first pulse signal corresponding to the first voltage rising time, a second pulse signal corresponding to the second voltage rising time and a third pulse signal corresponding to the third voltage rising time.

[0138] Step 205, the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first and second in-memory decoding units output a logic signal corresponding to the enable signal, and the rising time of the enable signal is the first voltage rising time, the second voltage rising time, the third voltage rising time or the fourth voltage rising time which is not the first voltage rising time, not the second voltage rising time and not the third voltage rising time.

[0139] Step 206, the logic signals output by each of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first in-memory decoding unit are respectively ANDed with the logic signals output by the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the second in-memory decoding unit, to obtain a lookup table address.

[0140] Specifically, the decoding circuit is composed of 16 AND gates, and the 16 AND gates obtain a 16-bit lookup table address by combining the logic signals output by the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first and second in-memory decoding units two by two, to complete the decoding operation.

[0141] In the scheme of the embodiment of the present application, different voltages are applied to the word lines connected to the two storage units to make the two storage units discharge in turn; the enable signals with different voltage rising time are formed according to the different resistance states of the two storage units and the different discharging speeds of the bit lines; the two storage decode units output logic signals respectively according to the rising time of the enable signals; and the address for table lookup is generated according to the logic signals output by the two storage decode units, so that the time and power consumption of the table lookup circuit can be effectively reduced without limiting the bandwidth of data transmission.

[0142] Since the principle of solving the problem of the method is similar to the above table lookup circuit, the implementation of the method can be referred to the implementation of the table lookup circuit, which will not be described here.

[0143] Each of the embodiments in the specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other. Each embodiment mainly describes the difference from other embodiments. Especially, since the system embodiment is basically similar to the method embodiment, the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0144] The above only describes the embodiments of the present application and is not used to limit the present application. The present application can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. An AES table lookup circuit based on in-memory decoding, characterized by, The circuit comprises a voltage / time difference conversion circuit, a data output circuit and a decoding circuit; The voltage / time difference conversion circuit is configured to apply different voltages to word lines connected to two storage units to make the two storage units discharge in sequence, and form an enable signal with different rising times of corresponding voltages according to different resistance states of the two storage units and different discharging speeds of bit lines; The data output circuit is configured to make the two storage decoding units output logic signals respectively according to the rising times of the enable signal; The decoding circuit is configured to generate a lookup table address according to the logic signals output by the two storage decoding units respectively; The voltage / time difference conversion circuit comprises a discharging control unit and an inverter; The discharging control unit is configured to apply different voltages to word lines connected to two storage units to make the two storage units discharge at different discharging speeds, and form a discharging voltage corresponding to the resistance states of the two storage units and the discharging speeds; The inverter is configured to output an enable signal with a corresponding rising time when the discharging voltage reaches a preset voltage threshold; The discharging control unit comprises two discharging units; Each discharging unit comprises a first discharging circuit, a second discharging circuit and a voltage output circuit; The first discharging circuit comprises a first power supply end, a first switching element, at least one first storage unit and a second switching element; The second discharging circuit comprises a second power supply end, a third switching element, at least one second storage unit and a fourth switching element; The voltage output circuit comprises a fifth switching element and a sixth switching element; The control ends of the first switching element and the third switching element are respectively connected to a bit line inputting a first pre-charge signal and a bit line inputting a second pre-charge signal, the first ends are respectively connected to the first power supply end and the second power supply end, and the second ends are respectively connected to the first end of the second switching element and the first end of the fourth switching element; The control ends of the second switching element and the fourth switching element are respectively connected to a word line inputting a first discharging signal and a word line inputting a second discharging signal, and the second ends are respectively connected to a signal input end of the first storage unit and a signal input end of the second storage unit; The signal output end of the at least one first storage unit is connected to the voltage output circuit; The signal output end of the at least one second storage unit is connected to the voltage output circuit; The control ends of the fifth switching element and the sixth switching element are connected to a third power supply end; The first ends of the fifth switching element and the sixth switching element are respectively connected to the signal output end of the first storage unit and the signal output end of the second storage unit, and the second ends are both connected to a voltage output end outputting an enable signal; The first switching element is turned on in response to the first pre-charge signal to make the first end of the second switching element conductive with the first power supply end, and the second switching element is turned on in response to the first discharging signal to make the first storage unit discharge under the action of the first power supply end; The third switch element is turned on in response to the second pre-charge signal to connect the first end of the fourth switch element to the second power supply end, and the fourth switch element is turned on in response to the second discharge signal to discharge the second storage unit under the action of the second power supply end.

2. The AES table lookup circuit based on- memory decoding according to claim 1, wherein, The voltage / time difference conversion circuit further comprises a buffer; The first end of the buffer is connected to the inverter, and the second end is connected to the data output circuit; The buffer is used to enhance the enable signal output by the inverter.

3. The table lookup circuit based on AES-IC based on claim 1, characterized in that, The data output circuit comprises a first in-memory decoding unit and a second in-memory decoding unit; The first in-memory decoding unit and the second in-memory decoding unit comprise first, second, third and fourth signal input ends and first, second, third and fourth signal output ends; The first signal input ends of the first in-memory decoding unit and the second in-memory decoding unit are respectively connected to the voltage output ends of the two discharge sub-units; The second, third and fourth signal input ends of the first in-memory decoding unit and the second in-memory decoding unit are respectively used to receive a first pulse signal corresponding to a first voltage rise time, a second pulse signal corresponding to a second voltage rise time and a third pulse signal corresponding to a third voltage rise time; The first, second, third and fourth signal output ends of the first in-memory decoding unit and the second in-memory decoding unit are used to output a logic signal corresponding to the rise time of the enable signal, and the rise time of the enable signal is the first voltage rise time, the second voltage rise time, the third voltage rise time or a fourth voltage rise time which is not the first voltage rise time, not the second voltage rise time and not the third voltage rise time.

4. The AES in-memory decoding based lookup table circuit according to claim 3, characterized in that, The decoding circuit is used to perform an AND operation on the logic signals output by each of the first, second, third and fourth signal output ends of the first in-memory decoding unit and the logic signals output by the first, second, third and fourth signal output ends of the second in-memory decoding unit, to obtain a lookup table address.

5. A memory, comprising: The AES in-memory decoding based lookup table circuit according to any one of claims 1-4.

6. A table lookup method of the table lookup circuit as claimed in claim 1, characterized by, The method comprises: Applying different voltages to the word lines connected to the two storage units to discharge the two storage units in turn; According to the different resistance states of the two storage units and the different discharge speeds of the bit lines, enable signals with different voltage rise times are formed; According to the rise time of the enable signal, the two in-memory decoding units output logic signals respectively; According to the logic signals output by the two in-memory decoding units respectively, a lookup table address is generated.

7. The AES table lookup method based on in-memory decoding according to claim 6, wherein, The storage unit comprises a first storage unit and a second storage unit; Before the two storage units are discharged in turn according to that different voltages are applied to the word lines connected with the two storage units, further comprising: controlling the first switch element to be turned on in response to the first pre-charging signal to make the first end of the second switch element connected with the first power supply end, and the second switch element is turned on in response to the first discharging signal to make the first storage unit discharge under the action of the first power supply end; controlling the third switch element to be turned on in response to the second pre-charging signal to make the first end of the fourth switch element connected with the second power supply end, and the fourth switch element is turned on in response to the second discharging signal to make the second storage unit discharge under the action of the second power supply end.

8. The AES table lookup method based on in-memory decoding according to claim 6, wherein, The enable signal with different rising time corresponding to the resistance state of the two storage units and the discharging speed of the bit line is formed according to that different voltages are applied to the word lines connected with the two storage units, comprising: different voltages are applied to the word lines connected with the two storage units to make the two storage units discharge at different discharging speeds, forming discharging voltages corresponding to the resistance state of the two storage units and the discharging speed; when the discharging voltage reaches the preset voltage threshold, the enable signal with corresponding rising time is output.

9. The AES table lookup method based on in-memory decoding of claim 6, wherein, The in-memory decoding unit comprises a first in-memory decoding unit and a second in-memory decoding unit; According to the rising time of the enable signal, the two in-memory decoding units output logic signals respectively, comprising: the first in-memory decoding unit and the second in-memory decoding unit receive the first pulse signal corresponding to the first voltage rising time, the second pulse signal corresponding to the second voltage rising time and the third pulse signal corresponding to the third voltage rising time through the second signal input end, the third signal input end and the fourth signal input end of the first in-memory decoding unit and the second in-memory decoding unit respectively; the first in-memory decoding unit and the second in-memory decoding unit output the logic signal corresponding to the enable signal through the first signal output end, the second signal output end, the third signal output end and the fourth signal output end, and the rising time of the enable signal is the first voltage rising time, the second voltage rising time, the third voltage rising time or the fourth voltage rising time which is not the first voltage rising time, not the second voltage rising time and not the third voltage rising time.

10. The AES table lookup method based on in-memory decoding of claim 6, wherein, The in-memory decoding unit comprises a first in-memory decoding unit and a second in-memory decoding unit, and the first in-memory decoding unit and the second in-memory decoding unit comprise a first signal output end, a second signal output end, a third signal output end and a fourth signal output end; According to the logic signals output by the two in-memory decoding units respectively, a lookup table address is generated, comprising: the logic signals output by each of the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the first in-memory decoding unit are respectively ANDed with the logic signals output by the first signal output end, the second signal output end, the third signal output end and the fourth signal output end of the second in-memory decoding unit to obtain the lookup table address.

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