Compression method for defect visibility in memory devices
By comparing column planes in the memory device to identify errors and compressing test data to generate error markers and location indicators, the problem of information loss caused by the large amount of test data in large-scale memory arrays is solved, and the effectiveness and optimization capability of test operations are improved.
CN113921078BActive Publication Date: 2026-07-07MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2021-07-05
- Publication Date
- 2026-07-07
Smart Images
Figure CN113921078B_ABST
Abstract
This disclosure relates to a compression method of defect visibility in a memory device. A memory device can identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with a first set of memory cells. The memory device can generate an indication of a location of the one or more errors in the first set of memory cells based on identifying the one or more errors and compress the first set of data to generate an error marker. The memory device can output the error marker and the indication based on generating the error marker and the indication of the location.
Need to check novelty before this filing date? Find Prior Art