Semiconductor package including semiconductor chip and dummy pads

Abstract

A semiconductor package includes semiconductor chips on a package substrate, and dummy pads disposed between and overlapping at least a portion of the semiconductor chips. The dummy pads are disposed on the package substrate and in a space between the package substrate and the semiconductor chips.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0084940, filed on July 9, 2020, with the Korean Intellectual Property Office, the subject of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to semiconductor packaging, and more specifically, to a semiconductor package known as a system-in-package (SiP), wherein a single semiconductor package comprises different types of semiconductor chips. Background Technology

[0004] The demand for portable devices continues to grow in the electronics market. As a result, miniaturization and weight reduction of components within electronic products have become significant design drivers. Various methods exist to achieve this miniaturization and weight reduction. For example, semiconductor packages mounted within electronic components can provide high-capacity data processing while reducing the overall size of the semiconductor package. Semiconductor chips mounted within semiconductor packages can be densely or highly integrated within a single package. In this way, various SiP (System-in-Package) technologies can be applied to efficiently arrange (or layout) multiple semiconductor chips within a semiconductor package. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor package including dummy pads that can prevent cracking in the molded component, thereby effectively protecting different types of semiconductor chips facing each other within the limited structure provided by the semiconductor package. However, embodiments of the present invention may provide other benefits and technical objectives, which will become apparent to those skilled in the art upon consideration of the following description.

[0006] According to one aspect of the present invention, a semiconductor package is provided, comprising: a package substrate; a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip on the package substrate; and a dummy pad laterally disposed between the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip to overlap at least a portion of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the dummy pad is disposed on the package substrate and in the space between the package substrate and the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.

[0007] According to one aspect of the present invention, a semiconductor package is provided, comprising: a redistribution structure; at least three semiconductor chips on the redistribution structure; a dummy pad between the redistribution structure and the at least three semiconductor chips; and a molding member filling the space between the at least three semiconductor chips such that the dummy pad overlaps with at least a portion of each of the at least three semiconductor chips, and the molding member covers at least a portion of the top surface of the dummy pad.

[0008] According to one aspect of the present invention, a semiconductor package is provided, comprising: an insert; a semiconductor chip including a memory chip, a logic chip, and a dummy chip disposed adjacent to the insert; a dummy pad disposed on the insert and between the insert and the semiconductor chip, wherein the dummy pad comprises a metallic material; a molding member covering a bottom surface and a side surface of the semiconductor chip, wherein the molding member covers a top surface and a side surface of the dummy pad; and solder bumps adhered to the bottom surface of the insert, wherein the dummy pads overlap at least a portion of each of the semiconductor chips. Attached Figure Description

[0009] The embodiments of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a plan (or top view) of a semiconductor package according to an embodiment of the present invention.

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken by line X-X';

[0012] Figure 3 , Figure 4 and Figure 5 yes Figure 1 The corresponding enlarged cross-sectional view of part III;

[0013] Figure 6 , Figure 7 and Figure 8 This is a corresponding plan view of a semiconductor package according to an embodiment of the present invention;

[0014] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 (collectively referred to as " Figures 9 to 14 ") is an embodiment of the concept of the present invention. Figure 1 The corresponding cross-sectional view intercepted by line XX′; and

[0015] Figure 15This is a block diagram illustrating a semiconductor package according to an embodiment of the concept of the present invention. Detailed Implementation

[0016] Throughout the written description and accompanying drawings, similar reference numerals and labels are used to denote similar or related elements and / or features. Throughout the written description, certain geometric terms may be used to emphasize the relative relationships between elements, components, and / or features of particular embodiments of the inventive concept. Those skilled in the art will recognize that such geometric terms are inherently relative, arbitrary in describing relationships, and / or relate to aspects of the illustrated embodiments. Geometric terms may include, for example, height / width; vertical / horizontal; top / bottom; higher / lower; closer / farther; thicker / thinner; near / far; above / below; below / above; upper / lower; center / side; around; between; cover / padded, etc.

[0017] Figure 1 This is a plan (or top view) view of a semiconductor package 10 according to an embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view taken by line X-X'; and Figure 3 , Figure 4 and Figure 5 yes Figure 1 The corresponding enlarged cross-sectional view of part III.

[0018] like Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown in at least one of the embodiments, the semiconductor package 10 may include at least a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300 disposed on the package substrate 400, relative to the molding member 500. A dummy pad DP is also disposed on the package substrate 400.

[0019] Therefore, the semiconductor package 10 can be understood as a structure in which multiple semiconductor chips are disposed (e.g., mounted) on a package substrate 400. In this respect, Figure 1An example of seven (7) semiconductor chips mounted on a packaging substrate 400 is shown. However, this is merely an example of an arbitrary choice, and the scope of the inventive concept is not limited thereto. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be arranged (or laid out) in a horizontal (or lateral) plane defined by a first direction (e.g., the X direction) and a second direction (e.g., the Y direction), wherein the first and second directions are oriented perpendicularly to each other. Furthermore, in this respect, the packaging substrate 400 may also be oriented according to a horizontal plane, and the various semiconductor chips may be vertically disposed (e.g., mounted) on the top surface of the packaging substrate 400 in a third direction (e.g., the Z direction).

[0020] Here, similar types of semiconductor chips can be described as chipsets. Therefore, in Figure 1 In the example shown, the first semiconductor chip 100, the second semiconductor chip 200 and the third semiconductor chip 300 can be the same type of semiconductor chip, can be two (2) different types of semiconductor chips, or can be three (3) different types of semiconductor chips.

[0021] For example, the first semiconductor chip 100 and the second semiconductor chip 200 can be active chips, and the third semiconductor chip 300 can be a dummy chip. More specifically, the first semiconductor chip 100 can be a logic chip, and the second semiconductor chip 200 can be a memory chip. However, the types of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 can vary depending on the design.

[0022] Here, a specific memory chip can be a volatile memory chip or a non-volatile memory chip. In some embodiments, the memory chip can be a high-bandwidth memory chip.

[0023] In this regard, the term volatile memory chip refers to one or more memory chips selected from the group consisting of at least one of the following: Dynamic Random Access Memory (DRAM), Static RAM (SRAM), Thyristor RAM (TRAM), Zero-Capacitor RAM (ZRAM), and Dual Transistor RAM (TTRAM). The term non-volatile memory chip refers to one or more memory chips selected from the group consisting of at least one of the following: Flash memory, Magnetic RAM (MRAM), Spin-Torque MRAM (STT-MRAM), Ferroelectric RAM (FRAM), Phase-Change RAM (PRAM), Resistive RAM (PRAM), Nanotube RRAM, Polymer RAM, Nanoscale Floating Gate Memory, Holographic Memory, Molecular Electronic Memory, and Insulator Resistance Variation Memory.

[0024] Logic chips can be implemented as, for example, microprocessors, graphics processors, signal processors, network processors, chipsets, audio codecs, video codecs, application processors, and system-on-a-chip (SoC). Here, a microprocessor can include single-core or multi-core processors.

[0025] A dummy chip may be disposed in an empty region of the package substrate 400 (i.e., a region of the package substrate 400 not occupied by an active chip). In some embodiments, the dummy chip may have a shape for suppressing warpage of the semiconductor package 10, and / or be formed of one or more suitable materials to suppress warpage of the semiconductor package 10. For example, the dummy chip may include a material with a relatively low Young's modulus (e.g., a material with a Young's modulus lower than that of the molding member 500). In some embodiments, when the package substrate 400 may be a semiconductor substrate such as a silicon wafer, the dummy chip may include the same material (or a similar material) as the material of the package substrate 400.

[0026] exist Figure 2 In the illustrated example, the first semiconductor chip 100 includes a first chip substrate 110, a first connection pad 120, and a first connection member 130. Here, the first semiconductor substrate 110 may have an active surface and a corresponding passive surface. The active surface of the first semiconductor substrate 110 may be the surface facing the top surface of the package substrate 400. Various active and / or passive components may be formed on the active surface of the first semiconductor substrate 110. One or more of these various components may be electrically connected to the first connection pad 120.

[0027] The first connection member 130 may be formed between the active surface of the first semiconductor substrate 110 and the package substrate 400. In some embodiments, the first connection member 130 may directly contact the first connection pad 120. The first semiconductor chip 100 may be electrically connected to the package substrate 400 through the first connection member 130.

[0028] The first semiconductor substrate 110 may include, for example, silicon (Si). Alternatively, the first semiconductor substrate 110 may include semiconductor elements such as germanium (Ge) or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the first semiconductor substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 110 may include a buried oxide (BOX) layer. The first semiconductor substrate 110 may include active regions, such as doped wells or doped structures. The first semiconductor substrate 110 may include various device isolation structures, such as shallow trench isolation (STI) structures.

[0029] A semiconductor device layer (not shown) may be formed on the active surface of the first semiconductor substrate 110. The semiconductor device layer may include various semiconductor wiring layers configured to connect various elements associated with the first semiconductor substrate 110. The semiconductor wiring layers may include metal wiring layers and / or vias (e.g., contacts, plugs, etc.). In some embodiments, the semiconductor wiring layer may be a multilayer structure including at least two metal wiring layers or at least two via plugs that may be alternately stacked.

[0030] The first connection pad 120 may be disposed on the semiconductor device layer and electrically connected to the semiconductor wiring layer. In this respect, the semiconductor wiring layer may be electrically connected to the first connection member 130 via the first connection pad 120. Here, the first connection pad 120 may include at least one of the following: aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0031] A passivation layer (not shown) may be formed on the semiconductor device layer to protect the semiconductor device layer, semiconductor wiring layer, and / or other structures from external mechanical shock, moisture, and contamination. When configured, the passivation layer 130 may selectively expose at least a portion of the first connection pad 120.

[0032] The first connection member 130 may be adhered to the first connection pad 120. The first connection member 130 may be used to electrically connect the first semiconductor chip 100 to the package substrate 400. That is, the first connection member 130 provides an electrical connection through which the first semiconductor chip 100 receives at least one externally provided signal (e.g., ground signal, power signal, command signal, address signal, data signal, etc.) associated with the execution of an operation of the first semiconductor chip 100 (e.g., read operation, programming (or write) operation, erase operation, etc.). The first connection member 130 may include at least one of, for example, a columnar structure, solder bumps, solder balls, and solder layers.

[0033] The second semiconductor chip 200 may include a second semiconductor substrate 210, a second connection pad 220, and a second connection member 230. Similar to the first semiconductor chip 100, the second semiconductor chip 200 may include a second semiconductor substrate 210 having an active surface and an opposing passive surface, wherein the active surface is the surface facing the top surface of the package substrate 400. Similarly, various active and / or passive components, as well as the second connection pad 220, may be formed on the second semiconductor substrate 210.

[0034] The second connection member 230 may be formed between the active surface of the second connection pad 220 and the package substrate 400. In some embodiments, the second connection member 230 may directly contact the second connection pad 220. The second semiconductor chip 200 may be electrically connected to the package substrate 400 through the second connection member 230.

[0035] The third semiconductor chip 300 may include a third semiconductor substrate and an adhesive film (not shown). The third semiconductor chip 300 may include a third semiconductor substrate having a top surface and a bottom surface opposite the top surface. The bottom surface of the third semiconductor substrate may be the surface facing the top surface of the package substrate 400. Because the third semiconductor chip 300 is a dummy chip, unlike the first semiconductor chip 100 and the second semiconductor chip 200, active components, passive components, or third connection pads are typically not formed on the third semiconductor substrate.

[0036] An adhesive film may be formed between the bottom surface of the third semiconductor chip 300 and the top surface of the packaging substrate 400. In some embodiments, the adhesive film may be a non-conductive film (NCF), and the third semiconductor chip 300 may be adhered to the packaging substrate 400 via the adhesive film. However, the inventive concept is not limited thereto, and the third semiconductor chip 300 may also be attached to the packaging substrate 400 in different ways (e.g., using a method substantially the same as that used for mounting the first semiconductor chip 100 and / or the second semiconductor chip 200).

[0037] In similar Figure 1 In some embodiments of the illustrated examples, the second semiconductor chip 200 and the third semiconductor chip 300 may be arranged laterally along one side of the first semiconductor chip 100. That is, the second semiconductor chip 200 and the third semiconductor chip 300 may be arranged in parallel along one side of the first semiconductor chip 100 (relative to the X or Y direction). In some embodiments, the third semiconductor chip may be arranged between two (2) second semiconductor chips 200. However, those skilled in the art will recognize that multiple semiconductor chips may be arranged differently relative to the first semiconductor chip 100.

[0038] exist Figure 2 In the example shown, the package substrate 400 (i.e., the support substrate) includes a body unit 410, a lower protective layer, and an upper protective layer. The package substrate 400 can be a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, an insert, etc.

[0039] The package substrate 400 may further include wiring 440 (e.g., one or more signal transmission paths) that is electrically connected to at least one of the first semiconductor chip 100 and the second semiconductor chip 200 via an upper electrode pad 420 formed in the top surface of the package substrate 400 through at least one of the first connection member 130 and the second connection member 230. Additionally, external connection terminals 450 may be disposed on a lower electrode pad 430 formed in the bottom surface of the package substrate 400, such that the package substrate 400 can be electrically connected to (and mounted on) a module substrate or system board of an electronic product.

[0040] Wiring 440 can have a multi-layer structure or a single-layer structure, and can be formed in the main body unit 410. Using the aforementioned configuration, external connection terminal 450 can be electrically connected to at least one of the first semiconductor chip 100 and the second semiconductor chip 200 via wiring 440.

[0041] In some embodiments, the packaging substrate 400 is an insert, and the packaging substrate 400 may include a body unit 410 and wiring 440 formed in the body unit 410. The body unit 410 may include a silicon wafer, which includes silicon (Si), such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

[0042] In this respect, the insert may also include a circuit region. For example, a buffer circuit capable of controlling the capacitive loading of the first semiconductor chip 100 and / or the second semiconductor chip 200 may be formed in the circuit region. In some embodiments, a semiconductor integrated circuit (IC) including at least one selected from transistors, diodes, capacitors, and resistors may be formed in the circuit region. However, in other embodiments, the circuit region may be omitted.

[0043] In some embodiments, the encapsulation substrate 400 may include a PCB. In such embodiments, forming the body unit 410 may at least include (1) forming a film by compressing a polymeric material (e.g., a thermosetting resin), an epoxy resin (e.g., flame retardant 4 (FR-4), bismaleimide triazine (BT), and Ajinomoto deposited film (ARF)), or a phenolic resin to a constant thickness, (2) coating both sides of the film with copper foil (or some other conductive material), and (3) performing a patterning process to form wiring 440. Except for the portions connected to terminals (e.g., upper electrode pad 420 and lower electrode pad 430), the entire top surface and / or the entire bottom surface of the body unit 410 may be coated with solder resist to form an upper protective layer and a lower protective layer.

[0044] In this regard, the aforementioned PCB can be a single-sided PCB in which wiring 440 is formed on only one surface, or a double-sided PCB in which wiring 440 is formed on two surfaces. In some embodiments, a PCB with a multilayer structure can be implemented using at least three copper foil layers, said at least three copper foil layers being formed using an insulator such as prepreg. Then, at least three wirings 440 can be formed depending on the number of copper foil layers formed. However, the package substrate 400 is not limited to the above-described structure or material of the PCB.

[0045] The molding member 500 may be formed to at least substantially surround the side surfaces, bottom surface, and top surface of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. However, at least some portion of the top surface of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be exposed through the molding member 500.

[0046] In some embodiments, the molded component 500 may include an epoxy molding compound. The epoxy molding compound may have a modulus between about 15 GPa and about 30 GPa, and a coefficient of thermal expansion (CTE) between about 3 ppm and about 30 ppm. Alternatively or additionally, the molded component 500 may include various materials, such as epoxy-based materials, thermosetting materials, thermoplastic materials, and ultraviolet (UV)-treated materials. Thermosetting materials may include phenolic, anhydride, and amine curing agents, as well as acrylic polymer additives.

[0047] Furthermore, a molded underfill (MUF) process can be used to form the molded component 500. Therefore, the material covering the exterior of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 can be the same material used to fill the spaces between the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and / or the packaging substrate 400.

[0048] In some embodiments, the first connecting member 130 and the second connecting member 230 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 200 and the packaging substrate 400, respectively. An adhesive film (not shown) may be disposed between the third semiconductor chip 300 and the packaging substrate 400. In some embodiments, the first connecting member 130, the second connecting member 230, and the adhesive film (not shown) may be surrounded by a molding member 500.

[0049] To form the molded component 500, a molding material can be injected onto the packaging substrate 400 using an injection process, and then the molding material can be cured using a curing process. Thus, the molded component 500 can form the shape of the semiconductor package 10. When needed, the shape of the semiconductor package 10 can be formed by applying pressure to the molding material using a pressurizing process (e.g., using pressure). Here, the physical properties of the molding material (e.g., viscosity) can be considered when setting the process conditions, such as the delay time between injection and pressurization of the molding material, the amount of molding material injected, and the pressurization temperature / pressure conditions.

[0050] The side and top surfaces of the molding member 500 may form right angles (e.g., approximately 90°). In the process of forming a separate semiconductor package 10 by cutting the package substrate 400 along a dicing line, the side and top surfaces of the molding member 500 may typically have right angles. Although not shown, marking patterns (e.g., barcodes, numbers, letters, and symbols) including information related to the semiconductor package 10 may be formed on a portion of the side surface of the semiconductor package 10.

[0051] With the aforementioned configuration, the molding member 500 can protect the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 from external impacts, vibrations, moisture, and contamination. Therefore, the molding member 500 can have a thickness sufficient to at least surround the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. Because the molding member 500 completely covers the packaging substrate 400, the width of the molding member 500 can be substantially equal to the width of the semiconductor package 10.

[0052] exist Figure 1 and Figure 2 In the example shown, the dummy pad DP is disposed on the package substrate 400 to at least partially overlap with the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. Figure 3 As shown in some additional details, the dummy pad DP may overlap with a portion of each of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. To meet this requirement, the lateral width (DP_X) of the dummy pad DP in the first direction must be greater than the lateral distance (SX) between the first semiconductor chip 100 and any one of the second semiconductor chip 200 and the third semiconductor chip 300. Furthermore, the longitudinal width (DP_Y) of the dummy pad DP in the second direction must be greater than the longitudinal distance (SY) between the second semiconductor chip 200 and the third semiconductor chip 300.

[0053] It should be noted that if both the lateral width (DP_X) and vertical width (DP_Y) of the dummy pad DP are too small, cracks may form. (See, for example, Figure 2 (Component CR). However, if the dummy pad PD is too large, it may adversely affect the overall layout of the semiconductor chip.

[0054] Therefore, in some embodiments, the lateral width (DP_X) of the dummy pad DP can be in the range of about 120% to about 300% of the lateral distance (SX) between the first semiconductor chip 100 and any one of the second semiconductor chip 200 and the third semiconductor chip 300. Additionally or alternatively, the longitudinal width (DP_Y) of the dummy pad DP can be in the range of about 120% to about 300% of the longitudinal distance (SY) between the second semiconductor chip 200 and the third semiconductor chip 300. In some specific embodiments, the foregoing results in the dummy pad DP having a lateral width (DP_X) and a longitudinal width (DP_Y) in the range of about 50 μm to about 90 μm.

[0055] In some embodiments, the top surface of the dummy pad DP may overlap with one side edge of the first semiconductor chip 100 and the side edges of both the second semiconductor chip 200 and the third semiconductor chip 300. Therefore, the entire top surface of the dummy pad DP may be covered by the molding member 500, and the molding member 500 may extend in a T-shape from the top surface of the dummy pad DP. (See, for example, [link to relevant documentation]). Figure 2 ).

[0056] The dummy pad DP can include at least one of the following metallic materials: for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). However, the dummy pad DP can be electrically isolated (i.e., not electrically connected) from any other active component or signal path of the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, or the package substrate 400.

[0057] Therefore, the exposed portion of the dummy pad DP can be surrounded by one or more insulating materials. That is, the top and side surfaces of the dummy pad DP can be surrounded (or encapsulated) by the molding member 500, while the bottom surface of the dummy pad DP adheres to (or contacts) the insulating member 460 disposed on the upper surface of the package substrate 400. Here, the insulating member 460 can be formed of one or more electrically insulating materials (e.g., silicon oxide or silicon nitride).

[0058] like Figure 2As shown, the dummy pad DP can be laterally disposed in the space between the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 (e.g., in the X / Y plane). The dummy pad DP can also be disposed in the vertical space (e.g., a vertical gap extending along the Z direction) between the package substrate 400 and each of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. Therefore, the thickness (DP_T) of the dummy pad DP can be less than the separation distance between the first connecting member 130 and the second connecting member 230. Therefore, the top surface of the dummy pad DP can be at a level lower than the top surface of either the first connecting member 130 or the second connecting member 230. In some specific embodiments, the foregoing can result in the thickness DP_T of the dummy pad DP being in the range of about 3 μm to about 30 μm.

[0059] like Figure 3 As shown, the dummy pad DP can have a flat shape. Alternatively, such as Figure 4 As shown, the dummy pad (DP_S) can have a strip shape. Alternatively, such as Figure 5 As shown, the dummy pad (DP_M) can have a matrix shape. That is, the dummy pad DP can be shaped differently to meet design requirements and priorities. However, as mentioned above, regardless of the overall shape, the dummy pad DP will overlap with at least a portion of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 (i.e., having a lateral width (DP_X) greater than the distance (SX) between the first semiconductor chip 100 and any one of the second semiconductor chip 200 and the third semiconductor chip 300, and a longitudinal width (DP_Y) greater than the distance (SY) between the second semiconductor chip 200 and the third semiconductor chip 300).

[0060] As mentioned above, various SiP methods have been applied to efficiently arrange semiconductor chips within the limited available structures provided by semiconductor packages (e.g., Figure 1In semiconductor packages (10), however, typical SiP methods result in very close arrangement of different types of semiconductor chips, with the resulting (separation) space between adjacent semiconductor chips filled with molding members. As a result, regions may exist in the semiconductor package where the differences in the corresponding CTEs between the package substrate, the various semiconductor chips, and the various materials included in the molding members are considered. Therefore, when temperature changes occur during the manufacture of the semiconductor package, the individual components may expand or contract differently. This different and varying expansion and / or contraction can cause deformation of the semiconductor package (e.g., warping). Furthermore, this warping can lead to cracks (e.g., extending from the top to the bottom of the molding member) in areas thermally affected by CTE differences. In some cases, cracks may extend to the top surface of the package substrate, exposing internal components to external conditions and causing defects in the semiconductor package.

[0061] To address the aforementioned problems, in a semiconductor package according to an embodiment of the present invention, dummy pads (DPs) can be effectively arranged on the package substrate 400 to minimize potential warpage caused by CTE differences in the region adjacent to the junction of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. That is, the dummy pads (DPs) can be positioned in the region where the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 face each other to prevent or minimize crack propagation in the molded component 500. As a result, in a semiconductor package according to an embodiment of the present invention, defects caused by cracks can be suppressed or minimized by using dummy pads (DPs) as described above. Furthermore, this result is evident even in highly integrated SiPs, thereby improving reliability and productivity.

[0062] Figure 6 , Figure 7 and Figure 8 These are corresponding plan views of semiconductor packages 10A, 10B, and 10C according to embodiments of the present invention.

[0063] The corresponding components included in the semiconductor packages 10A, 10B, and 10C described below, and the materials included in the components, are consistent with the above references. Figures 1 to 5 The components described are essentially the same. Therefore, only each of the semiconductor packages 10A, 10B, and 10C will be described primarily. Figure 1 The differences between semiconductor packages 10.

[0064] Figure 6A semiconductor package 10A is shown, which includes a first semiconductor chip 100, four (4) second semiconductor chips 200, two (2) third semiconductor chips 300, a package substrate 400, a molding member 500 and a plurality of dummy pads (DP_A), wherein each third semiconductor chip 300 is laterally bracketed by two (2) of the second semiconductor chips 200.

[0065] Accordingly, each dummy pad (DP_A) is disposed on the packaging substrate 400 between one of the two (2) second semiconductor chips 200 and one of the third semiconductor chips 300 in the first semiconductor chip 100. As can be seen from the plan view, the dummy pad (DP_A) overlaps with a portion of each of the first semiconductor chip 100, the two (2) second semiconductor chips 200, and the third semiconductor chip 300. That is, one dummy pad (DP_A) overlaps with a portion of four (4) semiconductor chips.

[0066] In some embodiments, a first side of the dummy pad (DP_A) may extend below the first semiconductor chip 100, and an opposite second side of the dummy pad (DP_A) may extend below a combination of two (2) second semiconductor chips 200 and a third semiconductor chip 300. Therefore, the entire top surface of the dummy pad (DP_A) may be covered by a molding member 500, which extends from the top surface of the dummy pad (DP_A) in a double-T shape.

[0067] Figure 7 Semiconductor package 10B is shown, which includes a first semiconductor chip 100, four (4) second semiconductor chips 200 and four (4) third semiconductor chips 300, a package substrate 400, a molding component 500 and a plurality of dummy pads (DP_B), wherein a pair of second semiconductor chips 200 are laterally surrounded by two (2) third semiconductor chips 300.

[0068] Therefore, each dummy pad (DP_B) is disposed on the packaging substrate 400 between one of the first semiconductor chip 100, one of the second semiconductor chip 200, and one of the third semiconductor chip 300. As can be seen from the plan view, the dummy pad (DP_B) overlaps with a portion of each of the first semiconductor chip 100, one of the second semiconductor chip 200, and one of the third semiconductor chip 300. That is, one dummy pad (DP_B) overlaps with a portion of three (3) semiconductor chips.

[0069] In some embodiments, a first side of the dummy pad (DP_B) may extend beneath the first semiconductor chip 100, and an opposite second side of the dummy pad (DP_B) may extend beneath a combination of one of the second semiconductor chips 200 and one of the third semiconductor chips 300. Therefore, the entire top surface of the dummy pad (DP_B) may be covered by a molding member 500, which extends in a T-shape from the top surface of the dummy pad (DP_B).

[0070] Figure 8 Semiconductor package 10C is shown, which includes eight (8) second semiconductor chips 200 and two (2) third semiconductor chips 300 on the left and right sides of two first semiconductor chips 100.

[0071] A dummy pad (DP_C) can be located between the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 and the package substrate 400. As shown in the plan view, the dummy pad (DP_C) can overlap with a portion of each of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. Here, one dummy pad (DP_C1) as part of the dummy pad (DP_C) can overlap with three (3) semiconductor chips. In addition, another dummy pad (DP_C2) as another part of the dummy pad (DP_C) can overlap with five (5) semiconductor chips. That is, dummy pads (DP_C) of effectively different sizes can be included in the semiconductor package 10C.

[0072] The top surface of a dummy pad (DP_C1), which is part of a dummy pad (DP_C), can overlap with one side of the first semiconductor chip 100 and with one edge of each of the second semiconductor chip 200 and the third semiconductor chip 300. Therefore, the entire top surface of the dummy pad (DP_C1) can be covered by a molding member 500, which extends in a T-shape from the top surface of the dummy pad (DP_C1). That is, one dummy pad (DP_C1) can overlap with three (3) semiconductor chips.

[0073] The top surface of the dummy pad (DP_C2), which is another part of the dummy pad (DP_C), can overlap with one side of the third semiconductor chip 300 and with one edge of each of the first semiconductor chip 100 and the second semiconductor chip 200. Therefore, the entire top surface of the dummy pad (DP_C2) can be covered by the molding member 500, which extends from the top surface of the dummy pad (DP_C2) in a triple-T shape. That is, another dummy pad (DP_C2) can overlap with five (5) semiconductor chips.

[0074] The foregoing examples merely represent embodiments of the invention that benefit from arrangements of numerous semiconductor chips including one or more dummy pads. In this regard, dummy pads can have various shapes and sizes, depending on design variations.

[0075] Figures 9 to 14 It is an embodiment of the concept of the present invention. Figure 1 The corresponding cross-sectional view taken from the line X-X'.

[0076] Included Figures 9 to 14 The corresponding components in semiconductor packages 20, 30, 40, 50, 60, and 70, as well as the materials included in the components, can be referenced above. Figure 2 The components described in semiconductor package 10 are substantially the same. Therefore, only each of semiconductor packages 20, 30, 40, 50, and 60 will be described primarily. Figure 2 The differences between semiconductor packages 10. Although in Figures 9 to 14 The embodiments are not shown Figure 1 The third semiconductor chip 300, however, according to the above inventive concept, various semiconductor packages 20, 30, 40, 50 and 60 may include one or more third semiconductor chips 300.

[0077] Figure 9 A semiconductor package 20 is shown, which includes a first semiconductor chip 100, a second semiconductor chip 200, a package substrate 400, a molding member 500, an underfill 510, and a dummy pad DP.

[0078] Here, underfill 510 can be formed between the packaging substrate 400 and the first semiconductor chip 100 and the second semiconductor chip 200. In the process of electrically connecting the first connecting member 130 and the second connecting member 230 to the first semiconductor chip 100 and the second semiconductor chip 200, a gap can be formed between the packaging substrate 400 and the first semiconductor chip 100 and the second semiconductor chip 200. Because gaps can cause problems with the reliability of the connection between the first semiconductor chip 100 and the second semiconductor chip 200 and the packaging substrate 400, underfill 510 can be injected to enhance the connection between the first semiconductor chip 100 and the second semiconductor chip 200 and the packaging substrate 400. In some cases, MUF (Multi-Installation Fusion) technology can be used instead of underfill 510.

[0079] The top surface and a portion of the side surface of the dummy pad DP can be covered by the bottom filler 510, and the remaining portion of the top surface of the dummy pad DP can be covered by the molding member 500. That is, the dummy pad DP can be completely surrounded by the insulating member 460, the molding member 500, and the bottom filler 510, which include three different types of insulating materials.

[0080] The entire top surface of the dummy pad DP can be covered by the molding member 500 and the bottom filler 510, and the molding member 500 can extend from the top surface of the dummy pad DP in a T-shape.

[0081] The dummy pad DP can be located in the empty space between the first semiconductor chip 100, the second semiconductor chip 200, and the packaging substrate 400. Figure 9 As can be seen, the first semiconductor substrate 110 and the second semiconductor substrate 210 can be spaced apart from the package substrate 400 in a third direction (e.g., the Z direction) by the first connecting member 130 and the second connecting member 230. A dummy pad DP can be arranged in the resulting empty space. Therefore, the thickness DP_T of the dummy pad DP can be less than the distance separating the first connecting member 130 and the second connecting member 230 from the top surface of the dummy pad DP. In this respect, the thickness DP_T of the dummy pad DP can be less than the thickness of the underfill 510, and the top surface of the dummy pad DP can be at a level lower than the top surface of the underfill 510.

[0082] Figure 10 A semiconductor package 30 is shown, which includes a first semiconductor chip 100, a stacked second semiconductor chip 200A, a package substrate 400, a molding component 500, and a dummy pad DP.

[0083] Here, the first semiconductor chip 100 may include a single logic chip and may be implemented as, for example, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a SoC, and is not limited thereto.

[0084] The stacked second semiconductor chip 200A may include a collection of memory chips, which includes multiple slices (e.g., 201, 202, 203, and 204) capable of merging data with each other. Slices 201, 202, and 203 included in the stacked second semiconductor chip 200A may include a semiconductor substrate 210 having active and passive surfaces opposite each other, upper connection pads 225, and through-silicon vias (TSVs) 240 formed through the semiconductor substrate 210. In another embodiment, the uppermost slice (e.g., slice 204) may not include the upper connection pads 225 and the TSV 240.

[0085] The number of slices (e.g., 201, 202, 203, and 204) included in the second semiconductor chip 200A can vary depending on the purpose of the semiconductor package 30. That is, the number of slices (e.g., 201, 202, 203, and 204) included in the second semiconductor chip 200A is not limited to... Figure 10 The quantity shown.

[0086] Slices 201, 202, 203, and 204 included in the stacked second semiconductor chip 200A can be stacked on (and adhered to) each other via a connecting member 230 and an adhesive film (AF) disposed around the connecting member 230. The adhesive film AF can be a die attachment film. The die attachment film can be classified as an inorganic adhesive and a polymeric adhesive. Alternatively, a hybrid type prepared by mixing inorganic and polymeric adhesives can be used.

[0087] Figure 11 A semiconductor package 40 is shown, which includes a first semiconductor chip 100, dual (upper / lower) second semiconductor chips 200B, a package substrate 400, a molding member 500, and a dummy pad DP.

[0088] The first semiconductor chip 100 may include a single logic chip and may be implemented as, for example, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a SoC, and is not limited thereto.

[0089] The dual second semiconductor chip 200B may include a collection of memory chips, the collection of memory chips comprising multiple slices (e.g., a lower slice 201 and an upper slice 202) capable of merging data with each other. The lower slice 201 included in the second semiconductor chip 200B may include a semiconductor substrate 210 having active and passive surfaces opposite each other, an upper connection pad 225, and a TSV 240 formed through the semiconductor substrate 210. In another embodiment, the upper slice 202 may not include the upper connection pad 225 and the TSV 240.

[0090] The lower slice 201 and upper slice 202 included in the second semiconductor chip 200B can be stacked, and the lower slice 201 and upper slice 202 can be electrically connected to each other using direct bonding technology. That is, the connecting member 230 between the lower slice 201 and the upper slice 202 can be omitted, and the upper connection pad 225 of the lower slice 201 and the connection pad 220 of the upper slice 202 can be directly bonded and electrically connected to each other.

[0091] Figure 12 A semiconductor package 50 is shown, which includes a first semiconductor chip 190, a second semiconductor chip 200, a molding component 500, a redistribution structure 600, and a dummy pad DP.

[0092] Here, the first semiconductor chip 100, the second semiconductor chip 200, and the dummy pad DP can be disposed on the redistribution structure 600. That is to say, Figure 2 The packaging substrate 400 can be replaced by a redistribution structure 600.

[0093] The top surface of the redistribution structure 600 may be a horizontal plane. The redistribution structure 600 may include an upper electrode pad 620 and two redistribution conductive layers 630 and 640, which are formed on the redistribution insulating layer 610. However, the inventive concept is not limited thereto, and the redistribution structure 600 may include a variable number of redistribution conductive layers compared to the two redistribution conductive layers 630 and 640.

[0094] The redistribution conductive layers 630 and 640 may comprise one or more conductive materials, such as copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), palladium (Pd), or alloys thereof. In some embodiments, an electroplating process may be used to form the redistribution conductive layers 630 and 640.

[0095] The redistribution conductive layers 630 and 640 may include redistribution vias 631 and 641 and redistribution lines 633 respectively in contact with the redistribution vias 631 and 641. The redistribution lines 633 may be arranged along a horizontal planar surface, and the redistribution lines 633 may be arranged vertically in multiple layers.

[0096] The redistribution conductive layers 630 and 640 can electrically connect the external connection terminal 650 to the first semiconductor chip 100 and the second semiconductor chip 200. Furthermore, the redistribution insulating layer 610 may include an insulating protective layer surrounding the redistribution conductive layers 630 and 640. The redistribution insulating layer 610 may include a polymer, benzocyclobutene (BCB), or a resin. When desired, the redistribution insulating layer 610 may include polyimide. However, the materials included in the redistribution insulating layer 610 are not limited thereto. For example, the redistribution insulating layer 610 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0097] The redistribution insulating layer 610 can expose the bottom surface of the lower electrode pad 643. An insulating member 660 can be formed on top of the redistribution insulating layer 610, and a dummy pad PB can be located on the insulating member 660.

[0098] The lower electrode pad 643 can be electrically connected to the various unit elements of the first semiconductor chip 100 and the second semiconductor chip 200 through the redistribution structure 600. Therefore, the circuit units of the first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected to the external connection terminal 650. In other words, the lower electrode pad 643 can also be referred to as under bump metal (UBM).

[0099] External connection terminal 650 can be electrically connected to redistribution structure 600 via lower electrode pad 643. Additionally, semiconductor package 50 can be electrically connected to and mounted on module substrate or system board of electronic product via external connection terminal 650.

[0100] Figure 13 A semiconductor package 60 is shown, which includes: a first sub-package SP1 (which includes a first semiconductor chip 100 and a second semiconductor chip 200), a second sub-package SP2 (which includes a fourth semiconductor chip 100S and a fifth semiconductor chip 200S), package substrates 400 and 400S, molding components 500 and 500S, and dummy pads DP.

[0101] According to embodiments of the present invention, configurations such as SiP and PoP (PoP) structures can be applied simultaneously to a semiconductor package according to semiconductor package 60.

[0102] In other words, a semiconductor package 60 can be formed by connecting a first sub-package SP1, including a first semiconductor chip 100 and a second semiconductor chip 200, to a second sub-package SP2, including a fourth semiconductor chip 100S and a fifth semiconductor chip 200S, using an inter-package connection structure (not shown).

[0103] The first sub-package SP1 can be used with the aforementioned semiconductor package (see reference). Figure 2 The second sub-package SP2 may include a fourth semiconductor chip 100S and a fifth semiconductor chip 200S, a package substrate 400S located below the fourth semiconductor chip 100S and the fifth semiconductor chip 200S, and a molded member 500S configured to protect the fourth semiconductor chip 100S and the fifth semiconductor chip 500S from external influences (e.g., contamination and impact).

[0104] In semiconductor package 60, the characteristics of the first sub-package SP1 can be basically the same as those of the second sub-package SP2.

[0105] Figure 14 A semiconductor package 70 is shown, which includes: a first subpackage SP1 (which includes a first semiconductor chip 100 and a second semiconductor chip 200), a second subpackage SP2 (which includes a fourth semiconductor chip 100S and a fifth semiconductor chip 200S), molding components 500 and 500S, redistribution structures 600 and 600S, and dummy pads DP.

[0106] According to an embodiment, configurations such as SiP structures and PoP structures can be applied simultaneously to a semiconductor package according to semiconductor package 70.

[0107] In other words, a semiconductor package 60 can be formed by connecting a first sub-package SP1, including a first semiconductor chip 100 and a second semiconductor chip 200, to a second sub-package SP2, including a fourth semiconductor chip 100S and a fifth semiconductor chip 200S, using an inter-package connection structure (not shown).

[0108] The first sub-package SP1 can be used with the aforementioned semiconductor package (see reference). Figure 12 The second subpackage SP2 may include a fourth semiconductor chip 100S and a fifth semiconductor chip 200S, a redistribution structure 600S located below the fourth semiconductor chip 100S and the fifth semiconductor chip 200S, and a molded member 500S configured to protect the fourth semiconductor chip 100S and the fifth semiconductor chip 200S from external influences (e.g., contamination and impact).

[0109] In the semiconductor package 60 according to the embodiment, the characteristics of the first sub-package SP1 may be substantially the same as those of the second sub-package SP2.

[0110] Figure 15 This is a block diagram illustrating a semiconductor package 1000 according to an embodiment of the present invention.

[0111] refer to Figure 15 The semiconductor package 1000 may include a microprocessor unit (MPU) 1010, a memory 1020, an interface 1030, a graphics processing unit (GPU) 1040, a function block 1050, and a system bus 1060 configured to connect the MPU 1010, memory 1020, interface 1030, GPU 1040, and function block 1050 to each other. The semiconductor package 1000 may include at least one of the MPU 1010 and GPU 1040.

[0112] The MPU 1010 may include cores and cache. For example, the MPU 1010 may include multiple cores. The individual cores in the multiple cores may have the same or different performance. In addition, the individual cores in the multiple cores may be activated at the same time or at different time points.

[0113] Memory 1020 can store the processing results of function block 1050 under the control of MPU 1010. Interface 1030 can send or receive information or signals to or from external devices. GPU 1040 can perform graphics functions. For example, GPU 1040 can perform video encoding / decoding operations or process 3D graphics. Function block 1050 can perform various functions. For example, when semiconductor package 1000 is an application processor for a mobile device, some function blocks 1050 can perform communication functions.

[0114] Semiconductor package 1000 may include the above references Figures 1 to 14 The semiconductor package described is any one of 10, 10A, 10B, 10C, 20, 30, 40, 50, 60 and 70.

[0115] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Packaging substrate; The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip on the packaging substrate; as well as A dummy pad is horizontally positioned between the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, overlapping at least a portion of each of the three semiconductor chips. The dummy pad is disposed on the packaging substrate and in the space between the packaging substrate and the first semiconductor chip, the second semiconductor chip and the third semiconductor chip.

2. The semiconductor package according to claim 1, further comprising: A molded component fills the space between the packaging substrate and the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip to cover the top surface of the dummy pad.

3. The semiconductor package according to claim 2, wherein, The molded component extends in a T-shape from the top surface of the dummy pad.

4. The semiconductor package according to claim 1, further comprising: Bottom filler fills the space between the packaging substrate and the first semiconductor chip, the second semiconductor chip and the third semiconductor chip, covers a portion of the top surface of the dummy pad, and covers the side surface of the dummy pad; as well as A molded component that covers another portion of the top surface of the dummy pad.

5. The semiconductor package according to claim 1, wherein, The second semiconductor chip and the third semiconductor chip are arranged in parallel along one side of the first semiconductor chip. The lateral width of the dummy pad is greater than the separation distance between the first semiconductor chip and any one of the second and third semiconductor chips, and The longitudinal width of the dummy pad is greater than the separation distance between the second semiconductor chip and the third semiconductor chip.

6. The semiconductor package according to claim 5, wherein, The dummy pad overlaps with one side of the first semiconductor chip, with one edge of the second semiconductor chip opposite to the one side of the first semiconductor chip, and with one edge of the third semiconductor chip opposite to the one side of the first semiconductor chip.

7. The semiconductor package according to claim 1, further comprising: The insulating film includes at least one of silicon oxide and silicon nitride disposed between the packaging substrate and the dummy pad.

8. The semiconductor package according to claim 1, wherein, The packaging substrate includes an insert configured to provide an electrical connection to at least one of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.

9. The semiconductor package according to claim 1, wherein, The dummy pad comprises a conductive metal material, and the dummy pad is electrically isolated from the packaging substrate, the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.

10. The semiconductor package according to claim 9, wherein, The dummy pad has at least one of the following shapes: flat plate, strip, and matrix.

11. A semiconductor package, comprising: Redistributed structure; At least three semiconductor chips on the redistributed structure; A dummy pad is provided between the redistribution structure and the at least three semiconductor chips; as well as A molded component fills the space between the at least three semiconductor chips such that the dummy pad overlaps with at least a portion of each of the at least three semiconductor chips, and the molded component covers at least a portion of the top surface of the dummy pad.

12. The semiconductor package of claim 11, wherein, The width of the dummy pad is greater than the separation distance between any two of the at least three semiconductor chips.

13. The semiconductor package of claim 11, wherein, The bottom surface of each of the at least three semiconductor chips contacts the molded component, and The bottom surface of the dummy pad contacts an insulating film, which is formed on the redistribution structure and includes at least one of silicon oxide and silicon nitride.

14. The semiconductor package of claim 11, wherein, The dummy pads are electrically isolated.

15. The semiconductor package of claim 11, wherein, One of the at least three semiconductor chips has a stacked structure including multiple slices, and Another of the at least three semiconductor chips has a single-layer structure.

16. A semiconductor package, comprising: Insert; Semiconductor chips, including memory chips, logic chips, and dummy chips disposed adjacent to the insert; A dummy pad is provided on the insert and between the insert and the semiconductor chip, wherein the dummy pad comprises a metallic material; A molded component covering the bottom and side surfaces of the semiconductor chip, wherein the molded component covers the top and side surfaces of the dummy pads; and Solder bumps adhere to the bottom surface of the insert. The dummy pads overlap with at least a portion of each of the semiconductor chips.

17. The semiconductor package of claim 16, wherein, The dummy pad overlaps one side of the logic chip and the edge of each of the memory chip and the dummy chip.

18. The semiconductor package of claim 17, wherein, The first planar region where the dummy pad overlaps with the logic chip is larger than each of the second and third planar regions where the dummy pad overlaps with the memory chip.

19. The semiconductor package of claim 16, wherein, The memory chip is a high-bandwidth memory chip and is a stacked structure comprising multiple slices.

20. The semiconductor package of claim 16, wherein, The width of the dummy pad is greater than the maximum distance that would separate the semiconductor chip.

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