Semiconductor structure and method of making same, integrated circuit, three-dimensional memory, and system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, an integrated circuit, a three-dimensional memory and a system, relates to the technical field of semiconductor chips, and aims to reduce the process difficulty of the alignment electrical connection between the conductor in the interconnection layer and the source and the drain of the transistor. The semiconductor structure comprises a substrate, a transistor, a first conductive layer and a second conductive layer, the transistor comprises a source, a drain, a gate dielectric layer and a gate, the gate dielectric layer is arranged on a first surface of the substrate and located between the source and the drain, the gate is arranged on a side of the gate dielectric layer away from the substrate, the first conductive layer covers and electrically contacts the source, and the area of the first conductive layer is larger than the area of the source; the second conductive layer covers and electrically contacts the drain, and the area of the second conductive layer is larger than the area of the drain. The above semiconductor structure is applied to the three-dimensional memory to realize the read and write operations of data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, an integrated circuit, a three-dimensional memory and system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] However, the transistors included in the integrated circuits in the peripheral devices are very small. Therefore, in the process of electrically connecting the transistors included in the integrated circuit to the memory array device through the interconnect layer to realize the functional support of the integrated circuit to the memory array device, the process of aligning and electrically connecting the conductors in the interconnect layer with the source and drain of the transistor is difficult and the product yield is low. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, an integrated circuit, a three-dimensional memory, and a system, aiming to reduce the technological difficulty of aligning and electrically connecting the source and drain of a transistor with a conductor in an interconnect layer.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, a transistor, a first conductive layer, and a second conductive layer. The substrate includes a transistor region. The transistor is disposed in the transistor region and includes a source, a drain, a gate dielectric layer, and a gate. The source and the drain are spaced apart and extend from a first surface of the substrate into the substrate; the first surface is one of two opposing main surfaces of the substrate. The gate dielectric layer is disposed on the first surface of the substrate and located between the source and the drain. The gate is disposed on the side of the gate dielectric layer away from the substrate. The first conductive layer and the second conductive layer are disposed on the first surface of the substrate; the first conductive layer covers and electrically contacts the source, and the area of ​​the first conductive layer is larger than the area of ​​the source; the second conductive layer covers and electrically contacts the drain, and the area of ​​the second conductive layer is larger than the area of ​​the drain.

[0008] The semiconductor structure provided in the above embodiments of this disclosure has a first conductive layer and a second conductive layer on the first surface of the substrate. The first conductive layer is in electrical contact with the source, and the second conductive layer is in electrical contact with the drain. Thus, during the process of electrically connecting the source and drain of the transistor to the array interconnect layer of the memory array device through a peripheral interconnect layer, the first contact plug in the peripheral interconnect layer can make electrical contact with the first conductive layer to achieve electrical connection with the source; the second contact plug can make electrical contact with the second conductive layer to achieve electrical connection with the drain.

[0009] Compared with related technologies, since the area of ​​the first conductive layer is larger than the area of ​​the source electrode and the area of ​​the second conductive layer is larger than the area of ​​the drain electrode, the setting area corresponding to the first contact plug and the second contact plug is increased. The process difficulty of aligning and electrically connecting the first contact plug and the second contact plug with the source electrode and the drain electrode is reduced, and the product yield is improved.

[0010] In some embodiments, the semiconductor structure further includes a first protective layer, a first interconnect, and a second interconnect. The first protective layer at least covers the gate, the first conductive layer, and the second conductive layer; the first interconnect and the second interconnect penetrate the first protective layer, with the first interconnect exposing the first conductive layer and the second interconnect exposing the second conductive layer.

[0011] In some embodiments, the semiconductor structure further includes an interlayer dielectric layer, a first via, a second via, a first contact plug, and a second contact plug. The interlayer dielectric layer covers the first protective layer. The first via and the second via penetrate the interlayer dielectric layer, with the first via communicating with the first connection hole and the second via communicating with the second connection hole. The first contact plug is disposed within the first via and the first connection hole and is in electrical contact with the first conductive layer. The second contact plug is disposed within the second via and the second connection hole and is in electrical contact with the second conductive layer.

[0012] In some embodiments, the semiconductor structure further includes a third conductive layer, a third interconnect, a third via, and a third contact plug. The third conductive layer covers the surface of the gate away from the substrate and is in electrical contact with the gate. The third interconnect penetrates the first protective layer and exposes the gate. The third via penetrates the interlayer dielectric layer and communicates with the third interconnect. The third contact plug is disposed within the third via and the third interconnect and is in electrical contact with the third conductive layer.

[0013] In some embodiments, the third conductive layer is made of the same material as the first conductive layer and the second conductive layer and is disposed in the same layer.

[0014] In some embodiments, the substrate further includes an isolation region located on at least one side of the transistor region. The semiconductor structure also includes an isolation structure disposed within the isolation region. The isolation structure includes an isolation recess and an isolation layer, the isolation layer being located within the isolation recess, and the thickness of the isolation layer being less than the depth of the isolation recess. The first protective layer further covers the isolation layer and the sidewalls of the isolation recess not covered by the isolation layer.

[0015] In some embodiments, the isolation trench includes a first opening segment and a second opening segment. The first opening segment is adjacent to a second surface of the substrate relative to the second opening segment; the second surface is one of two opposing main surfaces of the substrate opposite to the first surface. The isolation layer is disposed in the first opening segment. The semiconductor structure further includes an in-trench dielectric layer and an in-trench protective layer. The in-trench dielectric layer covers the sidewall of the second opening segment. The in-trench protective layer covers the in-trench dielectric layer, and the first protective layer covers the in-trench protective layer.

[0016] In some embodiments, the isolation groove further includes a third opening segment located on the side of the second opening segment away from the second surface. The semiconductor structure further includes a fourth conductive layer covering the sidewall of the third sub-opening segment, and the first protective layer covering the fourth conductive layer.

[0017] In some embodiments, the fourth conductive layer is made of the same material as the first conductive layer and the second conductive layer and is disposed in the same layer.

[0018] In some embodiments, in adjacent transistor regions and isolation regions, the one of the first conductive layer and the second conductive layer closest to the fourth conductive layer is integrally disposed with the fourth conductive layer.

[0019] In some embodiments, the in-groove dielectric layer and the gate dielectric layer are made of the same material and are disposed in the same layer.

[0020] In some embodiments, the transistor further includes a side protection layer. The side protection layer covers the side of the gate; the in-groove protection layer is made of the same material as the side protection layer and is disposed in the same layer.

[0021] In some embodiments, the materials of the first conductive layer and the second conductive layer include nickel silicon and / or cobalt silicon; when the semiconductor structure further includes a third conductive layer, the material of the third conductive layer includes nickel silicon and / or cobalt silicon; when the semiconductor structure further includes a fourth conductive layer, the material of the fourth conductive layer includes nickel silicon and / or cobalt silicon.

[0022] In some embodiments, the first conductive layer and the second conductive layer further cover the region in the transistor region that is not covered by the gate dielectric layer.

[0023] In some embodiments, the length of the transistor region along the length direction of the transistor channel is less than or equal to 70 nm.

[0024] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: fabricating an intermediate semiconductor structure; the intermediate semiconductor structure including a transistor region; the intermediate semiconductor structure including: a substrate; a source and a drain extending from a first surface of the substrate into the substrate and located in the transistor region, the first surface being one of two opposing main surfaces of the substrate; a gate dielectric film disposed on the first surface of the substrate; a gate disposed on the side of the gate dielectric film away from the substrate and located in the transistor region; and a second protective film covering the gate and the gate dielectric film. A first portion and a second portion of the second protective film are removed; the first portion covers the source and has an area larger than the source, and the second portion covers the drain and has an area larger than the drain. The portions of the gate dielectric film corresponding to the first and second portions are removed to expose the source and drain. A first conductive layer covering the source and a second conductive layer covering the drain are formed such that the first conductive layer is in electrical contact with the source, and the second conductive layer is in electrical contact with the drain.

[0025] In some embodiments, after forming the first conductive layer and the second conductive layer, the fabrication method further includes: forming a first protective layer covering the transistor region; forming an interlayer dielectric layer covering the first protective layer; forming a first via and a second via penetrating the interlayer dielectric layer and the first protective layer; the first via exposing the first conductive layer, and the second via exposing the second conductive layer; forming a first contact plug and a second contact plug; the first contact plug being disposed within the first via and in electrical contact with the first conductive layer; and the second contact plug being disposed within the second via and in electrical contact with the second conductive layer.

[0026] In some embodiments, during the removal of the first and second portions of the second protective film, a third portion of the second protective film is also removed, the third portion covering the surface of the gate remote from the substrate. During the removal of portions of the gate dielectric film corresponding to the first and second portions, a portion of the gate dielectric film corresponding to the third portion is also removed to expose the gate. During the formation of the first and second conductive layers, a third conductive layer is also formed covering the gate to make the third conductive layer electrically contact the gate.

[0027] In some embodiments, during the formation of a first via and a second via penetrating the interlayer dielectric layer and the first protective layer, a third via penetrating the interlayer dielectric layer and the first protective layer is also formed; the third via exposes the gate. During the formation of a first contact plug and a second contact plug, a third contact plug is also formed; the third contact plug is disposed within the third via and is in electrical contact with the third conductive layer.

[0028] In some embodiments, the fabrication of the intermediate semiconductor structure includes: forming a gate dielectric film on a first surface of the substrate; forming a gate electrode on the side of the gate dielectric film away from the substrate; forming a second protective film on the side of the gate electrode away from the substrate; ion-doping the substrate; and forming a source and a drain electrode on both sides of the gate electrode in the transistor region.

[0029] In some embodiments, prior to forming a gate dielectric film on a first surface of the substrate, the fabrication of the intermediate semiconductor structure further includes: forming an isolation trench extending from the first surface of the substrate into the substrate; and forming an isolation layer located within the isolation trench, wherein the thickness of the isolation layer is less than the depth of the isolation trench.

[0030] In some embodiments, the isolation groove includes a first opening segment and a second opening segment, the first opening segment being adjacent to a second surface of the substrate relative to the second opening segment; the second surface is one of two opposing main surfaces of the substrate opposite to the first surface; the isolation layer is disposed in the first opening segment. During the removal of the first and second portions of the second protective film, a fourth portion of the second protective film is also removed, the fourth portion covering the isolation layer. During the removal of the portions of the gate dielectric film corresponding to the first and second portions, the portion of the gate dielectric film corresponding to the fourth portion is also removed, the fourth portion covering the surface of the isolation layer adjacent to the first surface of the substrate.

[0031] In some embodiments, the isolation groove further includes a third opening segment located on the side of the second opening segment away from the second surface; during the removal of the first and second portions of the second protective film, a fifth portion of the second protective film is also removed, the fifth portion covering the sidewall of the third sub-opening segment. During the removal of the portions of the gate dielectric film corresponding to the first and second portions, the portion of the gate dielectric film corresponding to the fifth portion is also removed. During the formation of the first conductive layer and the second conductive layer, a fourth conductive layer covering the sidewall of the third sub-opening segment is also formed.

[0032] In another aspect, an integrated circuit is provided. The integrated circuit includes a semiconductor structure, which is the semiconductor structure described in some of the above embodiments or is fabricated by the method described in some of the above embodiments for fabricating a semiconductor structure.

[0033] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the integrated circuit and memory array device described in some embodiments above, wherein the memory array device is electrically connected to the integrated circuit.

[0034] In another aspect, a storage system is provided. The storage system includes a controller and a three-dimensional memory as described in some of the embodiments above, the controller being coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0035] It is understood that the beneficial effects that the semiconductor structure fabrication method, integrated circuit, three-dimensional memory and storage system provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0037] Figure 1 This is a block diagram of a storage system according to some embodiments;

[0038] Figure 2 A block diagram of a storage system according to some other embodiments;

[0039] Figure 3 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0040] Figure 4 This is a cross-sectional view of the device structure during the fabrication process of a semiconductor structure in related technologies;

[0041] Figure 5 A top view of an integrated circuit (peripheral device) of a three-dimensional memory according to some embodiments;

[0042] Figure 6 for Figure 5 A cross-sectional view of the peripheral device shown along section line AA';

[0043] Figure 7 for Figure 5 Another cross-sectional view of the peripheral device shown along section line AA';

[0044] Figure 8 This is a structural diagram of a substrate according to some embodiments of a semiconductor structure;

[0045] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0046] Figure 10 for Figure 9 The diagram shows the preparation steps of the preparation method.

[0047] Figure 11 for Figure 9 The diagram shows the preparation steps of the preparation method.

[0048] Figure 12 for Figure 9 The diagram shows the preparation steps of the preparation method.

[0049] Figure 13 for Figure 9 The diagram shows the preparation steps of the preparation method.

[0050] Figure 14 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0051] Figure 15 for Figure 14 The diagram shows the preparation steps of the preparation method.

[0052] Figure 16 for Figure 14 The diagram shows the preparation steps of the preparation method.

[0053] Figure 17 for Figure 14 The diagram shows the preparation steps of the preparation method.

[0054] Figure 18 for Figure 14 The diagram shows the preparation steps of the preparation method.

[0055] Figure 19 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0056] Figure 20 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation

[0057] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0058] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0059] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0060] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0061] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0062] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0063] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0064] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0065] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0066] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0067] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0068] like Figure 3As shown, the three-dimensional memory 300 includes an integrated circuit 200 and a memory array device 400. The memory array device 400 is electrically connected to the integrated circuit 200 to enable the integrated circuit 200 to support the functions of the memory array device 400, such as reading, writing, and erasing data in the memory cells.

[0069] In some embodiments, the memory array device 400 includes a memory cell string array 410 and an array interconnect layer 420 disposed on the side of the memory cell string array 410 near the integrated circuit 200, the memory cell string array 410 being electrically connected to the array interconnect layer 420. The integrated circuit 200 includes a series of circuits 210, such as logic circuits and page buffers, and a peripheral interconnect layer 220 disposed on the side of the series of circuits near the memory array device 400, the series of circuits 210 being electrically connected to the peripheral interconnect layer 220. The memory array device 400 and the integrated circuit 200 are electrically connected through the array interconnect layer 420 and the peripheral interconnect layer 220, thereby enabling the memory cell string array 410 to be electrically connected to the series of circuits 210.

[0070] In related technologies, such as Figure 4 As shown, the transistors 100' included in the aforementioned logic circuits, page buffers, and other circuits 210 include a gate 110', a source 120', and a drain 130'. The source 120' and drain 130' are located on both sides of the gate 110', and their corresponding contact areas M' are relatively small. Thus, combined with... Figure 1 In the process of electrically connecting the source 121 and drain 122 of the transistor 120 to the array interconnect layer 420 of the memory array device 400 through the peripheral interconnect layer 220, the process of aligning and electrically connecting the first contact plug 163 and the second contact plug 173 in the peripheral interconnect layer 220 with the source 121 and drain 122 is difficult and the product yield is low.

[0071] Based on this, please see Figure 6 Some embodiments of this disclosure provide a semiconductor structure 100, which includes a substrate 110, a transistor 120, a first conductive layer 131, and a second conductive layer 132. The transistor 120 may include, for example, a high-voltage (HV) transistor, a low-voltage (LV) transistor, and a low-low-voltage (LLV) transistor, but this disclosure is not limited thereto.

[0072] It should be noted that the semiconductor structure 100 provided in this embodiment can be used to construct peripheral devices in a three-dimensional memory. Please refer to... Figure 3 , Figure 3A cross-sectional structure of a three-dimensional memory 300 is shown, which includes a memory array device 400 and an integrated circuit 200 electrically connected to each other. See also... Figure 5 , Figure 5 The top view of the integrated circuit 200 is shown, and it can be seen that the integrated circuit 200 includes at least one of the aforementioned semiconductor structures 100.

[0073] Figure 6 It shows Figure 5 The cross-sectional structure of integrated circuit 200 along section line AA'. See also Figure 6 The substrate 110 includes a transistor region L and an isolation region S. The isolation region S is located on at least one side of the transistor region L to electrically isolate the transistor region L from at least a portion of the transistor region L adjacent to it.

[0074] For example, combined Figure 8 The isolation region S of the substrate 110 is provided with an isolation groove 112, which extends from the first surface 111 of the substrate 110 into the substrate 110 to divide the substrate 110 into individual transistor regions L. The first surface 111 is one of the two opposing main surfaces of the substrate 110. The isolation groove 112 is filled with an insulating material to form an isolation layer 113, thereby electrically isolating the transistor region L from at least a portion of the surrounding adjacent transistor regions L.

[0075] It should be noted that the substrate 110 may be made of at least one of silicon, silicon germanium, germanium and silicon-on-insulator thin film, but is not limited to this.

[0076] Transistor 120 is disposed in transistor region L. Transistor 120 includes source 121, drain 122, gate dielectric layer 123 and gate 124. Source 121 and drain 122 are spaced apart and extend from the first surface 111 of substrate 110 into substrate 110.

[0077] A gate dielectric layer 123 is disposed on the first surface 111 of the substrate 110 and located between the source 121 and the drain 122. The thickness of the gate dielectric layer 123 may vary depending on the performance requirements of the transistor. For example, the thickness of the gate dielectric layer 123 in an HV transistor is greater than that in a standard HV transistor. A gate 124 is disposed on the side of the gate dielectric layer 123 away from the substrate 110 to control the connection and disconnection between the source 121 and the drain 122. It should be noted that the material of the gate dielectric layer 123 includes silicon oxide, but is not limited to this.

[0078] A first conductive layer 131 and a second conductive layer 132 are disposed on a first surface 111 of a substrate 110. The first conductive layer 131 covers and electrically contacts a source electrode 121, and the area of ​​the first conductive layer 131 is larger than the area of ​​the source electrode 121. The second conductive layer 132 covers and electrically contacts a drain electrode 122, and the area of ​​the second conductive layer 132 is larger than the area of ​​the drain electrode 122.

[0079] As described above, in the semiconductor structure 100 provided in the above embodiments of this disclosure, the first surface 111 of the substrate 110 is provided with a first conductive layer 131 and a second conductive layer 132. The first conductive layer 131 is in electrical contact with the source 121, and the second conductive layer 132 is in electrical contact with the drain 122. Thus, combined with... Figure 3 In the process of electrically connecting the source 121 and drain 122 of the transistor 120 to the array interconnect layer 420 of the memory array device 400 through the peripheral interconnect layer 220, the first contact plug 163 in the peripheral interconnect layer 220 can make electrical contact with the first conductive layer 131 to achieve electrical connection with the source 121; the second contact plug 173 can make electrical contact with the second conductive layer 132 to achieve electrical connection with the drain 122.

[0080] Compared with related technologies, since the area of ​​the first conductive layer 131 is larger than the area of ​​the source 121 and the area of ​​the second conductive layer 132 is larger than the area of ​​the drain 122, the corresponding setting areas of the first contact plug 163 and the second contact plug 173 are increased. The process difficulty of aligning and electrically connecting the first contact plug 163 and the second contact plug 173 with the source 120 and the drain 130 is reduced, and the product yield is improved.

[0081] See Figure 5 In some embodiments, the length of transistor region L along the length direction Y of the channel of transistor 120 is less than or equal to 70 nm.

[0082] Furthermore, a first conductive layer 131 covers and electrically contacts the source electrode 121, and the area of ​​the first conductive layer 131 is larger than the area of ​​the source electrode 121. A second conductive layer 132 covers and electrically contacts the drain electrode 122, and the area of ​​the second conductive layer 132 is larger than the area of ​​the drain electrode 122. For example, as... Figure 6 As shown, the first conductive layer 131 and the second conductive layer 132 cover the area in transistor region L not covered by the gate dielectric layer 123. In this way, combined with... Figure 3 In the transistor region L, the area not covered by the gate dielectric layer 123 can be electrically connected to the source 121 or the drain 122 through the first conductive layer 131 or the second conductive layer 132, thereby increasing the setting area corresponding to the first contact plug 163 and the second contact plug 173, reducing the process difficulty, and improving the product yield.

[0083] See Figure 6In some embodiments, the semiconductor structure 100 further includes a first protective layer 150, a first connection hole 161, and a second connection hole 171. The first protective layer 150 at least covers the gate 124, the first conductive layer 131, and the second conductive layer 132 to electrically isolate the gate 124, the first conductive layer 131, and the second conductive layer 132 from other surrounding conductive structures, thereby protecting the gate 124, the source 121 which is electrically in contact with the first conductive layer 131, and the drain 122 which is electrically in contact with the second conductive layer 132.

[0084] The first connecting hole 161 penetrates the first protective layer 150 and exposes the first conductive layer 131, so that an external conductive structure (first contact plug 163) can be electrically connected to the source 121 through the first conductive layer 131. The second connecting hole 171 penetrates the first protective layer 150 and exposes the second conductive layer 132, so that an external conductive structure (second contact plug 173) can be electrically connected to the drain 122 through the second conductive layer 132. It should be noted that the material of the first protective layer 150 includes silicon nitride, but is not limited to it.

[0085] See Figure 7 and Figure 18 In some embodiments, the semiconductor structure 100 further includes an interlayer dielectric layer 180, a first via 162, a second via 172, a first contact plug 163, and a second contact plug 173. The interlayer dielectric layer 180 covers the first protective layer 150. The first via 162 and the second via 172 penetrate the interlayer dielectric layer 180, with the first via 162 communicating with a first connection hole 161 and the second via 172 communicating with a second connection hole 171. The first contact plug 163 is disposed within the first via 162 and the first connection hole 161, and is in electrical contact with the first conductive layer 131, thereby being electrically connected to the source 121. The second contact plug 173 is disposed within the second via 172 and the second connection hole 171, and is in electrical contact with the second conductive layer 132, thereby being electrically connected to the drain 122.

[0086] See Figure 7 and Figure 18 In some embodiments, the semiconductor structure 100 further includes a third conductive layer 133, a third connecting via 191, a third via 192, and a third contact plug 193. The third conductive layer 133 covers the surface of the gate 124 away from the substrate 110 and is in electrical contact with the gate 124 to reduce the contact resistance of the gate 124. The third connecting via 191 penetrates the first protective layer 150 and exposes the gate 124; the third via 192 penetrates the interlayer dielectric layer 180 and communicates with the third connecting via 191. The third contact plug 193 is disposed within the third via 192 and the third connecting via 191 and is in electrical contact with the third conductive layer 133, thereby being electrically connected to the gate 124.

[0087] See Figure 6 and Figure 7 In some embodiments, the third conductive layer 133 is made of the same material as the first conductive layer 131 and the second conductive layer 132 and is disposed in the same layer. For example, the materials of the first conductive layer 131, the second conductive layer 132 and the third conductive layer 133 include nickel silicon and / or cobalt silicon. Using nickel silicon and / or cobalt silicon simplifies the fabrication process of the first conductive layer 131, the second conductive layer 132 and the third conductive layer 133, and reduces the contact resistance of the source 121, the drain 122 and the gate 123.

[0088] like Figure 7 and Figure 8 As shown, in some embodiments, the thickness of the isolation layer 113 is less than the depth of the isolation groove 112. The first protective layer 150 also covers the isolation layer 113 and the sidewalls of the isolation groove 112 that are not covered by the isolation layer 113. The first protective layer 150 does not require patterning, which can simplify the process steps.

[0089] Based on this, refer to Figure 8 The isolation groove 112 includes a first opening segment 1121 and a second opening segment 1122. The first opening segment 1121 is closer to the second surface 114 of the substrate 110 relative to the second opening segment 1122; the second surface 114 is the side of the substrate 110 opposite to the first surface 111 among two opposing main surfaces. An isolation layer 113 is disposed in the first opening segment 1121. See also Figure 6 The semiconductor structure 100 also includes an in-cell dielectric layer 125 and an in-cell protective layer 126. The in-cell dielectric layer 125 covers the sidewall of the second opening segment 1122. The in-cell protective layer 126 covers the in-cell dielectric layer 125, and a first protective layer 150 covers the in-cell protective layer 126.

[0090] The in-groove dielectric layer 125 and the gate dielectric layer 123 are made of the same material and are disposed in the same layer. This allows the in-groove dielectric layer 125 and the gate dielectric layer 123 to use the same material and be fabricated in the same process, thus simplifying the process steps. It should be noted that the aforementioned in-groove dielectric layer 125 can be the gate dielectric film 128 remaining on the sidewall of the isolation groove 112 during the formation of the patterned gate dielectric layer 123 (see...). Figure 12 ).

[0091] In addition, see Figure 6The transistor 120 also includes a side protection layer 127 covering the side of the gate 124. The in-groove protection layer 126 is made of the same material as the side protection layer 127 and is disposed in the same layer. This allows the in-groove protection layer 126 and the side protection layer 127 to use the same material and be fabricated in the same process, thus simplifying the process steps. It should be noted that the aforementioned in-groove protection layer 126 may be a second protective film 129 remaining on the sidewall of the isolation groove 112 during the formation of the side protection layer 127 (see...). Figure 11 ).

[0092] See Figure 6 and Figure 8 In some embodiments, the isolation groove 112 further includes a third opening segment 1123 located on the side of the second opening segment 1122 away from the second surface 114. The semiconductor structure 100 also includes a fourth conductive layer 134 covering the sidewall of the third sub-opening segment 1123, and a first protective layer 150 covering the fourth conductive layer 134, to further increase the setting area corresponding to the first contact plug 163 and the second contact plug 173, reduce the process difficulty, and improve the product yield.

[0093] In the adjacent transistor region L and isolation region S, the one of the first conductive layer 131 and the second conductive layer 132 closest to the fourth conductive layer 134 is integrally disposed with the fourth conductive layer 134. In this way, the fourth conductive layer 134, the first conductive layer 131 and the second conductive layer 132 are fabricated in the same process, thereby simplifying the process steps.

[0094] like Figure 9 As shown, some embodiments of this disclosure also provide a semiconductor structure 100 (see...). Figure 6 The preparation methods include S1 to S3.

[0095] S1: See Figure 9 and Figure 10 , Prepare intermediate semiconductor structure 101.

[0096] In the above steps, the intermediate semiconductor structure 101 includes a transistor region L. The intermediate semiconductor structure 101 includes a substrate 110, a source 121 and a drain 122 extending from a first surface 111 of the substrate 110 into the substrate 110 and located in the transistor region L, a gate dielectric film 128 disposed on the first surface 111 of the substrate 110, a gate 124 disposed on the side of the gate dielectric film 128 away from the substrate 110 and located in the transistor region L, and a second protective film 129 covering the gate 124 and the gate dielectric film 128. It should be noted that the first surface 111 is one of two opposing main surfaces of the substrate 110.

[0097] S2: See also Figures 9-11Remove the first portion N1 and the second portion N2 from the second protective film 129.

[0098] In the above steps, the first portion N1 covers the source 121 and has an area larger than the source 121, and the second portion N2 covers the drain 122 and has an area larger than the drain 122. After removing the first portion N1 and the second portion N2 from the second protective film 129, the remaining portion of the second protective film 129 includes the side protection layer 127 of the semiconductor structure 100 provided in some of the above embodiments.

[0099] When removing the first portion N1 and the second portion N2 of the second protective film 129, dry etching can be used to remove the first portion N1 and the second portion N2 of the second protective film 129, thereby exposing the gate dielectric film 128 on the side of the second protective film 129 near the substrate 110.

[0100] S3: See also Figures 9-12 Remove the portions of the gate dielectric film 128 corresponding to the first portion N1 and the second portion N2 to expose the source 121 and the drain 122.

[0101] In the above steps, when removing the portions of the gate dielectric film 128 corresponding to the first portion N1 and the second portion N2, dry etching can be used to remove these portions (i.e., the portions of the gate dielectric film 128 exposed by the second protective film 129), thereby exposing the source 121 and drain 122 of the gate dielectric film 128 near the substrate 110. The remaining portion of the gate dielectric film 128 includes the gate dielectric layer 123 of the semiconductor structure 100 provided in some of the above embodiments.

[0102] S4: See also Figures 9-13 A first conductive layer 131 covering the source electrode 121 and a second conductive layer 132 covering the drain electrode 122 are formed, so that the first conductive layer 131 is in electrical contact with the source electrode 121 and the second conductive layer 132 is in electrical contact with the drain electrode 122.

[0103] In the above steps, the first conductive layer 131 and the second conductive layer 132 can be formed by implanting nickel ions and / or cobalt ions into the region of the substrate 110 exposed by the gate dielectric film 128 (i.e., the region corresponding to the first part N1 and the second part N2).

[0104] See Figure 14 After S4, the method for fabricating the semiconductor structure 100 also includes S5 to S8.

[0105] S5: See also Figure 14 and Figure 15 A first protective layer 150 is formed covering the transistor region L.

[0106] In the above steps, silicon nitride can be deposited on one side of the first surface 111 of the substrate 110 by chemical vapor deposition to form a first protective layer 150.

[0107] S6: See also Figure 14 and Figure 16 This forms an interlayer dielectric layer 180 covering the first protective layer 150.

[0108] In the above steps, the interlayer dielectric layer 180 is made of an insulating material, and the material of the interlayer dielectric layer 180 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and doped silicon oxide, but this disclosure is not limited thereto.

[0109] S7: See also Figure 14 and Figure 17 This forms a first through-hole 160 and a second through-hole 170 that penetrate the interlayer dielectric layer 180 and the first protective layer 150.

[0110] In the above steps, the first via 160 exposes the first conductive layer 131, and the second via 170 exposes the second conductive layer 132. The first via 160 includes a first connection hole 161 and a first through-hole 162 of the semiconductor structure 100 provided in some of the above embodiments, and the second via 170 includes a second connection hole 171 and a second through-hole 172 of the semiconductor structure 100 provided in some of the above embodiments.

[0111] S8: See also Figure 14 and Figure 18 This forms the first contact plug 163 and the second contact plug 173.

[0112] In the above steps, the first contact plug 163 is disposed within the first through hole 160 (i.e., the first connecting hole 161 and the first via hole 162) and is in electrical contact with the first conductive layer 131. The second contact plug is disposed within the second through hole 170 (i.e., the second connecting hole 171 and the second via hole 172) and is in electrical contact with the second conductive layer 132. It should be noted that the first contact plug 163 and the second contact plug 173 are made of conductive material, and the material of the first contact plug 163 and the second contact plug 173 includes at least one of tungsten, cobalt, copper, aluminum and metal silicides, and this disclosure is not limited thereto.

[0113] In some embodiments, during process S2, see Figure 10 and Figure 11 Furthermore, the third portion N3 of the second protective film 129 is removed, the third portion N3 covering the surface of the gate 124 away from the substrate 110. During process S3, see... Figure 12 Furthermore, the portion of the gate dielectric film 128 corresponding to the third portion N3 is removed to expose the gate 124. During process S4, see... Figure 13A third conductive layer 133 is also formed covering the gate 124 so that the third conductive layer 133 is in electrical contact with the gate 124.

[0114] Furthermore, in some embodiments, during process S7, see... Figure 17 Furthermore, a third via 190 is formed, penetrating the interlayer dielectric layer 180 and the first protective layer 150, exposing the gate 124. During process S8, see... Figure 18 A third contact plug 193 is also formed; the third contact plug 193 is disposed in the third through hole 190 and is in electrical contact with the third conductive layer 133.

[0115] See Figure 19 In some embodiments, S1 includes S11 to S14.

[0116] S11: See also Figure 10 and Figure 19 A gate dielectric film 128 is formed on the first surface 111 of the substrate 110.

[0117] In the above steps, any one of the following processes can be used to form the initial gate dielectric film: chemical vapor deposition, physical vapor deposition, or plasma-enhanced deposition. Then, the portion of the initial gate dielectric film not located in the target region is removed by etching or other processes, thereby forming the gate dielectric film 128. It should be noted that the target region is the region of the preset gate 124 in the transistor region L.

[0118] S12: See also Figure 10 and Figure 19 A gate 124 is formed on the side of the gate dielectric film 128 away from the substrate 110.

[0119] In the above steps, any of the processes such as atomic layer deposition, physical vapor deposition, or chemical vapor deposition can be used to form the gate conductive layer. Then, the portion of the gate conductive layer that is not in the target area is removed by etching or other processes to form the gate 124.

[0120] S13: See also Figure 10 and Figure 19 A second protective film 129 is formed on the side of the gate 124 away from the substrate 110.

[0121] In the above steps, silicon nitride can be deposited on the side of the gate 124 away from the substrate 110 using chemical vapor deposition to form a second protective film 129. The second protective film 129 covers the entire transistor region L, that is, it covers the portion of the first surface 111 of the substrate 110 excluding the gate, the surface of the gate 124 away from the substrate 110, and the side surface of the gate 124.

[0122] S14: See also Figure 10 and Figure 19 The substrate 110 is ion-doped to form a source 121 and a drain 122 on both sides of the gate 124 in the transistor region L. The ion doping method can be ion implantation or ion diffusion.

[0123] See Figure 20 In some embodiments, before S11, S1 further includes S15 to S16 for forming an isolation groove 112 in the isolation region S (see...). Figure 8 ) and isolation layer 113 (see Figure 10 ) isolation structure.

[0124] S15: See also Figure 10 and Figure 20 This forms an isolation groove 112.

[0125] In the above steps, the isolation groove 112 extends from the first surface 111 of the substrate 110 into the substrate 110.

[0126] S16: See also Figure 10 and Figure 20 , forming an isolation layer 113.

[0127] In the above steps, the isolation layer 113 is located within the isolation groove 112, and the thickness of the isolation layer 113 is less than the depth of the isolation groove 112. The isolation layer 113 includes an insulating material, which may include at least one of silicon oxide, silicon oxynitride, ethoxysilane, low-temperature oxide, high-temperature oxide, and silicon nitride; this disclosure is not limited thereto.

[0128] Based on this, see Figure 8 The aforementioned isolation groove 112 includes a first opening segment 1121 and a second opening segment 1122. The first opening segment 1121 is closer to the second surface 114 of the substrate 110 relative to the second opening segment 1122. The second surface 114 is the side of the substrate 110 opposite to the first surface 111 among the two opposing main surfaces of the substrate 110. The isolation layer 113 is disposed in the first opening segment 1121.

[0129] Based on this, in process S2, see Figure 10 and Figure 11 Furthermore, the fourth portion N4 of the second protective film 129 is removed, and the fourth portion N4 covers the isolation layer 113 to form the in-groove protective layer 126. See also the process in S3. Figure 10 and Figure 12 Furthermore, the portion of the gate dielectric film 128 corresponding to the fourth portion N4 is removed to form the in-groove dielectric layer 125.

[0130] In some implementations, the isolation groove 112 further includes a third opening segment 1123 located on the side of the second opening segment 1121 away from the second surface 114. In this case,

[0131] During S2, see Figure 8 , Figure 10 and Figure 11 In step S3, the fifth portion N5 of the second protective film 129, which covers the sidewall of the third sub-opening segment 1123, is also removed. In step S4, see [link to S3 process]. Figure 8 , Figure 10 and Figure 13 A fourth conductive layer 134 is also formed covering the sidewall of the third sub-opening segment 1123 to further increase the size of the first contact plug 163 (see...). Figure 3 ) and second contact plug 173 (see Figure 3 The corresponding settings area.

[0132] See Figure 5 Some embodiments of this disclosure also provide an integrated circuit 200, which includes a semiconductor structure 100. The semiconductor structure 100 is the semiconductor structure 100 of the above embodiments or is fabricated by the methods described above for fabricating the semiconductor structure 100. The integrated circuit 200 may, for example, be a three-dimensional memory 300 (see...). Figure 3 The array 410 (see) is used to control and detect each memory cell string array. Figure 3 ( ) is a peripheral device that enables data storage and retrieval by controlling the switching state of the device.

[0133] The peripheral device may include, for example, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, and a series of other circuits 210 (see [link to relevant documentation]). Figure 3 The peripheral device includes a series of circuits 210 (see...). Figure 3 At least one of them includes the aforementioned semiconductor structure 100.

[0134] Please see Figure 3 Some embodiments of this disclosure also provide a three-dimensional memory 300, which includes an integrated circuit 200 and a memory array device 400 as described in some embodiments above. The memory array device 400 is electrically connected to the integrated circuit 200 to enable the integrated circuit 200 to support the functions of the memory array device 400, such as reading, writing and erasing data in the memory cells.

[0135] See Figure 3In some embodiments, the memory array device 400 includes a memory cell string array 410 and an array interconnect layer 420 disposed on the side of the memory cell string array 410 near the integrated circuit 200, with the memory cell string array 410 electrically connected to the array interconnect layer 420. The integrated circuit 200 includes a series of circuits 210, such as page buffers, and a peripheral interconnect layer 220 disposed on the side of the series of circuits 210 near the memory array device 400, with the series of circuits 210 electrically connected to the peripheral interconnect layer 220. The memory array device 400 and the integrated circuit 200 are electrically connected through the array interconnect layer 420 and the peripheral interconnect layer 220, thereby enabling the memory cell string array 410 to be electrically connected to the series of circuits 210.

[0136] Figure 1 This is a block diagram of a storage system 10 according to some embodiments. Figure 2 This is a block diagram of a storage system 10 according to some other embodiments. See also... Figure 1 and Figure 2 Some embodiments of this disclosure also provide a storage system 10. The storage system 10 includes a controller 500 and a three-dimensional memory 300 as described in some of the embodiments above, the controller 500 being coupled to the three-dimensional memory 300 to control the three-dimensional memory 300 to store data.

[0137] The storage system 10 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 10 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0138] In some embodiments, see Figure 1 The storage system 10 includes a controller 500 and a three-dimensional memory 300, and the storage system 10 can be integrated into a memory card.

[0139] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0140] In other embodiments, see Figure 2 The storage system 10 includes a controller 500 and multiple three-dimensional storage devices 300, and the storage system 10 is integrated into a solid state drive (SSD).

[0141] In some embodiments of the storage system 10, the controller 500 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0142] In other embodiments, the controller 500 is configured to operate in a high duty cycle environment using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0143] In some embodiments, the controller 500 may be configured to manage data stored in the 3D memory 300 and to communicate with external devices (e.g., a host). In some embodiments, the controller 500 may also be configured to control the operation of the 3D memory 300, such as read, erase, and program operations. In some embodiments, the controller 500 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory 300, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 500 is also configured to process error correction codes relating to data read from or written to the 3D memory 300.

[0144] Of course, controller 500 can also perform any other suitable functions, such as formatting the three-dimensional memory 300. For example, controller 500 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0145] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0146] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a transistor region and an isolation region located on at least one side of the transistor region; A transistor, disposed in the transistor region, includes: A source and a drain electrode, spaced apart, extend from a first surface of the substrate into the substrate; the first surface is one of two opposing main surfaces of the substrate. A gate dielectric layer is disposed on a first surface of the substrate and located between the source and the drain; and, A gate electrode is disposed on the side of the gate dielectric layer away from the substrate; and, A first conductive layer and a second conductive layer are disposed on a first surface of the substrate; the first conductive layer covers and electrically contacts the source electrode, and the area of ​​the first conductive layer is larger than the area of ​​the source electrode; the second conductive layer covers and electrically contacts the drain electrode, and the area of ​​the second conductive layer is larger than the area of ​​the drain electrode. An isolation structure is disposed in the isolation area; the isolation structure includes an isolation groove and an isolation layer, the isolation layer being located within the isolation groove, and the thickness of the isolation layer being less than the depth of the isolation groove; the isolation groove includes a first opening segment and a second opening segment, the first opening segment being closer to a second surface of the substrate relative to the second opening segment; the second surface is one of the two opposing main surfaces of the substrate opposite to the first surface; the isolation layer is disposed in the first opening segment; the isolation groove further includes a third opening segment located on the side of the second opening segment away from the second surface; A fourth conductive layer covers the sidewall of the third opening segment; in adjacent transistor regions and isolation regions, the first conductive layer and the second conductive layer closest to the fourth conductive layer are integrally disposed with the fourth conductive layer.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A first protective layer covers at least the gate, the first conductive layer, and the second conductive layer; A first connecting hole and a second connecting hole penetrate the first protective layer, with the first connecting hole exposing the first conductive layer and the second connecting hole exposing the second conductive layer.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: An interlayer dielectric layer covers the first protective layer; A first via and a second via penetrate the interlayer dielectric layer. The first via is connected to the first connecting hole, and the second via is connected to the second connecting hole. The first contact plug is disposed in the first through hole and the first connection hole, and is in electrical contact with the first conductive layer; The second contact plug is disposed in the second through hole and the second connection hole, and is in electrical contact with the second conductive layer.

4. The semiconductor structure according to claim 3, characterized in that, Also includes: A third conductive layer covers the surface of the gate away from the substrate and is in electrical contact with the gate; A third connection hole penetrates the first protective layer and exposes the gate. The third via penetrates the interlayer dielectric layer and communicates with the third connecting hole; The third contact plug is disposed in the third through hole and the third connecting hole, and is in electrical contact with the third conductive layer.

5. The semiconductor structure according to claim 4, characterized in that, The third conductive layer is made of the same material as the first conductive layer and the second conductive layer and is disposed in the same layer.

6. The semiconductor structure according to claim 2, characterized in that, The first protective layer also covers the isolation layer and the sidewalls in the isolation groove that are not covered by the isolation layer.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: The medium layer inside the tank covers the sidewall of the second opening section; An inner protective layer covers the inner medium layer, and the first protective layer covers the inner protective layer.

8. The semiconductor structure according to claim 2, characterized in that, The first protective layer covers the fourth conductive layer.

9. The semiconductor structure according to claim 1, characterized in that, The fourth conductive layer is made of the same material as the first conductive layer and the second conductive layer and is disposed in the same layer.

10. The semiconductor structure according to claim 7, characterized in that, The dielectric layer inside the trench is made of the same material as the gate dielectric layer and is disposed in the same layer.

11. The semiconductor structure according to claim 7, characterized in that, The transistor also includes a side protection layer that covers the side of the gate; The inner protective layer of the groove is made of the same material as the side protective layer and is installed in the same layer.

12. The semiconductor structure according to any one of claims 1 to 11, characterized in that, The materials of the first conductive layer and the second conductive layer include nickel silicon and / or cobalt silicon; When the semiconductor structure further includes a third conductive layer, the material of the third conductive layer includes nickel silicon and / or cobalt silicon; In the case where the semiconductor structure further includes a fourth conductive layer, the material of the fourth conductive layer includes nickel silicon and / or cobalt silicon.

13. The semiconductor structure according to any one of claims 1 to 11, characterized in that, The first conductive layer and the second conductive layer also cover the areas in the transistor region that are not covered by the gate dielectric layer.

14. The semiconductor structure according to any one of claims 1 to 11, characterized in that, Along the length of the channel of the transistor, the length of the transistor region is less than or equal to 70 nm.

15. A method for fabricating a semiconductor structure, characterized in that, include: Preparation of intermediate semiconductor structures; The intermediate semiconductor structure includes a transistor region; the intermediate semiconductor structure includes: a substrate; a source and a drain extending from a first surface of the substrate into the substrate and located in the transistor region, the first surface being one of two opposing main surfaces of the substrate; a gate dielectric film disposed on the first surface of the substrate; a gate disposed on the side of the gate dielectric film away from the substrate and located in the transistor region; and a second protective film covering the gate and the gate dielectric film. Remove the first portion and the second portion of the second protective film; the first portion covers the source electrode and has an area larger than the source electrode, and the second portion covers the drain electrode and has an area larger than the drain electrode; Remove the portions of the gate dielectric film corresponding to the first and second portions to expose the source and the drain. A first conductive layer covering the source electrode and a second conductive layer covering the drain electrode are formed, such that the first conductive layer is in electrical contact with the source electrode and the second conductive layer is in electrical contact with the drain electrode; The preparation of the intermediate semiconductor structure includes: A gate dielectric film is formed on the first surface of the substrate; A gate is formed on the side of the gate dielectric film away from the substrate; A second protective film is formed on the side of the gate away from the substrate; The substrate is ion-doped to form a source and a drain on both sides of the gate in the transistor region; Before forming a gate dielectric thin film on the first surface of the substrate, the fabrication of the intermediate semiconductor structure further includes: An isolation groove is formed, the isolation groove extending from a first surface of the substrate into the substrate; An isolation layer is formed, the isolation layer being located within the isolation groove, and the thickness of the isolation layer being less than the depth of the isolation groove; the isolation groove includes a first opening segment and a second opening segment, the first opening segment being closer to the second surface of the substrate relative to the second opening segment; the second surface is one of the two opposing main surfaces of the substrate opposite to the first surface; the isolation layer is disposed in the first opening segment; the isolation groove further includes a third opening segment located on the side of the second opening segment away from the second surface; During the process of removing the first and second portions of the second protective film, a fifth portion of the second protective film is also removed, which covers the sidewall of the third opening segment. During the process of removing the portions of the gate dielectric film corresponding to the first and second portions, the portion of the gate dielectric film corresponding to the fifth portion is also removed; During the formation of the first conductive layer and the second conductive layer, a fourth conductive layer is also formed that covers the sidewall of the third opening segment.

16. The preparation method according to claim 15, characterized in that, After forming the first conductive layer and the second conductive layer, the process further includes: A first protective layer is formed covering the transistor region; An interlayer dielectric layer is formed covering the first protective layer; A first via and a second via are formed, penetrating the interlayer dielectric layer and the first protective layer; the first via exposes the first conductive layer, and the second via exposes the second conductive layer. A first contact plug and a second contact plug are formed; the first contact plug is disposed in the first through hole and is in electrical contact with the first conductive layer; the second contact plug is disposed in the second through hole and is in electrical contact with the second conductive layer.

17. The preparation method according to claim 16, characterized in that, During the removal of the first and second portions of the second protective film, a third portion of the second protective film is also removed, the third portion covering the surface of the gate away from the substrate; During the process of removing the portions of the gate dielectric film corresponding to the first portion and the second portion, the portion of the gate dielectric film corresponding to the third portion is also removed to expose the gate. During the formation of the first conductive layer and the second conductive layer, a third conductive layer is also formed to cover the gate so that the third conductive layer is in electrical contact with the gate.

18. The preparation method according to claim 17, characterized in that, During the formation of the first via and the second via penetrating the interlayer dielectric layer and the first protective layer, a third via penetrating the interlayer dielectric layer and the first protective layer is also formed; the third via exposes the gate. During the formation of the first and second contact plugs, a third contact plug is also formed; the third contact plug is disposed in the third through hole and is in electrical contact with the third conductive layer.

19. The preparation method according to claim 15, characterized in that, During the process of removing the first and second portions of the second protective film, a fourth portion of the second protective film, which covers the isolation layer, is also removed. During the process of removing the portions of the gate dielectric film corresponding to the first and second portions, the portions of the gate dielectric film corresponding to the fourth portion are also removed.

20. An integrated circuit, characterized in that, Includes a semiconductor structure, wherein the semiconductor structure is any one of claims 1 to 14, or is prepared by the method for preparing the semiconductor structure according to any one of claims 15 to 19.

21. A three-dimensional memory, characterized in that, include: The integrated circuit as described in claim 20; The storage array device is in electrical contact with the integrated circuit.

22. A storage system, characterized in that, It includes a controller and a three-dimensional memory as described in claim 21, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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