A multi-channel digital adjustable attenuator device and an attenuation control method

Abstract

The present invention discloses a multi-channel digital adjustable attenuator device, which includes a multi-channel digital attenuation circuit and an FPGA for controlling the attenuation value of the digital attenuation circuit. The output end of the FPGA is respectively connected to the input end of the multi-channel digital attenuation circuit to provide a digital control signal for the attenuation value to the digital attenuation circuit. The present invention uses an FPGA and a digital attenuation chip to form a multi-channel digital adjustable attenuator, which is convenient for debugging and use. The actual attenuation value can be controlled by using commands, without the need to replace a fixed attenuator or adjust the circuit. Compared with the debugging of a multi-channel fixed attenuator, the device loss is greatly reduced, thereby reducing the use cost and greatly improving the test efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital communication testing, and particularly relates to a multi-channel digital adjustable attenuator device and an attenuation control method. Background Art

[0002] An attenuator is a commonly used device for signal attenuation in the communication field. Currently, the commonly used attenuators are mainly fixed attenuators. The attenuation gain of this kind of attenuator is fixed, such as 3dB, 20dB, 30dB, etc.

[0003] During mobile communication testing, especially during 5G mobile communication testing, in order to accurately detect the accuracy of signal output power adjustment of mobile communication devices, the attenuator needs to be adjusted every 1dB, that is, attenuation values such as 15dB, 14dB, 13dB, 12dB, etc. may be required.

[0004] During transmission use, fixed-value attenuators such as 1dB, 2dB, 3dB, 5dB, etc. need to be gradually accumulated to achieve the purpose of preset attenuation. And this kind of adjustment requires a lot of time for connection work. Moreover, each adjustment can only adjust one channel. For the testing of multiple devices and multiple channels, multiple channels need to be adjusted simultaneously, consuming a lot of time. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a multi-channel digital adjustable attenuator device and an attenuation control method. It can achieve digital adjustable attenuation of any natural value within the range of 1 - 90dB, and can simultaneously provide multiple channels for testing. Once the device is assembled and connected, subsequent attenuation value adjustment does not require adjusting the hardware device, only the control value needs to be changed, which is convenient to use, has high test efficiency, and low cost.

[0006] To solve the above problems, the technical solution adopted by the present invention is:

[0007] A multi-channel digital adjustable attenuator device includes a multi-channel digital attenuation circuit and an FPGA for controlling the attenuation value of the digital attenuation circuit. The output end of the FPGA is respectively connected to the input end of the multi-channel digital attenuation circuit to provide a digital control signal for the attenuation value of the digital attenuation circuit.

[0008] Further, each digital attenuation circuit includes a plurality of digital attenuation chips, coupling capacitors, and RF connectors. Among them, the input RF connector is connected to the RF input end of the first digital attenuation chip, the RF output end of the first digital attenuation chip is connected to the RF input end of the second digital attenuation chip through a capacitor, and so on. The RF output end of the Nth digital attenuation chip is connected to the output RF connector.

[0009] Preferably, each digital attenuation circuit includes three digital attenuation chips, and the maximum attenuation value of each digital attenuation chip > 30dB.

[0010] Further, at least one of the three digital attenuation chips has an attenuation step gain of 0.25 dB.

[0011] Preferably, the models of the three digital attenuation chips are two HMC1122L and one HMC1119 respectively.

[0012] Further, the FPGA is an FPGA supporting Ethernet communication, and the FPGA is connected to the three-wire serial interface of the digital attenuation chip; the FPGA is of the EP3C5E1 series with more available interfaces.

[0013] Further, it further includes a control device, and the FPGA is connected to the control device through a network cable.

[0014] Furthermore, it further includes a switch, and the control device is connected to the FPGA through the switch; the control device is a computer or a human-machine terminal with a network interface.

[0015] An attenuation control method for a multi-channel digital adjustable attenuator device includes the following steps:

[0016] S1. The FPGA obtains attenuation control information;

[0017] S2. The FPGA sets the attenuation channel n according to the attenuation control information;

[0018] S3. The FPGA sets the attenuation value m according to the attenuation control information, converts the attenuation value m into a digital control signal and outputs it to the digital attenuation circuit to complete the attenuation control.

[0019] Further, in step S1, the FPGA supports Ethernet communication, and the FPGA obtains the attenuation control information sent by the control device through network monitoring; in step S3, the digital attenuation circuit is composed of two HMC1122L and one HMC1119 digital attenuation chips. Step S3 specifically includes the following steps:

[0020] S31. The FPGA compares the attenuation value m with a preset threshold range according to the attenuation control information;

[0021] S32. When the attenuation value m ≤ 31 dB, both HMC1122L are set to 0 dB attenuation value, and HMC1119 is set to the m attenuation value;

[0022] S33. When 31 dB < the attenuation value m ≤ 60 dB, one HMC1122L is set to 0 dB attenuation value, one HMC1122L is set to 30 dB attenuation value, and HMC1119 is set to the m - 30 attenuation value;

[0023] S34. When 60dB < attenuation value m ≤ 90dB, both HMC1122Ls are set to an attenuation value of 30dB, and HMC1119 is set to an attenuation value of m - 60.

[0024] The beneficial effects produced by adopting the above technical solutions are as follows:

[0025] The present invention uses an FPGA and digital attenuation chips to form a multi-channel digitally tunable attenuator, which is convenient for debugging and use. The actual attenuation value can be controlled by commands, without the need to replace fixed attenuators or adjust circuits anymore. Compared with the debugging of multi-channel fixed attenuators, the device loss is greatly reduced, thereby reducing the usage cost and greatly improving the test efficiency. Description of the Drawings

[0026] Figure 1 is the principle block diagram of the present invention;

[0027] Figure 2 is the block diagram of one-way digital attenuation circuit of the present invention;

[0028] Figure 3 is the schematic diagram of one-way digital attenuation circuit of the present invention;

[0029] Figure 4 is the flow chart of the attenuation control method of the present invention. Detailed Embodiments

[0030] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] The present invention is a multi-channel digital adjustable attenuator device. The present invention utilizes the characteristic of the FPGA having multiple output pins to construct a multi-channel digital adjustable attenuator. The EP3C5E1 series FPGA can be used in the present invention to construct up to 16 or 32 attenuation test channels. The present invention uses two types of digital attenuation chips, namely HMC1119 and HMC1122L. HMC1119 is a broadband, high-precision, 7-bit digital attenuator with a working frequency range from 0.1 GHz to 6.0 GHz, providing a 31.5 dB attenuation control range in 0.25 dB steps. HMC1122 is a 6-bit digital attenuator with a working frequency range from 0.1 GHz to 6 GHz, providing a 31.5 dB attenuation control range in 0.5 dB steps. Cascading (connecting in series) multiple digital attenuation chips can form an attenuation circuit with any attenuation value. The present invention uses 1 HMC1119 and 2 HMC1122L cascaded to form a 90 dB digital attenuation circuit. By using two types of digital attenuation chips with different attenuation step values, an attenuation value with a step value of 0.25 dB can be obtained, making the control accuracy of the attenuation higher. It meets more application scenarios and saves costs.

[0032] As shown in Figure 1 the figure, the present invention includes a multi-channel digital attenuation circuit and an FPGA for controlling the attenuation value of the digital attenuation circuit. The output terminals of the FPGA are respectively connected to the input terminals of the multi-channel digital attenuation circuit to provide digital control signals for the attenuation value of the digital attenuation circuit.

[0033] As a preferred embodiment of the present invention, the FPGA described in the present invention is an FPGA supporting Ethernet communication. And the present invention further includes a control device, and the FPGA is connected to the control device through a network cable. Of course, if one control device is used to control the digital adjustable attenuation circuits composed of multiple FPGAs, a switch is also required, and the control device is connected to the FPGA through the switch, so that one control for multiple can be achieved. In a further preferred implementation scheme, the control device is a computer or a human-machine terminal with a network interface.

[0034] As shown in Figure 2 the figure, each channel digital attenuation circuit of the present invention includes multiple digital attenuation chips, coupling capacitors, and RF connectors. Among them, the input RF connector is connected to the RF input terminal of the first digital attenuation chip, the RF output terminal of the first digital attenuation chip is connected to the RF input terminal of the second digital attenuation chip through a capacitor, and so on. The RF output terminal of the Nth digital attenuation chip is connected to the output RF connector.

[0035] As shown in Figure 3As shown in the figure, as a preferred embodiment of the present invention, each digital attenuation circuit includes 1 digital attenuation chip HMC1119 and 2 digital attenuation chips HMC1122L. The 3 digital attenuation chips are connected in series in turn through coupling capacitors to form a 90dB digital attenuation circuit. Since the attenuation step of HMC1119 is 0.25dB, the adjustment accuracy of each digital attenuation circuit can reach 0.25dB. The HMC1119 is connected to the FPGA through a 3-wire serial interface (SERIN on pin 18, CLK on pin 17, LE on pin 16), rather than using the GPIO (data0 - data6) port. The HMC1122L is connected to the FPGA through a 3-wire serial interface (SERIN on pin 3, CLK on pin 2, LE on pin 4), rather than using the GPIO (data0 - data5) port. This can save a large number of pins of the FPGA and can form more attenuation circuit channels. And using a 3-wire serial interface for control is relatively simple, and the circuit structure is also relatively simple.

[0036] In order to enable an FPGA to form more attenuation circuit channels, the FPGA selects the EP3C5E1 series with more available interfaces.

[0037] For the present invention, the attenuation control method based on the above digital adjustable attenuator device includes the following steps:

[0038] S1. The FPGA obtains attenuation control information;

[0039] S2. The FPGA sets the attenuation channel n according to the attenuation control information;

[0040] S3. The FPGA sets the attenuation value m according to the attenuation control information, converts the attenuation value m into a digital control signal and outputs it to the digital attenuation circuit to complete the attenuation control.

[0041] The control flow chart of the present invention is as Figure 4 shown. As a preferred embodiment of the present invention: in step S1, the FPGA supports Ethernet communication, and the FPGA obtains the attenuation control information sent by the control device through network monitoring; in step S3, the digital attenuation circuit is composed of two HMC1122L and one HMC1119 digital attenuation chip. Step S3 specifically includes the following steps:

[0042] S31. The FPGA compares the attenuation value m with a preset threshold range according to the attenuation control information;

[0043] S32. When the attenuation value m ≤ 31dB, both HMC1122L are set to an attenuation value of 0dB, and HMC1119 is set to an attenuation value of m;

[0044] S33. When 31 dB < attenuation value m ≤ 60 dB, one HMC1122L is set to an attenuation value of 0 dB, one HMC1122L is set to an attenuation value of 30 dB, and HMC1119 is set to an attenuation value of m - 30;

[0045] S34. When 60 dB < attenuation value m ≤ 90 dB, both HMC1122Ls are set to an attenuation value of 30 dB, and HMC1119 is set to an attenuation value of m - 60.

[0046] The above steps are the process of setting a digital attenuation circuit for one path. The setting methods and steps for other paths are the same as this path. In actual operation, the multi-path digital attenuation circuits use the same hardware circuit. In program control, different addresses are defined for each chip in each digital attenuation circuit so that the program can allocate the attenuation value to different digital attenuation chips.

Claims

1. An attenuation control method for a multi-channel digital adjustable attenuator device, comprising the following steps: S1. The FPGA obtains attenuation control information; S2. The FPGA sets attenuation channel n according to the attenuation control information; S3. The FPGA sets attenuation value m according to the attenuation control information, converts the attenuation value m into a digital control signal and outputs it to the digital attenuation circuit to complete attenuation control; In step S1, the FPGA supports Ethernet communication, and the FPGA listens for the attenuation control information sent by the control device through the network; the digital attenuation circuit in step S3 consists of two HMC1122Ls and one HMC1119 digital attenuation chip. Step S3 specifically includes the following steps: S31. The FPGA compares the attenuation value m with a preset threshold range according to the attenuation control information; S32. When the attenuation value m ≤ 31 dB, both HMC1122Ls are set to 0 dB attenuation value, and HMC1119 is set to m attenuation value; S33. When 31 dB < attenuation value m ≤ 60 dB, one HMC1122L is set to 0 dB attenuation value, one HMC1122L is set to 30 dB attenuation value, and HMC1119 is set to m - 30 attenuation value; S34. When 60 dB < attenuation value m ≤ 90 dB, both HMC1122Ls are set to 30 dB attenuation value, and HMC1119 is set to m - 60 attenuation value.

2. A multi-channel digital variable attenuator device, which is applied to the attenuation control method of the multi-channel digital variable attenuator device described in claim 1, and is characterized in that: It includes a multi-channel digital attenuation circuit and an FPGA for controlling the attenuation value of the digital attenuation circuit. The output end of the FPGA is respectively connected to the input end of the multi-channel digital attenuation circuit to provide a digital control signal of the attenuation value for the digital attenuation circuit.

3. The multi-channel digital adjustable attenuator device according to claim 2, characterized in that: Each digital attenuation circuit includes multiple digital attenuation chips, coupling capacitors and RF connectors. Among them, the input RF connector is connected to the RF input end of the first digital attenuation chip, the RF output end of the first digital attenuation chip is connected to the RF input end of the second digital attenuation chip through a capacitor, and so on. The RF output end of the Nth digital attenuation chip is connected to the output RF connector.

4. The multi-channel digital adjustable attenuator device according to claim 3, characterized in that: Each digital attenuation circuit includes three digital attenuation chips, and the maximum attenuation value of each digital attenuation chip > 30 dB.

5. A multi-channel digital adjustable attenuator device according to claim 4, characterized in that: At least one of the three digital attenuation chips has an attenuation step gain of 0.25 dB.

6. The multi-channel digital adjustable attenuator device according to claim 5, characterized in that: The models of the three digital attenuation chips are two HMC1122Ls and one HMC1119 respectively.

7. A multi-channel digital adjustable attenuator device according to any one of claims 3-6, characterized in that: The FPGA is an FPGA that supports Ethernet communication, and the FPGA is connected to the three-wire serial interface of the digital attenuation chip; the FPGA is of the EP3C5E1 series with more available interfaces.

8. A multi-channel digital adjustable attenuator device according to claim 2, characterized in that: It further includes a control device, and the FPGA is connected to the control device through a network cable.

9. The multi-channel digital adjustable attenuator device according to claim 8, wherein: It further includes a switch, and the control device is connected to the FPGA through the switch; the control device is a computer or a human-machine terminal with a network interface.

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