Circuit devices and real-time clock devices

Abstract

The system provides circuitry and a real-time clock, with a power-on reset circuit capable of releasing the reset at a desired voltage. The circuitry includes a comparator, a reference voltage generation circuit, and a connection control circuit. The comparator compares the monitored voltage, generated based on the power supply voltage, with the reference voltage, thereby outputting a power-on reset signal. The reference voltage generation circuit generates the reference voltage. The connection control circuit is connected between the power supply voltage node and the reference voltage node. The connection control circuit connects the reference voltage node and the power supply voltage node for a specified period after the power supply voltage is applied.

Description

Technical Field

[0001] This invention relates to circuit devices and real-time clock devices, etc. Background Technology

[0002] Power-on reset circuits are known to generate an internal reset signal when the circuit is powered on or when the power supply voltage drops. Patent Document 1 discloses a power-on reset circuit in a combined IC card having a contactless interface and a contact interface, which changes the threshold of the internal reset signal based on an externally supplied reset signal.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-123168

[0004] The power-on reset circuit described in Patent Document 1 generates an internal reset signal by comparing the voltage after the power supply voltage is divided with the reference voltage generated by the regulator.

[0005] When the initial power is turned on, there may be issues such as the rising edge of the reference voltage not following the power supply voltage, or instability in the performance of the regulator that generates the reference voltage. Due to this instability, the power-on reset circuit may release the reset with an unwanted voltage. Summary of the Invention

[0006] One aspect of this disclosure relates to a circuit arrangement comprising: a comparator that compares a monitored voltage generated based on a power supply voltage with a reference voltage, thereby outputting a power-on reset signal; a reference voltage generation circuit that generates the reference voltage and outputs the reference voltage to a reference voltage node; and a connection control circuit connected between a power supply voltage node supplied with the power supply voltage and the reference voltage node, the connection control circuit connecting the reference voltage node and the power supply voltage node for a predetermined period after the power supply voltage is turned on.

[0007] Another aspect of the present invention relates to a real-time clock device comprising: the circuit arrangement described above; and an oscillator, the circuit arrangement comprising: a regulator that, when the power supply voltage is set to a first power supply voltage, generates a second power supply voltage as the voltage of the monitored object based on the first power supply voltage; a processing circuit that operates according to the second power supply voltage, resetting and de-resetting via the power-on reset signal; and an oscillation circuit that causes the oscillator to oscillate, thereby generating a clock signal, the processing circuit comprising a timing circuit that performs timing processing based on the clock signal. Attached Figure Description

[0008] Figure 1 This is an example of the basic structure of a power-on reset circuit and circuit device.

[0009] Figure 2 This is a waveform diagram illustrating the first action of the power-on reset circuit in the basic structural example.

[0010] Figure 3 This is a waveform diagram illustrating the second operation of the power-on reset circuit in the basic structural example.

[0011] Figure 4 This is an example of the structure of a power-on reset circuit and circuit device.

[0012] Figure 5 This is a detailed structural example of a CR circuit.

[0013] Figure 6 It is a waveform diagram illustrating the operation of the CR circuit and the switch.

[0014] Figure 7 It is a waveform diagram illustrating the operation of the power-on reset circuit.

[0015] Figure 8 Examples of the structure of a real-time clock device, and examples of the structure of the circuitry included in a real-time clock device.

[0016] Figure 9 This is a detailed structural example of a power supply circuit.

[0017] Label Explanation

[0018] 10: Oscillator; 100: Circuit device; 110: Power supply circuit; 114: Switch control circuit; 115: First detection circuit; 116: Second detection circuit; 120: Processing circuit; 121: Timing circuit; 122: Temperature compensation circuit; 130: Power-on reset circuit; 131: Bias circuit; 132: Reference voltage generation circuit; 133: Comparator; 135: Connection control circuit; 136: CR circuit; 150: Oscillation circuit; 151-153: Regulator; 160: Temperature detection circuit; 170: Interface circuit; 200: Real-time clock device; CE: Electric Container; CRQ: Control signal; IE1: First inverter; IE2: Second inverter; NVDD: Power supply voltage node; NVREF: Reference voltage node; NVSS: Ground node; PORQ: Power-on reset signal; SWPU: Switch; TB1: Depletion-mode N-type transistor; TB2: Enhancement-mode N-type transistor; TE1: First P-type transistor; TE2: Second P-type transistor; TE3: N-type transistor; VBAT: Battery voltage; VDD: Power supply voltage; VLOG: Power supply voltage; VREF: Reference voltage; VSS: Ground voltage; Vof: Offset voltage. Detailed Implementation

[0019] The preferred embodiments of this disclosure will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and the structures described in these embodiments are not necessarily all essential structural elements.

[0020] 1. Basic Structure Example

[0021] First, the basic structure of the power-on reset circuit 130 and its related issues will be explained. Then, in Figure 4 The following will describe a structural example of the power-on reset circuit 130 of this embodiment. However, the basic structural example has the same characteristics as... Figure 4 The structural element is the same as the structural example, and regarding this structural element, it plays the same role as... Figure 4 The structural example has the same effect. Regarding this, in Figure 4 This will be explained later.

[0022] Figure 1 This is a basic structural example of the power-on reset circuit 130 and the circuit device 100. The circuit device 100 includes the power-on reset circuit 130 and the regulator 153. The power-on reset circuit 130 includes a bias circuit 131, a reference voltage generation circuit 132, and a comparator 133.

[0023] The power supply voltage VDD is supplied to the bias circuit 131. The bias circuit 131 generates a bias voltage VNA based on the power supply voltage VDD and outputs the bias voltage VNA to the reference voltage generation circuit 132 and the comparator 133. The power supply voltage VDD is supplied from outside the circuit device 100.

[0024] The power supply voltage VLOG is provided to the reference voltage generation circuit 132. The reference voltage generation circuit 132 generates a reference voltage VREF based on the power supply voltage VLOG and outputs the reference voltage VREF to the comparator 133. The power supply voltage VLOG is the internal power supply voltage of the circuit device 100, and the regulator 153 generates the power supply voltage VLOG based on the power supply voltage VDD.

[0025] The power supply voltage VLOG is provided to comparator 133. Comparator 133 compares the power supply voltage VLOG, which is the monitored voltage, with the reference voltage VREF, and outputs the result as the power-on reset signal PORQ. The monitored voltage refers to the voltage that the power-on reset circuit 130 monitors to determine the switching between reset and reset release. When the power supply voltage VLOG is lower than the determination voltage VREF+Vof, comparator 133 outputs the power-on reset signal PORQ indicating reset; when the monitored voltage is higher than the determination voltage VREF+Vof, it outputs the power-on reset signal PORQ indicating reset release. Vof is the input offset of comparator 133. That is, Vof is the offset voltage of the differential pair between the input monitored voltage and the reference voltage VREF. Furthermore, hereinafter, the power-on reset signal PORQ indicating reset is assumed to be low, and the power-on reset signal PORQ indicating reset release is assumed to be high.

[0026] Figure 2 This is an explanation Figure 1 The waveform diagram of the first operation of the power-on reset circuit 130. Figure 2 In this case, we assume that the power supply voltage VDD increases at a relatively slow rate over time.

[0027] Vtlg is the logic threshold voltage of the logic circuit that receives the power-on reset signal PORQ. That is, when the power supply voltage VLOG of comparator 133 is lower than the logic threshold voltage Vtlg, the logic level of the power-on reset signal PORQ is uncertain for the logic circuit. When the power supply voltage VLOG is higher than the logic threshold voltage Vtlg, the logic level of the power-on reset signal PORQ is determined to be either low or high for the logic circuit.

[0028] Set a reference voltage VREF and an offset voltage Vof such that the judgment voltage VREF+Vof after the reference voltage VREF converges to a specified voltage is higher than the threshold voltage Vtlg.

[0029] After the circuit device 100 is powered on by the power supply voltage VDD, the power supply voltage VLOG generated by the regulator 153 rises following the power supply voltage VDD. When the power supply voltage VDD rises with a relatively gradual time change, the reference voltage VREF rises following the power supply voltage VLOG. Therefore, the power supply voltage VLOG and the reference voltage VREF become approximately the same voltage and rise, exceeding the logic threshold voltage Vtlg when the power supply voltage VLOG is lower than the decision voltage VREF+Vof. Let this time be T1. Before time T1, the logic level of the power-on reset signal PORQ is uncertain; at time T1, the logic level of the power-on reset signal PORQ is determined to be low. Furthermore, in Figure 2 In Chinese, "X" is used to indicate uncertainty.

[0030] The reference voltage VREF converges to the specified voltage, and then the power supply voltage VLOG exceeds the judgment voltage VREF+Vof. Let this moment be T2. At time T2, the voltage of the power-on reset signal PORQ changes from the ground voltage VSS to the power supply voltage VLOG, and its logic level changes from low to high. That is, at time T2, the power-on reset circuit 130 outputs the power-on reset signal PORQ indicating that the reset is released.

[0031] In the first action described above, during the period from time T1 to T2, after outputting the power-on reset signal PORQ indicating reset, a power-on reset signal PORQ indicating reset release is output at time T2. Thus, the circuit that received the power-on reset signal PORQ is normally reset and de-reset.

[0032] Figure 3 This is an explanation Figure 1 The waveform diagram of the second operation of the power-on reset circuit 130. Figure 3 In this case, we assume that the power supply voltage VDD increases with a relatively rapid change over time.

[0033] After the power supply voltage VDD is switched on to the circuit device 100, the power supply voltage VLOG generated by the regulator 153 rises in line with the power supply voltage VDD. When the power supply voltage VDD rises with a relatively rapid change in time, the reference voltage VREF does not follow the power supply voltage VLOG. The rate of rise of the reference voltage VREF is determined by factors such as the current flowing through the reference voltage generation circuit 132. When the rate of rise of the power supply voltage VDD is faster than the rate of rise of the reference voltage VREF, the reference voltage VREF does not follow the power supply voltage VLOG. For example, when reducing the current flowing to the reference voltage generation circuit 132 to reduce power consumption, the state in which the reference voltage VREF does not follow the power supply voltage VLOG is likely to occur.

[0034] Since the power supply voltage VLOG follows the power supply voltage VDD, while the reference voltage VREF does not, the power supply voltage VLOG exceeds the decision voltage VREF+Vof before it exceeds the logic threshold voltage Vtlg. At time T1 when the power supply voltage VLOG exceeds the logic threshold voltage Vtlg, the logic level of the power-on reset signal PORQ is determined. However, at a previous time T2, the power supply voltage VLOG exceeds the decision voltage VREF+Vof, so at time T1, the logic level of the power-on reset signal PORQ is determined to be high.

[0035] In the second operation, at time T2, the power-on reset circuit 130 internally determines that the reset is released. However, at this time, the reference voltage VREF does not converge to the specified voltage, and the determination voltage VREF+Vof does not become the expected voltage. Therefore, the power-on reset signal PORQ indicating a reset is not output, while the power-on reset signal PORQ indicating a reset is output at time T1. The circuit that received the power-on reset signal PORQ cannot reset normally.

[0036] As described above, depending on the characteristics of the rising waveform and time variation of the power supply voltage VDD, power supply voltage VLOG, and reference voltage VREF when the power supply voltage is turned on, or the voltage conditions, it is possible that the power-on reset circuit 130 may be de-reset even though the voltage of the monitored object does not exceed the desired judgment voltage. As described above, the same problem also occurs in the prior art such as Patent Document 1.

[0037] 2. Structural Example

[0038] Figure 4 This is a structural example of the power-on reset circuit 130 and circuit device 100 in this embodiment. Figure 4 The power-on reset circuit 130 includes a bias circuit 131, a reference voltage generation circuit 132, a comparator 133, and a connection control circuit 135. Additionally, for... Figure 1 Structural elements that are identical to those described in the text are assigned the same labels. For content that has already been described about a structural element, its description is omitted appropriately.

[0039] Comparator 133 compares the monitored voltage generated based on the power supply voltage VDD with the reference voltage VREF and outputs a power-on reset signal PORQ. Reference voltage generation circuit 132 generates the reference voltage VREF and outputs it to the reference voltage node NVREF. Connection control circuit 135 is connected between the power supply voltage node NVDD (input power supply voltage VDD) and the reference voltage node NVREF. Connection control circuit 135 connects the reference voltage node NVREF and the power supply voltage node NVDD for a specified period after the power supply voltage VDD is turned on.

[0040] exist Figure 4In this circuit, the monitored voltage is the power supply voltage VLOG generated by the regulator 153 based on the power supply voltage VDD. However, the monitored voltage is not limited to the power supply voltage VLOG; it can be any voltage generated by some voltage generation circuit based on the power supply voltage VDD. Furthermore, the length of the specified period can be arbitrary. For example, the specified period can be longer than the time it takes for the reference voltage VREF to converge to the specified voltage after the power supply voltage VDD is turned on. Alternatively, the specified period can be longer than the time it takes for the monitored voltage to exceed the logic threshold voltage Vtlg after the power supply voltage VDD is turned on. Since the time it takes for the reference voltage VREF to converge to the specified voltage and the time it takes for the monitored voltage to exceed the logic threshold voltage Vtlg after the power supply voltage VDD is turned on vary depending on the rising waveform of the power supply voltage VDD, for example, a specified period with a margin for such variation can be set.

[0041] According to this embodiment, during a predetermined period after the power supply voltage VDD is applied to the circuit device 100, the connection control circuit 135 connects the reference voltage node NVREF and the power supply voltage node NVDD. Therefore, during this predetermined period, the monitored voltage will not exceed the determination voltage VREF+Vof. Then, after the predetermined period has elapsed, the connection control circuit 135 disconnects the connection between the reference voltage node NVREF and the power supply voltage node NVDD, thereby causing the reference voltage VREF to converge to the desired predetermined voltage. Thus, after the reference voltage VREF converges to the desired predetermined voltage, the comparator 133 can compare the monitored voltage and the reference voltage VREF. That is, according to this embodiment, the power-on reset circuit 130 does not determine that the reset is released until the monitored voltage exceeds the desired determination voltage VREF+Vof.

[0042] Furthermore, the reset is not considered released within the specified period, thus allowing the reset to be released after the power supply voltage VLOG and the reference voltage VREF have stabilized. Therefore, as described above... Figure 3 As shown, even when the reference voltage VREF does not follow the power supply voltage VDD, in this embodiment, a reset release is determined after the monitored voltage exceeds the desired determination voltage. Furthermore, when the power supply voltage VDD rises, the internal power supply voltage of the circuit device 100, i.e., the power supply voltage VLOG, may exhibit unstable performance such as overshoot. In this embodiment, since a reset release is not determined within a specified period, the reset of the circuit supplied with the power supply voltage VLOG is only released after the power supply voltage VLOG stabilizes.

[0043] The following is a detailed explanation. Figure 4 Example of a structure.

[0044] The bias circuit 131 includes P-type transistors TA1 and TA2, depletion-type N-type transistors TA3 and TA4. Additionally, the transistors not referred to as depletion-type are enhancement-type.

[0045] The sources of P-type transistors TA1 and TA2 are connected to the power supply voltage node NVDD, which supplies the power supply voltage VDD. The drain of P-type transistor TA1 is connected to the gates of P-type transistors TA1 and TA2, the drain of N-type transistor TA3, and the bias node NVRP. The source and gate of N-type transistor TA3 are connected to the ground node NVSS, which supplies the ground voltage VSS. The drain of P-type transistor TA2 is connected to the drain and gate of N-type transistor TA4, and the bias node NVNA. The source of N-type transistor TA4 is connected to the ground node NVSS. Furthermore, the ground voltage VSS only needs to be a power supply voltage lower than the power supply voltage VDD and the power supply voltage VLOG, which is the voltage being monitored.

[0046] The leakage current of N-type transistor TA3 flows through P-type transistor TA1, thereby generating a bias voltage VRP. Bias circuit 131 outputs the bias voltage VRP from the bias node NVRP to the control circuit 135 and comparator 133. The leakage current of N-type transistor TA3 is mirrored by P-type transistor TA2, whose leakage current flows through N-type transistor TA4, thereby generating a bias voltage VNA. Bias circuit 131 outputs the bias voltage VNA from the bias node NVNA to the reference voltage generation circuit 132 and comparator 133.

[0047] The reference voltage generation circuit 132 includes depletion-type N-type transistors TB1 and TB2.

[0048] The drain of N-type transistor TB1 is connected to the power supply voltage node NVDD, and its source is connected to the drain of N-type transistor TB2 and the reference voltage node NVREF. The source of N-type transistor TB2 is connected to the ground node NVSS. The gates of N-type transistors TB1 and TB2 are connected to the bias node NVNA.

[0049] A bias voltage VNA is applied to the gates of N-type transistors TB1 and TB2, causing current to flow through them. The reference voltage VREF is determined based on this current and the dimensions of N-type transistors TB1 and TB2. Here, the reference voltage VREF is a reference voltage that converges to a predetermined voltage. For example, by changing the mirror ratio of N-type transistors TA4 and TB2, the current flowing through N-type transistor TB1 changes, thus allowing adjustment of the reference voltage VREF. Alternatively, by changing the dimensions of N-type transistor TB1, the source-drain voltage of N-type transistor TB1 changes, thus allowing adjustment of the reference voltage VREF. The transistor dimensions may be, for example, gate length, gate width, or both.

[0050] Comparator 133 includes N-type transistors TC1 to TC6 and P-type transistors TC7 to TC9.

[0051] The sources of P-type transistors TC7 and TC8 are connected to the monitored object node NVLOG to which the monitored object voltage is supplied. The gate and source of P-type transistor TC7 are connected to the gate of P-type transistor TC8 and the drain of N-type transistor TC1. The drain of P-type transistor TC8 is connected to the drain of N-type transistor TC2 and the gate of P-type transistor TC9. The sources of N-type transistors TC1 and TC2 are connected to the drain of N-type transistor TC3. The gate of N-type transistor TC1 is connected to the reference voltage node NVREF, and the gate of N-type transistor TC2 is connected to the monitored object node NVLOG. The source of N-type transistor TC3 is connected to the drain of N-type transistor TC4, and the gate is connected to the bias node NVNA. The source of N-type transistor TC4 is connected to the ground node NVSS, and the gate is connected to the bias node NVNB. A bias voltage VNB is output from a bias circuit (not shown) to the bias node NVNB.

[0052] The source of P-type transistor TC9 is connected to the monitored object node NVLOG, and the source is connected to the drain of N-type transistor TC5 and the output node NPORQ of the power-on reset circuit 130. The source of N-type transistor TC5 is connected to the drain of N-type transistor TC7, and the gate is connected to the bias node NVNA. The source of N-type transistor TC6 is connected to the ground node NVSS, and the gate is connected to the bias node NVNB.

[0053] N-type transistors TC1 and TC2 form a differential pair. The gate of N-type transistor TC1 corresponds to the negative input node of comparator 133, and the gate of N-type transistor TC2 corresponds to the positive input node of comparator 133. A reference voltage VREF is input to the negative input node, and a power supply voltage VLOG is input to the positive input node. When VLOG > VREF, comparator 133 outputs a power-on reset signal PORQ of the power supply voltage VLOG to the output node NPORQ. When VLOG < VREF, comparator 133 outputs a power-on reset signal PORQ of the ground voltage VSS to the output node NPORQ.

[0054] The connection control circuit 135 includes a CR circuit 136 and a switch SWPU. The switch SWPU is composed of a transistor, which is assumed to be a P-type transistor here. <00​​​​The CR circuit 136 outputs a control signal CRQ to the control signal node NCRQ based on the power supply voltage VDD, used to control the switch SWPU to be on or off. For a specified period after the power supply voltage VDD is turned on, the CR circuit 136 maintains the control signal CRQ at a low level, thereby keeping the switch SWPU on. After the specified period has elapsed, the CR circuit 136 changes the control signal CRQ from low to high, thereby changing the switch SWPU from on to off.

[0057] In this embodiment described above, the connection control circuit 135 includes a switch SWPU and a CR circuit 136. The switch SWPU is located between the power supply voltage node NVDD and the reference voltage node NVREF. The CR circuit 136 outputs a control signal CRQ to the switch SWPU. After a predetermined period has elapsed since the power supply voltage VDD was turned on, the control signal CRQ controls the switch SWPU to turn off.

[0058] According to this embodiment, during a specified period after the power supply voltage VDD is turned on, the switch SWPU is turned on, so the reference voltage node NVREF is connected to the power supply voltage node NVDD.

[0059] Therefore, during the specified period after the power supply voltage VDD is turned on, the reference voltage VREF input to comparator 133 becomes the power supply voltage VDD. Furthermore, after the specified period has elapsed, the switch SWPU changes from on to off, so comparator 133 can compare the reference voltage VREF with the voltage of the monitored object.

[0060] Furthermore, in this embodiment, the reference voltage generation circuit 132 generates a reference voltage VREF based on the power supply voltage VDD.

[0061] When the switch SWPU connects the reference voltage node NVREF and the power supply voltage node NVDD, the power supply voltage node NVDD and the source of N-type transistor TB2 are connected via the switch SWPU and N-type transistor TB1. Different power supply voltages, such as power supply voltages VDD and VLOG, are preferably not connected; however, according to this embodiment, the source of N-type transistor TB2 is connected to the power supply voltage node NVDD.

[0062] In this embodiment, the reference voltage generation circuit 132 includes a depletion-type N-type transistor TB1 and an enhancement-type N-type transistor TB2. The depletion-type N-type transistor TB1 is disposed between the power supply voltage node NVDD and the reference voltage node NVREF, and its gate is biased by an input voltage VNA. The enhancement-type N-type transistor TB2 is disposed between the reference voltage node NVREF and the ground node NVSS, and its gate is biased by an input voltage VNA.

[0063] According to this embodiment, the minimum power supply voltage VDD required for comparator 133 to operate normally can be reduced. Normal operation of comparator 133 means that the transistors contained in comparator 133 operate in the saturation region.

[0064] For example, one could consider omitting the reference voltage generation circuit 132 of this embodiment and instead making the N-type transistor TC1 of comparator 133 depletion-type, with its gate connected to the ground node NVSS. When the offset voltage of the differential pair in this structure is set to Vof', the reset release determination voltage is Vof'. Consider the case where, due to process variations, for example, the threshold voltage of the P-type transistor increases while the threshold voltage of the N-type transistor decreases. In this case, before the power supply voltage VLOG drops to the determination voltage Vof', the P-type transistor TC8 cannot maintain its saturation region, the P-type transistor TC9 turns on, and the power-on reset signal PORQ becomes high, potentially releasing the reset. Therefore, it is necessary to make the minimum value of the power supply voltage VLOG, which should be near the determination voltage Vof', higher than the determination voltage Vof'. Since the power supply voltage VDD needs to be at least higher than the minimum value of the power supply voltage VLOG, the minimum value of the power supply voltage VDD also needs to be increased.

[0065] Regarding this point, according to this embodiment, by providing the reference voltage generation circuit 132 with the above-described structure, the N-type transistor TC1 of the differential pair can be made enhancement-mode, and the offset voltage of the differential pair can be reduced. As described above, by adjusting the dimensions of the N-type transistors TB1 and TB2 constituting the reference voltage generation circuit 132, the reference voltage VREF can be adjusted. By reducing the offset voltage of the differential pair and adjusting the reference voltage VREF, the minimum value of the power supply voltage VDD for normal operation of the comparator 133 can be reduced.

[0066] For use later Figure 8 As described herein, for example, a power-on reset circuit 130 is used in the circuit arrangement 100 of the real-time clock device 200. In a system including the real-time clock device 200 and a processor such as a CPU or microcomputer, the power supply voltage VDD is the system power supply voltage provided to the processor and the real-time clock device 200. In such a system, the real-time clock device 200 performs timing even when the processor is not working, therefore it is required that the real-time clock device 200 operate even at a low power supply voltage VDD when the processor is not working. Therefore, the lower the minimum value of the power supply voltage VDD, the better, and according to this embodiment, the minimum value of the power supply voltage VDD can be minimized.

[0067] In addition, Figure 1 In the circuit, the power supply voltage VLOG is provided to the reference voltage generation circuit 132, but the structures of transistors TB1 and TB2 are different from those of the reference voltage generation circuit 132. Figure 4The same applies. Therefore, the effect of reducing the minimum value of the power supply voltage VDD for comparator 133 to operate normally is achieved in... Figure 1 The same applies to the basic structural examples.

[0068] Figure 5 This is a detailed structural example of CR circuit 136. CR circuit 136 includes a first P-type transistor TE1, a second P-type transistor TA2, an N-type transistor TE3, a capacitor CE, a first inverter IE1, and a second inverter IE2.

[0069] The CR circuit outputs a control signal CRQ to the switch SWPU. After a predetermined period determined by the capacitance value of capacitor CE, the control signal CRQ changes from active to inactive. When the control signal CRQ changes from active to inactive, the switch SWPU changes from on to off. Furthermore, active is the logic level that turns the switch SWPU on, which is low. Inactive is the logic level that turns the switch SWPU off, which is high.

[0070] According to this embodiment, a predetermined period is set based on the capacitance value of capacitor CE, and a control signal CRQ is output that changes from active to inactive after the predetermined period has elapsed. Specifically, when the voltage at one end of capacitor CE is set to CROUT, the length of the predetermined period is determined based on the rate of change of voltage CROUT over time. The rate of change of voltage CROUT over time is determined by the capacitance value of capacitor CE and the current flowing through one end of capacitor CE.

[0071] The first P-type transistor TE1 is positioned between the power supply voltage node NVDD and one end of the capacitor CE. The gate of the first P-type transistor TE1 is biased by an input voltage VRP. Specifically, the source of the first P-type transistor TE1 is connected to the power supply voltage node NVDD, the drain is connected to one end of the capacitor CE, and the gate is connected to the bias node NVRP. The other end of the capacitor CE is connected to the ground node NVSS.

[0072] According to this embodiment, the first P-type transistor TE1 becomes a constant current source, charging the capacitor CE by inputting a constant current to one end of the capacitor CE. The length of the predetermined period is determined based on the value of the constant current and the capacitance value of the capacitor CE.

[0073] The drain of the N-type transistor TE3 is connected to one end of the capacitor CE, and the source and gate are connected to the ground node.

[0074] The first P-type transistor TE1 has a parasitic diode forward-biased from one end of capacitor CE toward the power supply voltage node NVDD, and the N-type transistor TE3 has a parasitic diode forward-biased from one end of capacitor CE toward the ground node NVSS. The forward voltage of these parasitic diodes is defined as Vdiode. Before the power supply voltage VDD is turned on, when the voltage is near ground, the voltage CROUT at one end of capacitor CE is in the range of -Vdiode to +Vdiode through the parasitic diodes. Therefore, when the power supply voltage VDD is turned on, the voltage CROUT at one end of capacitor CE rises from a roughly determined voltage, allowing it to remain approximately constant for a specified period.

[0075] The voltage CROUT is applied to one end of the capacitor CE in the first inverter IE1. The output signal IE1Q of the first inverter IE1 is applied to the second inverter IE2, and the second inverter IE2 outputs a control signal CRQ. The second P-type transistor TE2 is positioned between the power supply voltage node NVDD and one end of the capacitor CE, and its gate is input to the output signal IE1Q of the first inverter IE1. Specifically, the source of the second P-type transistor TE2 is connected to the power supply voltage node NVDD, the drain is connected to one end of the capacitor CE, and the gate is connected to the output node of the first inverter IE1.

[0076] According to this embodiment, the first inverter IE1 changes the output signal IE1Q from high to low when the voltage CROUT at one end of the capacitor CE exceeds the logic threshold voltage. The second inverter IE2 outputs the logic inverted signal of the output signal IE1Q as the control signal CRQ, and therefore changes the control signal CRQ from low to high when the output signal IE1Q changes from high to low. Thus, the period from the power supply voltage VDD being applied until the voltage CROUT at one end of the capacitor CE exceeds the logic threshold voltage is defined as a predetermined period.

[0077] Furthermore, according to this embodiment, when the output signal IE1Q of the first inverter IE1 changes from high to low, the second P-type transistor TE2 changes from off to on, connecting one end of the capacitor CE to the power supply voltage node NVDD. Therefore, since the voltage CROUT at one end of the capacitor CE is fixed to the power supply voltage VDD, the control signal CRQ is fixed at a high level. That is, the second P-type transistor TE2 functions as a latching mechanism for maintaining the reset-released state after the reset is released.

[0078] Figure 6This is a waveform diagram illustrating the operation of CR circuit 136 and switch SWPU. When the power supply voltage VDD is applied, capacitor CE begins charging, and the voltage CROUT at one end of capacitor CE gradually rises. At the moment Tcr, when voltage CROUT reaches the logic threshold voltage Tcr of the first inverter IE1, the output signal IE1Q of the first inverter IE1 changes from the power supply voltage VDD to ground voltage VSS. That is, the output signal IE1Q changes from high level to low level. Consequently, the second P-type transistor TE2 changes from cutoff to conduction, and the voltage CROUT at one end of capacitor CE becomes the power supply voltage VDD.

[0079] Before time Tcr, the output signal of the second inverter IE2, i.e., the control signal CRQ, is low. Therefore, before time Tcr, the switch SWPU is turned on, and the reference voltage VREF becomes the power supply voltage VDD. At time Tcr, the output signal of the second inverter IE2, i.e., the control signal CRQ, changes from low to high. Thus, the switch SWPU changes from on to off, the connection between the reference voltage node NFREF and the power supply voltage node NVDD is broken, and the reference voltage VREF generated by the reference voltage generation circuit 132 is input to the comparator 133. The period from turning on the power supply voltage VDD to time Tcr corresponds to a predetermined period. That is, the length of the predetermined period is determined by the time it takes for the voltage CROUT at one end of the capacitor CE to reach the logic threshold voltage of the first inverter IE1.

[0080] Figure 7 This is an explanation Figure 4 The waveform diagram shows the operation of the power-on reset circuit 130. When the power supply voltage VDD is turned on, the power supply voltage VLOG generated by the regulator 153 rises along with the power supply voltage VDD and then converges to a stable voltage. Figure 7 This represents an example of how the power supply voltage VLOG stabilizes after an overshoot.

[0081] From the moment the power supply voltage VDD is applied until time Tcr, switch SWPU is turned on, so the reference voltage VREF becomes the same as the power supply voltage VDD. Therefore, the decision voltage VREF+Vof of comparator 133 is maintained above the power supply voltage VLOG and is not determined to be reset.

[0082] At time Tlg, when the power supply voltage VLOG exceeds the logic threshold voltage Vtlg, the logic level of the power-on reset signal PORQ is determined from the uncertain X to either a high or low level. By pre-setting the capacitance value of capacitor CE, etc., so that time Tcr is later than time Tlg, the power-on reset signal PORQ can be determined to be low at time Tlg. That is, the circuit that has input the power-on reset signal PORQ can be reliably reset.

[0083] At time Tcr, since the switch SWPU changes from on to off, the reference voltage VREF drops from the power supply voltage VDD to a specified voltage. At time Tpor when the reference voltage VREF becomes such that VREF + Vof < VLOG, the power-on reset signal PORQ changes from low level to high level. Thus, the circuit to which the power-on reset signal PORQ is input is released from reset.

[0084] As described above, the reference voltage VREF temporarily becomes the power supply voltage VDD and after a specified period, the reference voltage VREF drops to the specified voltage. Thus, it is not determined that the reset is released at an undesired voltage.

[0085] In addition, by presetting the capacitance value of the capacitor CE etc. such that it becomes time Tcr after the power supply voltage VLOG stabilizes, it is possible to release the reset of the circuit that operates with the power supply voltage VLOG after the power supply voltage VLOG stabilizes. If the reset of the circuit is released while the power supply voltage VLOG remains unstable, there may be malfunctions such as circuit malfunction, but according to this embodiment, the possibility of such malfunctions can be reduced.

[0086] 3. Real-time clock device

[0087] As an example of the circuit device 100 including the power-on reset circuit 130, the circuit device 100 of the real-time clock device 200 will be described. However, the above-mentioned power-on reset circuit 130 can be built into circuit devices for various purposes.

[0088] Figure 8 is a structural example of the real-time clock device 200 and a third structural example of the circuit device 100. The real-time clock device 200 includes an oscillator 10 and a circuit device 100. The circuit device 100 includes a power supply circuit 110, a processing circuit 120, a power-on reset circuit 130, an oscillation circuit 150, a temperature detection circuit 160, an interface circuit 170, terminals TVDD, TVBAT, TVOUT, TIF, XI, XQ. Figure 8 The power-on reset circuit 130 corresponding to Figure 1 or Figure 4 The power-on reset circuit 130.

[0089] The power supply voltage VDD of the system including the real-time clock device 200 is supplied to the terminal TVDD. This system includes a processor as the host device of the real-time clock device 200, and this processor operates with the power supply voltage VDD. A battery is connected to the terminal TVBAT, and the battery voltage VBAT is supplied from this battery. The battery is a secondary battery or a primary battery and is the backup power supply of the real-time clock device

[0090] Power supply circuit 110 monitors the power supply voltage VDD and the battery voltage VBAT, switches the power supply voltage VDD and the battery voltage VBAT according to the monitoring results, and outputs the selected voltage as voltage VOUT. A stabilizing capacitor is connected to the terminal TVOUT to stabilize voltage VOUT. Power supply circuit 110 generates power supply voltages VOSC, VDDA, and VLOG from voltage VOUT, which serve as the internal power supply voltage of circuit device 100.

[0091] Processing circuit 120 is a logic circuit that operates using the power supply voltage VLOG, performing various processes including timing and controlling various parts of circuit device 100. Processing circuit 120 communicates with the processor via interface circuit 170. Interface circuit 170 is connected to the processor via terminal TIF. Figure 8 The TIF terminal is omitted as a single terminal, but multiple terminals are actually provided for the interface. A power-on reset signal PORQ is input to the processing circuit 120, and the processing circuit 120 is reset and de-reset according to the power-on reset signal PORQ. The processing circuit 120 includes a timing circuit 121 and a temperature compensation circuit 122.

[0092] The timing circuit 121 performs timing processing based on the clock signal generated by the oscillation circuit 150 to generate timing information. The timing circuit 121 has a counter that performs a counting action based on the clock signal, and outputs the count value of this counter as timing information. The processing of generating timing information through this counting action is equivalent to timing processing. The timing information represents the current time of the system, for example, the elapsed time since the real-time clock device 200 was started and initialized. The timing information can be read from the processor via the interface circuit 170.

[0093] The temperature compensation circuit 122 outputs temperature compensation data based on the temperature detection data output by the temperature detection circuit 160, which is used to keep the oscillation frequency of the oscillation circuit 150 constant regardless of temperature.

[0094] The temperature compensation circuit 122 extracts temperature compensation data corresponding to the temperature from a lookup table that tabulates the temperature characteristics of the oscillation frequency, or outputs temperature compensation data by substituting the temperature into a polynomial function that approximates the temperature characteristics of the oscillation frequency.

[0095] The temperature detection circuit 160 includes a temperature sensor and an A / D conversion circuit, operating on a power supply voltage VDDA. The temperature sensor utilizes the temperature dependence of the forward voltage of a diode to output a temperature detection voltage that depends on the temperature. The A / D conversion circuit performs A / D conversion on the temperature detection voltage and outputs the temperature detection data.

[0096] The input and output nodes of the oscillation circuit 150 are connected to terminals XI and XQ. The oscillation circuit 150 oscillates by driving a resonator connected to terminals XI and XQ, generating a clock signal through this oscillation. The resonator 10 is a component that generates mechanical vibration through an electrical signal. The resonator 10 can be various resonators such as a quartz resonator, a piezoelectric resonator, a SAW resonator, or a MEMS resonator. SAW is an abbreviation for Surface Acoustic Wave, and MEMS is an abbreviation for Micro Electromechanical Systems. The oscillation circuit 150 oscillates at an oscillation frequency corresponding to the temperature compensation data. For example, the oscillation circuit 150 includes a D / A conversion circuit for D / A conversion of the temperature compensation data, and a variable capacitor whose capacitance value can be variably controlled through the output of the D / A conversion. One end of the variable capacitor is connected to either the input or output node of the oscillation circuit 150.

[0097] Figure 9 Here is a detailed structural example of the power supply circuit 110. The power supply circuit 110 includes P-type transistors 111-113, a switch control circuit 114, a first detection circuit 115, a second detection circuit 116, and regulators 151-153.

[0098] The first detection circuit 115 detects whether the power supply voltage VDD at the power supply voltage node NVDD is lower than a first detection voltage, and outputs the result as a first detection signal DET1 to the switch control circuit 114. The first detection circuit 115 includes: a resistor divider circuit for dividing the power supply voltage VDD; and a comparator for comparing the divided voltage with the first detection voltage. The second detection circuit 116 detects whether the battery voltage VBAT at the battery voltage node NVBAT is lower than a second detection voltage, and outputs the result as a second detection signal DET2 to the switch control circuit 114. The second detection circuit 116 includes: a resistor divider circuit for dividing the battery voltage VBAT; and a comparator for comparing the divided voltage with the second detection voltage. The first and second detection voltages are generated, for example, by a voltage generation circuit (not shown).

[0099] One of the source and drain of P-type transistor 111 is connected to the power supply voltage node NVDD, and the other of the source and drain, along with the back gate, is connected to the node NVOUT. One of the source and drain of P-type transistor 112 is connected to the node NA, and the other of the source and drain, along with the back gate, is connected to the node NVOUT. One of the source and drain of P-type transistor 113 is connected to the node NA, and the other of the source and drain, along with the back gate, is connected to the battery voltage node NVBAT. Figure 9 The diode represented by the dashed line is a parasitic diode generated between one of the source and drain terminals and the back gate.

[0100] The switch control circuit 114 controls P-type transistors 111-113 to be turned on or off based on the first detection signal DET1 and the second detection signal DET2. Specifically, when the power supply voltage VDD is detected to be higher than the first detection voltage, the switch control circuit 114 turns on P-type transistor 111 and turns off P-type transistors 112 and 113. Thus, a voltage VOUT = VDD is output to node NVOUT. When the power supply voltage VDD is detected to be lower than the first detection voltage and the battery voltage VBAT is higher than the second detection voltage, the switch control circuit 114 turns off P-type transistor 111 and turns on P-type transistors 112 and 113. Thus, a voltage VOUT = VBAT is output to node NVOUT.

[0101] Regulator 151 generates a power supply voltage VOSC by adjusting the voltage VOUT and outputs this voltage to the oscillation circuit 150. Regulator 152 generates a power supply voltage VDDA by adjusting the voltage VOUT and outputs this voltage to the temperature detection circuit 160. Regulator 153 generates a power supply voltage VLOG by adjusting the voltage VOUT and outputs this voltage to the processing circuit 120. Regulators 151 to 153 are, for example, linear regulators composed of operational amplifiers and resistors.

[0102] In this embodiment described above, the circuit device 100 includes a regulator 153 and a processing circuit 120. The regulator 153 generates a second power supply voltage, which is the voltage to be monitored, based on a first power supply voltage. Figure 8 and Figure 9 In this circuit, power supply voltage VDD is the first power supply voltage, and power supply voltage VLOG is the second power supply voltage. The processing circuit 120 operates according to the second power supply voltage, and performs reset and reset release through the power-on reset signal PORQ.

[0103] For example, when the power supply voltage VDD or battery voltage VBAT is initially connected to the circuit device 100, or when the voltage VOUT temporarily drops due to a decrease in the power supply voltage VDD, the processing circuit 120 performs a reset and reset release. If the power-on reset does not proceed normally, an alternative method such as a soft reset is required via the interface circuit 170. Figure 8 Applications in China Figure 4The power-on reset circuit 130 avoids resetting at undesirable voltages, thus enabling reliable reset and reset termination. Furthermore, when the power supply voltage VDD drops, the power supply circuit 110 switches to the battery voltage VBAT, but this switching must occur before the voltage drops to the level required for power-on reset. If the power supply voltage VDD required for this power-on reset is set to a minimum value, this minimum value is preferably lower than the processor's operating voltage. That is, it is preferable to switch to backup power when the processor cannot operate at a power supply voltage. By... Figure 8 Applications in China Figure 1 and Figure 4 The power-on reset circuit 130, which forms the structure of the aforementioned reference voltage generation circuit 132 and comparator 133, can minimize the minimum value at which a reset is not performed when the power supply voltage VDD drops.

[0104] The circuit arrangement of this embodiment described above includes a comparator, a reference voltage generation circuit, and a connection control circuit. The comparator compares the monitored voltage generated based on the power supply voltage with a reference voltage, thereby outputting a power-on reset signal. The reference voltage generation circuit generates a reference voltage and outputs it to a reference voltage node. The connection control circuit is connected between the power supply voltage node and the reference voltage node. During a predetermined period after the power supply voltage is turned on, the connection control circuit connects the reference voltage node and the power supply voltage node.

[0105] According to this embodiment, during a predetermined period after the power supply voltage is applied to the circuit device, the connection control circuit connects the reference voltage node and the power supply voltage node. Therefore, during this predetermined period, the voltage of the monitored object will not exceed the judgment voltage of the comparator. The judgment voltage is the sum of the reference voltage after it converges to the predetermined voltage and the offset voltage of the comparator. Then, after the predetermined period has elapsed, the connection control circuit disconnects the connection between the reference voltage node and the power supply voltage node, thereby causing the reference voltage to converge to the desired predetermined voltage. Thus, after the reference voltage converges to the desired predetermined voltage, the comparator can compare the voltage of the monitored object with the reference voltage.

[0106] Alternatively, in this embodiment, the connection control circuit may also include: a switch disposed between the power supply voltage node and the reference voltage node; and a CR circuit that outputs a control signal to the switch, which controls the switch to open after a specified period has elapsed since the power supply voltage was turned on.

[0107] According to this embodiment, during a predetermined period after the power supply voltage is applied, the switch is turned on, so the reference voltage node is connected to the power supply voltage node. Therefore, during the predetermined period after the power supply voltage is applied, the reference voltage input to the comparator becomes the power supply voltage. Furthermore, after the predetermined period has elapsed, the switch changes from on to off, so the comparator can compare the reference voltage with the voltage of the monitored object.

[0108] Furthermore, in this embodiment, the CR circuit may also include a capacitor, which outputs a control signal to the switch. After a predetermined period determined by the capacitance value of the capacitor, the control signal changes from active to inactive. The switch can change from on to off when the control signal changes from active to inactive.

[0109] According to this embodiment, a predetermined period is set based on the capacitance value of the capacitor. Furthermore, the CR circuit can output a control signal that changes from active to inactive after the predetermined period has elapsed.

[0110] Furthermore, in this embodiment, the circuit arrangement may also include a bias circuit that generates a bias voltage. The CR circuit may include a first P-type transistor disposed between a power supply voltage node and one end of a capacitor, with its gate receiving an input bias voltage.

[0111] According to this embodiment, the first P-type transistor becomes a constant current source, charging the capacitor by inputting a constant current to one end of the capacitor. The length of the predetermined period is determined based on the value of the constant current and the capacitance value of the capacitor.

[0112] Alternatively, in this embodiment, the CR circuit may also include an N-type transistor, the drain of which is connected to one end of a capacitor, and the source and gate of which are connected to a ground node.

[0113] The first P-type transistor has a parasitic diode that is forward-biased from one end of the capacitor toward the power supply voltage node, and the N-type transistor has a parasitic diode that is forward-biased from one end of the capacitor toward the ground node. Thus, when the power supply voltage is applied, the voltage at one end of the capacitor rises from a roughly predetermined voltage, allowing it to remain approximately constant for a specified period.

[0114] Alternatively, in this embodiment, the CR circuit may also include: a first inverter, which receives the voltage at one end of the capacitor; a second inverter, which receives the output signal of the first inverter and outputs a control signal; and a second P-type transistor, which is disposed between the power supply voltage node and one end of the capacitor, with its gate receiving the output signal of the first inverter.

[0115] According to this embodiment, when the voltage at one end of the capacitor exceeds the logic threshold voltage, the first inverter changes the output signal from a high level to a low level. Therefore, the period from the power supply voltage being applied until the voltage at one end of the capacitor exceeds the logic threshold voltage is defined as a predetermined period. Furthermore, according to this embodiment, when the output signal of the first inverter changes from a high level to a low level, the second P-type transistor changes from off to on, connecting one end of the capacitor to the power supply voltage node. Thus, the second P-type transistor functions as a latching mechanism for maintaining the reset-released state after the reset is released.

[0116] Alternatively, in this embodiment, the reference voltage generation circuit can also generate a reference voltage based on the power supply voltage.

[0117] When the switch connects the reference voltage node and the power supply voltage node, the source of the transistor in the power supply voltage node and the reference voltage generation circuit are connected via the switch and the transistor in the reference voltage generation circuit. It is preferable that power supply voltages different from the internal power supply voltage not be connected, but according to this embodiment, the source of the transistor in the reference voltage generation circuit is connected to the power supply voltage node.

[0118] Furthermore, in this embodiment, the circuit arrangement may also include a bias circuit for generating a bias voltage. The reference voltage generation circuit may include a depletion-mode N-type transistor and an enhancement-mode N-type transistor. The depletion-mode N-type transistor is disposed between the power supply voltage node and the reference voltage node, and its gate is biased by an input voltage. The enhancement-mode N-type transistor may be disposed between the reference voltage node and the ground node, and its gate is biased by an input voltage.

[0119] According to this embodiment, since the comparator's offset voltage can be reduced and the reference voltage can be adjusted, the minimum power supply voltage for normal operation of the comparator can be lowered.

[0120] Furthermore, in this embodiment, the circuit device may also include a regulator and a processing circuit. The regulator can generate a second power supply voltage, which serves as the voltage to be monitored, based on the first power supply voltage when the power supply voltage is set to a first power supply voltage. The processing circuit can operate based on the second power supply voltage and can be reset and de-reset via a power-on reset signal.

[0121] By using the power-on reset circuit of this embodiment to reset and de-reset the processing circuit, the reset and de-reset will not be performed with an unwanted voltage, thus enabling reliable reset and de-reset of the processing circuit.

[0122] Furthermore, the real-time clock device of this embodiment includes the circuit arrangement and oscillator described in any of the above embodiments. The circuit arrangement includes a regulator, a processing circuit, and an oscillation circuit. When the power supply voltage is set to a first power supply voltage, the regulator generates a second power supply voltage as the voltage to be monitored based on the first power supply voltage. The processing circuit operates based on the second power supply voltage and is reset and de-reset via a power-on reset signal. The oscillation circuit generates a clock signal by oscillating the oscillator. The processing circuit includes a timing circuit that performs timing processing based on the clock signal.

[0123] Thus, the circuit arrangement of this embodiment can be applied to a real-time clock device. Furthermore, by using the power-on reset circuit of this embodiment to reset and de-reset the processing circuit, undesirable voltages are avoided during reset and de-reset, ensuring reliable reset and de-reset of the processing circuit of the real-time clock device.

[0124] Furthermore, although this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be implemented without substantially departing from the novelty and effects of this disclosure. Therefore, the scope of this disclosure includes all such modifications. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous may be replaced with that different term anywhere in the specification or drawings. Moreover, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of the power-on reset circuit, circuit arrangement, and real-time clock device are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, Include: A comparator compares the monitored voltage generated based on the power supply voltage with a reference voltage, thereby outputting a power-on reset signal; A reference voltage generation circuit generates the reference voltage and outputs the reference voltage to a reference voltage node; A connection control circuit is connected between the power supply voltage node supplied with the power supply voltage and the reference voltage node. as well as The bias circuit generates a bias voltage. The connection control circuit connects the reference voltage node and the power supply voltage node for a specified period after the power supply voltage is applied. The connection control circuit includes: A switch is disposed between the power supply voltage node and the reference voltage node; as well as The CR circuit outputs a control signal to the switch. After a predetermined period has elapsed since the power supply voltage was applied, the control signal switches the switch from on to off. The CR circuit includes: Capacitor; A first P-type transistor is disposed between the power supply voltage node and one end of the capacitor, and its gate is input with the bias voltage; and An N-type transistor, wherein its drain is connected to one end of the capacitor, and its source and gate are connected to a ground node. The CR circuit outputs the control signal to the switch, and after a predetermined period determined by the capacitance value of the capacitor, the control signal changes from active to inactive. The switch changes from on to off when the control signal changes from valid to invalid.

2. A circuit device, characterized in that, Include: A comparator compares the monitored voltage generated based on the power supply voltage with a reference voltage, thereby outputting a power-on reset signal; A reference voltage generation circuit generates the reference voltage and outputs the reference voltage to a reference voltage node; A connection control circuit is connected between the power supply voltage node supplied with the power supply voltage and the reference voltage node. as well as The bias circuit generates a bias voltage. The connection control circuit connects the reference voltage node and the power supply voltage node for a specified period after the power supply voltage is applied. The connection control circuit includes: A switch is disposed between the power supply voltage node and the reference voltage node; as well as The CR circuit outputs a control signal to the switch. After a predetermined period has elapsed since the power supply voltage was applied, the control signal switches the switch from on to off. The CR circuit has: Capacitor; A first P-type transistor is disposed between the power supply voltage node and one end of the capacitor, and its gate is input with the bias voltage. A first inverter, which is input with the voltage at one end of the capacitor; The second inverter receives the output signal from the first inverter and outputs the control signal. as well as A second P-type transistor is disposed between the power supply voltage node and one end of the capacitor, and its gate is input to the output signal of the first inverter. The CR circuit outputs the control signal to the switch, and after a predetermined period determined by the capacitance value of the capacitor, the control signal changes from active to inactive. The switch changes from on to off when the control signal changes from valid to invalid.

3. The circuit device according to claim 1 or 2, characterized in that, The reference voltage generation circuit generates the reference voltage based on the power supply voltage.

4. The circuit device according to claim 1 or 2, characterized in that, The reference voltage generation circuit includes: A depletion-type N-type transistor is disposed between the power supply voltage node and the reference voltage node, and its gate is input with the bias voltage; as well as An enhancement-mode N-type transistor is disposed between the reference voltage node and the ground node, and its gate is input with the bias voltage.

5. The circuit device according to claim 1 or 2, characterized in that, Include: A regulator that, when setting the power supply voltage to a first power supply voltage, generates a second power supply voltage as the voltage of the monitored object based on the first power supply voltage; and The processing circuit operates according to the second power supply voltage, and performs reset and reset release through the power-on reset signal.

6. A real-time clock device, characterized in that, Include: The circuit device according to any one of claims 1 to 5; and Vibration The circuit device includes: A regulator that, when the power supply voltage is set to a first power supply voltage, generates a second power supply voltage as the voltage of the monitored object based on the first power supply voltage; The processing circuit operates according to the second power supply voltage, and performs reset and reset release via the power-on reset signal; and An oscillating circuit causes the oscillator to oscillate, thereby generating a clock signal. The processing circuit includes a timing circuit that performs timing processing based on the clock signal.

Images