Power-on reset circuit

Abstract

The invention provides a power-on reset circuit, which comprises a current source starting circuit, a current source circuit, a voltage comparison circuit and a latch circuit, and is characterized in that the current source starting circuit is used for detecting the amplitude of power supply voltage, and when the power supply voltage is powered on, the current circuit is awakened to provide a reference voltage signal; the voltage comparison circuit determines whether the power supply voltage accords with a safe working threshold value or not based on the reference voltage signal, and the latch circuit outputs a reset signal under the condition that the power supply voltage accords with the working threshold value; in addition, after the current source circuit operates, a first feedback signal is output to close the current source starting circuit, and the latch circuit outputs a reset signal and a second feedback signal at the same time to close the voltage comparison voltage; therefore, when the power-on reset function is completed, the electric power consumption of the whole circuit is reduced.

Description

Technical Field

[0001] This invention relates to the field of power-on reset circuit technology, and particularly to a power-on reset circuit. Background Technology

[0002] The POR (Power-On Reset) circuit is widely used to generate a POR enable signal when the power supply is powered on or restarted after a power failure. This signal sets the initial state of modules with memory functions, such as latches, registers, and flip-flops, thereby ensuring that the circuit system enters a normal working state.

[0003] While POR circuits are crucial, many traditional or simple POR designs suffer from a significant drawback: high quiescent power consumption. This is a fatal flaw for power-sensitive applications such as battery-powered IoT devices, wearables, and medical implants. Summary of the Invention

[0004] The main objective of this invention is to provide a power-on reset circuit, specifically a low-power power-on reset circuit.

[0005] To achieve the above objectives, the present invention proposes a power-on reset circuit, comprising:

[0006] Current source startup circuit, current source circuit, voltage comparison circuit and latch circuit;

[0007] The power supply terminals of the current source starting circuit, the current source circuit, and the voltage comparison circuit are respectively connected to the power supply voltage; the first output terminal of the current source starting circuit is connected to the first input terminal of the current source circuit; the current source starting circuit is used to output a first signal through the first output terminal when the power supply voltage is greater than or equal to a first preset voltage value.

[0008] The first output terminal of the current source circuit is connected to the first input terminal of the current source start-up circuit, the second output terminal is connected to the first input terminal of the voltage comparison circuit, the third output terminal is connected to the first input terminal of the latch circuit, and the fourth output terminal is connected to the second input terminal of the latch circuit.

[0009] The current source circuit is used to establish a reference current based on the power supply voltage when the first signal is received, output a reference voltage signal corresponding to the reference current through the second output terminal of the current source circuit, and output a first feedback signal through the first output terminal of the current source circuit; the current source circuit also outputs a first preparation signal through the third output terminal of the current source circuit and a second preparation signal through the fourth output terminal of the current source circuit when the first signal is received.

[0010] The output terminal of the voltage comparison circuit is connected to the third input terminal of the latch circuit; the voltage comparison circuit is used to transform the power supply voltage connected to the voltage comparison circuit, and output a third preparation signal when the transformed voltage is greater than the reference voltage signal.

[0011] The first output terminal of the latch circuit is connected to the second input terminal of the voltage comparison circuit, and the second output terminal is connected to the reset terminal of the given device. The latch circuit is used to output a second feedback signal through the first output terminal of the latch circuit and output a reset signal to the reset terminal of the given device through the second output terminal of the latch circuit when receiving the first preparation signal, the second preparation signal and the third preparation signal.

[0012] The voltage comparison circuit is also used to cut off the electrical path for voltage conversion of the power supply voltage when the second feedback signal is received.

[0013] The current source start-up circuit is also used to stop outputting the first signal upon receiving the first feedback signal. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the first embodiment of the power-on reset circuit of the present invention;

[0016] Figure 2 This is a schematic diagram of the first structure of the second embodiment of the power-on reset circuit of the present invention;

[0017] Figure 3 This is a schematic diagram of the second structure of the power-on reset circuit of the present invention;

[0018] Figure 4 This is a schematic diagram of the third structure of the second embodiment of the power-on reset circuit of the present invention;

[0019] Figure 5 This is a schematic diagram of the first structure of the third embodiment of the power-on reset circuit of the present invention;

[0020] Figure 6 This is a schematic diagram of the second structure of the third embodiment of the power-on reset circuit of the present invention;

[0021] Figure 7This is a schematic diagram of the third structure of the third embodiment of the power-on reset circuit of the present invention;

[0022] Figure 8 This is a schematic diagram of the first structure of the fourth embodiment of the power-on reset circuit of the present invention;

[0023] Figure 9 This is a schematic diagram of the second structure of the fourth embodiment of the power-on reset circuit of the present invention;

[0024] Figure 10 This is a schematic diagram of the third structure of the fourth embodiment of the power-on reset circuit of the present invention;

[0025] Figure 11 This is a schematic diagram of the simulation results of the fourth embodiment of the power-on reset circuit of the present invention.

[0026] Explanation of icon numbers:

[0027]

[0028] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0031] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0033] This invention provides a power-on reset circuit, such as... Figure 1 As shown, in the first embodiment, the power-on reset circuit includes:

[0034] The circuit includes a current source starting circuit 10, a current source circuit 20, a voltage comparison circuit 30, and a latching circuit 40.

[0035] The power supply terminals of the current source starting circuit 10, the current source circuit 20, and the voltage comparison circuit 30 are respectively connected to the power supply voltage; the first output terminal of the current source starting circuit 10 is connected to the first input terminal of the current source circuit 20; the current source starting circuit 10 is used to output a first signal through the first output terminal when the power supply voltage is greater than or equal to a first preset voltage value.

[0036] The first output terminal of the current source circuit 20 is connected to the first input terminal of the current source start circuit 10, the second output terminal is connected to the first input terminal of the voltage comparison circuit 30, the third output terminal is connected to the first input terminal of the latch circuit 40, and the fourth output terminal is connected to the second input terminal of the latch circuit 40.

[0037] The current source circuit 20 is used to establish a reference current based on the power supply voltage when the first signal is received, output a reference voltage signal corresponding to the reference current through the second output terminal of the current source circuit 20, and output a first feedback signal through the first output terminal of the current source circuit 20; the current source circuit 20 also outputs a first preparation signal through the third output terminal of the current source circuit 20 and a second preparation signal through the fourth output terminal of the current source circuit 20 when the first signal is received.

[0038] The output terminal of the voltage comparison circuit 30 is connected to the third input terminal of the latch circuit 40; the voltage comparison circuit 30 is used to convert the power supply voltage connected to the voltage comparison circuit 30, and output a third preparation signal when the converted voltage is greater than the reference voltage signal.

[0039] The first output terminal of the latch circuit 40 is connected to the second input terminal of the voltage comparison circuit 30, and the second output terminal is connected to the reset terminal of the given device. The latch circuit 40 is used to output a second feedback signal through the first output terminal of the latch circuit 40 and output a reset signal to the reset terminal of the given device through the second output terminal of the latch circuit 40 when receiving the first preparation signal, the second preparation signal and the third preparation signal.

[0040] The voltage comparison circuit 30 is also used to cut off the electrical path for voltage conversion of the power supply voltage when the second feedback signal is received.

[0041] The current source start-up circuit 10 is also used to stop outputting the first signal upon receiving the first feedback signal.

[0042] It should be explained that the power-on reset circuit provided by this invention does not require manual triggering like an RC reset circuit. Instead, it detects the power supply voltage and outputs a reset signal to the reset terminal of the given device when the voltage reaches a safe operating threshold. Considering the wide range of applications for the power-on reset circuit, this invention does not limit the type of the given device. For example, the given device can be a mobile phone, computer, host, microsystem, or controller, or other electronic devices or components thereof.

[0043] The latch circuit 40 outputs a reset signal when it simultaneously receives the first, second, and third preparation signals. It should be noted that the first to third preparation signals should be interpreted as level signals with corresponding voltage amplitude ranges, rather than whether the latch circuit 40 has an electrical signal input. For example, the fourth output terminal of the current source circuit 20 outputs an electrical signal to the latch circuit 40, but the latch circuit 40 is considered to have received the second preparation signal only when the fourth output terminal of the current source circuit 20 outputs a low level.

[0044] To reduce power consumption, this embodiment uses a current source startup circuit 10 to detect the amplitude of the power supply voltage. When the power supply voltage is greater than or equal to a first preset voltage value, a first signal is output through the first output terminal. Upon receiving the first signal, the current source circuit 20 starts operating, outputting a first feedback signal to the current source startup circuit 10 and then shutting down the current source startup circuit 10, further reducing power consumption. Specifically, the current source circuit 20 establishes a reference current based on the power supply voltage, outputs a reference voltage signal corresponding to the reference current through the second output terminal of the current source circuit 20, and outputs the first feedback signal through the first output terminal of the current source circuit 20. Upon receiving the first feedback signal, the current source startup circuit 10 stops outputting the first signal, reducing power consumption.

[0045] Additionally, it should be explained that the power supply terminals of the current source startup circuit 10, the current source circuit 20, and the voltage comparison circuit 30 are respectively connected to power supply voltages. The current source startup circuit 10 outputs a first signal when the power supply voltage is greater than or equal to a first preset voltage value. It is particularly important to emphasize that the current source startup circuit 10 has low power consumption and is used to detect the presence (non-zero) of the power supply voltage. In this embodiment, the first preset voltage value is used to determine whether the power supply voltage is on; this first preset voltage value is determined by the R&D personnel. However, a power supply voltage greater than or equal to the first preset voltage value does not necessarily mean that the power supply voltage has reached a safe operating threshold. Upon receiving the first signal, the current source circuit 20 outputs a first preparation signal and a second preparation signal; it can be seen that the power supply voltage connected to the current source circuit 20 at this time is at least greater than or equal to the first preset voltage value.

[0046] After confirming the existence of a power supply voltage, it is also necessary to determine whether the amplitude of the power supply voltage meets the requirements. Upon receiving the first signal, the current source circuit 20 provides a reference voltage signal to the voltage comparison circuit 30 to determine whether the power supply voltage has reached a safe operating threshold. Specifically, the current source circuit 20 establishes a reference current, which remains constant and its value is independent of the specific amplitude of the power supply voltage, wherein the power supply voltage is greater than or equal to a first preset voltage value. Correspondingly, a reference voltage signal corresponding to the reference current is output. For example, the voltage across a resistor flowing through the reference current is used as the amplitude of the reference voltage signal. Since the reference current value does not change with power supply voltage fluctuations, the influence of power supply fluctuations on the reference voltage signal can be reduced, providing a high-precision reference voltage signal for high-precision voltage comparison in the voltage comparison circuit 30.

[0047] In addition, the current source circuit 20 also outputs a first preparation signal and a second preparation signal to the latch circuit 40 when it receives the first signal.

[0048] The voltage comparison circuit 30 transforms the input power supply voltage and compares the transformed voltage amplitude with the amplitude of the reference voltage signal. If the transformed voltage is greater than the reference voltage signal, a third preparation signal is output. It should be noted that the reference voltage signal is provided by the current source circuit 20 based on a reference current, and the reference current value does not change with the power supply voltage. Therefore, researchers can determine the reference voltage value by adjusting the cross-resistance gain of the reference current to the reference voltage value. Furthermore, researchers can fix the voltage gain of the voltage comparison circuit 30 when transforming the power supply voltage. It is known that the current source circuit 20 provides a reference point amplitude that does not change with the power supply voltage amplitude, while the voltage comparison circuit 30 provides a voltage value that changes with the power supply voltage amplitude. Researchers can determine the safe operating threshold of the power supply voltage and the reference current value, and then determine either the cross-resistance gain or the voltage gain to determine the other. Therefore, the power supply voltage can be transformed, and based on the comparison between the transformed voltage and the reference voltage signal, it can be determined whether the power supply voltage has reached the safe operating threshold. If the transformed voltage is greater than the reference voltage signal, a third preparation signal is output.

[0049] Upon receiving the first, second, and third preparation signals, the latch circuit 40 outputs a reset signal to the reset terminal of the given device to reset the given device, thereby achieving a power-on reset function. Additionally, the latch circuit 40 also outputs a second feedback signal to the second input terminal of the voltage comparator circuit 30 to cut off the electrical path for voltage conversion of the power supply voltage, reducing the power consumption of the voltage comparator circuit 30.

[0050] This invention proposes a power-on reset circuit, comprising a current source startup circuit 10, a current source circuit 20, a voltage comparison circuit 30, and a latch circuit 40. The current source startup circuit 10 detects the power supply voltage amplitude. When the power supply voltage is powered on, it wakes up the current source circuit to provide a reference voltage signal, so that the voltage comparison circuit 30 can determine whether the power supply voltage meets the safe operating threshold based on the reference voltage signal. If it meets the operating threshold, the latch circuit 40 outputs a reset signal. In addition, after the current source circuit 20 runs, it outputs a first feedback signal to shut down the current source startup circuit 10. The latch circuit 40 outputs a second feedback signal at the same time as outputting the reset signal, shutting down the voltage comparison voltage. Thus, while completing the power-on reset function, the power consumption of the entire circuit is reduced.

[0051] like Figure 2 As shown, in the second embodiment, the current source circuit 20 includes:

[0052] Reference current circuit 210, reference voltage circuit 220, and preparation signal circuit 230;

[0053] The reference current circuit 210, the reference voltage circuit 220, and the preparation signal circuit 230 are respectively connected to the power supply terminal of the current source circuit 20.

[0054] The input terminal of the reference current circuit 210 is connected to the first output terminal of the current source startup circuit 10, and the output terminal is connected to the input terminal of the reference voltage circuit 220; the first output terminal of the reference voltage circuit 220 is connected to the first input terminal of the current source startup circuit 10, and the second output terminal is connected to the first terminal of the voltage comparison circuit 30; the first output terminal of the preparation signal circuit 230 is connected to the first input terminal of the latch circuit 40, and the second output terminal is connected to the second input terminal of the latch circuit 40.

[0055] The reference current circuit 210 is used to output a reference current to the reference voltage circuit 220 when the first signal is received.

[0056] The reference voltage circuit 220 is used to output a first feedback signal to the current source start circuit 10 when the reference current is received, and to convert the reference current into the reference voltage signal and output the reference voltage signal to the first terminal of the voltage comparison circuit 30.

[0057] The preparation signal circuit 230 is used to output the first preparation signal and the second preparation signal when the power supply voltage is greater than the second preset voltage value.

[0058] It should be noted that this embodiment does not limit the relationship between the second preset voltage value and the first preset voltage value; the second preset voltage value is determined by the R&D personnel according to requirements. Since the preparation signal circuit 230 receiving the first signal indicates that the power supply voltage is greater than the first preset voltage value, if the second preset voltage value is less than or equal to the first preset voltage value, the preparation signal circuit 230 outputs a first preparation signal and a second preparation signal upon receiving the first signal. If the second preset voltage value is greater than the first preset voltage value, a higher requirement is placed on the amplitude of the power supply voltage, ensuring that the first and second preparation signals are output when the power supply voltage is greater than the second preset voltage value, thus avoiding the occurrence of the first and second preparation signals due to a small voltage value caused by external interference.

[0059] like Figure 3 As shown, the reference current circuit 210 includes: a first PMOS transistor to a fourth PMOS transistor, and a first NMOS transistor to a sixth NMOS transistor;

[0060] The sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply voltage. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the third PMOS transistor is connected to the gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor. The gate of the first NMOS transistor is connected to a power supply voltage, and its source is connected to the gates of the third PMOS transistor, the fourth PMOS transistor, and the second NMOS transistor. The gate of the second NMOS transistor is connected to... The gate of the third NMOS transistor is connected to the first output terminal of the current source startup circuit 10, and the source is connected to the drain of the fourth NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source is connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is grounded; the source of the fourth NMOS transistor is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the drain of the third NMOS transistor, and the source is grounded.

[0061] It should be noted that the sources of the first PMOS transistor and the second PMOS transistor are connected together and connected to a power supply voltage; the gates of the first PMOS transistor and the second PMOS transistor are connected together; the width-to-length ratio of the first PMOS transistor and the second PMOS transistor can be set to 1:1, so that the current flowing through the first PMOS transistor and the current flowing through the second PMOS transistor are equal, for example... Figure 3 As shown, the first PMOS transistor, the third PMOS transistor, the first NMOS transistor, the second NMOS transistor, the fourth NMOS transistor, the first resistor R1, and the sixth NMOS transistor are connected in series, and the second PMOS transistor, the fourth PMOS transistor, the third NMOS transistor, and the fifth NMOS transistor are connected in series. Therefore, the current flowing through the fourth NMOS transistor is equal to the current flowing through the fifth NMOS transistor.

[0062] When the circuit is first powered on, all 20 branches of the current source circuit have no current, and the circuit is at the zero-current degeneracy point; that is... Figure 3 In this circuit, the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned off, and the reference current iref is 0mA. As the power supply voltage increases or power-on is completed, the current source startup circuit 10 outputs a first signal to pull down the voltage of the first PMOS transistor and raise the potential of the second NMOS transistor; thus, the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned on; it is easy to understand that the first NMOS transistor is turned on. The reference current iref is established, and the circuit is started. The width-to-length ratio of the fourth and fifth NMOS transistors can be designed as K:1.

[0063] The width-to-length ratio of the first PMOS transistor and the second PMOS transistor is 1:1, and the current flowing through the first PMOS transistor is equal to the current flowing through the second PMOS transistor. The formula for calculating the reference current iref is as follows:

[0064] Where u is the carrier mobility, cox is the gate oxide capacitance per unit area, K is the width-to-length ratio of the fourth and fifth NMOS transistors, and V TH V is the threshold voltage of the NMOS transistor. GS4 V is the gate-source voltage of the fourth NMOS transistor. GS5 This is the gate-source voltage of the fifth NMOS transistor. This refers to the width-to-length ratio of the fifth NMOS transistor.

[0065] Other Where R DS_N6 Here, is the equivalent resistance of the sixth NMOS transistor, u is the carrier mobility, and cox is the gate oxide capacitance per unit area. V is the width-to-length ratio of the sixth NMOS transistor. GS5 V is the gate-source voltage of the fifth NMOS transistor. TH6 This is the threshold voltage of the sixth NMOS transistor.

[0066] In addition, there is ③V GS5 =V GS4 +iref*(R1+R DS_N6 ), where V GS5 V is the gate-source voltage of the fifth NMOS transistor. GS4 Ri is the gate-source voltage of the fourth NMOS transistor, iref is the reference current, R1 is the value of the first resistor, and Ri is the value of the first resistor. DS_N6 This is the equivalent resistance value of the sixth NMOS transistor.

[0067] Combining equations ①, ②, and ③, we can obtain the formula.

[0068] Because the resistor R1 and the MOSFET impedance R DS_N6 Conversely, by adjusting the device dimensions, a zero-temperature-coefficient reference current source can be obtained.

[0069] Therefore, the reference current circuit 210 can provide a reference current. It should be noted that the sixth NMOS transistor in this invention is a native transistor (low on-resistance, low threshold NMOS transistor). If a common NMOS transistor were used, the on-resistance would be larger, requiring a larger aspect ratio (W / L) and occupying too much layout area.

[0070] The reference voltage circuit 220 includes: a fifth PMOS transistor, a sixth PMOS transistor, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2;

[0071] The source of the fifth PMOS transistor is connected to the source of the first PMOS transistor and is connected to the power supply voltage. Its gate is connected to the gate of the first PMOS transistor, and its drain is connected to the source of the sixth PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, and its drain is connected to the first terminal of the second resistor R2, the first terminal of the first capacitor C1, and the first input terminal of the current source startup circuit 10. The second terminal of the second capacitor C2 is grounded. The second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3, the first terminal of the second capacitor C2, and the first terminal of the voltage comparator circuit 30. The second terminal of the second capacitor C2 is grounded. The second terminal of the third resistor R3 is grounded.

[0072] After the current source startup circuit 10 outputs the first signal, the reference current circuit 210 establishes a reference current, the gate potential of the fifth PMOS transistor is pulled low, the fifth PMOS transistor is turned on, and the sixth PMOS transistor is turned on. Since the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, a current mirror is formed. After the fifth and sixth PMOS transistors are turned on, the current flowing through the fifth PMOS transistor is the reference current value, i1 equal to iref, forming a reference voltage signal (vref in the figure) at the first end of the third resistor R3, and a first feedback signal (vstar in the figure) at the first end of the second resistor R2. Since the reference current circuit 210 can provide a reference current iref with zero temperature coefficient, a reference voltage signal is formed in the reference voltage circuit 220. The first capacitor C1 and the second capacitor C2 are used for voltage regulation.

[0073] The preparation signal circuit 230 includes: a sixth NMOS transistor, a seventh to eleventh PMOS transistors, a third capacitor C3 to a fifth capacitor C5, a first inverting Schmitt trigger SMT1, and a second inverting Schmitt trigger SMT2.

[0074] The source of the seventh PMOS transistor is connected to the source of the first PMOS transistor and is connected to a power supply voltage; the gate of the seventh PMOS transistor is connected to the gate of the first PMOS transistor, and the drain is connected to the source of the eighth PMOS transistor; the gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor, and the drain is connected to the gate and source of the sixth NMOS transistor; the drain of the sixth NMOS transistor is connected to the input of the first inverting Schmitt trigger SMT1, and the output of the first inverting Schmitt trigger SMT1 is connected to the first input of the latch circuit 40, the first terminal of the third capacitor C3, the first terminal of the fourth capacitor C4, and the ninth PMOS transistor. The source of the OS transistor and the gate of the tenth PMOS transistor; the second terminal of the third capacitor C3 is grounded, the second terminal of the fourth capacitor C4 is connected to the source of the tenth PMOS transistor; the drain of the tenth PMOS transistor is grounded, the drain of the ninth PMOS transistor is connected to the gate of the eleventh PMOS transistor, the first terminal of the fifth capacitor C5 and the input terminal of the first inverting Schmitt trigger SMT1; the output terminal of the first inverting Schmitt trigger SMT1 is connected to the second input terminal of the latch circuit 40; the second terminal of the fifth capacitor C5 is grounded; the source of the eleventh PMOS transistor is connected to the gate of the ninth PMOS transistor and the source of the eighth PMOS transistor, and the drain is grounded.

[0075] like Figure 4 As shown, the gate of the seventh PMOS transistor is connected to the gate of the first PMOS transistor, and the gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor. After the current source startup circuit 10 outputs the first signal, the gate of the first PMOS transistor is pulled low, thereby pulling the gate of the eighth PMOS transistor low. The seventh PMOS transistor and the first PMOS transistor form a current mirror. The sixth NMOS transistor is turned on under the action of the power supply voltage. The input of the first inverting Schmitt trigger SMT1 is at a high level, the input of the second inverting Schmitt trigger SMT2 is at a high level, the first inverting Schmitt trigger SMT1 outputs a low level as a first preparation signal, and the second inverting Schmitt trigger SMT2 outputs a low level as a second preparation signal. In particular, the sixth NMOS transistor is a native transistor (small on-resistance, low threshold NMOS transistor). After the sixth NMOS transistor is turned on, the first inverting Schmitt trigger SMT1 outputs a first ready signal, the tenth PMOS transistor is turned on, the third capacitor C3 and the fourth capacitor C4 begin charging, the ninth PMOS transistor is turned on, the second inverting Schmitt trigger SMT2 outputs a second ready signal, and the fifth capacitor C5 begins charging.

[0076] It should be noted that the inverting Schmitt trigger has a hysteresis voltage. When the input voltage rises from low to high and exceeds the positive threshold voltage, the output flips from high to low; when the input voltage falls from high to low and falls below the negative threshold voltage, the output flips from low to high. The inverting Schmitt trigger offers advantages in noise immunity and waveform shaping. Because the voltage build-up process at the input terminals of the first and second inverting Schmitt triggers (SMT1 and SMT2) corresponds to capacitor charging, the voltage rises slowly and linearly (ramp input). If a conventional inverter is used, when the input voltage is near the threshold voltage of a conventional inverter, any small noise (such as power supply ripple or substrate noise) can cause the output to oscillate rapidly between high and low levels, generating erroneous glitches. However, for the inverting Schmitt trigger, once the input voltage exceeds the higher positive threshold voltage, the output steadily flips to low. Even if noise subsequently causes a slight drop in the input voltage, as long as it does not fall below the negative threshold voltage, the output of the inverting Schmitt trigger will remain stable and will not oscillate. In addition, the slowly changing ramp signal was converted into a square wave signal with steep edges and high digital quality.

[0077] In another example, the preparation signal circuit 230 may further include a first buffer buff1 and a second buffer buff2. The input of the first buffer buff1 is connected to the output of the first inverting Schmitt trigger SMT1, and the output is connected to the first input of the latch circuit 40; the input of the second buffer buff2 is connected to the output of the second inverting Schmitt trigger SMT2, and the output is connected to the second input of the latch circuit 40.

[0078] The buffer is designed to have very low output resistance, strong output drive capability, and the ability to provide a large charging and discharging current. In this example, a buffer is placed at the output of an inverting Schmitt trigger. Although an inverting Schmitt trigger can achieve noise immunity and shaping, its output drive capability may be limited. The buffer can be used to provide drive capability and ensure that the signal edges of the generated first or second ready signal remain steep.

[0079] like Figure 5 As shown, in the third embodiment, the current source start-up circuit 10 includes:

[0080] The twelfth PMOS transistor to the seventeenth PMOS transistor, and the seventh NMOS transistor to the thirteenth NMOS transistor;

[0081] The sources of the twelfth, sixteenth, and seventeenth PMOS transistors are interconnected and connected to a power supply voltage; the drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the drain of the fourteenth PMOS transistor is connected to the source of the fifteenth PMOS transistor, and the drain of the fifteenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the second NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the seventh NMOS transistor; the twelfth PMOS transistor... The gates of the 13th, 14th, and 15th NMOS transistors are connected and grounded; the source of the 7th NMOS transistor is connected to the drain, gate, and gate of the 9th and 10th NMOS transistors; the source of the 9th NMOS transistor is grounded; the gate of the 16th PMOS transistor is connected to the drain, gate, and drain of the 17th and 8th NMOS transistors; the source of the 8th NMOS transistor is connected to the drain of the 10th NMOS transistor, and the source of the 10th NMOS transistor is grounded.

[0082] The drain of the seventeenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor; the gate of the eleventh NMOS transistor is connected to the first terminal of the second resistor R2, and its source is grounded; the source of the twelfth NMOS transistor is grounded; the source of the thirteenth NMOS transistor is grounded, and its drain is connected to the gate of the first PMOS transistor.

[0083] like Figure 5As shown, the twelfth to fifteenth PMOS transistors are connected in series, and their gates are grounded. These transistors form an inverting transistor, which has high impedance and low static power consumption. It is easy to understand that when the power supply voltage is applied, all of the twelfth to fifteenth PMOS transistors are turned on. The voltage at the drain of the fifteenth PMOS transistor rises with the power supply voltage, and the voltage at the drain of the fifteenth PMOS transistor (as shown in Figure vbn) is output to the gate of the second NMOS transistor in the reference current circuit 210. This causes the second NMOS transistor to conduct; furthermore, as the power supply voltage gradually increases, the vbn voltage gradually rises, causing the seventh and eighth NMOS transistors to conduct, and subsequently the ninth and tenth NMOS transistors to conduct; after the tenth and eighth NMOS transistors conduct, the voltage at the gate and drain of the sixteenth PMOS transistor is pulled low, causing the sixteenth PMOS transistor to conduct; and since the gates of the seventeenth, eighteenth, and sixteenth PMOS transistors are connected to form a current mirror, the seventeenth and eighteenth PMOS transistors conduct accordingly.

[0084] After the seventeenth PMOS transistor is turned on, the voltage at the gate of the twelfth NMOS transistor is increased, and the twelfth and thirteenth NMOS transistors are turned on. The drain of the thirteenth NMOS transistor is connected to the gate of the first PMOS transistor. After the thirteenth NMOS transistor is turned on, the gate of the first PMOS transistor is pulled low, and the first, second, fifth, and seventh PMOS transistors are turned on, starting the current source circuit 20.

[0085] Additionally, it should be noted that the gate of the eleventh NMOS transistor is connected to the first terminal of the first resistor R1. After the reference current is established in the current source circuit 20, the first terminal of the second resistor R2 is at a high level, the eleventh NMOS transistor is turned on, and the gates of the twelfth and thirteenth NMOS transistors are pulled low to zero, thereby turning off the twelfth and thirteenth NMOS transistors.

[0086] It should be explained that the seventh and eighth NMOS transistors form a current mirror, as do the sixteenth, seventeenth, and eighteenth PMOS transistors. Since the eighth and sixteenth PMOS transistors are connected in series, the currents flowing through the seventh, eighth, seventeenth, and eighteenth NMOS transistors are equal. However, due to the presence of the inverting transistor, the current flowing through the seventh NMOS transistor is smaller. Therefore, in this embodiment, the quiescent current of the current source startup circuit 10 is smaller, resulting in lower power consumption.

[0087] like Figure 6 As shown, the current source circuit 20 further includes a hysteresis circuit;

[0088] The hysteresis circuit includes: nineteenth PMOS transistors to twenty-first PMOS transistors, and fifteenth NMOS transistors to twenty-fourth NMOS transistors;

[0089] The source of the nineteenth PMOS transistor and the source of the twentieth PMOS transistor are connected to the source of the first PMOS transistor; the gate of the nineteenth PMOS transistor is connected to the gate of the twentieth PMOS transistor, the gate of the first PMOS transistor, and the drain of the thirteenth NMOS transistor; the drain of the nineteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor; the source of the fifteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor, the gate of the nineteenth NMOS transistor, the gate of the sixteenth NMOS transistor, and the drain of the sixteenth NMOS transistor; the source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor; the gate of the seventeenth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source is grounded;

[0090] The source of the 21st PMOS transistor is connected to the drain of the 20th PMOS transistor, its gate is connected to the gate of the 3rd PMOS transistor, and its drain is connected to the drain of the 18th NMOS transistor, the drain of the 19th NMOS transistor, the gate of the 18th NMOS transistor, the gate of the 20th NMOS transistor, the gate of the 23rd NMOS transistor, and the drain of the 24th NMOS transistor. The source of the 19th NMOS transistor is grounded. The source of the 18th NMOS transistor is connected to the drain of the 20th NMOS transistor. The source of the 20th NMOS transistor is connected to the drain of the 21st NMOS transistor, the gate of the 21st NMOS transistor, and the gate of the 22nd NMOS transistor. The drain of the 22nd NMOS transistor is connected to the source of the 21st NMOS transistor, and its source is grounded. The gate of the 24th NMOS transistor is connected to the drain of the 18th PMOS transistor, and its source is grounded. The source of the 23rd NMOS transistor is grounded, and its drain is connected to the source of the 6th NMOS transistor.

[0091] It should be noted that, as Figure 6As shown, the nineteenth PMOS transistor, the twentieth PMOS transistor, and the first PMOS transistor form a current mirror. The current flowing through the nineteenth and twentieth PMOS transistors is equal to the reference current value. The gate of the seventeenth NMOS transistor is connected to the gate of the fourth NMOS transistor (vbn1 in the figure). When the power supply voltage is applied, vbn1 rises, the seventeenth NMOS transistor turns on, and subsequently the sixteenth, fifteenth, and nineteenth NMOS transistors turn on. After the nineteenth NMOS transistor turns on, the voltage at its gate rises, and the nineteenth NMOS transistor turns on.

[0092] After the 20th and 21st PMOS transistors are turned on, the 18th to 22nd NMOS transistors are turned on accordingly. The gate of the 23rd NMOS transistor is at a high level. When the 23rd NMOS transistor is turned on, the voltage at the input terminals of the first inverting Schmitt trigger SMT1 and the second inverting Schmitt trigger SMT2 is pulled low.

[0093] Furthermore, when the nineteenth NMOS transistor is turned on, it provides a lower impedance path compared to the eighteenth to twenty-second NMOS transistors. The nineteenth NMOS transistor shunts current, resulting in a decrease in the gate voltage of the twenty-third NMOS transistor, which then turns off. The current flowing through the nineteenth NMOS transistor and the eighteenth NMOS transistor can be changed by adjusting the size of the nineteenth NMOS transistor, thereby altering the gate voltage of the twenty-third NMOS transistor. When the power supply voltage is successfully applied, the gate voltage of the nineteenth NMOS transistor is higher, and the current flowing through it is larger. Correspondingly, the gate voltage of the twenty-third NMOS transistor is lower, and it turns off. Since the power supply voltage is high at the input terminals of the first inverting Schmitt trigger SMT1 and the second inverting Schmitt trigger SMT2, the preparation signal circuit 230 outputs a first preparation signal and a second preparation signal. However, when the power supply voltage decreases, the conduction level of the nineteenth NMOS transistor decreases, the current flowing through the nineteenth NMOS transistor decreases, and correspondingly, the voltage at the gate of the twenty-third NMOS transistor increases until the twenty-third NMOS transistor turns on, pulling down the voltage at the input terminals of the first inverting Schmitt trigger SMT1 and the second inverting Schmitt trigger SMT2. The hysteresis circuit proposed in this embodiment keeps the twenty-third NMOS transistor in the off state after the power supply voltage is applied, and the preparation signal circuit 230 outputs a first preparation signal and a second preparation signal. If the power supply voltage fluctuates or drops slightly, the current flowing through the twenty-third NMOS transistor corresponding to the conduction level of the nineteenth NMOS transistor is insufficient to turn on the twenty-third NMOS transistor at the gate. The twenty-third NMOS transistor only turns on when the power supply voltage drops significantly. It is easy to understand that the power supply voltage value corresponding to the critical conduction of the 23rd NMOS transistor can be used as the lower threshold. As can be seen from the above, after the power supply voltage is powered on, the preparation signal circuit 230 outputs the first preparation signal and the second preparation signal, and the latch circuit 40 outputs a reset signal when it receives the first preparation signal, the second preparation signal and the third preparation signal. When the power supply voltage drops to the lower threshold, the hysteresis circuit turns on the 23rd NMOS transistor, and correspondingly, the preparation signal circuit 230 does not output the first preparation signal and the second preparation signal, so as to avoid the output of the latch circuit 40 flipping and realize the output of the hysteresis reset signal.

[0094] In addition, such as Figure 7 As shown, the current source startup circuit 10 further includes: a first diode D1, a fourteenth NMOS transistor, an eighteenth PMOS transistor, and a third inverting Schmitt trigger SMT3;

[0095] The source of the eighteenth PMOS transistor is connected to the source of the twelfth PMOS transistor, the gate is connected to the gate of the sixteenth PMOS transistor, the drain is connected to the drain of the fourteenth NMOS transistor and the input of the third inverting Schmitt trigger SMT3, and the output of the third inverting Schmitt trigger SMT3 is connected to the gate of the fourteenth NMOS transistor; the gate of the fourteenth NMOS transistor is grounded, and the source is connected to the anode of the first diode D1; the cathode of the first diode D1 is grounded.

[0096] It should be noted that the output terminal of the third inverting Schmitt trigger SMT3 is connected to the gate of the 24th NMOS transistor (as shown in por1 in the figure); when the power supply voltage is not powered on, the input terminal of the third inverting Schmitt trigger SMT3 is at a low level, and the output terminal outputs a high level to the gate of the 24th NMOS transistor; the 24th NMOS transistor is turned on, pulling down the gate voltage of the 23rd NMOS transistor, and the 23rd NMOS transistor is turned off; the preparation signal circuit 230 does not output the first preparation signal and the second preparation signal, ensuring that the latch circuit 40 does not output a reset signal when the power supply voltage is not powered on.

[0097] When the power supply voltage is applied, the input of the third inverting Schmitt trigger SMT3 is at a high level, and the output is at a low level, which is then sent to the gate of the 24th NMOS transistor, causing the 24th NMOS transistor to turn off.

[0098] The current source startup circuit 10 also includes: a third buffer buff3;

[0099] The input of the third buffer buff3 is connected to the output of the third inverting Schmitt trigger SMT3, and the output is connected to the gate of the twenty-fourth NMOS transistor. The third buffer buff3 is used to increase the output drive capability.

[0100] like Figure 8 As shown, in the fourth embodiment, the voltage comparison circuit 30 includes: a 22nd PMOS transistor to a 28th PMOS transistor, a 25th NMOS transistor to a 27th NMOS transistor, a fourth resistor R4 to an eighth resistor R8, a sixth capacitor C6, and a seventh capacitor C7.

[0101] The source of the 22nd PMOS transistor is connected to the source of the 24th PMOS transistor and the source of the 27th PMOS transistor, and is connected to a power supply voltage; the drain of the 22nd PMOS transistor is connected to the first terminal of the fourth resistor R4, and the gate is connected to the first output terminal of the latch circuit 40; the second terminal of the fourth resistor R4 is connected to the first terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6; the second terminal of the fifth resistor R5 is grounded; the second terminal of the sixth resistor R6 is connected to the first terminal of the sixth capacitor C6 and the gate of the 23rd PMOS transistor; the second terminal of the sixth capacitor C6 is grounded.

[0102] The drain of the 24th PMOS transistor is connected to the source of the 25th PMOS transistor, and the drain of the 25th PMOS transistor is connected to the source of the 23rd PMOS transistor and the source of the 26th PMOS transistor. The gate of the 26th PMOS transistor is connected to the first terminal of the seventh capacitor C7 and the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is connected to the second output terminal of the current source circuit 20, and the second terminal of the seventh capacitor C7 is grounded. The drain of the 25th NMOS transistor is connected to the drain of the 23rd PMOS transistor, the gate is connected to the gate of the 26th NMOS transistor, and the source is grounded. The seventh resistor R7 is connected in parallel. Between the drain and gate of the 25th NMOS transistor; the drain of the 26th PMOS transistor is connected to the drain of the 26th NMOS transistor and the gate of the 27th NMOS transistor; the source of the 26th NMOS transistor is grounded; the source of the 27th NMOS transistor is grounded, and its drain is connected to the third input terminal of the latch circuit 40 and the drain of the 28th PMOS transistor; the source of the 28th PMOS transistor is connected to the drain of the 27th PMOS transistor, and its gate is connected to the gate of the 25th PMOS transistor and the gate of the third PMOS transistor; the gate of the 24th PMOS transistor is connected to the gate of the first PMOS transistor.

[0103] It should be noted that the fourth resistor R4 and the fifth resistor R5 are connected in series to form a resistor voltage divider circuit, which is positioned between the power supply voltage and ground. When the twenty-second PMOS transistor is turned on, the resistor voltage divider circuit divides the power supply voltage and outputs it. After passing through the RC filter circuit composed of the sixth resistor R6 and the sixth capacitor C6, it reaches the gate of the twenty-third PMOS transistor. The sixth capacitor C6 in the RC filter circuit can also be used for voltage regulation, which can prevent the power supply from being pulled down momentarily (generally in the microsecond range) and causing a reset. The eighth resistor R8 is connected to the reference voltage signal, and the eighth resistor R8 and the seventh capacitor C7 form an RC filter circuit.

[0104] When the power supply voltage is applied, the Vbp1 signal in the current source startup circuit 10 is pulled low, and the Vbp2 signal in the current source circuit 20 is pulled low. Therefore, the 24th, 25th, 27th, and 28th PMOS transistors are turned on. It is easy to understand that after power-on, the 23rd and 26th PMOS transistors are turned on. Since the reference current corresponding to the reference voltage signal remains unchanged (as explained earlier), the conduction degree of the 23rd and 26th PMOS transistors is determined by the gate voltage of the 23rd and 26th PMOS transistors, respectively; correspondingly, the conduction degree affects the current flowing through them. The 25th and 26th PMOS transistors provide a path for current to ground.

[0105] The drain of the 27th NMOS transistor is connected to the third input terminal of the latch circuit 40, and the low level output to the second input terminal of the latch circuit 40 is used as the third preparation signal. When the power supply voltage is not powered on, the voltage at the first terminal of the fifth resistor R5 (at N1 in the figure) is zero. When the power supply voltage is powered on, the voltage at the gate of the 23rd PMOS transistor is low, and correspondingly, the current flowing through the 23rd PMOS transistor is large, the current flowing through the 26th NMOS transistor is small, the 27th NMOS transistor is cut off, and the drain of the 27th NMOS transistor is at a high level. As the amplitude of the power supply voltage increases, the current flowing through the 26th NMOS transistor increases until the 27th NMOS transistor is turned on, pulling down the potential of the 27th NMOS transistor and outputting the third preparation signal.

[0106] It is easy to understand that the power supply voltage amplitude corresponding to the conduction of the 27th NMOS transistor is set as the safe operating threshold of the power supply voltage; the 27th NMOS transistor can be made to conduct precisely at the safe operating threshold of the power supply voltage by adjusting the voltage division coefficients of the fourth resistor R4 and the fifth resistor R5. The safe operating threshold is determined by the R&D personnel based on actual needs.

[0107] Based on the above, it can be seen that in this embodiment, the voltage after the reference voltage signal and the power supply voltage are divided by a resistor is used to determine whether the 27th NMOS transistor is turned on; when the 27th NMOS transistor is turned on, the power supply voltage reaches the safe operating threshold.

[0108] In addition, the voltage comparison circuit 30 also includes an adjustable resistor (Restrim).

[0109] The adjustable resistor Restrim is connected in series with the fourth resistor R4 and the fifth resistor R5. It is easy to understand that during integrated circuit manufacturing, due to process fluctuations, the resistance, capacitance, and transistor parameters of the actual manufactured chip will deviate from the design values. This leads to a serious problem: in different voltage comparison circuits 30, the power supply voltage corresponding to the conduction of the 27th NMOS transistor will "diverge" around the design value; this can be precisely calibrated by changing the resistance value of the adjustable resistor Restrim, bringing it back to the design target value. Without the adjustable resistor Restrim for calibration, the circuit accuracy will be completely dependent on process fluctuations. With calibration, the system accuracy is no longer determined by the initial manufacturing deviation, but by the accuracy of subsequent testing and calibration. The final accuracy is far higher than the inherent deviations in chip manufacturing, thus achieving high precision.

[0110] Additionally, it should be noted that the source of the 22nd PMOS transistor is connected to the power supply voltage, the drain is connected to the first terminal of the fourth resistor R4, and the gate is connected to the first output terminal of the latch circuit 40. When no reset signal is output, the latch circuit 40 outputs a low level to the gate of the 22nd PMOS transistor, turning the 22nd PMOS transistor on. When a reset signal is output, the latch circuit 40 outputs a high level to the gate of the 22nd PMOS transistor, turning the 22nd PMOS transistor off and cutting off the path between the resistor divider circuit and the power supply circuit. This reduces static power consumption.

[0111] Furthermore, the process angle has little impact on this invention. Specifically, the reference current iref is larger at process angle ff than at process angle tt, but the resistance of the third resistor R3 is smaller at process angle ff than at process angle tt. By selecting different types of resistors for matching, a reference voltage signal vref that is less affected by the process angle can be obtained. Simulation results are shown in [link to simulation results]. Figure 11 As shown, under PVT(ss,tt,ff, temperature -25℃~175℃), the POR (reset signal) changes by only ±80mV.

[0112] Additionally, the voltage comparator circuit 30 may further include a fourth buffer, the input of which is connected to the drain of the 28th PMOS transistor and the drain of the 27th NMOS transistor. The fourth buffer is used to enhance the output drive capability.

[0113] The adjustable resistance Restrim can use polysilicon fuses or metal fuses, and its resistance value can be permanently changed during the testing phase by laser fusing or electric fusing. Alternatively, it can be adjusted using an antifuse, which is in a high-resistance state when unprogrammed and becomes a low-resistance state after programming. Or, it can be a combination of a resistor array (such as polysilicon resistor segments) and a MOS switch, and the switch can be switched by digital control signals (such as codes stored in EEPROM, Flash, or OTP) to adjust the resistance value. It can be adjusted multiple times, with high precision and good flexibility.

[0114] In one example, such as Figure 9 As shown, the voltage comparison circuit 30 further includes five delay circuits;

[0115] The input of the first delay circuit delay1 is connected to the first output of the latch circuit 40, and the output is connected to the input of the second delay circuit delay2; the output of the second delay circuit delay2 is connected to the input of the third delay circuit delay3, the output of the third delay circuit delay3 is connected to the input of the fourth delay circuit delay4, and the output of the fourth delay circuit delay4 is connected to the input of the fifth delay circuit delay5.

[0116] The voltage comparison circuit 30 further includes: the twenty-eighth NMOS transistor to the thirty-second NMOS transistor, the twenty-ninth PMOS transistor and the thirtieth PMOS transistor;

[0117] The source of the 29th PMOS transistor is connected to the drain of the 25th PMOS transistor, the gate is connected to the output of the fourth delay circuit delay4, and the drain is connected to the source of the 23rd PMOS transistor and the source of the 26th PMOS transistor; the source of the 30th PMOS transistor is connected to the drain of the 28th PMOS transistor, the gate is connected to the output of the second delay circuit delay2, and the drain is connected to the drain of the 27th NMOS transistor.

[0118] The drain of the 28th NMOS transistor is connected to the gate of the 25th NMOS transistor, the gate is connected to the output of the third delay circuit delay3, and the source is grounded; the drain of the 29th NMOS transistor is connected to the gate of the 27th NMOS transistor, the gate is connected to the output of the second delay circuit delay2, and the source is grounded; the drain of the 30th NMOS transistor is connected to the drain of the 27th NMOS transistor, the gate is connected to the output of the first delay circuit delay1, and the source is grounded; the drain of the 31st NMOS transistor is connected to the first end of the fifth resistor R5, the source is connected to the second end of the fifth resistor R5 and grounded, and the gate is connected to the third output of the current source circuit 20; the drain of the 32nd NMOS transistor is connected to the first end of the fifth resistor R5, the source is connected to the second end of the fifth resistor R5 and grounded, and the gate is connected to the output of the fifth delay circuit delay5.

[0119] The gate of the 22nd PMOS transistor is connected to the output terminal of the fifth delay circuit delay5.

[0120] It should be noted that the following settings can be made: the first delay circuit delay1 outputs the first delay signal, the second delay circuit delay2 outputs the second delay signal, the third delay circuit delay3 outputs the third delay signal, the fourth delay circuit delay4 outputs the fourth delay signal, and the fifth delay circuit delay5 outputs the fifth delay signal; there are time differences between each delay signal.

[0121] The gate of the thirtieth NMOS transistor is connected to the output terminal of the first delay circuit delay1, the gate of the twenty-ninth NMOS transistor is connected to the output terminal of the second delay circuit delay2, the gate of the twenty-eighth NMOS transistor is connected to the output terminal of the third delay circuit delay3, the gate of the twenty-ninth PMOS transistor is connected to the output terminal of the fourth delay circuit delay4, the gate of the thirty-second NMOS transistor is connected to the output terminal of the fifth delay circuit delay5, and the gate of the twenty-second PMOS transistor is connected to the output terminal of the fifth delay circuit delay5.

[0122] When the power supply voltage is not applied, the first to the fifth delay signals are at a low level, the 22nd, 29th and 30th PMOS transistors are turned on, and the 28th to 32nd NMOS transistors are turned off.

[0123] It should be noted that when the power supply voltage is applied, the first to fifth delay signals are at a high level, and the 22nd, 29th, and 30th PMOS transistors are cut off, cutting off the path of the power supply voltage to the voltage comparator circuit 30 and reducing power consumption; the 28th to 32nd NMOS transistors are turned off. Specifically, considering the timing sequence of the first to fifth delay signals, the 30th NMOS transistor is turned on first, pulling down the voltage at the input of the fourth buffer; then the 29th NMOS transistor is turned on and the 30th PMOS transistor is turned off, then the 28th NMOS transistor is turned on, then the 29th PMOS transistor is turned off, and finally the 32nd NMOS transistor is turned on and the 22nd PMOS transistor is turned off.

[0124] The gate of the thirty-first NMOS transistor is connected to the second output terminal of the preparation signal circuit 230. The thirty-first NMOS transistor is turned off when the second preparation signal (low level) is received, and turned on otherwise. If the thirty-first NMOS transistor and / or the thirty-second NMOS transistor are turned on, the fifth resistor R5 will be shorted, pulling the gate voltage of the twenty-third PMOS transistor down to zero, thereby turning off the twenty-seventh NMOS transistor.

[0125] It should be noted that if all MOSFETs are turned off simultaneously, the voltage at each node within the comparator circuit will experience unpredictable drift due to parasitic capacitance and charge injection effects. This drift may cause a brief glitch or oscillation at the output of the voltage comparator circuit 30 at the moment of power-off. If this glitch is sampled by the subsequent latch circuit, it may incorrectly flip the latch state, causing the system to re-enter the reset state immediately after the reset process, or produce other unpredictable behaviors. In this embodiment, the shutdown is performed first, by pulling the voltage at the input of the fourth buffer to ground. This is equivalent to using a "lock" to firmly fix the output signal at the correct low level before power-off. In this way, even if the subsequent shutdown process causes internal noise, the output of the voltage comparator circuit 30 will not change.

[0126] Then, the gate voltage of the 27th NMOS transistor is lowered, and the path between the fourth buffer and the power supply voltage is turned off. Next, the differential pair circuit of the 25th and 26th NMOS transistors is turned off by turning on the 28th NMOS transistor; finally, the path between the resistor divider circuit and the power supply voltage is cut off, and the fifth resistor R5 is shorted. This is where the majority of the power consumption occurs, because the resistor divider circuit is directly connected between the power supply voltage and ground; if it remains on, it will continuously consume a considerable current. After turning off the 22nd PMOS transistor, the power consumption of the voltage comparator circuit 30 drops to zero.

[0127] like Figure 10 As shown, the latch circuit 40 includes:

[0128] NOR gate, NOT1 first NOT gate, latch, level shifter and NOT2 second NOT gate;

[0129] The first input terminal of the NOR gate is connected to the output terminal of the voltage comparator circuit 30, the second input terminal is connected to the third output terminal of the current source circuit 20, and the output terminal is connected to the data input terminal of the latch.

[0130] The input terminal of the first NOT gate NOT1 is connected to the fourth output terminal of the current source circuit 20, and the output terminal is connected to the enable terminal of the latch.

[0131] The input terminal of the level converter is connected to the output terminal of the latch, and the output terminal is connected to the input terminal of the second NOT gate (NOT2) and the second input terminal of the voltage comparison circuit 30. The level converter is used to convert the voltage at the input terminal of the level converter according to a preset conversion coefficient and then output the voltage.

[0132] The output of the second NOT gate NOT2 is connected to the reset terminal of the given device.

[0133] It should be noted that the input of the first NOT gate (NOT1) is connected to the fourth output of the current source circuit 20 (corresponding to the rdy signal in the figure), and its output is connected to the data input of the latch (active low). The first input of the NOR gate (NOR) is connected to the output of the voltage comparator circuit 30 (corresponding to por_rst in the figure), and the second input of the NOR gate (NOR) is connected to the third output of the current source circuit 20 (corresponding to rdy_d in the figure). The output of the level converter is connected to the second input of the voltage comparator circuit 30 (corresponding to power_enn in the figure). Therefore, power_enn is high and the latch circuit 40 outputs a low-level reset signal only when rdy_d, por_rst, and rdy are all low.

[0134] It should be explained that since power_enn and the delay signals generated by the five delay circuits are connected to the gate of the MOSFET, the MOSFET's conduction and turn-off are controlled. In order to prevent the output voltage of the latch from being mismatched with the MOSFET and thus unable to control the MOSFET to conduct or turn off accordingly, the output voltage of the latch needs to be level-shifted to a suitable voltage domain.

[0135] The preset conversion coefficients are determined by the R&D personnel based on design requirements.

[0136] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A power-on reset circuit, characterized by comprising: The current source starting circuit, the current source circuit, the voltage comparison circuit and the latch circuit are included. The power supply end of the current source starting circuit, the power supply end of the current source circuit and the power supply end of the voltage comparison circuit are connected to the power supply voltage respectively; the first output end of the current source starting circuit is connected to the first input end of the current source circuit; the current source starting circuit is used for outputting the first signal through the first output end when the power supply voltage is greater than or equal to the first preset voltage value; The first output end of the current source circuit is connected to the first input end of the current source starting circuit, the second output end is connected to the first input end of the voltage comparison circuit, the third output end is connected to the first input end of the latch circuit, and the fourth output end is connected to the second input end of the latch circuit; The current source circuit is used for establishing the reference current based on the power supply voltage when the first signal is received, outputting the reference voltage signal corresponding to the reference current through the second output end of the current source circuit, and outputting the first feedback signal through the first output end of the current source circuit; the current source circuit is also used for outputting the first preparation signal through the third output end of the current source circuit and the second preparation signal through the fourth output end of the current source circuit when the first signal is received; The output end of the voltage comparison circuit is connected to the third input end of the latch circuit; the voltage comparison circuit is used for performing voltage transformation on the power supply voltage connected to the voltage comparison circuit, and outputting the third preparation signal when the transformed voltage is greater than the reference voltage signal; The first output end of the latch circuit is connected to the second input end of the voltage comparison circuit, and the second output end is connected to the reset end of the given device; The latch circuit is used for outputting the second feedback signal through the first output end of the latch circuit and outputting the reset signal to the reset end of the given device through the second output end of the latch circuit when the first preparation signal, the second preparation signal and the third preparation signal are received; The voltage comparison circuit is also used for cutting off the electric path for voltage transformation when the second feedback signal is received; The current source starting circuit is also used for stopping outputting the first signal when the first feedback signal is received. The current source circuit further includes:

2. The power-on reset circuit of claim 1, wherein, The reference current circuit, the reference voltage circuit and the preparation signal circuit; The reference current circuit, the reference voltage circuit and the preparation signal circuit are connected to the power supply end of the current source circuit respectively; The input end of the reference current circuit is connected to the first output end of the current source starting circuit, and the output end is connected to the input end of the reference voltage circuit; the first output end of the reference voltage circuit is connected to the first input end of the current source starting circuit, and the second output end is connected to the first end of the voltage comparison circuit; the first output end of the preparation signal circuit is connected to the first input end of the latch circuit, and the second output end is connected to the second input end of the latch circuit; The reference current circuit is used for outputting the reference current to the reference voltage circuit when the first signal is received. ​ The reference voltage circuit is configured to output a first feedback signal to the current source starting circuit and convert the reference current into the reference voltage signal and output the reference voltage signal to the first end of the voltage comparison circuit when the reference current is received. The preparation signal circuit is configured to output the first preparation signal and the second preparation signal when the first signal and the power supply voltage are greater than the second preset voltage value.

3. The power-on reset circuit of claim 2, wherein, The reference current circuit comprises first to fourth PMOS tubes and first to sixth NMOS tubes. The source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply voltage, the drain of the first PMOS tube is connected to the source of the third PMOS tube, and the drain of the second PMOS tube is connected to the source of the fourth PMOS tube; the drain of the third PMOS tube is connected to the gate of the first PMOS tube, the gate of the second PMOS tube and the drain of the first NMOS tube; the gate of the first NMOS tube is connected to the power supply voltage, and the source is connected to the gate of the third PMOS tube, the gate of the fourth PMOS tube and the drain of the second NMOS tube; the gate of the second NMOS tube is connected to the gate of the third NMOS tube and the first output end of the current source starting circuit, and the source is connected to the drain of the fourth NMOS tube; the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube, and the source is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; the source of the fourth NMOS tube is connected to one end of the first resistor, and the other end of the first resistor is connected to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the drain of the third NMOS tube, and the source is grounded. The reference voltage circuit comprises a fifth PMOS tube, a sixth PMOS tube, a second resistor, a third resistor, a first capacitor and a second capacitor. The source of the fifth PMOS tube is connected to the source of the first PMOS tube and connected to the power supply voltage, the gate is connected to the gate of the first PMOS tube, and the drain is connected to the source of the sixth PMOS tube; the gate of the sixth PMOS tube is connected to the gate of the third PMOS tube, and the drain is connected to the first end of the second resistor, the first end of the first capacitor and the first input end of the current source starting circuit; the second end of the second capacitor is grounded; the second end of the second resistor is connected to the first end of the third resistor, the first end of the second capacitor and the first end of the voltage comparison circuit; the second end of the second capacitor is grounded; and the second end of the third resistor is grounded.

4. The power-on reset circuit of claim 3, wherein, The preparation signal circuit comprises a sixth NMOS tube, seventh to eleventh PMOS tubes, third to fifth capacitors, a first inverting Schmitt trigger and a second inverting Schmitt trigger. The source of the seventh PMOS is connected to the source of the first PMOS, and is connected to a power supply voltage; the gate of the seventh PMOS is connected to the gate of the first PMOS, and the drain is connected to the source of the eighth PMOS; the gate of the eighth PMOS is connected to the gate of the third PMOS, and the drain is connected to the gate and source of the sixth NMOS; the drain of the sixth NMOS is connected to the first input of the latch circuit, the first end of the third capacitor, the first end of the fourth capacitor, the source of the ninth PMOS, and the gate of the tenth PMOS; the second end of the third capacitor is grounded, and the second end of the fourth capacitor is connected to the source of the tenth PMOS; the drain of the tenth PMOS is grounded, and the drain of the ninth PMOS is connected to the gate of the eleventh PMOS, the first end of the fifth capacitor, and the second input of the latch circuit; the second end of the fifth capacitor is grounded; the source of the eleventh PMOS is connected to the gate of the ninth PMOS and the source of the eighth PMOS, and the drain is grounded.

5. The power-on reset circuit of claim 4, wherein, The current source starting circuit comprises: twelfth to seventeenth PMOS and seventh to thirteenth NMOS; The source of the twelfth PMOS, the source of the sixteenth PMOS, and the source of the seventeenth PMOS are connected to each other and to a power supply voltage; the drain of the twelfth PMOS is connected to the source of the thirteenth PMOS, the drain of the thirteenth PMOS is connected to the source of the fourteenth PMOS, the drain of the fourteenth PMOS is connected to the source of the fifteenth PMOS, and the drain of the fifteenth PMOS is connected to the drain of the seventh NMOS, the gate of the second NMOS, the gate of the eighth NMOS, and the gate of the seventh NMOS; the gate of the twelfth PMOS, the gate of the thirteenth PMOS, the gate of the fourteenth PMOS, and the gate of the fifteenth PMOS are connected and grounded; the source of the seventh NMOS is connected to the drain of the ninth NMOS, the gate of the ninth NMOS, and the gate of the tenth NMOS; the source of the ninth NMOS is grounded; the gate of the sixteenth PMOS is connected to the drain of the sixteenth PMOS, the gate of the seventeenth PMOS, and the drain of the eighth NMOS; the source of the eighth NMOS is connected to the drain of the tenth NMOS, and the source of the tenth NMOS is grounded; The drain of the seventeenth PMOS is connected to the drain of the eleventh NMOS, the drain of the twelfth NMOS, the gate of the twelfth NMOS, and the gate of the thirteenth NMOS; the gate of the eleventh NMOS is connected to the first end of the second resistor, and the source is grounded; the source of the twelfth NMOS is grounded; the source of the thirteenth NMOS is grounded, and the drain is connected to the gate of the first PMOS.

6. The power-on reset circuit of claim 5, wherein, The current source circuit further comprises a hysteresis circuit; The hysteresis circuit comprises nineteenth to twenty-first PMOS and fifteenth to twenty-fourth NMOS; The source of the nineteenth PMOS tube and the source of the twentieth PMOS tube are connected to the source of the first PMOS tube; the gate of the nineteenth PMOS tube is connected to the gate of the twentieth PMOS tube, the gate of the first PMOS tube and the drain of the thirteenth NMOS tube; the drain of the nineteenth PMOS tube is connected to the drain of the fifteenth NMOS tube; the source of the fifteenth NMOS tube is connected to the gate of the fifteenth NMOS tube, the gate of the nineteenth NMOS tube, the gate of the sixteenth NMOS tube and the drain of the sixteenth NMOS tube; the source of the sixteenth NMOS tube is connected to the drain of the seventeenth NMOS tube; the gate of the seventeenth NMOS tube is connected to the gate of the fourth NMOS tube, and the source is grounded; The source of the twenty-first PMOS tube is connected to the drain of the twentieth PMOS tube, the gate is connected to the gate of the third PMOS tube, and the drain is connected to the drain of the eighteenth NMOS tube, the drain of the nineteenth NMOS tube, the gate of the eighteenth NMOS tube, the gate of the twentieth NMOS tube, the gate of the twenty-third NMOS tube and the drain of the twenty-fourth NMOS tube; the source of the nineteenth NMOS tube is grounded; the source of the eighteenth NMOS tube is connected to the drain of the twentieth NMOS tube; the source of the twentieth NMOS tube is connected to the drain of the twenty-first NMOS tube, the gate of the twenty-first NMOS tube and the gate of the twenty-second NMOS tube; the drain of the twenty-second NMOS tube is connected to the source of the twenty-first NMOS tube, and the source is grounded; the gate of the twenty-fourth NMOS tube is connected to the drain of the eighteenth PMOS tube, and the source is grounded; the source of the twenty-third NMOS tube is grounded, and the drain is connected to the source of the sixth NMOS tube; The current source starting circuit further comprises a first diode, a fourteenth NMOS tube, an eighteenth PMOS tube and a third inverting Schmitt trigger; The source of the eighteenth PMOS tube is connected to the source of the twelfth PMOS tube, the gate is connected to the gate of the sixteenth PMOS tube, and the drain is connected to the drain of the fourteenth NMOS tube and the input end of the third inverting Schmitt trigger, and the output end of the third inverting Schmitt trigger is connected to the gate of the twenty-fourth NMOS tube; the gate of the fourteenth NMOS tube is grounded, and the source is connected to the anode of the first diode; the cathode of the first diode is grounded.

7. The power-on reset circuit of claim 5, wherein, The voltage comparison circuit comprises a twenty-second PMOS tube to a twenty-eighth PMOS tube, a twenty-fifth NMOS tube to a twenty-seventh NMOS tube, a fourth resistor to an eighth resistor, a sixth capacitor and a seventh capacitor; The source of the twenty-second PMOS tube is connected to the source of the twenty-fourth PMOS tube and the source of the twenty-seventh PMOS tube, and is connected to the power supply voltage; the drain of the twenty-second PMOS tube is connected to the first end of the fourth resistor, and the gate is connected to the first output end of the latch circuit; the second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the sixth resistor; the second end of the fifth resistor is grounded; the second end of the sixth resistor is connected to the first end of the sixth capacitor and the gate of the twenty-third PMOS tube; the second end of the sixth capacitor is grounded; The drain of the twenty-fourth PMOS tube is connected to the source of a twenty-fifth PMOS tube, the drain of the twenty-fifth PMOS tube is connected to the source of a twenty-third PMOS tube and the source of a twenty-sixth PMOS tube; the gate of the twenty-sixth PMOS tube is connected to the first end of a seventh capacitor and the first end of an eighth resistor, the second end of the eighth resistor is connected to the second output end of the current source circuit, and the second end of the seventh capacitor is grounded; the drain of a twenty-fifth NMOS tube is connected to the drain of the twenty-third PMOS tube, the gate is connected to the gate of a twenty-sixth NMOS tube, and the source is grounded; a seventh resistor is connected in parallel between the drain and the gate of the twenty-fifth NMOS tube; the drain of the twenty-sixth PMOS tube is connected to the drain of the twenty-sixth NMOS tube and the gate of a twenty-seventh NMOS tube; the source of the twenty-sixth NMOS tube is grounded; the source of the twenty-seventh NMOS tube is grounded, and the drain is connected to the third input end of the latch circuit and the drain of a twenty-eighth PMOS tube; the source of the twenty-eighth PMOS tube is connected to the drain of a twenty-seventh PMOS tube, and the gate is connected to the gate of the twenty-fifth PMOS tube and the gate of a third PMOS tube; the gate of the twenty-fourth PMOS tube is connected to the gate of a first PMOS tube.

8. The power-on reset circuit of claim 7, wherein, The voltage comparison circuit further comprises five delay circuits; The input end of a first delay circuit is connected to the first output end of the latch circuit, and the output end is connected to the input end of a second delay circuit; the output end of the second delay circuit is connected to the input end of a third delay circuit, the output end of the third delay circuit is connected to the input end of a fourth delay circuit, and the output end of the fourth delay circuit is connected to the input end of a fifth delay circuit; The voltage comparison circuit further comprises twenty-eighth to thirty-second NMOS tubes, a twenty-ninth PMOS tube and a thirtieth PMOS tube; The source of the twenty-ninth PMOS tube is connected to the drain of the twenty-fifth PMOS tube, the gate is connected to the output end of the fourth delay circuit, and the drain is connected to the source of the twenty-third PMOS tube and the source of a twenty-sixth PMOS tube; the source of the thirtieth PMOS tube is connected to the drain of the twenty-eighth PMOS tube, the gate is connected to the output end of the second delay circuit, and the drain is connected to the drain of the twenty-seventh NMOS tube; The drain of the twenty-eighth NMOS tube is connected to the gate of the twenty-fifth NMOS tube, the gate is connected to the output end of the third delay circuit, and the source is grounded; the drain of the twenty-ninth NMOS tube is connected to the gate of the twenty-seventh NMOS tube, the gate is connected to the output end of the second delay circuit, and the source is grounded; the drain of the thirtieth NMOS tube is connected to the drain of the twenty-seventh NMOS tube, the gate is connected to the output end of the first delay circuit, and the source is grounded; the drain of a thirty-first NMOS tube is connected to the first end of a fifth resistor, the source is connected to the second end of the fifth resistor and grounded, and the gate is connected to the third output end of the current source circuit; the drain of a thirty-second NMOS tube is connected to the first end of the fifth resistor, the source is connected to the second end of the fifth resistor and grounded, and the gate is connected to the output end of the fifth delay circuit; A gate of the twenty-second PMOS is connected to an output end of the fifth delay circuit.

9. The power-on reset circuit of any one of claims 5 to 8, wherein, The sixth NMOS, the fourteenth NMOS and the sixteenth NMOS are low threshold NMOS.

10. The power-on reset circuit of claim 8, wherein, The latch circuit comprises: The NOR gate, the first NOT gate, the latch, the level converter and the second NOT gate; A first input end of the NOR gate is connected to an output end of the voltage comparison circuit, a second input end is connected to a third output end of the current source circuit, and an output end is connected to a data input end of the latch; An input end of the first NOT gate is connected to a fourth output end of the current source circuit, and an output end is connected to an enable end of the latch; An input end of the level converter is connected to an output end of the latch, and an output end is connected to an input end of the second NOT gate and a second input end of the voltage comparison circuit; the level converter is used for performing voltage amplitude conversion on a voltage at the input end of the level converter according to a preset conversion coefficient and then outputting; An output end of the second NOT gate is connected to a reset end of the given device.

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