Method for measuring and correcting offset between layers in a semiconductor device and offset target therefor

Abstract

A method for measuring offset in the manufacture of semiconductor device wafers, the method comprising: measuring the offset between layers of the semiconductor device wafer in a first example and providing a first offset indication; measuring the offset between layers of the semiconductor device wafer in a second example and providing a second offset indication; providing an offset measurement difference output in response to a difference between the first offset indication and the second offset indication; providing a baseline difference output; and improving the difference between the offset measurement difference output and the baseline difference output.

Description

[0001] References to related applications

[0002] Reference is made to U.S. Provisional Patent Application No. 62 / 825,262, filed on March 28, 2019, and entitled SINGLE LAYER OVERLAY, the disclosure of which is hereby incorporated by reference and priority to which is hereby claimed. Technical Field

[0003] The present invention relates to the field of metrology and more particularly to offset metrology procedures. Background Art

[0004] Various types of devices are known for metering and offset metering procedures. Summary of the invention

[0005] The present invention seeks to provide an improved method for measuring drift in the manufacture of semiconductor device wafers and improvements thereto.

[0006] Therefore, according to a preferred embodiment of the present invention, a method for measuring offset in the manufacture of semiconductor device wafers is provided, the method comprising: measuring the offset between layers of the semiconductor device wafer in a first example and providing a first offset indication; measuring the offset between layers of the semiconductor device wafer in a second example and providing a second offset indication; providing an offset measurement difference output in response to a difference between the first offset indication and the second offset indication; providing a baseline difference output; and improving the difference between the offset measurement difference output and the baseline difference output.

[0007] Preferably, the improvement comprises at least one of: changing an offset metrology; and changing at least one process step in the fabrication of a semiconductor device wafer.

[0008] According to a preferred embodiment of the present invention, the method for measuring the offset in the manufacturing of semiconductor device wafers further includes comparing the difference between the offset measurement difference output and the baseline difference output with a threshold value and the improvement occurs when the difference between the offset measurement difference output and the baseline difference output exceeds the threshold value. Additionally or alternatively, the baseline difference output represents a calculated summary of the difference between the first offset indication and the second offset indication.

[0009] According to a preferred embodiment of the present invention, the first example and the second example involve different stages in a manufacturing process of an intended same single batch of semiconductor device wafers from which the semiconductor device wafers are selected.

[0010] According to a preferred embodiment of the present invention, the same semiconductor device wafer is measured in the first example and the second example. Alternatively, different semiconductor device wafers selected from the single batch of semiconductor devices intended to be the same are measured in the first example and the second example.

[0011] Preferably, the first instance and the second instance comprise different regions of a single target on the semiconductor device wafer.

[0012] According to a preferred embodiment of the invention, the offset measurement difference output comprises an indication of metrology quality.

[0013] According to a preferred embodiment of the invention, said offset measurement difference output comprises an indication of the quality of at least one of said different phases.

[0014] Preferably, the method further comprises, in a third example, using at least one of the first offset measurement indication and the second offset measurement indication to improve offset measurement between layers of a semiconductor device. Additionally, the third example comprises a subsequent stage in the manufacturing process of the semiconductor device.

[0015] According to a preferred embodiment of the present invention, the method further comprises using the offset measurement difference output to improve parameters of the manufacturing process of the intended identical single batch of semiconductor devices from which the semiconductor device wafers are selected.

[0016] According to a preferred embodiment of the present invention, there is also provided a target for use in measuring an offset in the manufacture of a semiconductor device chip and in calibrating the measurement of the offset, the target comprising: at least a first structure arranged on a first layer of the semiconductor device chip; and at least a second and a third different structure arranged on a second layer of the semiconductor device.

[0017] Preferably, the second and third different structures are formed simultaneously using the same manufacturing tool and method. Additionally or alternatively, at least one of the first structure, the second structure and the third structure is defined by a plurality of sub-lines and sub-spaces between the sub-lines, the sub-lines being characterized by a pitch.

[0018] According to a preferred embodiment of the present invention, the second structure is defined by a plurality of second structure sub-lines and a plurality of second structure sub-spaces having a second structure pitch; the third structure is defined by a plurality of third structure sub-lines and a plurality of third structure sub-spaces having a third structure pitch; and the second structure pitch and the third structure pitch are different from each other.

[0019] According to a preferred embodiment of the present invention, the object is characterized by rotational symmetry. Additionally or alternatively, the first structure, the second structure and the third structure are periodic structures.

[0020] Preferably, the second structure and the third structure overlie the first periodic structure.

[0021] According to a preferred embodiment of the present invention, the first structure, the second structure and the third structure are rods. Alternatively, the first structure, the second structure and the third structure are rectangular frames.

[0022] According to a preferred embodiment of the present invention, the target further comprises at least a fourth structure and the first structure, the second structure, the third structure and the fourth structure are characterized by rotational symmetry. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be more fully understood and appreciated from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a simplified flow chart illustrating a method of measuring an offset between layers of a semiconductor device according to a preferred embodiment of the present invention;

[0025] Figure 2 yes Figure 1 A simplified illustration of an embodiment of a method showing multiple examples of measuring an offset between two layers of a semiconductor device wafer at different stages in a semiconductor manufacturing process;

[0026] Figure 3 yes Figure 1 A simplified illustration of an embodiment of a method showing multiple examples of measuring an offset between two layers of a semiconductor device wafer using different regions of a target;

[0027] Figure 4 yes Figure 1 A simplified illustration of an embodiment of a method showing multiple examples of measuring an offset between two layers of a semiconductor device wafer using different regions of a second target;

[0028] Figure 5 yes Figure 1 A simplified illustration of an embodiment of a method showing a plurality of examples of measuring an offset between two layers of a semiconductor device wafer using different regions of a third target;

[0029] Fig. 6A , 6B and 6C is Figure 1 a simplified illustration of yet another embodiment of a method showing multiple examples of measuring an offset between two layers of a semiconductor device wafer using different regions of a fourth target;

[0030] Fig. 7A and 7B yes Figure 1a simplified illustration of yet another embodiment of a method showing multiple examples of measuring an offset between two layers of a semiconductor device wafer using different regions of a fifth target;

[0031] Figure 8 is a simplified flow chart illustrating improvement of measured offsets by modifying parameters of a manufacturing process for a semiconductor device wafer; and

[0032] Fig.9A and 9B Together are simplified flow charts illustrating improvement of measured offsets by modifying metrology parameters associated with the measurement of offsets between layers of a semiconductor device wafer. DETAILED DESCRIPTION

[0033] Reference Figure 1 , which is a simplified flow chart illustrating a method for measuring offset between layers of a semiconductor device wafer according to a preferred embodiment of the present invention, and refers to Figure 2 7, which are illustrations of various embodiments of the method. It should be understood that Figure 1 The method described in can be used to manufacture a semiconductor device.

[0034] like Figure 1 As seen in FIG. 1 , in a first step 100 , an offset between two layers of a semiconductor device wafer selected from a batch of semiconductor device wafers (BSDWII) 102 intended to be the same is measured in a first example. A first offset indication is provided.

[0035] Thereafter, in a next step 110 , an offset between two layers of the semiconductor device wafer is measured in a second instance and a second offset indication is provided.

[0036] It should be appreciated that the semiconductor device wafer whose offset is measured in steps 100 and 110 may be the same. Alternatively, the semiconductor device wafer measured in the second example may be a different wafer selected from the same BSDWII 102 from which the semiconductor device wafer measured in the first example was selected.

[0037] It should be further understood that the first layer and the second layer of the semiconductor device wafer whose offset is measured in steps 100 and 110 may be the same. Alternatively, at least one of the first layer and the second layer of the semiconductor device wafer measured in the second example may be different from the first layer and the second layer of the semiconductor device wafer measured in the first example.

[0038] It should be further understood that the offset measurements in steps 100 and 110 may be measured using the same measurement parameters or using different measurement parameters.

[0039] As seen in the next step 120, the difference between the offset measured in the first instance and the offset measured in the second instance is stored and in a subsequent step 122, an offset measurement difference output is generated by comparing the stored difference to the baseline difference output. In a preferred embodiment of the present invention, the baseline difference output represents a calculated summary of the differences between the first offset indication and the second offset indication, such as an average or mean. In a preferred embodiment of the present invention, this calculated summary of the differences between the first offset indication and the second offset indication is obtained from the first offset indication and the second offset indication measured on a previously processed semiconductor device wafer selected from the BSDWII 102.

[0040] In a subsequent step 130 , the offset measurement difference output in the form of the difference between the offset measured in the first instance and the offset measured in the second instance stored in step 120 and the baseline difference output used in step 122 is compared to a predetermined threshold.

[0041] As indicated at subsequent step 132, if the offset measurement difference output of step 130 does not exceed a predetermined threshold, the method continues by checking whether there are additional semiconductor device wafers to be processed, and the method ends at step 134. If additional semiconductor device wafers are to be processed, the method continues to the next step 140, where conventional manufacturing and metrology continues for the next semiconductor wafer(s) in BSDWII 102. As indicated by arrow 142, the conventional manufacturing and metrology process includes repetition of steps 100, 110, 120, 122, and 130.

[0042] As indicated at subsequent step 150, if the deviation measurement difference output exceeds a predetermined threshold, then improvement in either or both wafer fabrication and metrology has occurred.

[0043] Figure 2 Five typical process stages in wafer fabrication are illustrated, indicated by steps 202, 204, 206, 208, and 210. These stages are identified as follows: photolithography step 202, mask opening step 204, etching step 206, polishing step 208, and forming additional layers step 210. It should be understood that not all of steps 202, 204, 206, 208, and 210 need to be performed. For example, typically only one of the steps mask opening 204 and etching 206 is performed on a given semiconductor device wafer. It should be further understood that other steps may also be performed before, between, or after steps 202, 204, 206, 208, and 210.

[0044] Figure 2Also illustrated in a simplified manner are the first layer 220 and the second layer 230 of a portion of a typical semiconductor wafer precursor at four intermediate stages indicated by stages 242, 244, 246 and 248, respectively, each of which is intermediate between pairs of corresponding process stages 202 and 204, 204 and 206, 206 and 208, and 208 and 210.

[0045] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above description of can be any two of the intermediate stages 242, 244, 246 and 248, respectively. Figure 1 The first offset indication and the second offset indication mentioned in the above description may be any two of the following offset indications: a post-lithography offset indication 252, a post-mask opening offset indication 254, a post-etch offset indication 256, and a post-polishing offset indication 258 corresponding to the intermediate stages 242, 244, 246, and 248, respectively.

[0046] According to the above reference Figure 1 Steps 120 and 130 are described as making a plurality of summaries of the differences between the offset indications 252, 254, 256, and 258. These summaries of the differences including the comparison between post-lithography offset and post-mask opening offset, the comparison between post-lithography offset and post-etch offset, the comparison between post-mask opening offset and post-etch offset, the comparison between post-lithography offset and post-polishing offset, the comparison between post-mask opening offset and post-polishing offset, and the comparison between post-etch offset and post-polishing offset are indicated by respective reference numerals 260, 262, 264, 266, 268, and 270. Each of these summaries may be compared to an appropriate threshold value, as described above with reference to Figure 1 describe.

[0047] It should be appreciated that any of the offset indications 252 , 254 , 256 , and 258 may be used to optimize offset measurements between layers of a semiconductor device at a subsequent stage in the manufacturing process of the BSDWII 102 .

[0048] Figure 3 The target 300 is preferably illustrated as having three periodic structures 302, 304 and 306. Figure 3 As particularly seen in the cross-sectional enlargement A of , a particular feature of the present invention is that the periodic structure 302 is formed on the first layer 310 of the semiconductor device wafer and both the periodic structures 304 and 306 are formed on the second layer 320 of the semiconductor device wafer. A particular feature of an embodiment of the present invention is that the periodic structures 304 and 306 are formed simultaneously using the same manufacturing tools and methods. It should be understood that the first layer 310 and the second layer 320 can be, but need not be, adjacent.

[0049] It should be noted that target 300 preferably includes four groups 330 of periodic structures 302, 304, and 306. Each of the groups 330 appears in target 300 in a different mutually orthogonal orientation, thereby giving rotational symmetry to target 300. It should be appreciated that each of the groups 330 of periodic structures 302, 304, and 306 are preferably identical to one another except for their orientation.

[0050] In a preferred embodiment of the present invention, the periodic structures 302, 304, and 306 are each defined by a plurality of mutually parallel lines 340, 342, and 344 and mutually parallel spaces 346, 348, and 350 between the respective mutually parallel lines 340, 342, and 344. The mutually parallel lines 340 and the mutually parallel spaces 346, the mutually parallel lines 342 and the mutually parallel spaces 348, and the mutually parallel lines 344 and the mutually parallel spaces 350 are arranged along axes 352, 354, and 356, respectively.

[0051] Preferably, lines 340, 342 and 346 have respective pitches C, D and E each in the range of 1 μm to 3 μm and line widths that are 10% to 90% of each respective pitch C, D or E (50% of C, D or E most typically).

[0052] Lines 340, 342, and 346 are typically segmented, but they need not be segmented. In embodiments where lines 340, 342, and 346 are segmented, such as in Figure 3 As seen in the enlarged view B of FIG. 3 , each of the lines 340, 342, and 346 is defined by a plurality of respective sub-lines 360, 362, and 364 and respective sub-spaces 366, 368, and 370 between the sub-lines 360, 362, and 364. Preferably, the sub-lines 360, 362, and 364 have respective segment pitches F, G, and H, each in the range of 10 nm to 200 nm.

[0053] The periodic structures 302 , 304 , and 306 may be distinguished from one another by any of their respective pitches C, D, and E, their respective line widths, and their segment pitches F, G, and H, and most preferably by their segment pitches F, G, and H.

[0054] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above discussion of can be offset measurements performed using the periodic structures 302 and 304 or the periodic structures 302 and 306. Correspondingly, in Figure 1 The first offset indication and the second offset indication mentioned in the above discussion of may be offset indications obtained from each of offset measurements made using the periodic structures 302 and 304 or the periodic structures 302 and 306 .

[0055] It will be appreciated that since periodic structures 304 and 306 are preferably formed together, any difference in the offset indication between periodic structures 302 and 304 and periodic structures 302 and 306 within a predetermined threshold indicates a need for improvement in the offset metrology process.

[0056] Figure 4 The target 400 is preferably illustrated as having three structures 402, 404 and 406. Figure 4 As particularly seen in the cross-sectional enlargement A of , a particular feature of the present invention is that structure 402 is formed on a first layer 410 of a semiconductor device wafer and both structures 404 and 406 are formed on a second layer 420 of a semiconductor device wafer. A particular feature of an embodiment of the present invention is that structures 404 and 406 are formed simultaneously using the same manufacturing tools and methods. It should be understood that the first layer 410 and the second layer 420 can, but need not, be adjacent.

[0057] It should be noted that target 400 preferably includes four groups 430 of structures 402, 404, and 406. Each of the groups 430 appears in target 400 in a different mutually orthogonal orientation, thereby giving target 400 rotational symmetry. It should be appreciated that, except for their orientation, each of the groups 430 of structures 402, 404, and 406 are preferably identical to each other. In a preferred embodiment of the present invention, structures 402, 404, and 406 are rods.

[0058] Preferably, structures 402, 404, and 406 have respective widths I, J, and K that are each in the range of 0.5 μm to 1.5 μm. Structures 402, 404, and 406 are typically segmented, but they need not be segmented. In embodiments where structures 402, 404, and 406 are segmented, such as in Figure 4 As seen in the enlarged view B of , each of the structures 402, 404, and 406 is defined by a plurality of respective sub-lines 460, 462, and 464 and respective sub-spaces 466, 468, and 470 between the sub-lines 460, 462, and 464. Preferably, the sub-lines 460, 462, and 464 have respective segment pitches L, M, and N, each in the range of 10 nm to 200 nm.

[0059] Structures 402 , 404 , and 406 may be distinguished from one another by any of their respective widths I, J, and K and their segment pitches L, M, and N, and most preferably by their segment pitches L, M, and N. FIG.

[0060] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above discussion of can be offset measurements performed using structures 402 and 404 or structures 402 and 406. Figure 1The first offset indication and the second offset indication mentioned in the above discussion of may be offset indications obtained from each of offset measurements made using structures 402 and 404 or structures 402 and 406 .

[0061] It should be appreciated that since structures 404 and 406 are preferably formed together, any difference in the offset indication between structures 402 and 404 and structures 402 and 406 within a predetermined threshold indicates a need for improvement in the offset metrology process.

[0062] Figure 5 The target 500 is preferably illustrated as having three structures 502, 504 and 506. Figure 5 500 . As can be seen in particular in the cross-sectional enlargement A of , a particular feature of the present invention is that structure 502 is formed on a first layer 510 of a semiconductor device wafer and both structures 504 and 506 are formed on a second layer 520 of a semiconductor device wafer. A particular feature of an embodiment of the present invention is that structures 504 and 506 are formed simultaneously using the same manufacturing tools and methods. It should be understood that the first layer 510 and the second layer 520 can but need not be adjacent. It should be noted that each of structures 502, 504, and 506 is characterized by rotational symmetry, thereby giving rotational symmetry to object 500. In a preferred embodiment of the present invention, structures 502, 504, and 506 are frames, preferably rectangular or square frames.

[0063] Preferably, structures 502, 504, and 506 have respective widths O, P, and Q that are each in the range of 0.5 μm to 1.5 μm. Structures 502, 504, and 506 are typically segmented, but they need not be segmented. In embodiments where structures 502, 504, and 506 are segmented, such as in Figure 5 As seen in the enlarged view B of , each of the structures 502, 504, and 506 is defined by a plurality of respective sub-lines 560, 562, and 564 and respective sub-spaces 566, 568, and 570 between the sub-lines 560, 562, and 564. Preferably, the sub-lines 560, 562, and 564 have respective segment pitches R, S, and T, each in the range of 10 nm to 200 nm.

[0064] Structures 502 , 504 , and 506 may be distinguished from one another by any of their respective widths O, P, and Q and their segment pitches R, S, and T, and most preferably by their segment pitches R, S, and T. As shown in FIG.

[0065] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above discussion of can be offset measurements performed using structures 502 and 504 or structures 502 and 506. Figure 1The first offset indication and the second offset indication mentioned in the above discussion of may be offset indications obtained from each of offset measurements made using structures 502 and 504 or structures 502 and 506 .

[0066] It should be appreciated that since structures 504 and 506 are preferably formed together, any difference in the offset indication between structures 502 and 504 and structures 502 and 506 within a predetermined threshold indicates a need for improvement in the offset metrology process.

[0067] Figures 6A to 6C The target 600 is preferably illustrated as having three periodic structures 602, 604 and 606. Fig. 6A As can be seen in particular in the cross-sectional enlargements A and B of FIG. 1 , periodic structure 602 is formed on a first layer 610 of a semiconductor device wafer and both periodic structures 604 and 606 are formed on a second layer 620 of a semiconductor device wafer. A particular feature of an embodiment of the present invention is that periodic structures 604 and 606 are formed simultaneously using the same manufacturing tools and methods. It should be understood that the first layer 610 and the second layer 620 may, but need not, be adjacent.

[0068] Figure 6B Description Formation Fig. 6A A preferred embodiment of a portion of a periodic structure 602 of a target 600 . Figure 6C Description Formation Fig. 6A A preferred embodiment of the periodic structures 604 and 606 of the portion of target 600 .

[0069] like Figure 6B As can be seen in particular, target 600 preferably includes four groups 622 of periodic structures 602 and four groups 624 of periodic structures 602. Figure 6C As can be seen in particular, target 600 preferably includes four groups 626 of periodic structure 604 and four groups 628 of periodic structure 606. Fig. 6A As can be seen in particular, group 626 of periodic structures 604 overlies group 622 of periodic structures 602 , and group 628 of periodic structures 606 overlies group 624 of periodic structures 602 .

[0070] like Figure 6B and 6C604 and 606 are formed parallel to the axis 630 and in the other two of the groups 622, 624, 626 and 628, the corresponding periodic structure 602, 604 or 606 is formed parallel to the axis 632 (which is perpendicular to the axis 630). Each pair of periodic structures 602 and 604 and 602 and 606 parallel to the same axis is distinguished from each other by having different offsets between the corresponding periodic structures 602 and 604 and 602 and 606, each in the range of 10 nm to 40 nm. It should be understood that each of the groups 622, 624, 626 and 628 of periodic structures 602, 604 and 606 are preferably identical to each other except for their orientation and offset.

[0071] like Figure 6B As can be seen in particular, in a preferred embodiment of the present invention, the periodic structure 602 is defined by a plurality of mutually parallel lines 640 and mutually parallel spaces 646 between the mutually parallel lines 640. The mutually parallel lines 640 and the mutually parallel spaces 646 are arranged along an axis parallel to the axis 630 or 632.

[0072] As in Figure 6C As seen in the embodiment illustrated in FIG. 1 , periodic structures 604 and 606 are each defined by a plurality of mutually parallel lines 642 and 644 and mutually parallel spaces 648 and 650 between the respective mutually parallel lines 642 and 644. The mutually parallel lines 642 and mutually parallel spaces 648 and the mutually parallel lines 644 and mutually parallel spaces 650 are arranged along an axis parallel to the axis 630 or 632.

[0073] Preferably, in the periodic structures 602, 604 and 606, the lines 640, 642 and 646 have respective pitches U, V and W each in the range of 300nm to 1μm and a line width that is 10% to 90% of each respective pitch U, V and W (most typically 50% of U, V and W).

[0074] In periodic structures 602, 604, and 606, lines 640, 642, and 646 are typically segmented, but they need not be segmented. In embodiments where lines 640, 642, and 646 are segmented, such as in Figure 6B The enlarged C and Figure 6C As seen in the enlarged views D and E of , each of the lines 640, 642, and 646 is defined by a plurality of respective sub-lines 660, 662, and 664 and respective sub-spaces 666, 668, and 670 between the sub-lines 660, 662, and 664. Preferably, the sub-lines 660, 662, and 664 have respective segment pitches α, β, and γ, each in the range of 10 nm to 200 nm.

[0075] The periodic structures 602, 604 and 606 may be distinguished from each other by any of their respective pitches U, V and W, their respective line widths, and their segment pitches α, β and γ, and most preferably by their segment pitches α, β and γ.

[0076] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above discussion of can be offset measurements performed using the periodic structures 602 and 604 or the periodic structures 602 and 606. Correspondingly, in Figure 1 The first offset indication and the second offset indication mentioned in the above discussion of may be offset indications obtained from each of offset measurements made using periodic structures 602 and 604 or periodic structures 602 and 606 .

[0077] It will be appreciated that since periodic structures 604 and 606 are preferably formed together, any difference in the offset indication between periodic structures 602 and 604 and periodic structures 602 and 606 within a predetermined threshold indicates a need for improvement in the offset metrology process.

[0078] Fig. 7A and 7B The target 700 is preferably illustrated as having four structures 701, 702, 704 and 706. Fig. 7A As can be seen particularly in the cross-sectional enlargements A and B of , a particular feature of the present invention is that both structures 701 and 702 are formed on a first layer 710 of a semiconductor device wafer and both structures 704 and 706 are formed on a second layer 720 of a semiconductor device wafer. A particular feature of an embodiment of the present invention is that the paired structures 701 and 702 and 704 and 706 are each formed simultaneously using the same manufacturing tools and methods. It should be understood that the first layer 710 and the second layer 720 can be adjacent but not necessarily so. It should be noted that each of the structures 701, 702, 704 and 706 is characterized by rotational symmetry, thereby giving the object 700 rotational symmetry.

[0079] It should be further understood that structures 701, 702, 704, and 706 may be any structure characterized by rotational symmetry. Fig. 7A and 7B 700 is shown as having four structures, but target 700 may have any even number of structures ranging from 4 to 20 structures, provided that each pair of structures follows the pattern of structure 701 with structure 704 and structure 702 with structure 706.

[0080] Structures 701, 702, 704, and 706 are typically segmented, but they need not be segmented. In embodiments where structures 701, 702, 704, and 706 are segmented, as in the enlarged Figure 7B As seen in FIG. 1 , each of structures 701, 702, 704, and 706 is defined by a plurality of respective sub-lines 760, 761, 762, and 764 and respective sub-spaces 766, 767, 768, and 770 between sub-lines 760, 761, 762, and 764. Preferably, sub-lines 760, 761, 762, and 764 have respective segment pitches δ, ε, ζ, and η, each in the range of 10 nm to 200 nm. Structures 701, 702, 704, and 706 are preferably distinguished from each other by any of their respective segment pitches δ, ε, ζ, and η.

[0081] A particular feature of an embodiment of the present invention is that Figure 1 The first example and the second example mentioned in the above discussion of can be offset measurements performed using structures 701 and 704 or structures 702 and 706. Figure 1 The first offset indication and the second offset indication mentioned in the above discussion of may be offset indications obtained from each of offset measurements made using structures 701 and 704 or structures 702 and 706 .

[0082] It will be appreciated that since each of the paired structures 701 and 702 and 704 and 706 are preferably each formed together, any difference in the offset indication between structures 701 and 704 and 702 and 706 within a predetermined threshold indicates a need for improvement in the offset metrology process.

[0083] Reference Figure 8 , which is a description that can be combined with the above reference Figures 1 to 2 A simplified flow chart of a method 800 for improving a measured shift by modifying parameters of a manufacturing process for a semiconductor device wafer using a method described herein.

[0084] It should be understood that the method 800 described below is executed as Figure 1 The method described in step 150 is used to determine Figure 2 Which stage of the process described in needs improvement?

[0085] As seen in a first step 804 , the method 800 determines whether the first offset indication and the second offset indication are the post-lithography offset indication 252 and the post-mask opening offset indication 254 .

[0086] If the first and second offset indications are the post-lithography offset indication 252 and the post-mask opening offset indication 254, the method 800 proceeds to the next step 806, where the mask opening stage 204 is modified in preparation for processing further semiconductor device wafers. For example, the etch depth of the mask opening stage may be modified or material properties such as the refractive index or dielectric constant of the measured layer may be modified.

[0087] If the first and second offset indications are not the post-lithography offset indication 252 and the post-mask opening offset indication 254 , the method 800 proceeds to the next step 808 where the method 800 determines whether the first and second offset indications are the post-lithography offset indication 252 and the post-etch offset indication 256 .

[0088] If the first and second shift indications are post-lithography shift indication 252 and post-etch shift indication 256, then method 800 proceeds to next step 810, where etching phase 206 is modified in preparation for processing further semiconductor device wafers. For example, etching time may be modified or material properties such as the refractive index or dielectric constant of the measured layer may be modified.

[0089] If the first and second offset indications are not the post-lithography offset indication 252 and the post-etch offset indication 256 , the method 800 proceeds to the next step 812 where the method 800 determines whether the first and second offset indications are the post-mask opening offset indication 254 and the post-etch offset indication 256 .

[0090] If the first and second shift indications are the post-mask open shift indication 254 and the post-etch shift indication 256, the method 800 proceeds to the next step 814, where the etching phase 206 is modified in preparation for processing further semiconductor device wafers. For example, the etching time may be modified or a material property such as the refractive index or dielectric constant of the measured layer may be modified.

[0091] If the first and second offset indications are not the post-mask open offset indication 254 and the post-etch offset indication 256 , the method 800 proceeds to the next step 816 where the method 800 determines whether the first and second offset indications are the post-lithography offset indication 252 and the post-polishing offset indication 258 .

[0092] If the first and second shift indications are the post-lithography shift indication 252 and the post-polishing shift indication 258, the method 800 proceeds to the next step 818, where at least one of the etching phase 206 and the polishing phase 208 is modified in preparation for processing further semiconductor device wafers. For example, any of the etching time, polishing time, polishing angle, and material used in the polishing phase may be adjusted or material properties such as the refractive index or dielectric constant of the measured layer may be modified.

[0093] If the first and second offset indications are not the post-lithography offset indication 252 and the post-polishing offset indication 258 , the method 800 proceeds to the next step 820 where the method 800 determines whether the first and second offset indications are the post-mask opening offset indication 254 and the post-polishing offset indication 258 .

[0094] If the first and second offset indications are the post-mask open offset indication 254 and the post-polish offset indication 258, the method 800 proceeds to the next step 822, where the polishing phase 208 is modified in preparation for processing further semiconductor device wafers. For example, any of the polishing time, polishing angle, and material used in the polishing phase may be adjusted or material properties such as the refractive index or dielectric constant of the measured layer may be modified.

[0095] If the first and second offset indications are not the post-mask open offset indication 254 and the post-polish offset indication 258 , the method 800 proceeds to the next step 824 where the method 800 determines whether the first and second offset indications are the post-etch offset indication 256 and the post-polish offset indication 258 .

[0096] If the first and second offset indications are the post-etch offset indication 256 and the post-polish offset indication 258, the method 800 proceeds to the next step 826, where the polishing phase 208 is modified in preparation for processing further semiconductor device wafers. For example, any of the polishing time, polishing angle, and material used in the polishing phase may be adjusted or material properties such as the refractive index or dielectric constant of the measured layer may be modified.

[0097] Reference Fig.9A and 9B , which together illustrate that the above reference Figure 1 FIG. 7 is a simplified flow chart of a method 900 for improving measured offsets by modifying metrology parameters associated with the measurement of offsets between layers of a semiconductor device wafer as used by the method described in FIG. 7 .

[0098] It should be understood that as an alternative to method 800, the method 900 described below may be performed as Figure 1In a preferred embodiment of the present invention, method 900 is performed if other metrics (such as acceptable Q merit value or high tool induced shift) indicate that the drifting metrology measurement may be problematic.

[0099] As seen in a first step 902, the method 900 determines whether a non-zero offset (NZO) calibration should be performed. If an NZO calibration should be performed, then (for example) the calibration described above with reference to Figure 3 In the embodiment described in FIG. 7 , method 900 continues to the next step 904 where NZO calibration is performed.

[0100] If NZO calibration should not be performed, the method 900 proceeds to the next step 908 where the method 900 determines whether the first offset indication and the second offset indication are the post-lithography offset indication 252 and the post-mask opening offset indication 254 .

[0101] If the first and second offset indications are the post-lithography offset indication 252 and the post-mask opening offset indication 254 , the method 900 proceeds to the next step 910 where at least one of the post-lithography offset measurement parameters and the post-mask opening offset measurement parameters is modified.

[0102] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-lithography offset indication 252 and the post-mask opening offset indication 254. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-lithography offset measurement and the post-mask opening offset measurement.

[0103] If the first and second offset indications are not the post-lithography offset indication 252 and the post-mask opening offset indication 254 , the method 900 proceeds to the next step 912 where the method 900 determines whether the first and second offset indications are the post-lithography offset indication 252 and the post-etch offset indication 256 .

[0104] If the first and second offset indications are the post-lithography offset indication 252 and the post-etch offset indication 256 , the method 900 proceeds to the next step 914 where at least one of the post-lithography offset measurement parameters and the post-etch offset measurement parameters is modified.

[0105] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-lithography offset indication 252 and the post-etch offset indication 256. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-lithography offset measurement and the post-etch offset measurement.

[0106] If the first and second offset indications are not the post-lithography offset indication 252 and the post-etch offset indication 256 , the method 900 proceeds to the next step 916 where the method 900 determines whether the first and second offset indications are the post-mask opening offset indication 254 and the post-etch offset indication 256 .

[0107] If the first and second offset indications are the post-mask opening offset indication 254 and the post-etch offset indication 256 , the method 900 proceeds to the next step 918 where at least one of the post-mask opening offset measurement parameters and the post-etch offset measurement parameters is modified.

[0108] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-mask opening offset indication 254 and the post-etch offset indication 256. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-mask opening offset measurement and the post-etch offset measurement.

[0109] If the first and second offset indications are not the post-mask open offset indication 254 and the post-etch offset indication 256 , the method 900 proceeds to the next step 920 where the method 900 determines whether the first and second offset indications are the post-lithography offset indication 252 and the post-polish offset indication 258 .

[0110] If the first and second offset indications are the post-lithography offset indication 252 and the post-polishing offset indication 258 , the method 900 proceeds to the next step 922 where at least one of the post-lithography offset measurement parameters and the post-polishing offset measurement parameters is modified.

[0111] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-lithography offset indication 252 and the post-polishing offset indication 258. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-lithography offset measurement and the post-polishing offset measurement.

[0112] If the first and second offset indications are not the post-lithography offset indication 252 and the post-polishing offset indication 258 , the method 900 proceeds to the next step 924 where the method 900 determines whether the first and second offset indications are the post-mask opening offset indication 254 and the post-polishing offset indication 258 .

[0113] If the first and second offset indications are the post-mask opening offset indication 254 and the post-polishing offset indication 258 , the method 900 proceeds to the next step 926 where at least one of the post-mask opening offset measurement parameters and the post-polishing offset measurement parameters is modified.

[0114] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-mask opening offset indication 254 and the post-polish offset indication 258. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-mask opening offset measurement and the post-polish offset measurement.

[0115] If the first and second offset indications are not the post-mask open offset indication 254 and the post-polish offset indication 258 , the method 900 proceeds to the next step 928 where the method 900 determines whether the first and second offset indications are the post-etch offset indication 256 and the post-polish offset indication 258 .

[0116] If the first and second offset indications are the post-etch offset indication 256 and the post-polish offset indication 258, the method 900 proceeds to the next step 930 where at least one of the post-etch offset measurement parameters and the post-polish offset measurement parameters is modified.

[0117] For example, the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture may be adjusted to reduce the difference between the post-etch offset indication 256 and the post-polish offset indication 258. As an additional example, outlier measurements may be identified and removed from the offset measured in at least one of the post-etch offset measurement and the post-polish offset measurement.

[0118] Those skilled in the art will appreciate that the present invention is not limited to what has been particularly shown and described above. The scope of the present invention includes both combinations and sub-combinations of the various features described above and modifications thereof, all of which are not in the prior art.

Claims

1. A method for measuring offset in the manufacture of a semiconductor device wafer, the method comprising: measuring an offset between layers of a semiconductor device wafer at a first instance after a first process stage and providing a first offset indication; measuring an offset between layers of a semiconductor device wafer at a second instance after a second process stage subsequent to the first process stage and providing a second offset indication; providing an offset measurement difference output in response to a difference between the first offset indication and the second offset indication; providing a baseline difference output, the baseline difference output being an average of differences between the indication of the shift at the first instance and the indication of the shift at the second instance on a previous wafer; and A difference between the offset measurement difference output and the baseline difference output is improved.

2. The method of claim 1, wherein the improving comprises at least one of: Change the offset measurement; and At least one process step in the fabrication of a semiconductor device wafer is altered.

3. The method of claim 1 , further comprising comparing the difference between the offset measurement difference output and the baseline difference output to a threshold and wherein the improving occurs when the difference between the offset measurement difference output and the baseline difference output exceeds the threshold. 4 . The method of claim 1 , wherein the baseline difference output represents a calculated summary of differences between the first excursion indication and the second excursion indication.

5. The method of claim 1, wherein the first example and the second example comprise selecting the semiconductor device wafers from a same single batch of semiconductor device wafers at different stages in a manufacturing process of the same single batch of semiconductor device wafers. 6 . The method of claim 5 , wherein the same semiconductor device wafer is measured in the first instance and the second instance.

7. The method of claim 5, wherein different semiconductor device wafers selected from the single batch of semiconductor devices intended to be the same are measured in the first instance and the second instance.

8. The method of claim 1, wherein the first instance and the second instance comprise different areas of a single target on the semiconductor device wafer.

9. The method of claim 1, wherein the offset measurement difference output comprises an indication of metrology quality.

10. The method of claim 5, wherein the offset measurement difference output includes an indication of a quality of at least one of the different phases.

11. The method of claim 5, further comprising using at least one of the first offset indication and the second offset indication in a third instance to improve offset measurement between layers of a semiconductor device.

12. The method of claim 11, wherein the third instance comprises a subsequent stage in the manufacturing process of the semiconductor device.

13. The method of claim 5, further comprising using the offset measurement difference output to improve parameters of the manufacturing process of the intended identical single batch of semiconductor devices from which the semiconductor device wafers are selected.

14. An apparatus for use in the measurement of offset in the manufacture of semiconductor device wafers and in the calibration of said measurement of offset, said apparatus comprising: at least a first structure disposed on a first layer of a semiconductor device wafer; and At least a second different structure and a third different structure are arranged on a second layer of the semiconductor device wafer along different axes, wherein the second different structure and the third different structure have different line widths and pitches.

15. The device of claim 14, wherein the second different structure and the third different structure are formed simultaneously using the same manufacturing tools and methods.

16. The device of claim 14, wherein at least one of the first structure, the second different structure, and the third different structure is defined by a plurality of sub-lines and sub-spaces between the sub-lines, the sub-lines having a pitch.

17. The device according to claim 16, wherein: The second different structure is defined by a plurality of second structure sub-lines having a second structure pitch and a plurality of second different structure sub-spaces; The third different structure is defined by a plurality of third structure sub-lines having a third structure pitch and a plurality of third different structure sub-spaces; and The second structural pitch and the third structural pitch are different from each other.

18. The device of claim 14, wherein the device has rotational symmetry.

19. The device of claim 14, wherein the first structure, the second different structure, and the third different structure are periodic structures.

20. The device of claim 19, wherein the second different structure and the third different structure overlie the first structure.

21. The device of claim 14, wherein the first structure, the second different structure, and the third different structure are rods or rectangular frames.

22. The device of claim 14, further comprising at least a fourth structure and wherein the first structure, the second different structure, the third different structure, and the fourth structure have rotational symmetry.

23. The device of claim 14, wherein the first layer and the second layer are adjacent.

24. The device of claim 14, wherein the first structure, the second different structure, and the third different structure have different mutually orthogonal orientations.

25. The device of claim 14, wherein the first structure, the second different structure, and the third different structure comprise a plurality of mutually parallel lines.

26. The device of claim 25, wherein the mutually parallel lines are each segmented into sub-lines.

27. The device of claim 26, wherein the sub-wires have a segment pitch in the range of 10 nm to 200 nm.

28. The device of claim 14, wherein line widths of the first structure, the second different structure, and the third different structure are 10% to 90% of pitches of the first structure, the second different structure, and the third different structure, respectively.

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