Three-dimensional memory device and method for forming the same

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source terminals of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of manufacturing the same. Background Art

[0002] Improvements in process technology, circuit design, programming algorithms, and manufacturing techniques have enabled planar memory cells to shrink to ever-smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processing and manufacturing techniques become challenging and costly. Consequently, the storage density of planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuits for facilitating the operation of the memory array. Summary of the Invention

[0004] One aspect of the present disclosure provides a 3D memory device comprising a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. The first semiconductor structure comprises an array of NAND memory strings, a semiconductor layer contacting source terminals of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure comprises a transistor.

[0005] Another aspect of the present disclosure provides a 3D memory device comprising a first semiconductor structure having a core region and a non-array region. The first semiconductor structure comprises an array of NAND memory strings in a subregion of the core region, a semiconductor layer in contact with the source terminals of the array of NAND memory strings, a non-conductive layer in the non-array region, and a plurality of contact structures in the non-conductive layer and in another subregion of the non-array region. The non-conductive layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device comprises a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure comprises a transistor.

[0006] Another aspect of the present disclosure provides a method for forming a 3D memory device. The method includes bonding a first semiconductor structure to a second semiconductor structure, the first semiconductor structure having a core region and a non-array region. The method also includes: depositing an undoped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure; converting a first portion of the undoped amorphous silicon layer into a doped polysilicon layer; retaining a second portion of the undoped amorphous silicon layer in the non-array region; and forming a first contact portion in the second portion of the undoped amorphous silicon layer. The first contact portion contacts a second contact portion in the first semiconductor structure.

[0007] Another aspect of the present disclosure provides a system including a memory device configured to store data. The memory device includes a first semiconductor structure having an array of NAND memory strings, a semiconductor layer in contact with source terminals of the array of NAND memory strings, a non-conductive layer in contact with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The memory device also includes a second semiconductor structure bonded to the first semiconductor structure and having a transistor. The system also includes a memory controller coupled to the memory device and configured to control the array of NAND memory strings through peripheral circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art to make and use the disclosure.

[0009] Figure 1A Schematic diagram showing a cross section of a 3D memory device according to some aspects of the present disclosure.

[0010] Figure 1B An overview of a 3D memory device according to some aspects of the present disclosure is shown.

[0011] Figure 1C Shown Figure 1A and Figure 1B Side view of an example of a 3D memory device.

[0012] Figure 2 According to some aspects of the present disclosure Figure 1A and Figure 1B Side view of an example of a 3D memory device.

[0013] Figures 3A-3Q Some aspects of the present disclosure are shown for forming Figure 2 The manufacturing process of 3D memory devices in

[0014] Figure 4 Some aspects of the present disclosure are shown for forming Figure 2 Flowchart of a method for a 3D memory device in FIG.

[0015] Figure 5 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0016] Figure 6A A diagram showing an exemplary memory card having a memory device according to some aspects of the present disclosure is shown.

[0017] Figure 6B A diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0018] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements have been discussed, it should be understood that such discussion is for illustrative purposes only. As such, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be employed in a variety of other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with one another in ways not specifically depicted in the accompanying drawings, so that such combinations, adjustments, and modifications are within the scope of this disclosure.

[0020] In general, terms should be understood, at least in part, by their use in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, and, instead, may allow for the presence of other factors that may not be explicitly stated, again depending, at least in part, on the context.

[0021] It should be readily understood that the terms “on,” “above,” and “over…” in this disclosure should be interpreted in the broadest manner, and that “on…” encompasses not only the meaning of being directly on something, but also the meaning of being on something with intervening features or layers therebetween, and that “above…” or “over…” encompasses not only the meaning of being above or over something, but also the meaning of being above or over something with no intervening features or layers therebetween (i.e., directly on something).

[0022] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein for ease of description to describe an element or feature in its relationship to another element or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0023] As used herein, the term "layer" may refer to a portion of a material comprising an area having a thickness. A layer may extend over an entire underlying structure or an overlying structure, or may have a range smaller than the range of the underlying structure or the overlying structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any paired horizontal planes between the top surface and the bottom surface of the continuous structure, or may be located at the top surface and the bottom surface. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers located thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (in which interconnect lines and / or vertical interconnect channel (via) contacts are formed) and one or more dielectric layers.

[0024] In a 3D memory device, the peripheral circuits and the memory cell array are arranged in different planes (levels, layers) in the vertical direction, that is, stacked on top of each other, to reduce the planar chip size of the peripheral circuits and the total chip size of the memory device. In a 3D memory device, the memory cells are formed by the intersection of NAND memory strings and word lines. The NAND memory strings are formed to extend vertically in the memory stack (e.g., a conductive / dielectric layer pair), and the source terminal of the NAND memory string contacts a semiconductor layer that acts as part of the source contact for applying a source voltage to the NAND memory string. In a 3D NAND flash memory device, the memory stack and the peripheral circuits are often integrated together by bonding.

[0025] To form electrical connections within a 3D memory device (e.g., between a memory cell array and peripheral circuitry) and / or outside a 3D memory device (e.g., between a 3D NAND flash memory device and external circuitry), through-silicon contacts (TSCs) are often formed. To insulate the TSCs from the semiconductor layer, the portion of the semiconductor layer that contacts the NAND memory strings is often disconnected from the portion of the semiconductor layer through which the TSCs extend. An insulating portion is formed between these two portions of the semiconductor layer to achieve insulation. Simultaneously, corresponding insulating spacers are formed in the semiconductor layer, thereby insulating each TSC from the semiconductor layer through the corresponding insulating spacers. The insulating spacers and insulating portions are often formed by patterning the semiconductor layer to form openings and filling the openings with a dielectric material. Due to the small critical dimensions of these openings, the deposition of the dielectric material often involves atomic layer deposition (ALD). This manufacturing process is costly due to the high costs of photolithography, etching, and deposition. At the same time, the small critical dimensions of the openings may make the etching process for forming the openings undesirably complex, and precise alignment between the openings and the TSC is also challenging.

[0026] To address one or more of the aforementioned problems, the present disclosure provides a structure and manufacturing method for a 3D memory device, wherein the critical dimension of the opening for forming a non-conductive layer to insulate the TSC from the semiconductor layer is increased, and the etching process for forming the opening is omitted. This can reduce the cost and difficulty of insulating different portions of the semiconductor layer. The 3D memory device having a core region and a non-array region includes multiple NAND memory strings in the core region and one or more TSCs in the non-array region. The semiconductor layer contacts the source terminals of the NAND memory strings in the core region. According to the present disclosure, instead of forming corresponding insulating spacers to insulate each TSC from the semiconductor layer, a single non-conductive layer can be formed to insulate multiple TSCs from the semiconductor layer. The lateral width of the non-conductive layer is large enough to insulate any (e.g., all) TSCs from the semiconductor layer. The non-conductive layer can be formed at any suitable location where insulation is required and away from the source terminal of the NAND memory string. For example, the non-conductive layer can be formed in the non-array region. The non-conductive layer is in lateral contact with the semiconductor layer and has the same thickness as the semiconductor layer. In some embodiments, the non-conductive layer includes a non-conductive material, such as undoped amorphous silicon.

[0027] Unlike existing patterning techniques that include photolithography and etching processes, the formation of the non-conductive layer disclosed herein includes depositing a layer of non-conductive material and retaining the non-conductive material in the non-array area. For example, an undoped amorphous silicon layer is first deposited in the non-array area and the core area. The portion of the undoped amorphous silicon layer in the core area (in contact with the source terminal of the NAND memory string) undergoes a doping process, thereby being converted into a doped amorphous silicon portion. In some embodiments, an ion implantation process is used to convert the portion of the undoped amorphous silicon layer into a doped amorphous silicon portion. A localized heat treatment (such as a laser annealing process) is then used to convert the doped amorphous silicon portion into a doped polysilicon layer, for example, a semiconductor layer. The remaining portion of the undoped amorphous silicon layer (undoped and untreated) then acts as a non-conductive layer for insulating the TSC from the semiconductor layer and the NAND memory string. The untreated portion of the undoped amorphous silicon layer can act as a non-conductive layer that covers any TSC to be insulated and does not overlap with the source terminal of the NAND memory string. The non-conductive layer may be further patterned to enable the TSC to extend through the non-conductive layer.

[0028] In the manufacturing process disclosed herein, the formation of the non-conductive layer utilizes the material used to form the semiconductor layer. In some embodiments, an undoped amorphous silicon layer (non-conductive) is deposited in both the core area and the non-array area. Undoped amorphous silicon can provide the desired insulation between the TSC and the semiconductor layer. No additional insulating material needs to be deposited to form the non-conductive layer. Accordingly, after the non-conductive layer is formed, no additional etching process is required to remove any excess insulating material. The critical dimension of the semiconductor layer is a desirable large size, so that the laser beam can be precisely controlled for the annealing process. Compared with existing patterning techniques, the difficulty and cost of patterning can be reduced. The increased area of ​​the non-conductive layer can also reduce the parasitic capacity of the 3D memory device.

[0029] Figure 1A A schematic diagram illustrating a cross-section of a 3D memory device 100 according to some aspects of the present disclosure is shown. Figure 1B An overview of a 3D memory device 100 according to some aspects of the present disclosure is shown. The 3D memory device 100 represents an example of a bonded die. In some embodiments, at least some of the components of the 3D memory device 100 (e.g., the memory cell array and peripheral circuits) are formed separately and in parallel on different substrates and then joined together to form the bonded die (a process referred to herein as a "parallel process").

[0030] It should be noted that the x-axis, y-axis, and z-axis are added to the figures of the present disclosure to further illustrate the spatial relationship of the components of the semiconductor device. The substrate of the semiconductor device (e.g., 3D memory device 100) includes two lateral surfaces (e.g., top and bottom surfaces) extending laterally along the x-direction and the y-direction (i.e., the lateral direction or width direction). The x-direction is the word line direction of the 3D memory device 100, the y-direction is the bit line direction of the 3D memory device 100, and the z-direction is perpendicular to the xy plane. In some embodiments, the z-direction is the NAND direction along which the NAND memory string extends vertically. As used herein, when the substrate of a semiconductor device is in the lowest plane of the semiconductor device along the z-direction (vertical direction or thickness direction), whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) is determined relative to the substrate along the z-direction. This same concept for describing spatial relationships will be used throughout the present disclosure.

[0031] The 3D memory device 100 may include a first semiconductor structure 102 including an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array may be used as an example to describe the memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few examples.

[0032] The first semiconductor structure 102 can be a NAND flash memory device, wherein the memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers, which are in turn organized into blocks, in which each NAND memory cell is coupled to a separate line called a bit line (BL). All cells with the same vertical position in the NAND memory cell can be coupled by a word line (WL) via a control gate. In some embodiments, a memory chip storage area contains a certain number of blocks coupled by the same bit line. The first semiconductor structure 102 can include one or more memory chip storage areas, and the peripheral circuitry required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104.

[0033] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some embodiments, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series (similar to a NAND gate) and two selection transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., referred to herein as a flat two-dimensional (2D) surface, as distinct from the term "memory slice storage area" in this disclosure). In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically (in 3D) above the semiconductor layer through a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), the 3D NAND memory string typically includes a certain number of NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor.

[0034] like Figure 1AAs shown in , the 3D memory device 100 may further include a second semiconductor structure 104 having peripheral circuitry for the memory cell array in the first semiconductor structure 102. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuitry may include one or more of a page buffer, a decoder (e.g., a row decoder or a column decoder), a sense amplifier, a driver (e.g., a word line driver), an I / O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the functional circuitry mentioned above, or any active or passive component (e.g., a transistor, a diode, a resistor, or a capacitor) of the circuitry. The peripheral circuitry in the second semiconductor structure 104 may use complementary metal-oxide-semiconductor (CMOS) technology, which may be implemented, for example, in a logic process at any suitable technology node.

[0035] like Figure 1A As shown in , according to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are stacked on top of each other in different planes. Therefore, the memory cell array in the first semiconductor structure 102 and the peripheral circuits in the second semiconductor structure 104 can be stacked on top of each other in different planes, thereby reducing the planar size of the 3D memory device 100 compared to a memory device in which all peripheral circuits are arranged in the same plane. Figure 1A As shown in FIG, in some embodiments, the first semiconductor structure 102 is above the second semiconductor structure 104 and includes a pad extraction interconnect layer for pad extraction purposes. TSVs extending in the first semiconductor structure 102 can be formed to provide electrical connections between components in the memory device 100 (e.g., peripheral circuits and / or memory cell arrays) and any external circuitry.

[0036] like Figure 1A As shown in , the 3D memory device 100 further includes a bonding interface 106 vertically located between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 106 can be an interface between two semiconductor structures formed by any suitable bonding technology as described in detail below, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few examples. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuit in the second semiconductor structure 104 can be performed through an interconnect (e.g., a bonding contact) across the bonding interface 106. Figure 1AAs shown in , in some embodiments, along the z direction, the memory cell array is above the bonding interface 106 and the peripheral circuit is below the bonding interface 106 .

[0037] As described in detail below, some of the first semiconductor structure 102 and the second semiconductor structure 104 can be separately manufactured using parallel processes (and in some embodiments are manufactured in parallel), so that the thermal budget of manufacturing one of the first semiconductor structure 102 and the second semiconductor structure 104 does not impose a constraint on the process of manufacturing the other of the first semiconductor structure 102 and the second semiconductor structure 104. In addition, a large number of interconnects (e.g., bonding contacts and / or inter-layer vias (ILVs) / through substrate vias (TSVs)) can be formed across the bonding interface 106, thereby establishing direct, short-distance (e.g., micrometer-scale or sub-micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0038] Figure 1B 1 shows an overview of a memory device 100 according to some aspects of the present disclosure. Specifically, Figure 1B The core region 108 and the non-array region 110 in the first semiconductor structure 102 are shown in the xy plane. In some embodiments, the memory cell array is formed in the core region 108, and the TSC is formed in the non-array region 110. In some embodiments, the non-array region 110 is located at the periphery of the core region 108 or surrounds the core region 108. The non-array region 110 can represent any area where the TSC is formed. For example, the non-array region 110 can be an area away from the memory cell array, such as a step region. In various embodiments, other areas can be included in the non-array region 110, but are not part of the step region. In some embodiments, in the xy plane, the non-array region 110 and the core region 108 do not overlap each other.

[0039] Figure 1CA side view of a portion of a 3D memory device 103, an example of a memory device 100, is shown. The 3D memory device includes a first semiconductor structure 105 and a second semiconductor structure 107 bonded to each other at a bonding interface 109. The first semiconductor structure 105 is an example of the first semiconductor structure 102, and the second semiconductor structure 107 is an example of the second semiconductor structure 104. The first semiconductor structure 105 includes a plurality of NAND memory strings 117, a plurality of TSCs 115, a semiconductor layer 111, and a plurality of pad lead interconnects 119. The source terminals of the NAND memory strings 117 located in the core region 108 are in contact with a first portion 111-1 of the semiconductor layer. A second portion 111-2 of the semiconductor layer is insulated from / disconnected from the first portion 111-1 of the semiconductor layer by an insulating portion 113 comprising a dielectric material, such as silicon oxide. The TSCs 115 are located in the non-array region 110 and extend through the second portion 111-2 of the semiconductor layer. The pad extraction interconnect 119 can be conductively connected to components in the 3D memory device 103 for pad extraction purposes. Each TSC 115 is located in (e.g., passes through) a corresponding insulating spacer 121 in the second portion 111-2 of the semiconductor layer. The insulating spacer 121 includes the same material as the insulating portion 113, such as silicon oxide.

[0040] The insulating portion 113 and the insulating spacer 121 are formed by patterning the semiconductor layer 111 to form corresponding openings and filling the openings with a dielectric material. This patterning process often includes a photolithography process followed by an etching process. The openings used to form the insulating spacer 121 are precisely aligned with the TSC 115. Due to the small critical dimensions of the insulating portion 113 and the insulating spacer 121, the dielectric material is often deposited using ALD. As a result, the manufacturing process for forming the 3D memory device 103 can be challenging and costly.

[0041] Figure 2 A side view of a portion of an exemplary 3D memory device 200 according to some aspects of the present disclosure is shown in the xz plane. According to some embodiments, the 3D memory device 200 may be an example of the memory device 100 and is a chip including a first semiconductor structure 203 and a second semiconductor structure 207 that are stacked in different planes along a vertical direction (e.g., the z direction). According to some embodiments, the first semiconductor structure 203 and the second semiconductor structure 207 are bonded at a bonding interface 209 located therebetween. It should be noted that Figure 2 and Figures 3A-3Q The components shown in are intended to illustrate relative positions and not to indicate actual electrical connections within the 3D memory device 200 .

[0042] like Figure 2 As shown in , the first semiconductor structure 203 and the second semiconductor structure 207 can be bonded to each other in a face-to-face manner at a bonding interface 209. The second semiconductor structure 207 may include a substrate 202 and a device layer 204 located above and in contact with the substrate 202. The substrate 202 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable semiconductor material. In some embodiments, element 202 represents a semiconductor layer, which can be formed by thinning the substrate. In some embodiments, the substrate 202 includes single crystal silicon. In some embodiments, the device layer 204 includes peripheral circuits (details not shown in the figure). The peripheral circuits may include high voltage (HV) circuits such as driver circuits and low voltage (LV) circuits such as page buffer circuits and logic circuits. In some embodiments, the peripheral circuitry includes a plurality of transistors in contact with the substrate 202 (or semiconductor layer 202 where applicable). These transistors may include any transistor disclosed herein, such as planar transistors and 3D transistors.

[0043] In some embodiments, the second semiconductor structure 207 further includes an interconnect layer 205 above the device layer 204 to transmit electrical signals to and from peripheral circuits in the device layer 204. Figure 2As shown in , the interconnect layer 205 can be vertically located between the bonding interface 209 and the device layer 204 (including the transistors of the peripheral circuit). The interconnect layer 205 can include multiple interconnects, including lateral lines and vias. As used herein, the term "interconnect" can broadly include any appropriate type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect can be coupled to the transistors of the peripheral circuit in the device layer 204. The interconnect layer 205 can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers"), and the lateral lines and vias can be formed in the ILD layers. That is, the interconnect layer 205 can include lateral lines and vias in multiple ILD layers. In some embodiments, the devices in the device layer 204 are coupled to each other through the interconnects in the interconnect layer 205. The interconnects in the interconnect layer 205 may be comprised of a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer 205 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 205 include W. Among conductive metal materials, W has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids).

[0044] like Figure 2As shown in , the second semiconductor structure 207 may further include a bonding layer 206 located above and in contact with the interconnect layer 205 at a bonding interface 209. The bonding layer 206 may include a plurality of bonding contacts 233 and a dielectric isolating the bonding contacts 233. The bonding contacts 233 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination of W, Co, Cu, Al, and silicide. In some embodiments, the bonding contacts 233 of the bonding layer 206 include Cu. The remaining area of ​​the bonding layer 206 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. The bonding contact 233 in the bonding layer 206 and the surrounding dielectric can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously obtain metal-metal (e.g., Cu to Cu) bonding and dielectric-dielectric (e.g., SiO2 to SiO2) bonding.

[0045] like Figure 2 As shown in , the first semiconductor structure 102 may further include a bonding layer 208 at a bonding interface 209, for example, on the opposite side of the bonding interface 209 relative to the bonding layer 206 in the second semiconductor structure 207. The bonding layer 208 may include a plurality of bonding contacts 231 and a dielectric electrically isolating the bonding contacts 231. The bonding contacts 231 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 208 may be formed using a dielectric material, such as silicon oxide. The bonding contacts 231 and the surrounding dielectric in the bonding layer 208 may be used for hybrid bonding. In some embodiments, the bonding interface 209 is where the bonding layers 208 and 206 meet and bond. In practice, the bonding interface 209 may be a layer having a certain thickness including the top surface of the bonding layer 206 and the bottom surface of the bonding layer 208. For example, the bonding interface may be distinguished based on the relative positions (eg, displacement) of the bonding contact portions 231 and 233 .

[0046] like Figure 2As shown in , the first semiconductor structure 203 may further include an interconnect layer 210 located above and in contact with the bonding layer 208 to transmit electrical signals. The interconnect layer 210 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 210 also include local interconnects, such as bitline contacts and wordline contacts. The interconnect layer 210 may further include one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer 210 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination of W, Co, Cu, Al, and silicide. The ILD layer in the interconnect layer 210 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectrics.

[0047] like Figure 2 As shown in FIG, first semiconductor structure 203 may include an array of memory cells, such as an array of NAND memory strings 217, located above and in contact with interconnect layer 210. In some embodiments, interconnect layer 210 is vertically positioned between NAND memory strings 217 and bonding interface 209. According to some embodiments, each NAND memory string 217 vertically extends through multiple pairs of gate conductive layers 239 and dielectric layers 240. The stacked and interleaved gate conductive layers 239 and dielectric layers 240 are also referred to herein as a stack structure, such as memory stack 212. According to some embodiments, the interleaved gate conductive layers 239 and dielectric layers 240 in memory stack 212 alternate in a vertical direction. Each gate conductive layer 239 may include a gate electrode (gate line) and a gate dielectric layer surrounded by an adhesive layer. The adhesive layer may include a conductive material, such as titanium nitride (TiN), which can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the gate conductive layer 239 may extend laterally as a word line, with the gate electrode terminating at one or more stepped structures of the memory stack 212. The stepped structures located in the stepped region that is part of the non-array region 110 may contact a plurality of word line contacts 237 for applying a voltage to the gate conductive layer 239.

[0048] The number of pairs of gate conductive layers 239 and dielectric layers 240 in the memory stack 212 can be one of the factors that determine the number of memory cells in the memory cell array. The gate conductive layers 239 can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, each gate conductive layer 239 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 239 includes a doped polysilicon layer. Each gate conductive layer 239 can include a control gate surrounding the memory cell.

[0049] like Figure 2 As shown, each NAND memory string 217 includes a channel structure extending vertically through the memory stack 212. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure can have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially in this order from the center of the column toward the outer surface of the column. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination of silicon oxide and silicon oxynitride. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination of silicon nitride, silicon oxynitride, and silicon. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination of silicon oxide, silicon oxynitride, and a high dielectric constant (high-k) dielectric. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure may further include a channel plug at the drain end of the NAND memory string 217. The channel plug may include polysilicon and may be in contact with the semiconductor channel. In some embodiments, each NAND memory string 217 is a "charge capture" type NAND memory string. It should be understood that the NAND memory string 217 is not limited to a "charge capture" type NAND memory string and may be a "floating gate" type NAND memory string in other examples.

[0050] According to some embodiments, the NAND memory string 217 does not have any semiconductor plugs at its source terminal. Instead, the 3D memory device 200 includes a semiconductor layer 211 above and in contact with the memory stack 212. The semiconductor layer 211 can contact the sidewalls of the semiconductor channel of the channel structure at the source terminal of each NAND memory string 217. The semiconductor layer 211 can include a semiconductor material, such as doped polysilicon. In some embodiments, the semiconductor layer 211 is doped with N-type dopants, such as phosphorus and / or arsenic. The thickness of the semiconductor layer 211 can be in a range of 100 nm to 600 nm. In some embodiments, the semiconductor layer 211 and the source contact (e.g., an array common source or ACS, not shown) in the gap structure can together serve as part of a source line (not shown) coupled to the source terminal of the NAND memory string 217, for applying an erase voltage to the source terminal of the NAND memory string 217, for example, during an erase operation.

[0051] The non-conductive layer 213 can be laterally aligned with the semiconductor layer (e.g., at the same height along the z-direction) and can have the same thickness as the semiconductor layer 211. In some embodiments, the non-conductive layer 213 is in contact with the semiconductor layer 211. The semiconductor layer 211 partially or completely located in the core region 108 can be above and in contact with the source terminals of the NAND memory strings 217. The area of ​​the semiconductor layer 211 can be sufficiently large, e.g., greater than or equal to the total area where all NAND memory strings 217 are formed (e.g., a sub-region of the core region 108), so as to be in contact with the source terminals of all NAND memory strings 217. The area of ​​the non-conductive layer 213 can be sufficiently large, e.g., greater than or equal to the total area of ​​some or all of the contact structures 215 (e.g., a sub-region of the non-array region 110). In some embodiments, the non-conductive layer 213 extends laterally from the boundary of the semiconductor layer 211 to the outer periphery of the non-array region 110. In some embodiments, the top surface of the non-conductive layer 213 is coplanar with the top surface of the semiconductor layer 211, and the bottom surface of the non-conductive layer 213 is coplanar with the bottom surface of the semiconductor layer 211. The non-conductive layer 213 can include a non-conductive material, such as undoped amorphous silicon. In some embodiments, the non-conductive layer 213 is a single insulating layer including a uniform dielectric / material in the xy plane. That is, the non-conductive layer 213 can be disconnected between any two contact structures 215.

[0052] like Figure 2As shown in FIG, the first semiconductor structure 203 may further include one or more contact structures 215 extending vertically through the non-conductive layer 213. In some embodiments, the contact structures 215 couple the interconnects in the interconnect layer 210 to the pad lead-out interconnects 219 in the pad lead-out interconnect layer 216 to facilitate electrical connection through the first semiconductor structure 203. The contact structures 215 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination of W, Co, Cu, Al, and silicide. In some embodiments, the contact structures 215 include W. In some embodiments, each of the contact structures 215 may be a TSV having a depth (e.g., a length along the z-direction) on the order of micrometers or tens of micrometers (e.g., between 1 μm and 100 μm).

[0053] like Figure 2 As shown in FIG, the contact structure 215 can be located in the non-array region 110 of the first semiconductor structure 203, or can be located away from the NAND memory string 217. In some embodiments, the non-conductive layer 213 can be partially or completely located in the non-array region 110, thereby providing insulation between at least one contact structure 215 and the semiconductor layer 211. In some embodiments, the non-conductive layer 213 is located in a stepped region of the 3D memory device 200. In some other embodiments, the non-conductive layer 213 is located outside the stepped region but in the non-array region 110. In some embodiments, the width of the non-conductive layer 213 in the x-direction and / or the y-direction is large enough to surround multiple (e.g., all) contact structures 215 in the non-array region 110, thereby insulating all contact structures 215 in / surrounded by the non-conductive layer 213 from the semiconductor layer 211. In various embodiments, the non-conductive layer 213 can be spaced away from the source end of the NAND memory string 217 in the xy plane, and it is desirable that the width and / or area of ​​the non-conductive layer 213 be large so as to insulate the maximum number of contact structures 215. For example, the area of ​​the non-conductive layer 213 can be greater than or equal to the total area where the contact structures 215 are located. The orthogonal projection of the non-conductive layer 213 in the xy plane can cover multiple (e.g., all) contact structures 215. In some embodiments, the non-conductive layer 213 is located in the non-array region 110. In various embodiments, the orthogonal projection of the non-conductive layer 213 at least partially overlaps the stepped region. In some embodiments, the orthogonal projection of the non-conductive layer 213 does not overlap the core region 108. In some embodiments, the orthogonal projection of the insulating layer 213 partially overlaps the core region 108. In some embodiments, the ratio of the depth to the width of the non-conductive layer 213 is less than or equal to 1 / 3. For example, the ratio is less than or equal to 1 / 5.

[0054] like Figure 2As shown in FIG, the first semiconductor structure 203 may further include a pad extraction interconnect layer 216 located above and in contact with the semiconductor layer 211. In some embodiments, the semiconductor layer 211 is vertically (e.g., along the z-direction) located between the pad extraction interconnect layer 216 and the NAND memory string 217. The pad extraction interconnect layer 216 may include a first insulating layer 214 located above and in contact with the semiconductor layer 211 and the non-conductive layer 213, a plurality of contacts 241 located above and in contact with the semiconductor layer 211, a first contact layer 221 located above and in contact with the contact structure 215, a second contact layer 223 located above and in contact with the contacts 241, a second insulating layer 227 located above and in contact with the first and second contact layers 221 and 223, and a plurality of pad extraction interconnects 219 (e.g., contact pads) located in the second insulating layer 227. In some embodiments, pad-out interconnects 219 conductively connected to contact structures 215 are used to drive transistors in peripheral circuits in device layer 204. In some embodiments, pad-out interconnects 219 conductively connected to NAND memory strings 217 are used to provide voltages for operations of memory cells, such as erasing, writing, and reading.

[0055] The first insulating layer 214 can provide insulation between the contact structure 215 and the contact portion 241. The first contact layer 221, in contact with the contact structure 215 and the corresponding pad lead-out interconnect 219, can provide an electrical connection between the contact structure 215 and the corresponding pad lead-out interconnect 219. The second contact layer 223, in contact with the contact portion 241 and the corresponding pad lead-out interconnect 219, can provide an electrical connection between the source terminal of the NAND memory string 217 and the corresponding pad lead-out interconnect 219. The first contact layer 221 and the second contact layer 223 can be insulated from each other, for example, by one or more insulating portions 225. In some embodiments, the pad lead-out interconnect 219 can transmit electrical signals between the 3D memory device 200 and external devices, for example, to achieve pad lead-out purposes. In some embodiments, the first insulating layer 214, the insulating portion 225, and the second insulating layer 227 may each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any combination of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. Each of the first insulating layer 214 and the second insulating layer 227 may be a single-layer structure or a multi-layer structure. For example, the second insulating layer 227 may include a silicon nitride layer on a silicon oxide layer. The silicon oxide layer may contact the first contact layer 221 and the second contact layer 223, and the silicon nitride layer may cover the silicon oxide layer. The silicon oxide layer may provide balanced stress for the first and second contact layers and the silicon nitride layer. The silicon nitride layer may provide desired isolation against contamination (such as moisture, air, and / or chemicals). The contact structure 215, the contact portion 241, the first and second contact layers 221 and 223, and the pad lead interconnection 219 may each include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, the contact structure 215, the contact portion 241, and the pad lead interconnection 219 may each include tungsten.

[0056] Figures 3A-3Q A fabrication process for forming a 3D memory device 200 according to some aspects of the present disclosure is shown. Figure 4 A flow chart of a method 400 for forming a 3D memory device 200 according to some aspects of the present disclosure is shown. It should be understood that the operations shown in the method 400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 4 Executed in the order shown.

[0057] refer to Figure 4The method 400 begins at operation 402 by forming an undoped amorphous silicon layer over a semiconductor structure having a core region and a non-array region. Figure 3A The corresponding structure is shown.

[0058] like Figure 3A As shown in FIG, an undoped amorphous silicon layer 320 is formed on a semiconductor structure 350 having a core region 108 and a non-array region 110. The semiconductor structure 350 may be an example of a 3D memory device 200. Figure 3A As shown in , the semiconductor structure 350 may include a portion of a first semiconductor structure bonded to a second semiconductor structure at a bonding interface 309. The second semiconductor structure may include a substrate 302, a device layer 304, an interconnect layer 305, and a bonding layer 306. The portion of the first semiconductor structure may include a bonding layer 308, an interconnect layer 310, and an array stack 312. The array stack 312 may include a plurality of staggered gate conductive layers 339 and a plurality of dielectric layers 340. The array stack 312 may also include an array of NAND memory strings 317 extending in the staggered gate conductive layers 339 and dielectric layers 340. The first semiconductor structure may also include one or more contact portions 315-1 extending vertically and coupled to the interconnect layer 310. The first contact portion 315-1 may subsequently form a lower portion of a TSV (e.g., contact structure 215). The NAND memory string 317 may be located in the core region 108, and the first contact portion 315-1 may be located in the non-array region 110. A detailed description of each component can be referred to in detail. Figure 2 The description of the 3D memory device 200 is given in detail in detail and is not repeated here.

[0059] To form the first semiconductor structure, a stack structure, such as a memory stack including alternating gate conductive layers and dielectric layers, is formed on a first substrate to form an array stack 312. In some embodiments, the first substrate includes a suitable base material, such as silicon. To form the memory stack, in some embodiments, a dielectric stack (not shown) including alternating sacrificial layers (not shown) and dielectric layers is formed on the first substrate. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The alternating sacrificial layers and dielectric layers can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The dielectric stack can be repeatedly patterned to form a plurality of steps in the non-array area 110. The memory stack can then be formed by a gate replacement process, for example, by replacing the sacrificial layer with a conductive layer using a wet / dry etch that is selective to the dielectric layer and filling the resulting recess with a conductive layer. In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack can also be formed by alternating deposition of conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without the need for a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide (e.g., thermally grown local oxidation of silicon (LOCOS)) is formed between the memory stack and the first substrate. A plurality of contact vias extending vertically and falling on the steps can be formed to form an electrical connection between the gate conductive layer 339 and the interconnect layer 310 to be formed.

[0060] NAND memory strings 317 may be formed above the first substrate. Each NAND memory string 317 extends vertically through the dielectric stack (or memory stack, depending on the manufacturing process) to contact the first substrate. In some embodiments, the manufacturing process for forming the NAND memory strings 317 includes forming a channel hole through the dielectric stack (or memory stack) and into the first substrate using dry etching and / or wet etching (such as deep reactive-ion etching (DRIE)), followed by filling the channel hole with multiple layers using a thin film deposition process such as ALD, CVD, PVD, or any combination of ALD, CVD, and PVD, such as a memory film (e.g., a tunneling layer, a storage layer, and a barrier layer) and a semiconductor layer.

[0061] In some embodiments, an interconnect layer 310 is formed above the array of NAND memory strings 317 on a first substrate. The interconnect layer 310 may include a first plurality of interconnects in one or more ILD layers. The interconnect layer 310 may include interconnects of the MEOL and / or BEOL in the multiple ILD layers, thereby forming electrical connections with the NAND memory strings 317. In some embodiments, the interconnect layer 310 includes multiple ILD layers formed in multiple processes and interconnects in the multiple ILD layers. For example, the interconnects in the interconnect layer 310 may include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination of CVD, PVD, ALD, electroplating, and electroless plating. The manufacturing process for forming the interconnects may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layer may include dielectric materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination of CVD, PVD, and ALD. The illustrated ILD layer and interconnects may be collectively referred to as an interconnect layer 310. In some embodiments, the interconnects in the interconnect layer 310 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0062] In some embodiments, a bonding layer 308 is formed above the interconnect layer 310. The bonding layer 308 may include a plurality of first bonding contacts 331 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 310 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination of CVD, PVD, and ALD. Then, the first bonding contacts 331 that pass through the dielectric layer and contact the interconnects in the interconnect layer 310 can be formed by first patterning contact holes through the dielectric layer using a patterning process (photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0063] To form the second semiconductor structure, a device layer 304 is formed on a substrate 302 (e.g., a second substrate). The device layer 304 may include a plurality of transistors on the substrate 302. The substrate 302 may be a silicon substrate comprising single crystal silicon. The transistors may be formed by a variety of processes, including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions serving as, for example, wells and source / drain regions of the transistors are formed in the substrate 302 by ion implantation and / or thermal diffusion. In some embodiments, isolation regions (e.g., shallow trench isolation (STI)) are also formed in the substrate 302 by wet / dry etching and thin film deposition. These transistors may function as part or all of the peripheral circuitry for controlling the NAND memory string 317. It should be understood that the details used to fabricate the transistors may vary depending on the type of transistor, and thus, exhaustive details are not provided for ease of description.

[0064] In some embodiments, an interconnect layer 305 is formed above the transistors on the substrate 302. The interconnect layer 305 may include a plurality of interconnects in one or more ILD layers. Figures 3A-3QAs shown in FIG, an interconnect layer 305 can be formed above the transistors in device layer 304. Interconnect layer 305 can include interconnects of MEOL and / or BEOL in multiple ILD layers, thereby achieving electrical connection with these transistors. In some embodiments, interconnect layer 305 includes multiple ILD layers formed in multiple processes and interconnects in these multiple ILD layers. In some embodiments, first contact portion 315-1 can be formed in non-array area 110, extending in array stack 312 and coupled to the interconnects in interconnect layer 305. The formation of first contact portion 315-1 can include photolithography, etching, and deposition. For example, first contact portion 315-1 and the interconnects in interconnect layer 305 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination of CVD, PVD, ALD, electroplating, and electroless plating. The manufacturing process for forming the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination of CVD, PVD, and ALD. The ILD layer and the interconnects may be collectively referred to as interconnect layer 305. In some embodiments, the interconnects in interconnect layer 305 include W, which has a relatively high thermal budget among conductive metal materials to withstand subsequent high temperature processes.

[0065] In some embodiments, a bonding layer 306 is formed above the interconnect layer 305. The bonding layer 306 may include a plurality of second bonding contacts 333 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 305 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination of CVD, PVD, and ALD. Then, the second bonding contacts 333 that pass through the dielectric layer and contact the interconnects in the interconnect layer 305 can be formed by first patterning a contact hole through the dielectric layer using a patterning process (photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0066] like Figure 3AAs shown in , the first semiconductor structure (e.g., the array stack 312 and the NAND memory string 317 formed through the array stack 312) is turned upside down. The downward bonding layer 308 is bonded to the upward bonding layer 306, that is, in a face-to-face manner, thereby forming a bonding interface 309. That is, the first bonding contact portion and the second bonding contact portion in the bonding layer 308 and the bonding layer 306 are bonded at the bonding interface 309. In some embodiments, a treatment process is applied to the bonding surface before bonding, for example, a plasma treatment, a wet treatment and / or a local heat treatment. As a result of bonding (e.g., hybrid bonding), the first bonding contact portion 331 and the second bonding contact portion 333 on opposite sides of the bonding interface 309 can be fused to each other. According to some embodiments, after bonding, the first bonding contact 331 in the bonding layer 308 is aligned with and contacts the second bonding contact 333 in the bonding layer 306, so that the array stack 312 and the NAND memory string 317 formed through the array stack 312 can be coupled to the transistor through the bonded bonding contact across the bonding interface 309. Then, the first substrate can be partially or completely removed to expose the source terminal of the NAND memory string 317. In some embodiments, the removal of the first substrate includes an appropriate etching process (e.g., dry etching and / or wet etching) and / or a planarization process (e.g., chemical mechanical polishing or CMP). The bonded chip with the first substrate partially or completely removed can be referred to as a semiconductor structure 350.

[0067] An undoped amorphous silicon layer 320 may be deposited over the semiconductor structure 350 on the side / surface exposing the source terminals of the NAND memory strings 317. The undoped amorphous silicon layer 320 may contact at least the source terminals of multiple (e.g., all) NAND memory strings 317 in the core region 108. In some embodiments, the undoped amorphous silicon layer 320 covers and contacts at least one (e.g., all) first contact portions 315-1 in the non-array region 110. For example, the undoped amorphous silicon layer 320 may cover both the core region 108 and the non-array region 110. In some embodiments, the undoped amorphous silicon layer 320 is deposited using a low-temperature deposition process, such as low-temperature chemical vapor deposition (CVD). For example, the deposition temperature may be in the range of 400 degrees Celsius to 450 degrees Celsius. In some embodiments, the thickness of the undoped amorphous silicon layer 320 is in the range of 100 nm to 600 nm. In various embodiments, the thickness of the undoped amorphous silicon layer 320 is controlled to a desired range so that a subsequent localized thermal treatment (eg, a laser annealing process) can fully transform the selected region. In some embodiments, the selected region is transformed from the corresponding top surface to the corresponding bottom surface.

[0068] Method 400 proceeds to operation 404 in which a first portion of the undoped amorphous silicon layer in the non-array region is retained to form a non-conductive layer, and a second portion of the undoped amorphous silicon layer in the core region is converted into a doped amorphous silicon portion using an ion implantation process. Figures 3B-3D The corresponding structure is shown.

[0069] like Figure 3B As shown in FIG, a patterned photoresist layer 351 can be formed to expose a first portion 320a of the undoped amorphous silicon layer and over a second portion 320b of the undoped amorphous silicon layer. The second portion 320b of the undoped amorphous silicon layer can cover multiple (e.g., all) first contact portions 315-1 in the non-array region 110, and the first portion 320a of the undoped amorphous silicon layer can cover the source terminals of all NAND memory strings 317 in the core region 108. The lateral dimension L1 (e.g., along the x-direction and / or the y-direction) of the second portion 320b of the undoped amorphous silicon layer (or the patterned photoresist layer 351) can be large enough to at least cover multiple (e.g., all) first contact portions 315-1. For example, the lateral dimension L1 can be equal to or less than the lateral dimension of the non-array region 110 along the x-direction. In some embodiments, the lateral dimension L1 can be equal to or less than the lateral dimension of the stepped region. In some embodiments, the lateral dimension L1 (e.g., along the x-direction and / or y-direction) can be equal to or greater than three times the thickness of the undoped amorphous silicon layer 320a along the z-direction. In some embodiments, the area of ​​the second portion 320b of the undoped amorphous silicon layer can cover the total area of ​​all first contact portions 315-1 along all lateral directions. Meanwhile, the lateral dimension L2 of the first portion 320a of the undoped amorphous silicon layer can be greater than or equal to the lateral dimensions of all NAND memory strings 317. For example, the area of ​​the first portion 320a of the undoped amorphous silicon layer can completely cover all NAND memory strings 317 and thus be equal to or greater than the total area of ​​all NAND memory strings 317. In some embodiments, the lateral dimension L2 is equal to or greater than the lateral dimension of the core region 108 along the x-direction. The patterned photoresist layer 351 can be formed by coating a photoresist layer over the undoped amorphous silicon layer 320 and performing a photolithography process to remove the portion of the photoresist layer over the first portion 320a of the undoped amorphous silicon layer.

[0070] like Figure 3CAs shown in FIG, the first portion 320a of the undoped amorphous silicon layer can be converted into a doped amorphous silicon layer 311a. In some embodiments, the conversion of the undoped amorphous silicon into the doped amorphous silicon includes an ion implantation process. In some embodiments, the dopant includes an N-type dopant, and the N-type dopant includes, for example, phosphorus and / or arsenic. The second portion 320b of the undoped amorphous silicon layer covered by the patterned photoresist layer 351 can remain undoped. Figure 3D As shown in , the patterned photoresist layer 351 may be removed using, for example, an ashing process and / or wet etching. The second portion 320b of the undoped amorphous silicon layer may be referred to as a non-conductive layer 313.

[0071] Return Reference Figure 4 The method 400 proceeds to operation 406 in which the doped amorphous silicon layer is converted into a doped polysilicon layer using a laser annealing process. Figure 3E The corresponding structure is shown.

[0072] like Figure 3E As shown in , the doped amorphous silicon layer 311a can be converted into a doped polysilicon layer referred to as a semiconductor layer 311. The conversion of the doped amorphous silicon to doped polysilicon can include a localized heat treatment, such as a laser annealing process. The localized heat treatment can be confined to the intended controlled area and will not affect other heat-sensitive structures, such as the bonding contacts 331 and 333 at the bonding interface 309 and other copper structures / interconnects. The doped amorphous silicon layer 311a can be crystallized during the localized heat treatment and form a doped polysilicon layer, for example, a semiconductor layer 311. In some embodiments, the temperature of the laser annealing process is in the range of 1300 degrees Celsius to 1700 degrees Celsius. In some embodiments, the laser annealing process includes a plurality of laser pulses, each laser pulse having a pulse time of 100ns (i.e., nanoseconds) to 300ns.

[0073] The localized thermal treatment (e.g., laser annealing process) can be controlled to be performed only on the doped amorphous silicon layer 311a. The lateral dimension L2 of the semiconductor layer 211 can be greater than or equal to the total lateral dimension of all NAND memory strings 317. For example, the area of ​​the semiconductor layer 311 can completely cover all NAND memory strings 317 and thus be equal to or greater than the total area of ​​all NAND memory strings 317.

[0074] Return Reference Figure 4 The method 400 proceeds to operation 408 in which a first insulating layer is formed over the non-conductive layer and the semiconductor layer. Figure 3F The corresponding structure is shown.

[0075] like Figure 3FAs shown in FIG, an insulating material may be deposited over semiconductor layer 311 and non-conductive layer 313 to form a first insulating layer 314. The insulating material (e.g., a dielectric material) may include silicon oxide, silicon nitride, silicon oxynitride, and / or other low-k dielectrics. The insulating material may be deposited using a suitable deposition method such as CVD, PVD, and / or ALD. In some embodiments, the deposition of the insulating material does not include ALD.

[0076] Return Reference Figure 4 , method 400 proceeds to operation 410 in which a plurality of first openings are formed through the non-conductive layer and the first insulating layer in the non-array region, and one or more second openings are formed in the first insulating layer in the core region. Figures 3G-3J The corresponding structure is shown.

[0077] Figures 3G-3J For example, different patterning processes are used to form the first openings ( Figure 3H 360 shown in FIG) and the second opening ( Figure 3J 358) process shown in FIG. Figure 3G As shown in FIG, a first patterned photoresist layer 352 may be first formed over the first insulating layer 314 in the core region 108 and the non-array region 110. In some embodiments, the first opening 360 may be first formed by patterning the non-conductive layer 313 and the first insulating layer 314 using the first patterned photoresist layer 352 including an opening 356 for forming the first opening 360 instead of the second opening 358. Figure 3H As shown in , the non-conductive layer 313 and the first insulating layer 314 can then be etched by a first etching process in the non-array region 110 to form first openings 360 each aligned with a corresponding first contact portion 315-1. The first patterned photoresist layer 352 can be removed.

[0078] like Figure 3I As shown in , another photoresist layer is then spin-coated onto the first insulating layer 314 and fills the first openings 360, thereby forming a photoresist portion 359 in each first opening 360. The photoresist layer can be patterned to form a second patterned photoresist layer 353, which includes one or more openings 354 each for forming a second opening 358 in the first insulating layer 314. A second etching process can be performed using the second patterned photoresist layer 353 as an etching mask to form the second opening 358 in the first insulating layer 314. The second patterned photoresist layer 353 and the photoresist portion 359 can then be removed, as shown in FIG. Figure 3JIn some embodiments, the first etching process and the second etching process may include appropriate dry etching and / or wet etching. In some embodiments, the removal of the photoresist may include an ashing process and / or wet etching.

[0079] In some other embodiments, the first opening 360 and the second opening 358 are formed in the same patterning process. For example, the patterned photoresist layer formed on the first insulating layer 314 may include one or more openings for forming the first opening 360 and one or more openings for forming the second opening 358. The openings can all contact the first insulating layer 314. In some embodiments, the one or more openings can be aligned with the corresponding first contact portion 315-1 along the z-direction, and the one or more openings can all be located above the source end of the NAND memory string 317. The patterned photoresist layer can be formed by coating a photoresist layer on the first insulating layer 314 and performing a photolithography process for forming the openings. The patterned photoresist layer can be used as an etching mask to perform an appropriate etching process (e.g., dry etching and / or wet etching) to form a plurality of first openings 360 that pass through the non-conductive layer 313 and the first insulating layer 314 and are all in contact with the corresponding first contact portion 315-1. In the same etching process, one or more second openings 358 are formed in the first insulating layer 314 and contact the semiconductor layer 311. The patterned photoresist layer may then be removed, for example, using an ashing process and / or wet etching.

[0080] Return Reference Figure 4 The method 400 proceeds to operation 412 in which a second contact portion is formed in each first opening and a third contact portion is formed in each second opening. Figure 3K The corresponding structure is shown.

[0081] like Figure 3KAs shown in FIG, a second contact portion 315-2 is formed in each first opening 360, and a third contact portion 341 is formed in each second opening 358. Each second contact portion 315-2 can contact a corresponding first contact portion 315-1. In some embodiments, each first contact portion 315-1 and the corresponding second contact portion 315-2 can form a contact structure 315, such as a TSC. Each second contact portion 315-2 and third contact portion 341 can include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, the second contact portion 315-2 and third contact portion 341 can be formed by depositing a layer of conductive material to fill the second opening 360 and the third opening 358 and performing a recess etch (e.g., a blanket etch) to remove any excess conductive material on the first insulating layer 314. In some embodiments, the deposition of the conductive material includes CVD, PVD, ALD, electroplating, electroless plating, or a combination of CVD, PVD, ALD, electroplating, and electroless plating. The recess etching may include appropriate dry etching and / or wet etching.

[0082] Return Reference Figure 4 The method 400 proceeds to operation 414 in which a first contact layer conductively connected to the second contact portion is formed, and a second contact layer conductively connected to the third contact portion is formed. Figures 3L-3N The corresponding structure is shown.

[0083] like Figure 3L As shown in FIG, a contact material layer 362 can be formed to contact the second contact portion 315-2 and the third contact portion 341. The contact material layer 362 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, the contact material layer 362 can be deposited using CVD, PVD, ALD, electroplating, electroless plating, or a combination of CVD, PVD, ALD, electroplating, and electroless plating.

[0084] like Figure 3MAs shown in , a patterned photoresist layer 364 can be formed over the contact material layer 362. The patterned photoresist layer 364 can include one or more openings 366 for patterning the contact material layer 362 so as to disconnect a portion of the contact material layer 362 that is conductively connected to the third contact portion 341 (e.g., the NAND memory string 317) from another portion of the contact material layer 362 that is conductively connected to the contact structure 315. In some embodiments, in the xy plane, the opening 366 can be located between the third contact portion 341 and the contact structure 315 and can contact the contact material layer 362. The patterned photoresist layer 364 can be formed by spin-coating a photoresist layer over the contact material layer 362 and patterning the photoresist layer using a photolithography process.

[0085] like Figure 3N As shown in FIG, a first contact layer 321 conductively connected to the second contact portion 315-2 (or contact structure 315) is formed, and a second contact layer 323 conductively connected to the third contact portion 341 is formed. The first contact layer 321 can be disconnected from the second contact layer 323 by one or more openings 325, which are located between the first contact layer 321 and the second contact layer 323 and disconnect them. The openings 325 can be formed by etching the contact material layer 362 using the patterned photoresist layer 364 as an etching mask. In some embodiments, the etching of the contact material layer 362 includes appropriate dry etching and / or wet etching. The patterned photoresist layer 364 can then be removed using an ashing process.

[0086] Return Reference Figure 4 , the method 400 proceeds to operation 416 in which the first pad-out interconnect is conductively connected to the first contact layer and the second pad-out interconnect is conductively connected to the second contact layer. Figures 3O-3Q The corresponding structure is shown.

[0087] like Figure 3OAs shown in , a dielectric material can be deposited over the first contact layer 321 and the second contact layer 323 to form one or more dielectric layers. The dielectric material can fill the opening 325, thereby providing insulation between the first contact layer 321 and the second contact layer 323. In some embodiments, a first dielectric material is deposited in contact with the first contact layer 321 and the second contact layer 323 and filling the opening 325, thereby forming a first dielectric layer 327. A second dielectric material can be deposited over the first dielectric layer 327, thereby forming a second dielectric layer 329. In some embodiments, the first dielectric layer 327 includes silicon oxide and the second dielectric layer 329 includes silicon nitride. The deposition of the first and second dielectric materials can each include CVD, PVD, ALD, or a combination of CVD, PVD, and ALD.

[0088] like Figure 3P As shown in FIG, a patterned photoresist layer 368 can be formed over the second dielectric layer 329. The patterned photoresist layer 368 can include one or more openings 370 for patterning the first dielectric layer 327 and the second dielectric layer 329 and forming a pad lead-out interconnect. In some embodiments, the openings 370 can be located above the contact structure 315 and the third contact portion 341, respectively. The patterned photoresist layer 368 can be formed by spin-coating a photoresist layer over the second dielectric layer 329 and patterning the photoresist layer using a photolithography process. The patterned photoresist layer 368 can be used as an etch mask to etch the first dielectric layer 327 and the second dielectric layer 329 to form corresponding openings (not shown) in the first dielectric layer 327 and the second dielectric layer 329. At least one opening can be in contact with the first contact layer 321, and at least one opening can be in contact with the second contact layer 323. The patterned photoresist layer 368 may be removed using an ashing process.

[0089] like Figure 3QAs shown in FIG, a plurality of pad lead-out interconnects 319 are formed in the openings. The pad lead-out interconnects 319 may include at least one first pad lead-out interconnect 319 in contact with the first contact layer 321 and at least one second pad lead-out interconnect 319 in contact with the second contact layer 323. The pad lead-out interconnects 319 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide. In some embodiments, the pad lead-out interconnects 319 may be deposited using CVD, PVD, ALD, electroplating, electroless plating, or a combination of CVD, PVD, ALD, electroplating, and electroless plating. In some embodiments, a recess etch, such as a dry etch and / or a wet etch, may be performed after deposition to remove any excess conductive material on the second dielectric layer 329.

[0090] Figure 5 1 is a block diagram of a system 500 having a memory device according to some aspects of the present disclosure. The system 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device located therein. Figure 5 As shown in FIG, system 500 may include a host 508 and a memory system 502 having one or more memory devices 504 and a memory controller 506. The host 508 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 508 may be configured to send or receive data to or from the memory device 504.

[0091] The memory device 504 can be any memory device disclosed herein, such as the 3D memory device 200. In some embodiments, each memory device 504 includes an array of memory cells and peripheral circuitry for the array of memory cells. As detailed above, the array of memory cells and the peripheral circuitry are stacked on top of each other in different planes.

[0092] According to some embodiments, the memory controller 506 is coupled to the memory device 504 and the host 508 and is configured to control the memory device 504. The memory controller 506 can manage data stored in the memory device 504 and communicate with the host 508. In some embodiments, the memory controller 506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 506 can be configured to control operations of the memory device 504, such as read, erase, and program operations. In some embodiments, the memory controller 506 is configured to control the array of memory cells via the first peripheral circuit and the second peripheral circuit. The memory controller 506 may also be configured to manage various functions related to data stored in or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 504. Any other appropriate functions may also be performed by the memory controller 506, such as formatting the memory device 504. The memory controller 506 may communicate with an external device (e.g., a host 508) according to a specific communication protocol.For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the peripheral component interconnection (PCI) protocol, the high-speed PCI (PCI-express, PCI-E) protocol, the advanced technology attachment (ATA) protocol, the serial ATA protocol, the parallel ATA protocol, the small computer small interface (SCSI) protocol, the enhanced small disk interface (ESDI) protocol, the integrated drive electronics (IDE) protocol, the Firewire protocol, etc.

[0093] The memory controller 506 and the one or more memory devices 504 can be integrated into various types of memory devices, for example, included in the same package (such as a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 502 can be implemented and packaged into different types of final electronic products. Figure 6A In one example shown in FIG, the memory controller 506 and the single memory device 504 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may further include a memory card 602 that connects the memory card 602 to a host (e.g., Figure 5 The memory card connector 604 is coupled to the host 508 in FIG. Figure 6B In another example shown in FIG, the memory controller 506 and the plurality of memory devices 504 may be integrated into an SSD 606. The SSD 606 may further include a processor that interfaces the SSD 606 with a host (e.g., Figure 5 In some embodiments, the storage capacity and / or operating speed of the SSD 606 is higher than the storage capacity and / or operating speed of the memory card 602.

[0094] According to one aspect of the present disclosure, a 3D memory device includes a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source terminals of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

[0095] In some embodiments, the non-conductive layer is a single layer in contact with the semiconductor layer.

[0096] In some embodiments, the first semiconductor structure further includes a second contact structure passing through the non-conductive layer. The non-conductive layer insulates the contact structure and the second contact structure from each other and from the semiconductor layer.

[0097] In some embodiments, the semiconductor layer is located in a core region of the first semiconductor structure, and the non-conductive layer is located in a non-array region of the first semiconductor structure.

[0098] In some embodiments, the non-conductive layer is located in the stepped region of the first semiconductor structure.

[0099] In some embodiments, the non-conductive layer is located outside the stepped region of the first semiconductor structure.

[0100] In some embodiments, the non-conductive layer includes a non-conductive material.

[0101] In some embodiments, the non-conductive layer includes undoped amorphous silicon.

[0102] In some embodiments, the area of ​​the non-conductive layer is larger than the area where the plurality of contact structures are formed and is smaller than or equal to the non-array area.

[0103] In some embodiments, the semiconductor layer and the non-conductive layer have the same thickness in the range of 100 nm to 600 nm.

[0104] In some embodiments, the semiconductor layer includes doped polysilicon.

[0105] In some embodiments, the area of ​​the semiconductor layer is greater than or equal to the area where all NAND memory strings are formed.

[0106] In some embodiments, the first semiconductor structure further includes a pad lead-out interconnect layer; and the second semiconductor structure further includes a substrate.

[0107] Another aspect of the present disclosure provides a 3D memory device comprising a first semiconductor structure having a core region and a non-array region. The first semiconductor structure comprises an array of NAND memory strings in a subregion of the core region, a semiconductor layer in contact with the source terminals of the array of NAND memory strings, a non-conductive layer in the non-array region, and a plurality of contact structures in the non-conductive layer and in another subregion of the non-array region. The non-conductive layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device comprises a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure comprises a transistor.

[0108] In some embodiments, the non-conductive layer is a single layer.

[0109] In some embodiments, an area of ​​the non-conductive layer is equal to or greater than an area of ​​the another sub-region and less than or equal to an area of ​​the non-array region; and the non-conductive layer insulates the contact structures from each other.

[0110] In some embodiments, the area of ​​the semiconductor layer is equal to or greater than the area of ​​the sub-region.

[0111] In some embodiments, the non-conductive layer includes a non-conductive material.

[0112] In some embodiments, the non-conductive layer includes undoped amorphous silicon.

[0113] In some embodiments, the semiconductor layer and the non-conductive layer have the same thickness in the range of 100 nm to 600 nm.

[0114] In some embodiments, the semiconductor layer includes doped polysilicon.

[0115] In some embodiments, the first semiconductor structure further includes a pad lead-out interconnect layer; and the second semiconductor structure further includes a substrate.

[0116] Another aspect of the present disclosure provides a method for forming a 3D memory device. The method includes bonding a first semiconductor structure to a second semiconductor structure, the first semiconductor structure having a core region and a non-array region. The method also includes: depositing an undoped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure; converting a first portion of the undoped amorphous silicon layer into a doped polysilicon layer; retaining a second portion of the undoped amorphous silicon layer in the non-array region; and forming a first contact portion in the second portion of the undoped amorphous silicon layer. The first contact portion contacts a second contact portion in the first semiconductor structure.

[0117] In some embodiments, the method further includes: converting a first portion of the undoped amorphous silicon layer into a doped amorphous silicon layer; and converting the doped amorphous silicon layer into a doped polysilicon layer.

[0118] In some embodiments, converting the first portion of the doped amorphous silicon layer includes performing a localized thermal treatment on the first portion of the doped amorphous silicon layer.

[0119] In some embodiments, the localized heat treatment includes a laser annealing process.

[0120] In some embodiments, the laser annealing process has an annealing temperature in a range of 1300 degrees Celsius to 1700 degrees Celsius and includes a plurality of laser pulses, each laser pulse having a pulse time of 100 ns to 300 ns.

[0121] In some embodiments, the undoped amorphous silicon layer is deposited using a low temperature deposition process, and converting the undoped amorphous silicon layer into the doped amorphous silicon layer includes performing an ion implantation process.

[0122] In some embodiments, the doped amorphous silicon layer is doped with an N-type dopant, and the N-type dopant includes at least one of phosphorus or arsenic.

[0123] In some embodiments, forming the first semiconductor structure includes: forming an array of NAND memory strings and the second contact portion above a substrate; and thinning the substrate to expose source terminals of the NAND memory strings.

[0124] In some embodiments, an undoped amorphous silicon layer is deposited in contact with the source terminals of the NAND memory strings.

[0125] In some embodiments, the method further includes forming an insulating layer over the second portion of the undoped amorphous silicon layer and the doped polysilicon layer.

[0126] In some embodiments, the method further includes forming a first opening in the non-array region. The first opening passes through the insulating layer and the second portion of the undoped amorphous silicon layer, exposing a second contact portion. The method further includes forming a second opening in the core region. The second opening passes through the insulating layer and exposes the doped polysilicon layer. The method further includes forming a first contact portion in the first opening and a third contact portion in the second opening. The third contact portion contacts the doped polysilicon layer.

[0127] In some embodiments, the first opening and the second opening are formed in the same patterning process.

[0128] In some embodiments, the method further includes forming a first contact layer conductively connected to the first contact portion and a second contact layer conductively connected to the third contact portion over the non-conductive layer. The first contact layer and the second contact layer are insulated from each other. The method further includes forming a pad lead-out interconnect layer over the first contact layer and the second contact layer. The pad lead-out interconnect layer includes corresponding contact structures conductively connected to the first contact layer and the second contact layer.

[0129] In some embodiments, forming the second semiconductor structure includes forming a peripheral circuit on the corresponding substrate. The peripheral circuit includes a plurality of transistors.

[0130] Another aspect of the present disclosure provides a system including a memory device configured to store data. The memory device includes a first semiconductor structure having an array of NAND memory strings, a semiconductor layer in contact with a source terminal of the array of NAND memory strings, a non-conductive layer in contact with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The memory device also includes a second semiconductor structure bonded to the first semiconductor structure and including a transistor. The system also includes a memory controller coupled to the memory device and configured to control the array of NAND memory strings through peripheral circuitry.

[0131] The foregoing description of the specific embodiments can be easily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adaptations and modifications fall within the meaning and range of equivalents of the disclosed embodiments.

[0132] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure comprising: an array of NAND memory strings; a semiconductor layer in contact with source terminals of the array of NAND memory strings; a non-conductive layer aligned with the semiconductor layer; and a contact structure in the non-conductive layer, wherein the non-conductive layer electrically insulates the contact structure from the semiconductor layer; and A second semiconductor structure including a transistor is bonded to the first semiconductor structure.

2. The 3D memory device according to claim 1, wherein The non-conductive layer is a single layer in contact with the semiconductor layer.

3. The 3D memory device according to claim 1 , wherein: The first semiconductor structure further includes a second contact structure passing through the non-conductive layer; The non-conductive layer insulates the contact structure and the second contact structure from each other; and The non-conductive layer insulates the contact structure and the second contact structure from the semiconductor layer.

4. The 3D memory device according to any one of claims 1 to 2, wherein: The semiconductor layer is located in the core region of the first semiconductor structure; and The non-conductive layer is located in a non-array region of the first semiconductor structure.

5. The 3D memory device according to claim 4, wherein The non-conductive layer is located in the stepped region of the first semiconductor structure.

6. The 3D memory device according to claim 4, wherein The non-conductive layer is located outside the stepped region of the first semiconductor structure.

7. The 3D memory device according to any one of claims 1 to 2, wherein: The non-conductive layer includes a non-conductive material.

8. The 3D memory device according to any one of claims 1 to 2, wherein: The non-conductive layer includes undoped amorphous silicon.

9. The 3D memory device according to any one of claims 1 to 2, wherein: The area of ​​the non-conductive layer is larger than the area where the multiple contact structures are formed and is smaller than or equal to the non-array area.

10. The 3D memory device according to any one of claims 1 to 2, wherein: The semiconductor layer and the non-conductive layer have the same thickness in the range of 100 nm to 600 nm.

11. The 3D memory device according to any one of claims 1 to 2, wherein: The semiconductor layer includes doped polysilicon.

12. The 3D memory device according to any one of claims 1 to 2, wherein: The area of ​​the semiconductor layer is greater than or equal to the area where all the NAND memory strings are formed.

13. The 3D memory device according to claim 12, wherein: The first semiconductor structure further comprises a pad lead-out interconnect layer; and The second semiconductor structure further includes a substrate.

14. A three-dimensional (3D) memory device comprising: A first semiconductor structure having a core region and a non-array region, the first semiconductor structure comprising: an array of NAND memory strings in a sub-region of the core area; a semiconductor layer in contact with source terminals of the array of NAND memory strings; A non-conductive layer in the non-array area; and a plurality of contact structures in the non-conductive layer and in another sub-region of the non-array area, wherein the non-conductive layer electrically insulates the contact structures from the semiconductor layer; and A second semiconductor structure including a transistor is bonded to the first semiconductor structure.

15. The 3D memory device according to claim 14, wherein The non-conductive layer is a single layer.

16. The 3D memory device according to claim 14 or 15, wherein: The area of ​​the non-conductive layer is equal to or greater than the area of ​​the other sub-region, and is less than or equal to the area of ​​the non-array region; and The non-conductive layer insulates the contact structures from each other.

17. The 3D memory device according to any one of claims 14-15, wherein: The area of ​​the semiconductor layer is equal to or larger than the area of ​​the sub-region.

18. The 3D memory device according to any one of claims 14-15, wherein The non-conductive layer includes a non-conductive material.

19. The 3D memory device according to any one of claims 14-15, wherein The non-conductive layer includes undoped amorphous silicon.

20. The 3D memory device according to any one of claims 14-15, wherein The semiconductor layer and the non-conductive layer have the same thickness in the range of 100 nm to 600 nm.

21. The 3D memory device according to any one of claims 14-15, wherein The semiconductor layer includes doped polysilicon.

22. The 3D memory device according to any one of claims 14-15, wherein: The first semiconductor structure further comprises a pad lead-out interconnect layer; and The second semiconductor structure further includes a substrate.

23. A method for forming a three-dimensional (3D) memory device, comprising: bonding a first semiconductor structure and a second semiconductor structure together, wherein the first semiconductor structure includes a core region and a non-array region; depositing an undoped amorphous silicon layer on the core region and the non-array region of the first semiconductor structure; converting a first portion of the undoped amorphous silicon layer into a doped polysilicon layer; retaining a second portion of the undoped amorphous silicon layer in the non-array region; as well as A first contact portion is formed in the second portion of the undoped amorphous silicon layer, the first contact portion being in contact with a second contact portion in the first semiconductor structure.

24. The method of claim 23, further comprising: converting the first portion of the undoped amorphous silicon layer into a doped amorphous silicon layer; as well as The doped amorphous silicon layer is converted into the doped polysilicon layer.

25. The method according to claim 24, wherein Converting the first portion of the doped amorphous silicon layer includes performing a localized thermal treatment on the first portion of the doped amorphous silicon layer.

26. The method according to claim 25, wherein The local heat treatment includes a laser annealing process.

27. The method according to claim 26, wherein The laser annealing process has an annealing temperature in a range of 1300 degrees Celsius to 1700 degrees Celsius and includes a plurality of laser pulses each having a pulse time of 100 ns to 300 ns.

28. The method according to any one of claims 24 to 27, wherein: The undoped amorphous silicon layer is deposited using a low temperature deposition process; and Converting the undoped amorphous silicon layer into the doped amorphous silicon layer includes performing an ion implantation process.

29. The method according to claim 28, wherein The doped amorphous silicon layer is doped with an N-type dopant, and the N-type dopant includes at least one of phosphorus or arsenic.

30. The method according to any one of claims 23 to 27, wherein: Forming the first semiconductor structure includes: forming an array of NAND memory strings and the second contact portion above a substrate; and The substrate is thinned to expose source terminals of the NAND memory strings.

31. The method according to claim 30, wherein The undoped amorphous silicon layer is deposited in contact with the source terminal of the NAND memory string.

32. The method of any one of claims 23-27, further comprising forming an insulating layer over the second portion of the undoped amorphous silicon layer and the doped polysilicon layer.

33. The method of claim 32, further comprising forming: a first opening in the non-array region, the first opening passing through the insulating layer and the second portion of the undoped amorphous silicon layer and exposing the second contact portion; a second opening in the core region, the second opening passing through the insulating layer and exposing the doped polysilicon layer; as well as The first contact portion is in the first opening and the third contact portion is in the second opening, wherein the third contact portion is in contact with the doped polysilicon layer.

34. The method according to claim 33, wherein The first opening and the second opening are formed in the same patterning process.

35. The method of claim 34, further comprising, forming a first contact layer conductively connected to the first contact portion and a second contact layer conductively connected to the third contact portion over the insulating layer, the first contact layer and the second contact layer being insulated from each other; and A pad lead-out interconnection layer is formed on the first contact layer and the second contact layer, wherein: The pad lead-out interconnect layer includes respective contact structures conductively connected to the first contact layer and the second contact layer.

36. The method according to any one of claims 23 to 27, wherein: Forming the second semiconductor structure includes forming a peripheral circuit structure on the corresponding substrate, wherein the peripheral circuit includes a plurality of transistors.

37. A memory system comprising: A memory device configured to store data, comprising: A first semiconductor structure comprising: an array of NAND memory strings; a semiconductor layer in contact with source terminals of the array of NAND memory strings; a non-conductive layer in contact with the semiconductor layer; a contact structure in the non-conductive layer, wherein the non-conductive layer electrically insulates the contact structure from the semiconductor layer; and a second semiconductor structure including a transistor bonded to the first semiconductor structure; and A memory controller is coupled to the memory device and configured to control the array of NAND memory strings through peripheral circuits.

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