Display device

Abstract

A display device is provided. The display device includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The drive controller receives image signals and control signals, and controls the data driving circuit and the scan driving circuit to display an image on the display panel. Based on the image signals, the drive controller divides the display panel into a first display area and a second display area, and outputs a start signal and a masking signal indicating the start of a frame and the start of the second display area, respectively. The first frame and the second frame have a first duration and a second duration, respectively. The scan driving circuit sequentially drives scan lines synchronously with the start signal, and stops driving the scan line corresponding to the second display area in response to the masking signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0079610, filed on June 29, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display devices, and more particularly, to display devices having high operating speeds. Background Technology

[0004] Organic light-emitting diode (OLED) displays, as a type of display device, use organic light-emitting diodes (OLEDs) to display images. Light is generated in OLEDs through the recombination of electrons and holes. These OLED displays offer technological advantages such as fast response times and low power consumption.

[0005] Organic light-emitting display devices include pixels connected to data lines and scan lines. Typically, each pixel includes an organic light-emitting diode (OLED) and a circuit section that controls the amount of current flowing through the OLED. In the circuit section, the amount of current flowing through the OLED is controlled by a data signal. In this case, the brightness of the light generated by the OLED is determined by the amount of current.

[0006] When displaying video images on a display device, a higher drive frequency results in better display quality. However, manufacturing display devices that operate at high drive frequencies increases manufacturing costs. Summary of the Invention

[0007] An embodiment of the present invention provides a display device in which the display area is driven at a frequency higher than the normal frequency.

[0008] According to an embodiment of the present invention, a display device includes: a display panel comprising a plurality of pixels connected to a plurality of data lines and a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a drive controller receiving an image signal and a control signal and controlling the data driving circuit and the scan driving circuit to display an image on the display panel. The drive controller divides the display panel into a first display area and a second display area based on the image signal, and outputs a start signal indicating the start of a frame and a masking signal indicating the start of the second display area. The first frame has a first duration, and a second frame following the first frame has a second duration. The scan driving circuit sequentially drives the plurality of scan lines synchronously with the start signal, and stops driving the scan line corresponding to the second display area in response to the masking signal.

[0009] In an implementation, during the first mode, the second duration of the second frame may be shorter than the first duration of the first frame.

[0010] In an implementation, during a second mode that differs from the first mode, the first duration of the first frame may be equal to the second duration of the second frame.

[0011] In an implementation, the first duration of the first frame during the first mode may be equal to the first duration of the first frame during the second mode.

[0012] In this implementation, during the second mode, the first display area and the second display area can be driven at a predetermined frequency. During the first mode, the first display area can be driven at a first driving frequency higher than the predetermined frequency, and the second display area can be driven at a second driving frequency lower than the predetermined frequency.

[0013] In one implementation, the drive controller may provide image data signals corresponding to the first display area and the second display area to the data drive circuit during the first frame of the first mode, and may provide image data signals corresponding to the first display area but not the second display area to the data drive circuit during the second frame of the first mode.

[0014] In one implementation, the drive controller can provide image data signals corresponding to the first and second display areas to the data drive circuit during each frame in a second mode that is different from the first mode.

[0015] In an implementation, the scan driving circuit may include multiple driving stages, each of which drives a corresponding scan line among multiple scan lines. Each of the multiple driving stages may include: a driving circuit that outputs a scan signal to an output terminal in response to a clock signal and a carry signal from a driving controller, and a masking circuit that disables the driving circuit from outputting the scan signal in response to a masking signal.

[0016] In the implementation, the first driver stage among multiple driver stages can receive a start signal as a carry signal.

[0017] In an implementation, in response to a clock signal and a carry signal, the driving circuit can also output a first scan signal to a first output terminal and a second scan signal to a second output terminal.

[0018] In one implementation, a second scan signal output from the j-th drive stage among a plurality of drive stages can be provided as a carry signal for the (j+k)-th drive stage, where j and k are natural numbers.

[0019] In an implementation, the masking signal may include a first masking signal and a second masking signal. The masking circuit may include a first masking circuit electrically connected to a first voltage terminal and a first output terminal in response to the first masking signal, and a second masking circuit electrically connected to the first output terminal and the second output terminal in response to the second masking signal.

[0020] In one implementation, during a first mode, a first masking circuit may, in response to a first masking signal of a first level, electrically connect a first voltage terminal to a first output terminal. During the first mode, a second masking circuit may, in response to a second masking signal of a second level different from the first level, disconnect the electrical connection between the first output terminal and the second output terminal.

[0021] According to an embodiment of the present invention, a display device includes: a display panel including a plurality of pixels connected to a plurality of data lines and a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a drive controller receiving an image signal and a control signal and controlling the data driving circuit and the scan driving circuit to display an image on the display panel. In a plan view, a first non-folding area, a folding area, and a second non-folding area are defined in the display panel. The drive controller divides the display panel into a first display area and a second display area corresponding to the first non-folding area and the second non-folding area, respectively, and outputs a start signal indicating the start of a frame and a masking signal indicating the start of the second display area. The first frame has a first duration, and a second frame following the first frame has a second duration. The scan driving circuit sequentially drives the plurality of scan lines synchronously with the start signal and stops driving the scan line corresponding to the second display area in response to the masking signal.

[0022] In an implementation, during the first mode, the second duration of the second frame may be shorter than the first duration of the first frame.

[0023] In one implementation, the drive controller may provide image data signals corresponding to the first display area and the second display area to the data drive circuit during the first frame of the first mode, and may provide image data signals corresponding to the first display area but not the second display area to the data drive circuit during the second frame of the first mode.

[0024] In this implementation, the image data signal provided to the first display area during the first mode may be a moving image signal, and the image data signal provided to the second display area during the first mode may be a still image signal.

[0025] In one embodiment, the folding area of ​​the display panel can be foldable along a folding axis extending in a predetermined direction.

[0026] According to an embodiment of the present invention, a display device includes: a display panel comprising a plurality of pixels connected to a plurality of data lines and a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a drive controller receiving image signals and control signals and controlling the data driving circuit and the scan driving circuit to display an image on the display panel. The drive controller divides the display panel into a first display area and a second display area based on the image signals, provides image data signals corresponding to the first and second display areas to the data driving circuit during a first frame, and provides image data signals corresponding to the first display area but not the second display area to the data driving circuit during a second frame after the first frame.

[0027] In one implementation, the drive controller may output a start signal indicating the start of a frame and a mask signal indicating the start of a second display area. The scan drive circuit may sequentially drive multiple scan lines in sync with the start signal, and may stop driving the scan line corresponding to the second display area in response to the mask signal.

[0028] In an implementation, the scan driving circuit may include multiple driving stages, each of which drives a corresponding scan line among multiple scan lines. Each of the multiple driving stages may include a driving circuit that outputs a scan signal to an output terminal in response to a clock signal and a carry signal from a driving controller, and a masking circuit that disables the driving circuit from outputting the scan signal in response to a masking signal.

[0029] In the implementation, the first driver stage among multiple driver stages can receive a start signal as a carry signal.

[0030] In the implementation, the driving circuit can respond to the clock signal and the carry signal, and output the first scan signal and the second scan signal to the first output terminal and the second output terminal, respectively.

[0031] In one implementation, a second scan signal output from the j-th drive stage among a plurality of drive stages can be provided as a carry signal for the (j+k)-th drive stage, where j and k are natural numbers.

[0032] In an implementation, the masking signal may include a first masking signal and a second masking signal. The masking circuit may include a first masking circuit electrically connected to a first voltage terminal and a first output terminal in response to the first masking signal, and a second masking circuit electrically connected to the first output terminal and the second output terminal in response to the second masking signal. Attached Figure Description

[0033] The exemplary embodiments will be more clearly understood through the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0034] Figure 1A This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention.

[0035] Figure 1B This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention.

[0036] Figure 2 This is a diagram illustrating the operation of the display device in normal frequency mode.

[0037] Figure 3 This is a diagram illustrating the operation of the display device in multi-frequency mode.

[0038] Figure 4 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0039] Figure 5 This is an equivalent circuit diagram illustrating a pixel according to an embodiment of the concept of the present invention.

[0040] Figure 6 It is shown Figure 5 A timing diagram of the operation of pixels in a display device.

[0041] Figure 7 This is a block diagram illustrating a scan drive circuit according to an embodiment of the concept of the present invention.

[0042] Figure 8 It shows Figure 7 One of the driver levels (e.g., the j-th driver level).

[0043] Figure 9 This is an example shown Figure 7 Timing diagrams of the operations of the (j-1)th drive stage, the jth drive stage, and the (j+1)th drive stage in the scan drive circuit.

[0044] Figure 10 This is an example illustrating the effect of switching from the normal frequency mode. Figure 4 The drive controller provides to Figure 7 The scanning drive circuit and Figure 4 The diagram shows the signals of the data driving circuit and the image data signals.

[0045] Figures 11A to 11C This is an example illustrating how to use multi-frequency mode from Figure 4 The drive controller provides to Figure 7 The scanning drive circuit and Figure 4 The diagram shows the signals of the data driving circuit and the image data signals.

[0046] Figure 12This is an example diagram showing the first scan signal output from the scan drive circuit in multi-frequency mode.

[0047] Figure 13 This is an example illustrating how to use multi-frequency mode from Figure 4 The drive controller provides to Figure 7 A diagram of the start signal of the scan drive circuit.

[0048] Figure 14 This is a top plan view illustrating a display device according to an embodiment of the concept of the present invention.

[0049] Figure 15 This is a top plan view illustrating a display device according to an embodiment of the concept of the present invention.

[0050] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and are intended to supplement the written description provided below. However, these figures are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or properties included in the exemplary embodiments. For example, the relative thicknesses and locations of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0051] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments. However, these example embodiments of the inventive concept may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be exhaustive and complete, and will fully convey the concept of the example embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are enlarged for clarity. Similar reference numerals in the drawings denote similar elements, and therefore their descriptions are omitted.

[0052] It should be understood that when an element is referred to as “connected” or “linked” to another element, the element can be directly connected to or linked to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly linked” to another element, there are no intermediate elements. Similar reference numerals throughout the document indicate similar elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Other terms used to describe relationships between elements or layers should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, “on” vs. “directly on”).

[0053] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion without departing from the teachings of the exemplary embodiments.

[0054] Spatial relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., may be used herein for descriptive convenience to describe the relationship of one element or feature to another element(s)(s) shown in the figures. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that the terms “comprise,” “comprising,” “includes,” and / or “including,” if used herein, indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] Example embodiments of the inventive concept are described herein with reference to schematic cross-sectional views illustrating idealized embodiments (and intermediate structures) as exemplary embodiments. Thus, variations in the shape of the figures are contemplated due to factors such as manufacturing techniques and / or tolerances. Therefore, the example embodiments of the inventive concept should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to factors such as manufacturing processes.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments of the concepts of this invention pertain. It should also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the context of the relevant field, and shall not be interpreted in an idealized or overly rigid sense unless expressly so defined herein.

[0058] Figure 1A This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention. Figure 1B This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention. Figure 1A The display device DD in its unfolded state is shown, and Figure 1B The display device DD is shown in a folded state.

[0059] Figure 1A and Figure 1B The illustration shows a display device DD as an example of a cellular phone. However, the inventive concept is not limited to this example. The display device DD may include a tablet PC (“PC”), a smartphone, a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a game console, a watch-type electronic device, etc. The display device DD can be used in large electronic devices (e.g., a television set or an outdoor billboard) or small or medium-sized electronic devices (e.g., a personal computer, a laptop computer, an information kiosk system, a car navigation system, or a camera). However, it should be understood that these are merely exemplary embodiments of the inventive concept, and other electronic devices may be used to implement the inventive concept as long as they do not depart from it.

[0060] The display device DD may include a display area DA and a non-display area NDA. The display device DD may display an image through the display area DA. When the display device DD is in an unfolded state, the display area DA may include a flat surface defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD may be parallel to a third direction DR3 that intersects both the first direction DR1 and the second direction DR2. The front or top surface and the rear or bottom surface of each component constituting the display device DD may be defined based on the third direction DR3. The non-display area NDA may be referred to as a border area. As an example, the display area DA may be rectangular or square. The non-display area NDA may surround the display area DA.

[0061] The display area DA may include a first non-folding area NFA1, a folding area FA, and a second non-folding area NFA2. The folding area FA may be flexible, extending along a folding axis FX in the first direction DR1.

[0062] If the display device DD is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can face each other. Therefore, when the display device DD is in a fully folded state, the display area DA is not exposed to the outside, and this state can be referred to as the "inward folding" state. However, the operation of the display device DD is not limited to this example.

[0063] In one implementation, for example, the display device DD can be folded such that the first non-folding region NFA1 and the second non-folding region NFA2 are back-to-back with each other. In this folded state, the first non-folding region NFA1 is exposed to the outside, and this state can be referred to as the "outward folding" state.

[0064] The display device DD can operate in either an inward folding mode or an outward folding mode. Alternatively, the display device DD can operate in both an inward folding mode and an outward folding mode. In this case, a specific area of ​​the display device DD (e.g., the folding area FA) can be folded together during both the inward folding and outward folding operations. In some embodiments, the display device DD may include at least two different areas, one of which is folded inward and the other of which is folded outward.

[0065] Figure 1A and Figure 1B An example is shown that provides one folded area and two non-folded areas, but the number of folded and non-folded areas is not limited thereto. For example, in another embodiment, the display device DD may include three or more non-folded areas and two or more folded areas, each of the folded areas being arranged between adjacent non-folded areas.

[0066] exist Figure 1A and Figure 1B In this diagram, the folding axis FX is shown as parallel to the minor axis (i.e., the horizontal axis) of the display device DD, but the concept of the invention is not limited to this example. For instance, the folding axis FX may be parallel to the major axis (i.e., the vertical axis) of the display device DD (e.g., the second direction DR2). In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially on the first direction DR1.

[0067] Multiple display areas DA1 and DA2 can be defined in the display device DD. Figure 1A An example with two display areas DA1 and DA2 is shown, but the number of display areas DA1 and DA2 according to the present invention is not limited thereto.

[0068] Display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be an area displaying a first image IM1, and the second display area DA2 may be an area displaying a second image IM2, but the concept of the present invention is not limited thereto. For example, the first image IM1 may be a video image (i.e., a moving image), and the second image IM2 may be a still image or text image that does not change over a relatively long period of time compared to the moving image.

[0069] When the display device DD is in normal frequency mode, both the first display area DA1 and the second display area DA2 can be driven at a predetermined normal frequency (e.g., 60 Hz). When the display device DD is in multi-frequency mode, the first display area DA1, which displays the first image IM1, can be driven at a first driving frequency higher than the normal frequency, and the second display area DA2, which displays the second image IM2, can be driven at a second driving frequency lower than the normal frequency. Due to the increase in the driving frequency of the first display area DA1, the display quality of the video image (i.e., moving image) displayed on the display device DD can be improved. Due to the decrease in the driving frequency of the second display area DA2, the power consumption of the display device DD can be reduced.

[0070] The size of each of the first display area DA1 and the second display area DA2 may be predetermined, but can be changed by an application or according to the type of image displayed on the first display area DA1 and the second display area DA2. In one embodiment, the first display area DA1 may correspond to a first non-folding area NFA1, and the second display area DA2 may correspond to a second non-folding area NFA2. In another embodiment, a portion of the folding area FA may correspond to the first display area DA1, and another portion of the folding area FA may correspond to the second display area DA2.

[0071] In this implementation, the first display area DA1 may correspond to a portion of the first non-folded area NFA1, and the second display area DA2 may correspond to another portion of the first non-folded area NFA1, the folded area FA, and the second non-folded area NFA2. In other words, the area of ​​the first display area DA1 may be smaller than the area of ​​the second display area DA2.

[0072] In another embodiment, the first display area DA1 may correspond to a portion of the first non-folding area NFA1, the folding area FA, and the second non-folding area NFA2, and the second display area DA2 may correspond to another portion of the second non-folding area NFA2. In other words, the area of ​​the second display area DA2 may be smaller than the area of ​​the first display area DA1.

[0073] like Figure 1BAs shown, when the folded area FA is in a folded state, the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the folded area FA and the second non-folded area NFA2.

[0074] Figure 1A and Figure 1B An example of a foldable display device used as a display device DD is shown, but the concept of the invention is not limited to this example. For example, the concept of the invention can be applied to unfoldable display devices, display devices having one or more folding areas, rollable display devices, etc.

[0075] Figure 2 This is a diagram illustrating the operation of the display device in normal frequency mode. Figure 3 This is a diagram illustrating the operation of the display device in multi-frequency mode.

[0076] First refer to Figure 2 In Normal Frequency Mode (NFM), the driving frequency of the first display area DA1 and the second display area DA2 of the display device DD can be the normal frequency. For example, the predetermined normal frequency can be 60Hz. In Normal Frequency Mode (NFM), for 1 second (sec), images can be displayed on the first display area DA1 and the second display area DA2 of the display device DD from frame 1 F1 to frame 60 F60.

[0077] Reference Figure 3 In multi-frequency mode (MFM), the driving frequency of the first display area DA1 of the display device DD can be a first driving frequency higher than the normal frequency, and the driving frequency of the second display area DA2 can be a second driving frequency lower than the normal frequency. With a normal frequency of 60Hz, examples of the first and second driving frequencies can be given in Table 1 below.

[0078] [Table 1]

[0079] First driving frequency Second driving frequency 80Hz 40Hz 90Hz 30Hz 102Hz 18Hz 110Hz 10Hz 118Hz 2Hz 119Hz 1Hz

[0080] In implementation examples, for instance, in a multi-frequency mode MFM, when the first drive frequency is 80Hz and the second drive frequency is 40Hz (e.g.) Figure 3 As shown in the diagram, for 1 second, a first image IM1 can be displayed on the first display area DA1 of the display device DD at frames 1-80 (F1 to F80), and a second image IM2 can be displayed on the second display area DA2 at odd-numbered frames F1, F3, ..., F79 of the 80 frames. In other words, in multi-frequency mode (MFM), the first image IM1, which appears 80 times per second, can be displayed on the first display area DA1, and the second image IM2, which appears 40 times per second, can be displayed on the second display area DA2.

[0081] Since the first image IM1, which is a video image (i.e., a moving image), is displayed on the first display area DA1 at a first driving frequency of 80Hz, which is higher than the normal frequency of 60Hz, the display quality in the first display area DA1 can be improved. Since the second image IM2, which is a still image, is displayed on the second display area DA2 at a second driving frequency of 40Hz, which is lower than the normal frequency of 60Hz, the power consumption of the display device DD can be reduced.

[0082] Figure 4 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0083] Reference Figure 4 The display device DD may include a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0084] The drive controller 100 can receive image signals RGB and control signals CTRL. The drive controller 100 can convert the data format of the image signals RGB to generate image data signals DATA suitable for the interface specifications with the data drive circuit 200. The drive controller 100 can output scan control signals SCS and data control signals DCS.

[0085] The data drive circuit 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal, and then outputs the data signal to multiple data lines DL1-DLm (described below). The data signal may be an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0086] The voltage generator 300 generates voltages for the operation of the display panel DP. In this embodiment, the voltage generator 300 generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT.

[0087] The display panel DP may include first scan lines SL0-SLn, second scan lines SWL2-SWLn+1, emission control lines EML1-EMLn, data lines DL1-DLm, and pixels PX. The display panel DP may also include a scan drive circuit SD. In an embodiment, the scan drive circuit SD may be placed near a first side of the display panel DP. The first scan lines SL0-SLn, the second scan lines SWL2-SWLn+1, and the emission control lines EML1-EMLn may extend from the scan drive circuit SD along a first direction DR1.

[0088] The first scan lines SL0-SLn, the second scan lines SWL2-SWLn+1, and the transmit control lines EML1-EMLn can be arranged to be spaced apart from each other in the second direction DR2. The data lines DL1-DLm can run from the data drive circuit 200 in the opposite direction to the second direction DR2 (i.e., Figure 4 The middle extends from the top to the bottom and can be arranged to be spaced apart from each other in the first direction DR1.

[0089] Pixels PX can be electrically connected to the first scan lines SL0-SLn, the second scan lines SWL2-SWLn+1, the emission control lines EML1-EMLn, and the data lines DL1-DLm. Each pixel PX can be electrically connected to four scan lines. For example, the pixels in the first row (i.e., the pixels arranged in the first row in the display panel DP) can be connected to scan lines SL0, SL1, SWL2, and EML1, as shown below. Figure 4 As shown in the diagram. Furthermore, the pixels in the second row can be connected to scan lines SL1, SL2, SWL3, and EML2.

[0090] Each of the pixels PX may include a light-emitting diode ED (e.g., see...). Figure 5 ) and the pixel circuit section PXC that controls the light emission operation of the light-emitting diode ED (see, for example, see Figure 5 The pixel circuitry (PXC) may include multiple transistors and at least one capacitor. The scan drive circuitry (SD) may include transistors formed using the same fabrication process as the pixel circuitry (PXC).

[0091] Each pixel PX can receive a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0092] The scan drive circuit SD can receive the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can output a first scan signal to the first scan lines SL0-SLn and a second scan signal to the second scan lines SWL2-SWLn+1. The circuit structure and operation of the scan drive circuit SD will be described in more detail below.

[0093] exist Figure 4 In the example shown, the scan drive circuit SD can output an emission control signal to the emission control lines EML1-EMLn. In some embodiments, the display device DD may also include a separate light-emitting drive circuit for generating the emission control signal. In this case, the scan drive circuit SD can output a first scan signal to be provided to the first scan lines SL0-SLn and a second scan signal to be provided to the second scan lines SWL2-SWLn+1, and the light-emitting drive circuit can output the emission control signal to be provided to the emission control lines EML1-EMLn.

[0094] In one implementation, the drive controller 100 may divide the display panel DP into a first display area DA1 (e.g., see FIG. 1) and a second display area DA2 (e.g., see FIG. 1) based on the image signal RGB, and may output at least one masking signal indicating the start of the second display area DA2. The at least one masking signal may be included in the scan control signal SCS.

[0095] Figure 5 This is an equivalent circuit diagram illustrating a pixel according to an embodiment of the concept of the present invention.

[0096] Figure 5 An equivalent circuit diagram of pixel PXij is shown as an example, with pixel PXij connected to... Figure 4 The data lines DL1-DLm include the i-th data line DL1, the (j-1)-th first scan line SLj-1 and the j-th first scan line SLj in the first scan lines SL0-SLn, the (j+1)-th second scan line SWLj+1 in the second scan lines SWL2-SWLn+1, and the j-th transmit control line EMLj in the transmit control lines EML1-EMLn. Here, i is a natural number equal to or less than m, and j is a natural number equal to or less than n.

[0097] Figure 4 Each of the pixels PX shown can be configured to have the same characteristics as... Figure 5 The pixel PXij has the same circuit structure. In this embodiment, the pixel circuit section PXC of pixel PXij may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Each of the first transistors T1 to the seventh transistor T7 may be a p-type transistor having a low-temperature polycrystalline silicon (“LTPS”) semiconductor layer. However, the concept of the invention is not limited to this example, and in another embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an n-type transistor having a semiconductor layer made of at least one of oxide semiconductor materials. In another embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an n-type transistor, and the other transistors may be p-type transistors. Furthermore, the concept of the invention is not limited to this example. Figure 5 The circuit structure of pixel PXij is shown. Figure 5 The pixel circuit section (PXC) can be a single instance, and the structure of the pixel circuit section (PXC) can be modified in various ways.

[0098] Reference Figure 5The pixel PXij of the display device DD may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. In this embodiment, an example in which a pixel PXij includes a light-emitting diode ED will be described.

[0099] The (j-1)th first scan line SLj-1, the jth first scan line SLj, the (j+1)th second scan line SWLj+1, and the jth transmit control line EMLj can be used to transmit the (j-1)th first scan signal SCj-1, the jth first scan signal SCj, the (j+1)th second scan signal SWj+1, and the jth transmit control signal EMj, respectively. The i-th data line DL1 can be used to transmit the i-th data signal Di. The i-th data signal Di may have the same characteristics as the signal to be input to the display device DD (e.g., see...). Figure 4 The voltage levels corresponding to the corresponding portions of the RGB portion of the image signal. The first driving voltage line VL1, the second driving voltage line VL2, and the third driving voltage line VL3 can be used to transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT, respectively.

[0100] The first transistor T1 may include a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. If the i-th data signal Di is provided to the first transistor T1 via the i-th data line DLi through the switching operation of the second transistor T2, the first transistor T1 can supply a drive current Id to the light-emitting diode ED.

[0101] The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line SLj. The second transistor T2 may be turned on by the j-th first scan signal SCj transmitted through the j-th first scan line SLj, and in this case, the i-th data signal Di of the i-th data line DLi may be applied to the first electrode of the first transistor T1 through the second transistor T2.

[0102] The third transistor T3 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line SLj. The third transistor T3 may be turned on by a j-th first scan signal SCj sent through the j-th first scan line SLj to connect the gate electrode and the second electrode of the first transistor T1 to each other, and in this case, the first transistor T1 may behave like a diode.

[0103] The fourth transistor T4 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 that transmits the initialization voltage VINT, and a gate electrode connected to the (j-1)th first scan line SLj-1. The fourth transistor T4 may be turned on by the (j-1)th first scan signal SCj-1 transmitted via the (j-1)th first scan line SLj-1, and in this case, the initialization voltage VINT may be applied to the gate electrode of the first transistor T1 via the fourth transistor T4. The initialization voltage VINT may be used for an initialization operation to initialize the voltage at the gate electrode of the first transistor T1.

[0104] The fifth transistor T5 may include a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th emitter control line EMLj.

[0105] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the j-th emission control line EMLj.

[0106] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on by the j-th transmit control signal EMj sent through the j-th transmit control line EMLj, and in this case, the first drive voltage ELVDD can be compensated by the first transistor T1 connected as a diode, and then it can be provided to the light-emitting diode ED.

[0107] The seventh transistor T7 may include a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the (j+1)th second scan line SWLj+1.

[0108] As described above, one end of capacitor Cst can be connected to the gate electrode of the first transistor T1, and the other end can be connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The structure of pixel PXij according to the concept of the present invention is not limited to... Figure 5 The structure allows for various modifications to the number of transistors and capacitors constituting the pixel PXij, as well as the connection structure between them.

[0109] Figure 6 It is shown Figure 5 A timing diagram of the operation of pixels in a display device. (Refer to...) Figure 5 and Figure 6 The operation of a display device according to an embodiment of the concept of the present invention is described.

[0110] Reference Figure 5 and Figure 6 During the initialization period in a single frame F, a low-level first scan signal SCj-1 can be provided via the (j-1)th first scan line SLj-1. The fourth transistor T4 can be turned on by the low-level first scan signal SCj-1, and in this case, the initialization voltage VINT can be applied to the gate electrode of the first transistor T1 via the fourth transistor T4 to initialize the first transistor T1.

[0111] Next, during the data programming and compensation cycle, the third transistor T3 can be turned on by a low-level first scan signal SCj supplied through the j-th first scan line SLj. If the third transistor T3 is turned on, the first transistor T1 can function like a diode under forward bias conditions. Additionally, the second transistor T2 can be turned on by the low-level first scan signal SCj. Then, a compensation voltage can be applied to the gate electrode of the first transistor T1, given by the difference between the voltage of the i-th data signal Di supplied from the i-th data line DL1 and the threshold voltage of the first transistor T1. That is, the compensation voltage is equal to the voltage of the i-th data signal Di minus the threshold voltage of the first transistor T1. In other words, the gate voltage applied to the gate electrode of the first transistor T1 can become the compensation voltage.

[0112] A first driving voltage ELVDD and a compensation voltage can be applied to opposite ends of capacitor Cst, and in this case, capacitor Cst can store charge, the amount of which is determined by the voltage difference between opposite ends of capacitor Cst.

[0113] If a low-level second scan signal SWj+1 is applied to the gate electrode of the seventh transistor T7 through the second scan line SWLj+1, then the seventh transistor T7 can be turned on. In this case, a portion of the drive current Id, which serves as the bypass current Ibp, can be discharged through the seventh transistor T7.

[0114] If the light-emitting diode ED emits light through a drive current Id corresponding to the minimum current of the first transistor T1, the black representation properties of pixel PXij may be degraded. However, according to an embodiment of the present invention, the seventh transistor T7 in pixel PXij allows a portion of the minimum current of the first transistor T1 to constitute a bypass current Ibp, which discharges through a current path that does not pass through the light-emitting diode ED (e.g., to the seventh transistor T7). Here, the minimum current of the first transistor T1 refers to the current under the condition that the first transistor T1 is turned off because its gate-source voltage is less than its threshold voltage. Under the condition that the first transistor T1 is turned off, pixel PXij can display a black brightness image when a minimum drive current (e.g., less than 10 picoamperes (pA)) is supplied to the light-emitting diode ED. When pixel PXij is used to display a black image, the amount of the bypass current Ibp can greatly affect the minimum drive current, but when pixel PXij is used to display an image of typical color or white, the amount of the bypass current Ibp can be ignored. According to an embodiment of the present invention, due to the presence of the seventh transistor T7, when the driving current Id is supplied to the light-emitting diode ED to display a black image, the light-emitting current Ied supplied to the light-emitting diode ED can be reduced to a level obtained by subtracting the bypass current Ibp from the driving current Id. Therefore, the light-emitting current Ied can have a minimum current amount sufficient to more effectively display a black image. That is, using the seventh transistor T7, a more accurate black brightness image can be achieved, thereby improving the contrast of pixel PXij. In this embodiment, the bypass signal can be a low-level (j+1)th second scan signal SWj+1, but the present invention is not limited to this example.

[0115] Next, during the emission cycle, the j-th emission control signal EMj supplied from the j-th emission control line EMLj can change from a high level to a low level. During the emission cycle, the fifth transistor T5 and the sixth transistor T6 can be turned on by the low-level j-th emission control signal EMj. In this case, the drive current Id can be generated by the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and the drive current Id can be supplied to the light-emitting diode ED through the sixth transistor T6.

[0116] Figure 7 This is a block diagram illustrating a scan drive circuit SD according to an embodiment of the concept of the present invention. Figure 7 This is a schematic diagram showing only the scan drive circuit SD, and... Figure 7 The light-emitting drive circuit that generates the emission control signal is omitted.

[0117] Reference Figure 7The scan drive circuit SD may include drive stages ST0-STn+1.

[0118] Each of the drive levels ST0-STn+1 can be obtained from Figure 2 The drive controller 100 receives a scan control signal SCS. The scan control signal SCS may include a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a masking signal. The masking signal may include a first masking signal MS1 and a second masking signal MS2. Each of the drive stages ST0-STn+1 can receive a first voltage VGL and a second voltage VGH. Even now, as... Figure 7 As shown, but the first voltage VGL and the second voltage VGH can be provided from the voltage generator 300.

[0119] The first masking signal MS1 and the second masking signal MS2 can be used during multi-frequency mode MFM to select some of the drive stages ST0-STn+1 (i.e., corresponding to...) Figure 1A The first and second scan signals output by the second display area (DA2) are masked to a specific level.

[0120] In this implementation, the driver stage ST0-STn+1 can output a first scan signal SC0-SCn and a second scan signal SW0-SWn+1. The first scan signal SC0-SCn can be provided to... Figure 4 The first scan lines SL0-SLn, and the second scan signals SW2-SWn+1 can be provided to Figure 4 The second scan line is SWL2-SWLn+1.

[0121] Figure 4 The display panel DP may only include the second scan lines SWL2-SWLn+1, but may not include the second scan lines SWL0 and SWL1. Therefore, the second scan signals SW0 and SW1 output from the driver stages ST0 and ST1 may only be provided to the next driver stages ST1 and ST2, and not to the display panel DP.

[0122] Driver stage ST0 can receive the start signal FLM as a carry signal. Each of driver stages ST1-STn+1 has a subordinate connection that receives the second scan signal output from the previous driver stage as a carry signal. For example, driver stage ST1 can receive the second scan signal SW0 output from the previous driver stage ST0 as a carry signal, and driver stage ST2 can receive the second scan signal SW1 output from the previous driver stage ST1 as a carry signal. Figure 7An example is shown where the j-th second scan signal SWj output from the j-th driver stage STj is provided as a carry signal for the (j+1)-th driver stage STj+1, but the concept of the invention is not limited to this example. In another embodiment, the j-th second scan signal SWj output from the j-th driver stage STj can be provided as a carry signal for the (j+k)-th driver stage STj+k, where j and k are natural numbers.

[0123] Figure 8 An example is shown Figure 7 One of the driver levels ST0-STn+1 (e.g., the j-th driver level STj), where j is a positive integer. Figure 7 Each of the driver stages ST0-STn+1 can be configured to have the same circuit structure as the j-th driver stage STj. In the following text, the j-th driver stage STj may be referred to as driver stage STj.

[0124] Reference Figure 8 The driver stage STj may include a driver circuit DC, a masking circuit, first input terminals IN1 to fifth input terminals IN5, a first voltage terminal V1 and a second voltage terminal V2, and a first output terminal OUT1 and a second output terminal OUT2. The masking circuit may include a first masking circuit MSC1 and a second masking circuit MSC2.

[0125] The DC drive circuit may include transistors PT1-PT7 and capacitors PC1 and PC2.

[0126] The DC drive circuit can receive the first clock signal CLK1, the second clock signal CLK2, and the (j-1)th carry signal CRj-1 through the first input terminal IN1 to the third input terminal IN3, respectively. The DC drive circuit can receive the first voltage VGL and the second voltage VGH through the first voltage terminal V1 and the second voltage terminal V2, respectively. The DC drive circuit can output the j-th first scan signal SCj and the j-th second scan signal SWj through the first output terminal OUT1 and the second output terminal OUT2, respectively. The j-th second scan signal SWj can be provided as the j-th carry signal CRj to the next drive stage STj+1. The (j-1)th carry signal CRj-1 received through the third input terminal IN3 can be used as the carry signal from the (j-1)th carry signal CRj-1. Figure 7 The second scan signal SWj-1, output by the previous drive stage STj-1, is shown as (j-1)th. Figure 7 The carry signal of the drive stage ST0 can be the start signal FLM.

[0127] for Figure 7In some of the driver stages ST0-STn+1 shown (e.g., odd-numbered driver stages), the first input terminal IN1 of each of them can receive the first clock signal CLK1, and the second input terminal IN2 of each of them can receive the second clock signal CLK2. Additionally, for some of the driver stages ST0-STn+1 (e.g., even-numbered driver stages), the first input terminal IN1 of each of them can receive the second clock signal CLK2, and the second input terminal IN2 of each of them can receive the first clock signal CLK1.

[0128] Transistor PT1 may be connected between the third input terminal IN3 and the first node N1, and may include a gate electrode connected to the first input terminal IN1. Transistor PT2 may be connected between the second voltage terminal V2 and the third node N3, and may include a gate electrode connected to the second node N2. Transistor PT3 may be connected between the third node N3 and the first node N1, and may include a gate electrode connected to the second input terminal IN2.

[0129] Transistor PT4 may be connected between the second node N2 and the first input terminal IN1, and may include a gate electrode connected to the first node N1. Transistor PT5 may be connected between the second node N2 and the first voltage terminal V1, and may include a gate electrode connected to the first input terminal IN1. Transistor PT6 may be connected between the second voltage terminal V2 and the second output terminal OUT2, and may include a gate electrode connected to the second node N2. Transistor PT7 may be connected between the second output terminal OUT2 and the second input terminal IN2, and may include a gate electrode connected to the first node N1.

[0130] Capacitor PC1 can be connected between the first node N1 and the second output terminal OUT2. Capacitor PC2 can be connected between the second voltage terminal V2 and the second node N2.

[0131] The first masking circuit MSC1 may include a first masking transistor MT1. The first masking circuit MSC1 may stop the output of the j-th first scan signal SCj in response to a first masking signal MS1 received via the fourth input terminal IN4. The first masking transistor MT1 may be connected between the second voltage terminal V2 and the first output terminal OUT1, and may include a gate electrode connected to the fourth input terminal IN4.

[0132] The second masking circuit MSC2 may include a second masking transistor MT2. The second masking transistor MT2 may be connected between the first output terminal OUT1 and the second output terminal OUT2 and may include a gate electrode connected to the fifth input terminal IN5.

[0133] Figure 9 This is an example shown Figure 7 Timing diagrams of the operations of the (j-1)th drive stage STj-1, the jth drive stage STj, and the (j+1)th drive stage STj+1 in the scan drive circuit SD.

[0134] Reference Figure 7 , Figure 8 and Figure 9 The first clock signal CLK1 and the second clock signal CLK2 can be signals with different frequencies to each other and that change to an active level (e.g., low level) in different horizontal periods H. The horizontal period H can be the display panel DP (e.g., see [link]). Figure 4 The time interval at which pixels PX in the same row on the first direction DR1 are driven. Horizontal periods Hj-4, Hj-3, Hj-2, Hj-1, Hj, and Hj+1 are instances of horizontal period H.

[0135] If the first masking signal MS1 is at the second level (e.g., high level), the first masking transistor MT1 can be turned off, and therefore the second voltage terminal V2 and the first output terminal OUT1 can remain disconnected from each other. If the second masking signal MS2 is at the first level (e.g., low level), the second masking transistor MT2 can be turned on, and therefore the first output terminal OUT1 and the second output terminal OUT2 can remain electrically connected to each other.

[0136] The (j-1)th driver level STj-1 can be operated as follows:

[0137] The (j-1)th driver stage STj-1 can receive the second clock signal CLK2 through the first input terminal IN1, and can receive the first clock signal CLK1 through the second input terminal IN2.

[0138] In the (j-2)th horizontal period Hj-2, if the second clock signal CLK2 received through the first input terminal IN1 is low, transistor PT1 in the DC drive circuit can be turned on. In this case, the low-level (j-2)th carry signal CRj-2 can be sent to the first node N1 through transistor PT1. If the second clock signal CLK2 is low, transistor PT5 can be turned on, and therefore, the second node N2 can discharge to the first voltage VGL. If the second node N2 is low, transistor PT6 can be turned on, and the second output terminal OUT2 can output the high-level (j-1)th second scan signal SWj-1. In addition, if the first node N1 is low, transistor PT7 can be turned on, and the second output terminal OUT2 can be kept high by the first clock signal CLK1 received through the second input terminal IN2.

[0139] In the (j-1)th horizontal period Hj-1, if the second clock signal CLK2 is high, transistor PT5 can be turned off, and the second node N2 can be changed to a high level by the transistor PT4, which is in the on state, thereby turning off transistor PT6. If the first clock signal CLK1 received through the second input terminal IN2 is low, the first node N1 can be changed to a low level by the capacitor PC1, thereby turning on transistor PT7. In this case, the second output terminal OUT2 can output a low-level (j-1)th second scan signal SWj-1. Since the second masking transistor MT2 is in the on state due to the low-level second masking signal MS2, the (j-1)th first scan signal SCj-1 can be activated to a low level. That is, in the (j-1)th horizontal period Hj-1, the (j-1)th driver stage STj-1 can output a low-level (j-1)th first scan signal SCj-1 and a low-level (j-1)th second scan signal SWj-1.

[0140] In the j-th horizontal period Hj, if the first masking signal MS1 changes from high level to low level and the second masking signal MS2 changes from low level to high level, then the first masking transistor MT1 in the first masking circuit MSC1 can be turned on and the second masking transistor MT2 in the second masking circuit MSC2 can be turned off.

[0141] The j-th driver level STj can be operated as follows:

[0142] The j-th driver stage STj can receive the first clock signal CLK1 through the first input terminal IN1, and can receive the second clock signal CLK2 through the second input terminal IN2.

[0143] In the (j-1)th horizontal period Hj-1, if the first clock signal CLK1 is low, transistor PT1 is turned on. In this case, the low-level (j-1)th carry signal CRj-1 (i.e., the (j-1)th second scan signal SWj-1) can be sent to the first node N1 through transistor PT1. If the first clock signal CLK1 is low, transistor PT5 is turned on, and therefore, the second node N2 can discharge to the first voltage VGL. If the second node N2 is low, transistor PT6 is turned on, and in this case, the second output terminal OUT2 can output the high-level jth second scan signal SWj. Alternatively, if the first node N1 is low, transistor PT7 is turned on, and in this case, the second output terminal OUT2 can be kept high by the second clock signal CLK2 received through the second input terminal IN2.

[0144] In the j-th horizontal period Hj, if the first clock signal CLK1 is high, transistor PT5 can be turned off, and the second node N2 can be changed to a high level by transistor PT4, which is in the on state, thereby turning off transistor PT6. If the second clock signal CLK2 received through the second input terminal IN2 is low, the first node N1 can be changed to a low level by capacitor PC1, thereby turning on transistor PT7. In this case, the second output terminal OUT2 can output a low-level j-th second scan signal SWj. Here, since the second masking transistor MT2 is turned off due to the high-level second masking signal MS2, and the first masking transistor MT1 is turned on due to the low-level first masking signal MS1, the j-th first scan signal SCj can remain high. That is, in the j-th horizontal period Hj, the j-th driver stage STj can output a high-level j-th first scan signal SCj and a low-level j-th second scan signal SWj.

[0145] The (j+1)th driver level STj+1 can be operated as follows:

[0146] The (j+1)th driver stage STj+1 can receive the second clock signal CLK2 through the first input terminal IN1, and can receive the first clock signal CLK1 through the second input terminal IN2.

[0147] In the j-th horizontal period Hj, if the second clock signal CLK2 received through the first input terminal IN1 is low, transistor PT1 in the DC drive circuit can be turned on. In this case, the low-level j-th carry signal CRj can be sent to the first node N1 through transistor PT1. If the second clock signal CLK2 is low, transistor PT5 can be turned on, and therefore, the second node N2 can discharge to the first voltage VGL. If the second node N2 is low, transistor PT6 can be turned on, and the second output terminal OUT2 can output the high-level (j+1)-th second scan signal SWj+1. In addition, if the first node N1 is low, transistor PT7 can be turned on, and the second output terminal OUT2 can be kept high by the first clock signal CLK1 received through the second input terminal IN2.

[0148] In the (j+1)th horizontal period Hj+1, if the second clock signal CLK2 is low, transistor PT5 can be turned on. The second node N2 can be held low by the on-state transistor PT5, and transistor PT6 can be turned on. Therefore, the (j+1)th second scan signal SWj+1 can be output at a high level. Since the first masking transistor MT1 is turned on due to the low-level first masking signal MS1, the (j+1)th first scan signal SCj+1 can be held high. In other words, the (j+1)th driver stage STj+1 can output the high-level (j+1)th first scan signal SCj+1 and the high-level (j+1)th second scan signal SWj+1.

[0149] Assumption Figure 1A The first display area DA1 includes pixels from row 0 to row (j-1), and it is assumed that the second display area DA2 includes pixels from row j to row n. In this case, during the j-th horizontal period Hj, the j-th first scan signal SCj can be masked to a high level by changing the first masking signal MS1 from high to low and the second masking signal MS2 from low to high. Subsequently, by keeping the first clock signal CLK1 and the second clock signal CLK2 low, the (j+1)-th second scan signal SWj+1 can be masked to a high level.

[0150] Reference Figure 5 and Figure 9 The pixel PXij in the j-th row can be connected to the (j-1)-th first scan line SLj-1, the j-th first scan line SLj, and the (j+1)-th second scan line SWLj+1. When the j-th first scan signal SCj provided to the pixel PXij in the j-th row corresponding to the second display area DA2 is masked to a high level, the j-th second scan signal SWj should be output normally so that the image can be displayed normally on the pixel PXij-1 in the (j-1)-th row corresponding to the first display area DA1.

[0151] Figure 10 This is an example illustrating the effect of switching from the normal frequency mode. Figure 4 The drive controller 100 provides signals to the scan drive circuit SD and image data signals DATA from the drive controller 100 to the data drive circuit 200.

[0152] Reference Figure 4 , Figure 7 and Figure 10In normal frequency mode NFM, the start signal FLM can be activated low 60 times per second (assuming a normal frequency of 60Hz). That is, the start signal FLM can be activated low in every frame (e.g., each from frame 1 F1 to frame 60 F60). During normal frequency mode NFM, the first masking signal MS1 can remain high, and the second masking signal MS2 can remain low. In normal frequency mode NFM, the duration of a single frame can be a first time (e.g., 16.67 milliseconds (ms)).

[0153] The drive controller 100 can sequentially provide image data signals DATA, including data signals DS1 to DS60, to the data drive circuit 200. Here, data signals DS1 to DS60 can correspond to image data signals DATA at frames 1 to 60 respectively.

[0154] Figures 11A to 11C This is an example illustrating how to use multi-frequency mode from Figure 4 The drive controller 100 provides signals to the scan drive circuit SD and image data signals DATA from the drive controller 100 to the data drive circuit 200.

[0155] Figure 11A This is an example illustrating how, in multi-frequency mode MFM, the first display area DA1 (for example, see...) Figure 3 The first driving frequency is 80Hz and the second display area DA2 (see, for example, see...) Figure 3 When the second driving frequency is 40Hz, it provides to Figure 4 Timing diagram of the signals and image data signals DATA of the scan drive circuit SD and the data drive circuit 200.

[0156] Reference Figure 4 , Figure 7 and Figure 11A In Multi-Frequency Mode (MFM), the Start Signal FLM can be activated low 80 times per second. That is, the Start Signal FLM can be activated low in every frame (e.g., in each of frames 1 (F1) to 80 (F80)).

[0157] When the first display area DA1 (for example, see...) Figure 1A The first driving frequency is 80Hz and the second display area DA2 (see, for example, see...) Figure 1AWhen the second driving frequency is 40Hz, the duration of each of the odd-numbered frames F1, F3, F5, ..., F79 can be different from the duration of each of the even-numbered frames F2, F4, F6, ..., F80. For example, the duration of each of the odd-numbered frames F1, F3, F5, ..., F79 can be 16.67ms, and the duration of each of the even-numbered frames F2, F4, F6, ..., F80 can be 8.34ms. In other words, the duration of the first frame in the multi-frequency mode MFM can be the same as the duration of the first frame in the normal frequency mode NFM (e.g., 16.67ms), and the duration of the second frame after the first frame can be a second time shorter than the first time.

[0158] If as referenced Figure 3 In the multi-frequency mode (MFM), the first driving frequency and the second driving frequency are 80Hz and 40Hz, respectively. Therefore, for one second, the first image IM1 can be displayed on the first display area DA1 of the display device DD from frame 1 (F1) to frame 80 (F80), and the second image IM2 can be displayed on the second display area DA2 at odd-numbered frames F1, F3, ..., F79 within the 80 frames. In other words, the second image IM2 may not be displayed at even-numbered frames F2, F4, ..., F80.

[0159] Assuming that the k-th driver stage STk in the driver stages ST0-STn+1 of the scan driver circuit SD corresponds to the starting position of the second display area DA2, the first masking signal MS1 can be changed to a low level, and the second masking signal MS2 can be changed to a high level, so as to mask (i.e., block) the first scan signal SCk-SCn and the second scan signal SWk+1-SWn+1 output from the driver stages STk-STn+1 at even frames F2, F4, ..., F80 of the multi-frequency mode MFM. The driver stages STk-STn+1 can respond to the low-level first masking signal MS1 and the high-level second masking signal MS2 by not activating the first scan signal SCk-SCn and the second scan signal SWk+1-SWn+1 to a low level. When an even-numbered frame (e.g., F2) ends and the next odd-numbered frame (e.g., F3) begins, the first masking signal MS1 and the second masking signal MS2 can be changed to high and low levels respectively to prepare for the new frame.

[0160] Figure 11B This is an example illustrating how, in multi-frequency mode MFM, the first display area DA1 (for example, see...) Figure 1A The first driving frequency is 80Hz and the second display area DA2 (see, for example, see...) Figure 1A When the second driving frequency is 40Hz, from Figure 4The drive controller 100 provides timing diagrams of signals and image data signals DATA to the scan drive circuit SD and the data drive circuit 200.

[0161] Reference Figure 4 , Figure 7 and Figure 11B Even in multi-frequency mode MFM, the frequency of the image signal RGB provided to the drive controller 100 from the outside can be 60Hz. In other words, 60 frames of image signal RGB per second can be provided to the drive controller 100. When the drive frequency of the first display area DA1 is changed to a first drive frequency of 80Hz, which is higher than the normal frequency of 60Hz, the drive controller 100 should further generate 20 frames of image data signal DATA per second. In this case, the drive controller 100 can output the image data signal used for the previous frame as the image data signal used for the current frame.

[0162] In one implementation, for example, the drive controller 100 may output a data signal DS1 as an image data signal DATA at the first frame F1, and may repeatedly output a data signal DS2 as an image data signal DATA at the second frame F2 and the third frame F3. Since the drive controller 100 outputs the same data signal DS2 twice as the image data signal DATA, the brightness properties of the image displayed on the first display area DA1 of the display device DD can be improved. Because the refresh cycle of the first display area DA1, which displays video images (i.e., moving images), is shortened, the display quality can be improved.

[0163] Figure 11C This is an example illustrating how, in multi-frequency mode MFM, the first display area DA1 (for example, see...) Figure 1A The first driving frequency is 119Hz and the second display area DA2 (see, for example, see...) Figure 1A When the second driving frequency is 1Hz, from Figure 4 The drive controller 100 provides timing diagrams of signals and image data signals DATA to the scan drive circuit SD and the data drive circuit 200.

[0164] Reference Figure 4 , Figure 7 and Figure 11C In Multi-Frequency Mode (MFM), the Start Signal FLM can be activated low 119 times per second. That is, the Start Signal FLM can be activated low in every frame (e.g., in each of frames 1 through 119).

[0165] When the first display area DA1 (for example, see...) Figure 1A The first driving frequency is 119Hz and the second display area DA2 (see, for example, see...) Figure 1AWhen the second driving frequency is 1Hz, the duration of the first frame F1 can be different from the duration of each of the remaining frames F2-F119. For example, the duration of the first frame F1 can be 16.67ms, and the duration of each of the second frame F2 to the 119th frame F119 can be 8.34ms.

[0166] Assuming that the k-th driver stage STk in the driver stages ST0-STn+1 of the scan driver circuit SD corresponds to the starting position of the second display area DA2, the first masking signal MS1 can be changed to a low level, and the second masking signal MS2 can be changed to a high level, so as to mask (i.e., block) the first scan signal SCk-SCn and the second scan signal SWk+1-SWn+1 output from the driver stages STk-STn+1 at frames F2-F119 of the multi-frequency mode MFM. The driver stages STk-STn+1 can respond to the low-level first masking signal MS1 and the high-level second masking signal MS2 by holding the first scan signal SCk-SCn and the second scan signal SWk+1-SWn+1 at a high level. When the second frame F2 is completed and the next third frame F3 begins, the first masking signal MS1 and the second masking signal MS2 can be changed to a high level and a low level, respectively, to prepare for the new frame.

[0167] Figure 12 This is an example diagram showing the first scan signal output from the scan drive circuit SD in multi-frequency mode.

[0168] Figure 12 An example is shown in multi-frequency mode MFM, when the first display area DA1 (e.g., see...) Figure 1A The first driving frequency is 80Hz and the second display area DA2 (see, for example, see...) Figure 1A When the second driving frequency is 40Hz, from Figure 7 The first scan signal SC0-SC3840 is output by the scan drive circuit SD.

[0169] Assumption Figure 1A The first display area DA1 includes pixels from row 0 to row 1920, and it is assumed that the second display area DA2 includes pixels from row 1921 to row 3840.

[0170] Reference Figure 4 , Figure 7 and Figure 12 In Multi-Frequency Mode (MFM), the Start Signal FLM can be activated low 80 times per second. That is, the Start Signal FLM can be activated low in every frame (e.g., in each of frames 1 (F1) to 80 (F80)).

[0171] When the first display area DA1 (for example, see...) Figure 1AThe first driving frequency is 80Hz and the second display area DA2 (see, for example, see...) Figure 1A When the second driving frequency is 40Hz, the duration of each of the odd-numbered frames F1, F3, F5, ..., F79 can be 16.67ms, and the duration of each of the even-numbered frames F2, F4, F6, ..., F80 can be 8.34ms.

[0172] At odd frames F1, F3, F5, ..., F79 in the multi-frequency mode MFM, the drive stages ST0-STn in the scan drive circuit SD can sequentially output the first scan signals SC0-SCn.

[0173] Assuming that the 1921st driver stage ST1921 in the driver stages ST0-ST3840 of the scan driver circuit SD corresponds to the starting position of the second display area DA2, at the even-numbered frames F2, F4, F6, ..., F80 of the multi-frequency mode MFM, the driver stages ST0-ST1920 can sequentially activate the first scan signals SC0-SC1920 to a low level, and the driver stages ST1921-ST3840 can keep the first scan signals SC1921-SC3840 at a high level.

[0174] Similarly, in the driver stages ST0-ST3840 of the scan driver circuit SD, driver stages ST0-ST1920 corresponding to the first display area DA1 can operate sequentially in each frame to display the first image IM1 on the first display area DA1. In the driver stages ST0-ST3840 of the scan driver circuit SD, driver stages ST1921-ST3840 corresponding to the second display area DA2 can operate sequentially only in some frames (e.g., odd-numbered frames F1, F3, F5, ..., F79) to display the second image IM2 on the second display area DA2. Since driver stages ST1921-ST3840 in the driver stages ST0-ST3840 of the scan driver circuit SD do not operate in some frames (e.g., even-numbered frames F2, F4, F6, ..., F80), power consumption can be reduced.

[0175] In addition, since the first display area DA1 is driven at a higher frequency (e.g., 80Hz) than the normal frequency (e.g., 60Hz), the display quality can be improved by displaying the first image IM1 as a video image (i.e., a moving image).

[0176] Figure 13 This is an example illustrating how to use a multi-frequency mode MFM. Figure 4 The drive controller 100 provides to Figure 7 A diagram of the start signal of the scan drive circuit SD.

[0177] When the normal frequency is 60Hz, the duration of the full-frame FF is 16.67ms, and the duration of the half-frame HF is 8.34ms. The full-frame FF can be the first display area DA1 and the second display area DA2 (see, for example, [reference]). Figure 1A Both are driven frames, and half-frame HF can be the frame in between where only the first display area DA1 is driven.

[0178] The period FT1 of the start signal FLM1 can include a full frame FF and a half frame HF, and can have a duration of 25.0ms.

[0179] The first driving frequency DF1 of the first display area DA1 can be calculated using the following formula 1.

[0180] [Formula 1]

[0181] DF1=1000ms / ((FFT+HFT) / (1+HFN))

[0182] The second driving frequency DF2 of the second display area DA2 can be calculated using the following formula 2.

[0183] [Formula 2]

[0184] DF2 = 1000ms / (FFT + HFT)

[0185] In Formulas 1 and 2, FFT, HFT, and HFN represent the duration of the full-frame FF, the duration of the half-frame HF (i.e., the duration of all included half-frames), and the number of half-frame HFs within the period FT1, respectively.

[0186] Since the normal frequency is 60Hz, the duration of the full frame FF within the period FT1 of the start signal FLM1 is 16.67ms, the duration of the half frame HF is 8.34ms, and the number of half frames HF is 1, so the first driving frequency DF1 of the first display area DA1 is 80Hz (i.e., 1000ms / ((16.67ms+8.34ms) / (1+1))), and the second driving frequency DF2 of the second display area DA2 is 40Hz (i.e., 1000ms / (16.67ms+8.34ms)).

[0187] The period FT2 of the start signal FLM2 may include a full frame FF and two half frames HF1 and HF2, and may have a duration of 33.3ms.

[0188] Since the normal frequency is 60Hz, the duration of the full frame FF within the period FT2 of the start signal FLM2 is 16.67ms, the duration of the sum of half frames HF1 and HF2 is 16.68ms, and the number of half frames HF1 and HF2 is 2. Therefore, the first driving frequency DF1 of the first display area DA1 is 90Hz (i.e., 1000ms / ((16.67ms+16.68ms) / (1+2))), and the second driving frequency DF2 of the second display area DA2 is 30Hz (i.e., 1000ms / (16.67ms+16.68ms)).

[0189] The period FT3 of the start signal FLM3 can include a full frame FF and 118 half frames HF1, HF2, ..., HF118, and can have a duration of 1000ms.

[0190] Since the normal frequency is 60Hz, the duration of the full frame FF within the period FT3 of the start signal FLM3 is 16.67ms, the duration of the sum of half frames HF1, HF2, ..., HF118 is 983.32ms, and the number of half frames HF1, HF2, ..., HF118 is 118. Therefore, the first driving frequency DF1 of the first display area DA1 is 119Hz (i.e., 1000ms / (16.67ms+983.32ms) / (1+118))), and the second driving frequency DF2 of the second display area DA2 is 1Hz (i.e., 1000ms / (16.67ms+983.32ms)).

[0191] Table 2 below shows how the first drive frequency DF1 of the first display area DA1 and the second drive frequency DF2 of the second display area DA2 change with the number of half-frame HFs within the period of the start signal FLM when the normal frequency is 60Hz and the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:1. The results in Table 2 are obtained under the assumption that the duration of the full frame FF is 16.66ms and the duration of each half-frame HF is 8.33ms when the normal frequency is "60Hz".

[0192] [Table 2]

[0193]

[0194] Table 3 below shows how the first drive frequency DF1 of the first display area DA1 and the second drive frequency DF2 of the second display area DA2 change with the number of half-frame HFs within the period of the start signal FLM when the normal frequency is 120Hz and the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:1. The results in Table 3 are obtained under the assumption that the duration of the full frame FF is 8.34ms when the normal frequency is "120Hz" and the duration of each half-frame HF is 4.17ms.

[0195] [Table 3]

[0196] Number of half-frame HF First driving frequency DF1 Second driving frequency DF2 1 159.87Hz 79.94Hz 2 179.86Hz 59.95Hz 3 191.85Hz 47.96Hz 10 219.82Hz 19.98Hz 20 228.91Hz 10.9Hz 100 237.46Hz 2.35Hz 239 238.81Hz 1.0Hz

[0197] Table 4 below shows how the first drive frequency DF1 of the first display area DA1 and the second drive frequency DF2 of the second display area DA2 vary with the number of half-frame HFs within the period of the start signal FLM when the normal frequency is 144Hz and the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:1. The results in Table 4 are obtained under the assumption that the duration of the full frame FF is 6.94ms and the duration of each half-frame HF is 3.47ms when the normal frequency is "144Hz".

[0198] [Table 4]

[0199] Number of half-frame HF First driving frequency DF1 Second driving frequency DF2 1 192.12Hz 96.06Hz 2 216.14Hz 72.05Hz 3 230.55Hz 57.64Hz 10 264.17Hz 24.02Hz 20 275.09Hz 13.10Hz 100 285.36Hz 2.83Hz 287 287.19Hz 1.0Hz

[0200] Figure 14 This is a top plan view showing a display device DD2 according to an embodiment of the concept of the present invention.

[0201] Reference Figure 14 The display surface of the display device DD2 may be parallel to the surface defined by the first direction DR1 and the second direction DR2. The display surface of the display device DD2 may include multiple different areas. The display surface may include a display area DA displaying the first image IM11 and the second image IM12, and a non-display area NDA adjacent to the display area DA. As an example, the display area DA may be rectangular or square. The non-display area NDA may surround the display area DA. In addition, although not shown, the display device DD2 may include a partially bent shape. In this case, the area in the display area DA may have a bent or circular shape.

[0202] The display area DA of the display device DD2 may include a first display area DA11 and a second display area DA12. In a particular application, the first display area DA11 may be used to display a first image IM11, and the second display area DA12 may be used to display a second image IM12. In an embodiment, the first image IM11 may be a video image (i.e., a moving image), and the second image IM12 may be a still image or text image that does not change over a relatively long period of time compared to the moving image.

[0203] like Figure 14 As shown, the area of ​​the first display area DA11, which displays the first image IM11 or a video image, may be smaller than the area of ​​the second display area DA12, which displays the second image IM12 or a still image. In this case, compared to the case where the first display area DA11 and the second display area DA12 have the same area, the first display area DA11 can operate at an increased driving frequency, and the second display area DA12 can operate at a decreased driving frequency.

[0204] Table 5 below shows how the first drive frequency DF1 of the first display area DA1 and the second drive frequency DF2 of the second display area DA2 vary with the number of half-frame HFs within the period of the start signal FLM when the normal frequency is 60Hz and the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:2. The results in Table 5 are obtained under the assumption that the duration of the full frame FF is 16.66ms and the duration of each half-frame HF is 5.55ms when the normal frequency is 60Hz. When the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:2, the duration of each half-frame HF can be 1 / 3 of the duration of the full frame FF.

[0205] [Table 5]

[0206]

[0207]

[0208] Table 6 below shows how the first drive frequency DF1 of the first display area DA1 and the second drive frequency DF2 of the second display area DA2 vary with the number of half-frame HFs within the period of the start signal FLM when the normal frequency is 60Hz and the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:3. The results in Table 6 are obtained under the assumption that the duration of the full frame FF is 16.66ms and the duration of each half-frame HF is 4.17ms when the normal frequency is 60Hz. When the length ratio of the first display area DA1 to the second display area DA2 in the second direction DR2 is 1:3, the duration of each half-frame HF can be 1 / 4 of the duration of the full frame FF.

[0209] [Table 6]

[0210]

[0211] Figure 15 This is a top plan view showing a display device DD3 according to an embodiment of the concept of the present invention.

[0212] Reference Figure 15 The display surface of the display device DD3 may be parallel to the surface defined by the first direction DR1 and the second direction DR2. The display surface of the display device DD3 may include multiple different areas. The display surface may include a display area DA displaying the first image IM21 and the second image IM22, and a non-display area NDA adjacent to the display area DA.

[0213] The display area DA of the display device DD3 may include a first display area DA21 and a second display area DA22. In a particular application, a first image IM21 may be displayed on the first display area DA21, and a second image IM22 may be displayed on the second display area DA22. For example, the first image IM21 may be a video image (i.e., a moving image), and the second image IM22 may be a still image or text image that has not changed over a relatively long period of time compared to the moving image.

[0214] like Figure 15 As shown, the area of ​​the first display area DA21 displaying the first image IM21 or a video image can be larger than the area of ​​the second display area DA22 displaying the second image IM22 or a still image. In this case, compared to the case where the first display area DA21 and the second display area DA22 have the same area, the first display area DA21 can operate at a lower drive frequency, and the second display area DA22 can operate at a higher drive frequency.

[0215] like Figure 14 and Figure 15As shown, the driving frequency of the first display area DA11 or DA21 and the driving frequency of the second display area DA12 or DA22 can be determined by considering the ratio between the area displaying video images (i.e., moving images) and the area displaying still images.

[0216] Figure 7 The scan drive circuit SD shown can sequentially output a first scan signal from SC0 to SCn, and sequentially output a second scan signal from SW0 to SWn+1. In another embodiment, if the scan drive circuit SD can sequentially output a first scan signal from SCn to SC1, and can sequentially output a second scan signal from SWn+1 to SW0, then when a video image (i.e., a moving image) is displayed on the second display areas DA2, DA12, and DA22, Figure 1A Display device DD, Figure 14 The display device DD2 and Figure 15 The display device DD3 can operate in multi-frequency mode. In this mode, the first display areas DA1, DA11, and DA21 can be driven by a second driving frequency lower than the normal frequency, while the second display areas DA2, DA12, and DA22 can be driven by a first driving frequency higher than the normal frequency.

[0217] According to an embodiment of the present invention, a display device may include a first display area and a second display area. The first display area is used to display video images (i.e., moving images), and the second display area is used to display still images and operates at a drive frequency different from that of the first display area. For example, the first display area displaying video images can be operated at a drive frequency higher than the normal frequency, and in this case, the display quality of the display device can be improved. Furthermore, the second display area displaying still images can be operated at a drive frequency lower than the normal frequency, and in this case, the power consumption of the display device can be reduced.

[0218] While exemplary embodiments of the concepts of the present invention have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels connected to a plurality of data lines and a plurality of scan lines; Data driving circuit, which drives the plurality of data lines; A scan driving circuit that drives the plurality of scan lines; as well as A drive controller receives image signals and control signals, and controls the data drive circuit and the scan drive circuit to display images on the display panel. The drive controller divides the display panel into a first display area and a second display area based on the image signal, and outputs a start signal indicating the start of a frame and a masking signal indicating the start of the second display area. The first frame has a first duration, and the second frame following the first frame has a second duration, and The scan driving circuit sequentially drives the plurality of scan lines in sync with the start signal, and stops driving the scan line corresponding to the second display area in response to the masking signal. The scan driving circuit includes multiple driving stages, each of which drives a corresponding scan line among the multiple scan lines. Each of the plurality of driver levels includes: A driving circuit, which, in response to a clock signal and a carry signal from the driving controller, outputs a first scan signal to a first output terminal; and A masking circuit, in response to a masking signal, prevents the driving circuit from outputting the first scan signal. The driving circuit also responds to the clock signal and the carry signal by outputting a second scan signal to the second output terminal. The masking signals include a first masking signal and a second masking signal, and The masking circuit includes: A first masking circuit, which responds to the first masking signal and is electrically connected to a first voltage terminal and a first output terminal; and The second masking circuit is electrically connected to the first output terminal and the second output terminal in response to the second masking signal.

2. The display device according to claim 1, wherein, During the first mode, the second duration of the second frame is shorter than the first duration of the first frame.

3. The display device according to claim 2, wherein, During a second mode that differs from the first mode, the first duration of the first frame is equal to the second duration of the second frame.

4. The display device according to claim 3, wherein, The first duration of the first frame during the first mode is equal to the first duration of the first frame during the second mode.

5. The display device according to claim 3, wherein, During the second mode, the first display area and the second display area are driven at a predetermined frequency, and During the first mode, the first display area is driven at a first driving frequency higher than the predetermined frequency, and the second display area is driven at a second driving frequency lower than the predetermined frequency.

6. The display device according to claim 1, wherein, The drive controller provides image data signals corresponding to the first display area and the second display area to the data drive circuit during the first frame of the first mode, and provides image data signals corresponding to the first display area but not to the second display area to the data drive circuit during the second frame of the first mode.

7. The display device according to claim 6, wherein, During each frame of a second mode, which is different from the first mode, the drive controller provides image data signals corresponding to the first display area and the second display area to the data drive circuit.

8. The display device according to claim 1, wherein, The first driver stage among the plurality of driver stages receives the start signal as the carry signal.

9. The display device according to claim 1, wherein, The second scan signal output from the j-th drive stage of the plurality of drive stages is provided as the carry signal for the (j+k)-th drive stage, where j and k are natural numbers.

10. The display device according to claim 1, wherein, During the first mode, the first masking circuit, in response to the first masking signal of the first level, electrically connects the first voltage terminal to the first output terminal, and During the first mode, the second masking circuit disconnects the electrical connection between the first output terminal and the second output terminal in response to a second masking signal of a second level different from the first level.

11. A display device, comprising: The display panel includes a plurality of pixels connected to a plurality of data lines and a plurality of scan lines; Data driving circuit, which drives the plurality of data lines; A scan driving circuit that drives the plurality of scan lines; as well as A drive controller receives image signals and control signals, and controls the data drive circuit and the scan drive circuit to display images on the display panel. The drive controller divides the display panel into a first display area and a second display area based on the image signal. During the first frame, it provides image data signals corresponding to the first display area and the second display area to the data drive circuit. During the second frame following the first frame, it provides image data signals corresponding to the first display area but not the second display area to the data drive circuit. The drive controller outputs a start signal indicating the start of a frame and a masking signal indicating the start of the second display area. The scan driving circuit sequentially drives the plurality of scan lines in sync with the start signal, and stops driving the scan line corresponding to the second display area in response to the masking signal. The scan driving circuit includes multiple driving stages, each of which drives a corresponding scan line among the multiple scan lines. Each of the plurality of driver levels includes: A driving circuit, which, in response to a clock signal and a carry signal from the driving controller, outputs a first scan signal to a first output terminal; and A masking circuit, in response to a masking signal, prevents the driving circuit from outputting the first scan signal. The driving circuit also responds to the clock signal and the carry signal by outputting a second scan signal to the second output terminal. The masking signals include a first masking signal and a second masking signal, and The masking circuit includes: A first masking circuit, which responds to the first masking signal and is electrically connected to a first voltage terminal and a first output terminal; and The second masking circuit is electrically connected to the first output terminal and the second output terminal in response to the second masking signal.

Images