Semiconductor device and method of manufacturing integrated circuit

Abstract

A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed proximate to the at least one memory cell and includes a plurality of fins. The plurality of fins is divided into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method of fabricating an integrated circuit is also disclosed.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing integrated circuits. Background Technology

[0002] Static random access memory (SRAM), which contains bit cells and peripheral cells, is typically implemented using semiconductor devices. One way to represent a semiconductor device is using a planar diagram known as a layout diagram with a grid. The layout diagram is generated within the context of design rules. For example, for peripheral cells in the layout diagram, the arrangement of each fin-shaped active region is constrained by the corresponding cell height, and this arrangement also constrains the density of the active regions and the area ratio of the layout diagram. Summary of the Invention

[0003] According to one aspect of the present invention, a semiconductor device is provided, comprising: at least one memory cell; and at least one logic cell disposed adjacent to the at least one memory cell, including: a plurality of fins, wherein the plurality of fins are divided into a plurality of fin groups for forming transistors, wherein the distance between two adjacent groups of the plurality of fin groups is different from the distance between another two adjacent groups of the plurality of fin groups.

[0004] According to another aspect of the present invention, a semiconductor device is provided, comprising: a memory cell having a cell height and including: a plurality of first fins extending along a first direction; and a logic cell adjacent to the memory cell and having a cell height, including: a plurality of second fins extending along the first direction based on the cell height and a plurality of fin grids extending along the first direction, wherein there is a fin spacing between each adjacent pair of fin grids, wherein at least one of the plurality of second fins is substantially aligned with at least one of the plurality of first fins, and at least one of the plurality of second fins is not aligned with the plurality of fin grids.

[0005] According to another aspect of the present invention, a method for manufacturing an integrated circuit (IC) is provided, comprising: forming at least three fin groups that are separated from each other and extend along a first direction in a logic cell disposed adjacent to a memory cell, within a cell height of a logic cell equal to the cell height of a memory cell in a layout view, for forming corresponding transistors in the integrated circuit. Attached Figure Description

[0006] When with attachment Figure 1 When reading this invention, the various aspects can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the various functional components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1Block diagram of a semiconductor device according to some embodiments of the present invention.

[0008] Figure 2 This corresponds to some embodiments of the present invention. Figure 1 The diagram shows a memory device of a semiconductor device.

[0009] Figure 3 This corresponds to some embodiments of the present invention. Figure 1 The diagram shows a memory device of a semiconductor device.

[0010] Figure 4 According to some embodiments of the present invention Figure 3 The layout diagram of the storage device is shown.

[0011] Figure 5 This corresponds to some embodiments of the present invention. Figure 1 The diagram shows the layout of the memory device in the semiconductor device.

[0012] Figures 6A-6B According to some embodiments of the present invention Figure 3 The layout diagram of the storage device is shown.

[0013] Figures 7A-7B According to some embodiments of the present invention Figure 3 The layout diagram of the storage device is shown.

[0014] Figure 8A This is a flowchart of a method for generating an integrated circuit (IC) layout diagram including storage devices according to some embodiments of the present invention.

[0015] Figure 8B This is a flowchart of a method for generating an integrated circuit (IC) for a storage device according to some embodiments of the present invention.

[0016] Figure 9 This is a block diagram of a system for designing IC layout according to some embodiments of the present invention.

[0017] Figure 10 This is a block diagram of an integrated circuit (IC) manufacturing system and related IC manufacturing processes according to some embodiments of the present invention; Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] The terms used in this specification have their common meanings in the art and in the specific text in which each term is used. Examples used in this specification, including instances of any terms discussed herein, are merely illustrative and are in no way intended to limit the scope and meaning of the invention or any exemplary terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0020] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish different elements. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0021] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0022] As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, within which any approximation varies according to the respective fields to which it pertains, and whose range is subject to the broadest interpretation understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, the given value or range should generally be within 20%, preferably within 10%, and more preferably within 5%. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred, or imply other approximations.

[0023] For reference Figure 1 . Figure 1 A simplified block diagram of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor device 100 includes a circuit macro (hereinafter simply referred to as macro) 102. In some embodiments, macro 102 is a static random access memory (SRAM) macro. In other embodiments, macro 102 is a macro other than an SRAM macro.

[0024] In some embodiments, macro 102 includes a memory unit ( Figure 1 (not shown in the image) and peripheral circuits ( Figure 1 (Not shown in the diagram). Memory cells are also called bit cells and are configured to store memory bits. Peripheral cells are also called logic cells surrounding bit cells and are configured to implement various logic functions. The logic functions of a logic cell include, for example, write and / or read decoding, word line selection, bit line selection, data driving, and memory self-test. For illustrative purposes, the logic functions of the above-described logic cells are given. Various logic functions of logic cells are within the scope of this invention.

[0025] In some embodiments, bit cells and logic cells are used in memory devices including, for example, SRAM. Alternatively, based on macro 102, the memory device includes at least one bit cell and at least one logic cell. In some embodiments, at least one of the bit cell and logic cell is implemented by six or eight transistors.

[0026] For reference Figure 2 . Figure 2 This corresponds to some embodiments of the present invention. Figure 1 A schematic diagram of the memory device MC0 of the semiconductor device 100 shown. In some embodiments, the memory device MC0 is based on... Figure 1 It is generated using macro 102 as shown.

[0027] In order to Figure 2As described, the memory device MC0 includes bit cells 210 and logic cells 220. Logic cells 220 are adjacent to bit cells 210. Logic cells 220 include active regions AA1, AA2, and AA3 (also referred to as active regions) configured to form transistors. For simplicity, each of the active regions AA1, AA2, and AA3 is referred to as AA hereinafter for illustration, as in some embodiments each of the active regions AA1, AA2, and AA3 operates in a similar manner. Bit cells 210 also include active regions AA (not shown) for forming transistors separate from those formed in logic cells 220. For simplicity, only a few active regions AA are shown in logic cells 220. Figure 2 In other embodiments of the invention, various elements for forming transistors or other circuit units comprising conductive portions, for example, corresponding to the source and drain of a transistor, are not shown.

[0028] In logic cell 220, the active regions AA arranged in columns contain active elements 221, 222, 223, 224, 225, and 226. For simplicity, each of the active elements 221, 222, 223, 224, 225, and 226 is referred to hereinafter as FN for illustrative purposes, as in some embodiments, each of the active elements 221, 222, 223, 224, 225, and 226 operates in a similar manner. Active elements FN are formed in the respective active regions AA. Specifically, active elements 221 and 222 are formed in active region AA1; active elements 223 and 224 are formed in active region AA2; and active elements 225 and 226 are formed in active region AA3. Furthermore, the active elements FN are divided into several groups, including, for example, a first group T1 for forming transistors, a second group T2 for forming another transistor, and a third group T3 for forming yet another transistor. Alternatively, a logic unit 220 contains three or more transistors, and each of these transistors is formed by at least two active elements FN. In other words, refer to... Figure 2 The logic unit 220 contains three transistors, and each of these transistors is generated based on two active elements FN divided into three groups T1, T2 and T3.

[0029] In some embodiments, the active region AA is polycrystalline silicon. In some embodiments, the active region AA is composed of p-type doped material. In other embodiments, the active region AA is composed of n-type doped material. In various embodiments, the active region AA is configured to form the channel of a transistor. In still other embodiments, the active region AA is a finned active region and is configured to form a fin structure for forming a fin field-effect transistor (FinFET). The active element FN formed in these active regions AA is a fin structure (hereinafter referred to as fin FN in some embodiments of the invention). For simplicity, only the active regions AA and fin FN are shown in logic cell 220. Different numbers of active regions AA and fin FN in logic cell 220 are within the scope of this invention.

[0030] For illustrative purposes, the structure of the memory device MC0 is given. Various configurations of the memory device MC0 are within the scope of this invention. Furthermore, for illustrative purposes, the number and arrangement of fins (FNs) are given. Various numbers and arrangements of fins (FNs) implementing the logic unit 220 are within the scope of this invention. For example, in some embodiments, the number of fins (FNs) in a corresponding group is more than two (e.g., three fins (FNs) in group T1), and the corresponding transistor is a FinFET with a multi-fin structure (e.g., a three-fin FinFET formed in group T1). In alternative embodiments, the fins (FNs) are arranged in rows.

[0031] For reference Figure 3 . Figure 3 This corresponds to some embodiments of the present invention. Figure 1 A schematic diagram of the memory device MC1 of the semiconductor device 100 shown. In some embodiments, the memory device MC1 is configured according to... Figure 1 The macro 102 shown is used for generation. In some embodiments, the storage device MC1 is based on... Figure 2 The storage device MC0 shown is used for construction.

[0032] In order to Figure 3 The description states that the memory device MC1 includes bit cells 310 and 330 and logic cells 320 and 340. The bit cells 310 and 330 and the logic cells 320 and 340 are arranged in an array in rows and columns. The bit cells 310 are arranged in one row adjacent to the logic cells 320, while the bit cells 330 are arranged in another row adjacent to the logic cells 340, which is adjacent to the row where the bit cells 310 and the logic cells 320 are arranged together.

[0033] In some embodiments, bit cell 310 is identical to bit cell 330. In other embodiments, bit cell 310 differs from bit cell 330, and the differences include, for example, cell height and the number of transistors formed. In various embodiments, bit cells 310, 330 and Figure 2 The bit unit 210 shown is exactly the same.

[0034] In some embodiments, bit unit 310 is connected to at least one bit line configured to receive bit data transmitted from a bit line, and this at least one bit line is also connected to bit unit 330. Alternatively, bit unit 310 and bit unit 330 share at least one bit line for receiving the same bit data. In various embodiments, bit unit 310 is connected to at least one word line configured to receive program data transmitted from a word line, and this at least one word line is also connected to bit unit 330. Alternatively, bit unit 310 and bit unit 330 share at least one word line for receiving the same program data.

[0035] In some embodiments, logic unit 320 is identical to logic unit 340. In other embodiments, logic unit 320 differs from logic unit 340, and the differences between them include, for example, unit height and logic function. In various embodiments, logic units 320, 340 and Figure 2 The bit unit 210 shown is exactly the same.

[0036] In some embodiments, logic unit 320 is connected to at least one signal line configured to receive program data transmitted from the signal line, and the at least one signal line is also connected to logic unit 340. In various embodiments, logic unit 320 is connected to multiple signal lines configured to receive program data transmitted from the signal lines, and these signal lines are optionally connected to logic unit 340.

[0037] Continue to refer to Figure 3 Logic unit 320 includes active regions AA1, AA2, and AA3, and the active regions AA1, AA2, and AA3 are configured to form column-arranged fins 321, 322, 323, 324, 325, and 326, respectively. Logic unit 340 includes active regions AA4, AA5, and AA6, and the active regions AA4, AA5, and AA6 are configured to form column-arranged fins 341, 342, 343, 344, 345, and 346, respectively. For simplicity, each of fins 321, 322, 323, 324, 325, 326, 341, 342, 343, 344, 345, and 346 is referred to hereinafter as FN for illustrative purposes, because in some embodiments of the invention, each of fins 321, 322, 323, 324, 325, 326, 341, 342, 343, 344, 345, and 346 is a fin structure and operates in a similar manner.

[0038] refer to Figure 3The fins FN are divided into multiple groups, including groups T1, T2, T3, T4, T5, and T6, for forming corresponding transistors. For simplicity, each of groups T1, T2, T3, T4, T5, and T6 is referred to as TN below for illustrative purposes, as in some embodiments, each of groups T1, T2, T3, T4, T5, and T6 operates in a similar manner. Specifically, in logic unit 320, fins 321 and 322 contained in active region AA1 are grouped into group T1; fins 323 and 324 contained in active region AA2 are grouped into group T2; and fins 325 and 326 contained in active region AA3 are grouped into group T3. In logic unit 340, fins 341 and 342 contained in active region AA4 are grouped into group T4; fins 343 and 344 contained in active region AA5 are grouped into group T5; and fins 345 and 346 contained in active region AA6 are grouped into group T6. Alternatively, the multiple transistors formed in the finned FN are divided into corresponding groups, and these groups are arranged adjacent to each other in columns. For example, see reference... Figure 3 A transistor (not shown) is formed in group T1 containing fins 321 and 322, and another transistor is formed in group T2 containing fins 323 and 324 adjacent to the transistor.

[0039] Each pair of adjacent groups TN constitutes a device unit. Specifically, groups T1 and T2 are denoted as device unit DU1; groups T3 and T4 are denoted as device unit DU2; and groups T5 and T6 are denoted as device unit DU3. Alternatively, a device unit DU1, DU2, or DU3 comprises two adjacent groups TN, and each of these groups TN contains two fins FN for forming a transistor. (Reference) Figure 3Device unit DU1 includes groups T1 and T2, which contain fins 321, 322, 323, and 324 for forming two adjacent transistors; device unit DU2 includes groups T3 and T4, which contain fins 325, 326, 341, and 342 for forming another two adjacent transistors; and device unit DU3 includes groups T5 and T6, which contain fins 343, 344, 345, and 346 for forming yet another two adjacent transistors. In other words, device units DU1 and half of device unit DU2 are arranged in logic unit 320, and half of device unit DU2 and device unit DU3 are arranged in logic unit 340. Therefore, one or more device units DU1, DU2, or DU3 are arranged in logic units 320 or 340, and two or more device units DU1, DU2, or DU3 are arranged in logic units 320 and 340 in memory device MC1. For simplicity, each of device units DU1, DU2 and DU3 will be referred to as DU below, since in some embodiments each of device units DU1, DU2 and DU3 operates in a similar manner.

[0040] In some embodiments, the transistors formed in at least two adjacent groups TN are different from each other. For example, reference Figure 3 In logic unit 320, the transistor formed in group T1 is a p-type metal-oxide-semiconductor (PMOS) transistor, and the transistor formed in group T2 is an n-type metal-oxide-semiconductor (NMOS) transistor. Furthermore, the device unit DU1, which includes groups T1 and T2, contains one PMOS transistor and one NMOS transistor. In some other embodiments, the transistors formed in at least two adjacent groups TN are different from each other. For example, refer to... Figure 3 In logic cell 320, the transistors formed in group T2 are NMOS transistors, and the transistors formed in group T3 are also NMOS transistors. In various embodiments, the transistor type in the corresponding group TN is determined based on the arrangement of device cells DU, and each device cell DU contains two transistors of different types. For example, refer to... Figure 3 Device unit DU1 includes a PMOS transistor formed in group T1 and an NMOS transistor formed in group T2; device unit DU2 includes an NMOS transistor formed in group T3 and a PMOS transistor formed in group T4; and device unit DU3 includes a PMOS transistor formed in group T5 and an NMOS transistor formed in group T6. In some embodiments, a device unit DU including at least one PMOS and at least one NMOS is also represented as a logic circuit unit for implementing basic logic functions.

[0041] For illustrative purposes, the above-described structure of the storage device MC1 has been presented. Various embodiments of the storage device MC1 are within the scope of this invention. For example, in various embodiments, bit cells 310 and 330 are arranged in rows, and logic cells 320 and 340 are arranged in columns.

[0042] In some methods, only a few fins formed in the corresponding active regions are arranged in the logic cell. Specifically, the number of fins in a logic cell is limited to fewer than four, for forming fewer than two (i.e., fewer than one device cell) transistors. Alternatively, fewer than two device cells are contained in two adjacent logic cells, and their active region density is low, which also results in a poor area ratio in a memory device.

[0043] Compared with the methods described above, in embodiments of the present invention, for example, referring to... Figure 3 In a logic cell 320 or 340, the number of fins (FNs) is at least six, used to form more than three transistors and more than one and a half device cells (DUs). Alternatively, refer to... Figure 3 It can accommodate three device cells DU, which are used to implement three logic circuit units in two adjacent logic cells 320 and 340. Therefore, in the two adjacent logic cells 320 and 340 of the memory device, the active region density and area ratio are increased simultaneously, and the device cell density is further increased by 1.5 times.

[0044] For reference Figure 4 . Figure 4 According to some embodiments of the present invention Figure 3 The layout diagram ML1 shows the storage device MC1. For simplicity, only the fins FN are shown in the layout diagram ML1, and each of the fins FN is located in a corresponding active region (not labeled). Figure 4 Or, in other embodiments of the invention, various patterns for forming transistors or other circuit units including, for example, conductive portions and through-holes are not shown. See also... Figure 3 The embodiments are provided for ease of understanding. Figure 4 Similar elements in the model are assigned the same reference numerals.

[0045] refer to Figure 3 and Figure 4 Bit unit 410 corresponds to Figure 3 Bit unit 310 is shown; bit unit 430 corresponds to Figure 3 The bit unit 330 shown; logic unit 420 corresponds to Figure 3 The logic unit 320 shown; logic unit 440 corresponds to Figure 3 The logic unit 340 is shown. Furthermore, in logic unit 420, fins 421, 422, 423, 424, 425, and 426 respectively correspond to… Figure 3 The fins shown are 321, 322, 323, 324, 325, and 326; in logic unit 440, fins 441, 442, 443, 444, 445, and 446 respectively correspond to Figure 3 Fins 341, 342, 343, 344, 345, and 346 are shown.

[0046] and Figure 3 Compared to the embodiments shown, bit units 410 and 430 include separate fins FN. For simplicity, in Figure 4 Only a few fins FN in bit cells 410 and 430 are labeled for illustration, including, for example, fins 411, 412, 413, 414, 415, and 416 in bit cell 410, and fins 431, 432, 433, 434, 435, and 436 in bit cell 430. In some embodiments, each fin FN in bit cells 410 and 430 is configured to form a transistor. For example, in bit cell 410, a first transistor is formed in an active region (not shown) containing fin 411; a second transistor is formed in an active region containing fin 412 adjacent to the first transistor; a third transistor is formed in an active region containing fin 413; a fourth transistor is formed in an active region containing fin 414; a fifth transistor is formed in an active region containing fin 415; and a sixth transistor is formed in an active region containing fin 416; thus, at least six transistors are generated in one bit cell 410. Similarly, bit cell 430 also contains six transistors formed with the corresponding fin FN.

[0047] Furthermore, bit cell 410 has a cell height H1, and bit cell 430 has a cell height H2. In some embodiments, cell height H1 is equal to cell height H2. In other embodiments, cell height H1 is substantially equal to cell height H2. In various embodiments, cell height H1 is different from cell height H2. In some embodiments, cell height H1 or H2 is determined based on the type of bit cell 410 or 430, which is one of the standard cells in a standard cell library (see reference 1). Figure 9 (To be discussed). In various embodiments, bit units 410 and 430 are symmetrical structures of the reference column.

[0048] In some embodiments, the cell height of logic unit 420 is determined based on the cell height H1 of bit unit 410, and the cell height of logic unit 440 is determined based on the cell height H2 of bit unit 430. In various embodiments, logic unit 420 disposed adjacent to bit unit 410 also has a cell height H1, and logic unit 440 disposed adjacent to bit unit 430 also has a cell height H2.

[0049] The width of the fin (FN) is fixed. In some embodiments of the invention, the active region containing the fin (FN) (e.g., Figure 3 The active regions AA1-AA6 shown are fin-shaped active regions used to form the fin structure of the transistor, and the fins FN are fin structures. The fixed width of each fin in FN is represented as a fin width, for example, Figure 4 The fin width P of fin 421 shown. (Continue to refer to...) Figure 4 Each of the fins FN in all bit units 410, 430 and logic units 420 and 440 has a fixed width, also referred to as the fin width P. For simplicity, only one fin width P is shown for fin 431.

[0050] At least one fin FN in bit units 410 and 430 has a different length than the other fin FN in bit units 410 and 430. The fin FN lengths in logic units 420 and 440 are the same as each other. In some embodiments, the fin FN lengths in bit units 410 and 430 are different from the fin FN lengths in logic units 420 and 440. In other embodiments, the fin FN lengths in bit units 410 and 430 are shorter than the fin FN lengths in logic units 420 and 440. In various embodiments, the fin FN lengths in bit units 410 and 430 are substantially equal to the fin FN lengths in logic units 420 and 440.

[0051] Furthermore, the distance between any two adjacent groups TN is expressed as Figure 4 The distance S1 shown is used in some embodiments. In some embodiments, the distance S1 between two adjacent active regions (i.e., two adjacent groups TN) is also represented as the active region gap constrained by the design rules of layout diagram ML1. Alternatively, one fin FN of one group TN (here referred to as group T1') is separated from another fin FN of another group TN (here referred to as group T2'). Group T1' is positioned adjacent to group T2' and is separated from each other by at least one active region gap. (Continue to refer to...) Figure 4 The distance between any two adjacent groups TN, including, for example, the distances between groups T1 and T2, T2 and T3, T3 and T4, T4 and T5, and T5 and T6, are all the same and equal to the distance S1. For simplicity, in Figure 4 Only one distance S1 between groups T1 and T2 is shown. Specifically, distance S1 is the distance between the top edge of a fin FN in group T1' and the top edge of a fin in another group T2' adjacent to group T1'. For example, as Figure 4 As shown, distance S1 is the distance between the top edge of fin 422 in group T1 and the top edge of fin 423 in group T2.

[0052] In some embodiments, the distance between at least two adjacent groups TN is different from the distance between other two adjacent groups TN. Alternatively, at least two adjacent groups TN are separated by a first distance, and at least two other adjacent groups TN are separated by a second distance. The first distance is different from the second distance. For example, refer to... Figure 4 Group T1 is separated from Group T2 by the first distance (i.e., distance S1); Group T2 is separated from Group T3 by the second distance ( Figure 4 (not shown in the image); the third distance separating group T3 and group T4 ( Figure 4 (not shown in the image); the fourth distance separating group T4 and group T5 ( Figure 4 (not shown in the image); and the fifth distance separating group T5 and group T6 (not shown in the image); Figure 4 (Not shown in the diagram). The first distance differs from at least one of the second, third, fourth, or fifth distances. In other words, at least one active region gap between several groups of TN differs from the other groups.

[0053] Furthermore, the distance between any two adjacent fins FN in a group TN is expressed as Figure 4 The distance S2 shown. In some embodiments, the distance S2 between two adjacent fins FN in each group TN is also expressed as the fin spacing (to be referenced). Figures 6A to 6B (For discussion purposes only), the fin spacing is limited by at least one of the cell height, the design rules of layout ML1, and manufacturing constraints. Alternatively, one fin FN (here referred to as fin F1) is separated from another fin FN (here referred to as fin F2). Fins F1 and F2 are both represented as a group used to form the same transistor. Fin F1 is positioned immediately adjacent to fin F2 and separated from fin F2 by at least one fin spacing. (Continue to reference...) Figure 4 The distance between any two adjacent fins FN in the corresponding group TN, including, for example, the distance between fins 421 and 422 in group T1, the distance between fins 423 and 424 in group T2, the distance between fins 425 and 426 in group T3, the distance between fins 441 and 442 in group T4, the distance between fins 442 and 444 in group T5, and the distance between fins 445 and 446 in group T6, is the same as each other and equal to distance S2. For simplicity, in Figure 4 Only one distance S2 between adjacent fins 423 and 424 of group T2 is shown.

[0054] In some embodiments, the distance between two adjacent fins (FN) of one group of TNs is different from the distance between two adjacent fins (FN) of another group of TNs. Alternatively, at least two adjacent fins (FN) of at least one group of TNs are separated from each other by a first distance, and at least two adjacent fins (FN) of another group of TNs are separated from each other by a second distance. The first distance is different from the second distance. For example, refer to... Figure 4 Fins 421 and 422 of group T1 separated at the first distance ( Figure 4(not shown in the diagram); fins 423 and 424 of group T2 are separated by a second distance (i.e., distance S2); fins 425 and 426 of group T3 are separated by a third distance; fins 441 and 442 of group T4 are separated by a fourth distance; fins 442 and 444 of group T5 are separated by a fifth distance; and fins 445 and 446 of group T6 are separated by a sixth distance. The first distance is different from at least one of the second, third, fourth, fifth, or sixth distances.

[0055] For illustrative purposes, the structure of layout diagram ML1 is given. Various configurations of layout diagram ML1 are within the scope of this invention. For example, in various embodiments, each fin FN in bit cells 410 and 430 has a substantially equal length to each other.

[0056] For reference Figure 5 . Figure 5 This corresponds to some embodiments of the present invention. Figure 1 The layout diagram ML2 shows the memory device of the semiconductor device 100. In some embodiments, Figure 5 The layout diagram ML2 shown is Figure 4 An optional embodiment of the layout diagram ML1 shown. Refer to... Figure 4 The embodiments are provided for ease of understanding. Figure 5 Similar elements in the model are assigned the same reference numerals.

[0057] and Figure 4 Compared to the embodiments shown, the number of fins FN included in each of bit units 510 and 530 is greater than that included in the embodiments shown. Figure 4 The number of fins (FNs) in each of the bit units 410 and 430 shown. In other words, the number of transistors formed in bit units 510 and 530 is greater than that in… Figure 4 The number of transistors formed in bit units 410 and 430 shown. For example, refer to Figure 5 In bit cell 510, transistors corresponding to groups T9, T10, T11, T12, T13, T14, T15, and T16 are formed in the corresponding active regions (unlabeled) containing fins FN (not labeled individually for simplicity). Therefore, at least eight transistors are generated in one bit cell 510, which is more than in... Figure 4 At least six transistors are generated in bit cell 410. Similarly, bit cell 530 formed in the corresponding active region (unlabeled) containing fin FN also contains eight transistors, including, for example, transistors corresponding to groups T17, T18, T19, T20, T21, T22, T23 and T24.

[0058] Furthermore, the number of fins FN contained in each of logic units 520 and 540 is greater than the number contained in each of the logic units 520 and 540. Figure 4The number of fins (FNs) in each of the logic units 420 and 440 shown. In other words, the number of transistors formed in logic units 520 and 540 is greater than that in... Figure 4 The number of transistors formed in the logic units 420 and 440 shown. For example, refer to Figure 5 In logic cell 520, transistors corresponding to groups T1, T2, T3, and T4 are formed. Therefore, at least four transistors are generated in one logic cell 520, which is more than in... Figure 4 The logic unit 420 contains three transistors. Similarly, logic unit 540 also contains four transistors corresponding to groups T5, T6, T7, and T8.

[0059] Furthermore, in some embodiments, two adjacent groups TN are divided into one device cell DU. The number of device cells DU contained in each of logic cells 520 and 540 is greater than the number contained in... Figure 4 The number of device cells DU in each of the logic cells 420 and 440 shown. For example, refer to Figure 5 The logic unit 520 includes at least two device units DU, for example, device unit DU1 containing groups T1 and T2, and device unit DU2 containing groups T3 and T4. This is more than Figure 4 The diagram shows 0.5 device units DU contained in logic unit 420. Similarly, logic unit 540 also contains two device units DU, which include, for example, device unit DU3 containing groups T5 and T6, and device unit DU4 containing groups T7 and T8.

[0060] Now for reference Figure 6A and Figure 6B . Figures 6A-6B Each of these is an embodiment of the present invention. Figure 3 The layout diagram ML1 of the storage device MC1 is shown. In some embodiments, Figures 6A-6B The layout diagram ML1 shown is Figure 4 An optional embodiment of the layout diagram ML1 shown. Refer to... Figures 3-4 The embodiments are provided for ease of understanding. Figures 6A-6B Similar elements in the reference numerals are assigned the same reference numerals. For simplicity, refer to... Figures 3-4 The embodiments are provided for ease of understanding. Figures 6A to 6B Some components are not labeled with the exact same component.

[0061] and Figure 4Compared to the illustrated embodiment, an active region grid FN' is shown, which extends along rows across bit cells and logic cells. In some embodiments of the invention, the fin FN is a fin structure of a transistor, and the active region grid FN' is referred to below as a fin grid FN'. In some embodiments, the widths of the fin grids FN' are equal to each other and also equal to the width of each fin FN. Alternatively, each fin grid FN' has a width equal to a fixed width of the fin FN, which is referred to as... Figure 4 and Figure 6A The fin width P is shown. In some embodiments, the distance between any two adjacent fin grids FN' is equal to each other and is referred to as the fin spacing. In various embodiments, the fin grid FN' is a reference grid used to produce the layout diagram ML1. Or, the layout diagram ML1, which contains bit cells and logic cells, is generated based on the fin grid FN'.

[0062] Figure 6A The distance between every two adjacent fins FN along the column is shown. Figure 6B This shows the distance between every two adjacent fins (FN) along the row. Or, in other words, Figure 6A The vertical distance between fins FN is shown. Figure 6B The horizontal distance between fins (FN) is shown. In some embodiments, Figures 6A to 6B The distance shown is also referred to as the interval between fins (FN). For example, see reference... Figure 6A The vertical distance between fins (i.e., denoted as distance S3) is calculated from the bottom edge of one fin (i.e., denoted as group T7) to the top edge of the other fins (i.e., denoted as group T8). Figure 6B Another example is shown where the horizontal distance between fins (FN) (i.e., denoted as distance D3) is from the right edge of a fin FN (i.e., denoted as...). Figure 6A The values ​​are calculated from the left edge of the other fins (T7) to the left edge of the other fins (i.e., denoted as T1). For illustrative purposes, the following are given: Figures 6A-6B The distances shown are within the scope of this invention. Various configurations of the distances are also within the consideration of this invention.

[0063] refer to Figure 6AThe fins (FNs) in a bit cell are separated by different distances along the columns. For the leftmost column of the bit cell (denoted as column C1), the twelve fins are arranged in rows and separated from each other by different distances, including, for example, distances from top to bottom of S3, S5, S5, S5, S5, S3, S5, S3, S5, S5, S5, and S3. For the middle column of the bit cell (denoted as column C2), the twelve fins are arranged in columns and separated from each other by different distances, including, for example, distances from top to bottom of S3, S6, S3, S6, S3, S5, S3, S6, S6, and S3. For the rightmost column of the bit cell (denoted as column C3), the twelve fins are arranged in rows and separated from each other by different distances, including, for example, distances from top to bottom of S3, S7, S3, S5, S3, S7, and S3.

[0064] Furthermore, in the bit cells, in layout diagram ML1, some fins FN are directly disposed within fin grids FN'. Alternatively, in the layout view, some fins FN in the bit cells directly overlap with fin grids FN', and the layout view also indicates that these fins FN are arranged on fin grids FN'. Alternatively, in the layout view, some fins FN in the bit cells are separated from fin grids FN', and the layout view also indicates that these fins FN are arranged outside of fin grids FN'. In some embodiments, in the layout view, some fins FN in the bit cells partially overlap with fin grids FN', and the layout view is also shown as indicating that these fins FN are arranged outside of fin grids FN'. For example, refer to... Figure 6A In the middle column C2 of the bit cell, group T9 completely overlaps with the corresponding fin grid FN', while in the rightmost column C3 of the bit cell, group T8 does not overlap with the corresponding fin grid FN'.

[0065] In a logic unit, fins (FNs) are separated by different distances along the column. Specifically, in a logic unit, two adjacent fins (FNs) in a corresponding group (TN) are separated by a first gap (denoted as distance S3). Furthermore, two adjacent groups (TN) are separated by a second gap (denoted as distance S4).

[0066] In some embodiments, each fin FN in the corresponding group TN is separated by the same gap (e.g. Figure 6A The distance S3 shown. In some embodiments, the distance between two adjacent fins FN in one group TN is different from the distance between two adjacent fins FN in another group TN. For example, continue to refer to Figure 6A In group T1, the distance between two adjacent fins FN is S3, and in group T2, the distance between two adjacent fins FN is different from the distance S3.

[0067] In some embodiments, every two adjacent groups of TN are separated by the same gap (e.g., Figure 6AThe distance S4 is shown. For example, continue to refer to... Figure 6A Two adjacent groups T1 and T2 are separated from each other by a distance S4. In some other embodiments, at least two adjacent groups TN are separated from each other by a different gap. Or, at least two adjacent groups TN are separated from each other by a first distance, and another two adjacent groups TN are separated from each other by a second distance different from the first distance. For example, continuing to refer to Figure 6A The distance between groups T1 and T2 is different from at least one of the following distances: the distance between groups T2 and T3, the distance between groups T3 and T4, the distance between groups T4 and T5, or the distance between groups T5 and T6.

[0068] Furthermore, in the logic cell, in layout diagram ML1, some fins FN are partially disposed within fin grids FN'. Alternatively, in the layout view, some fins FN in the logic cell partially overlap with fin grids FN', and the layout view also indicates that these fins FN are arranged outside of fin grids FN'. In some embodiments, in the layout view, some fins FN in the logic cell are separated from fin grids FN', and the layout view is also shown as indicating that these fins FN are arranged outside of fin grids FN'. In various embodiments, in the logic cell, in layout diagram ML1, some fins FN are partially disposed within fin grids FN'. Alternatively, in the layout view, some fins FN in the logic cell directly overlap with fin grids FN', and the layout view also indicates that these fins FN are arranged on fin grids FN'. For example, refer to... Figure 6A Fins FN are arranged outside fin grids FN'.

[0069] In some embodiments, because the layout diagram ML1 is generated based on the fin grid FN', the distance between two adjacent fins FN is determined based on the fin pitch. Furthermore, the design of the fins FN used to form the fin structure of the transistor is also based on advanced technology. In other words, the arrangement of the fins FN is determined based on the fin grid FN' and manufacturing constraints. In some embodiments, the arrangement of the fins FN is also determined based on the cell height of the bit cells.

[0070] For example, refer to Figure 6A For cells with cell heights H1 and H2, the distance S3 is essentially equal to the distance between two adjacent fin grids FN' (i.e., one fin spacing) minus the width of the fin grid FN' (i.e., the distance P). Alternatively, the two adjacent fin grids FN' are separated from each other by a distance S2 (refer to...). Figure 4(Discussed further), and in some embodiments also represented as a fin spacing. Distance S4 is in the range of one fin spacing to twice the fin spacing (i.e., S4 = 1 * fin spacing to 2 * fin spacing). Distance S5 is in the range of one fin spacing to twice the fin spacing (i.e., S5 = 1 * fin spacing to 2 * fin spacing), and is greater than distance S3. Distance S6 is in the range of twice the fin spacing to three times the fin spacing (i.e., S6 = 2 * fin spacing to 3 * fin spacing). Distance S7 is in the range of five to six times the fin spacing (i.e., S7 = 5 * fin spacing to 6 * fin spacing).

[0071] In some embodiments, the distance between at least two adjacent groups TN in a logic unit is not an integer multiple of the fin pitch. For example, in some embodiments, the distance S4 between two adjacent groups TN is essentially equal to the fin pitch multiplied by a number that is not an integer and is in the range of one to two. Specifically, distance S4 is the distance between the top edge of a fin FN in group T1 and the top edge of a fin FN in group T2. Distance S4 is not an integer multiple of the fin pitch. On the other hand, the distance S2 between two adjacent fin FNs in the corresponding group TN (in...) Figure 4 (As shown in the diagram) is essentially equal to the fin spacing multiplied by an integer, which is 1. This integer is less than the number. For example, this integer equals 1, so the distance S2 between two adjacent fins FN is equal to the fin spacing multiplied by 1. This number equals 1.2 (greater than the integer 1), so the distance S4 between two adjacent groups TN is equal to the fin spacing multiplied by 1.2. In some other embodiments, this number is less than this integer, and the number is not an integer either. In some other embodiments, the distance between at least two adjacent groups TN in a logic cell is an integer multiple of the fin spacing when at least two adjacent groups TN are arranged outside the fin grid FN' and have the same offset from the reference fin grid FN'.

[0072] Furthermore, referring to adjacent fin grids FN' in these fins FN, some fins FN in the bit cell are not aligned with some fins FN in the logic cell. In other words, at least one fin FN in the bit cell is not aligned with or substantially aligned with at least one fin FN in the logic cell along the row. For example, in some embodiments, continuing with... Figure 6A In the rightmost column C3 of the bit cell, groups T7 and T8 are arranged outside the fin grid FN', and group T1, which is immediately adjacent to these groups T7 and T8 along the same row, is also arranged outside the fin grid FN'. Because the spacing between groups T7 and T8 and the fin grid FN' is different from the spacing between group T1 and the fin grid FN', groups T7 and T8 in the bit cell are not aligned with group T1 along the same row in the logic cell. Groups T11 and T12 in the rightmost column C3 of the bit cell are not aligned with group T3 along the same row in the logic cell. Similarly, in the rightmost column C3 of the bit cell, groups T13 and T14 are not aligned with group T4 along the same row in the logic cell, and groups T17 and T18 are not aligned with group T6 along the same row in the logic cell.

[0073] In some embodiments, referring to adjacent fin grids FN' in these fins FN, some fins FN in a bit cell are aligned with some fins FN in a logic cell. Alternatively, at least one fin FN in a bit cell is aligned row-wise with at least one fin FN in a logic cell. For example, continuing to refer to... Figure 6A In the middle column C2 of the bit cell, groups T9 and T10 are aligned with group T2 in the logic cell along the row, and groups T15 and T16 are aligned with group T5 in the logic cell along the row.

[0074] refer to Figure 6B In a logic cell, the fins (FNs) are separated by different distances along the rows. In a bit cell, the distance between the fin (FN) in the leftmost column C1 and the fin (FN) in the middle column C2 includes, for example, the distance from top to bottom row, distances D1, D2, D1, D1, D1, D2, and D1. In some embodiments, the fins (FNs) in a bit cell are separated by the same distance along the rows. For example, continuing to refer to... Figure 6A The separation distance between fin FN in the middle column C2 and fin FN in the rightmost column C3 includes, for example, the distance from the top row to the bottom row, distances D1, D1, D1, and D1.

[0075] Furthermore, the groups between bit cells and logic cells are separated by different distances along the row. Specifically, one fin FN in a bit cell is separated from the fin FN of group TN by a first distance, and another fin FN in a bit cell is separated from the fin FN of group TN by a second distance different from the first distance. For example, continue to refer to Figure 6A In the rightmost column C3 of the bit cell, group T8 (in Figure 6A The distance D3 between group T1 and logic unit T1 in the middle column C2; group T10 in the middle column C2 (in Figure 6A The distance between group T11 (marked in the middle) and group T2 is D4; the distance between group T11 (marked in the rightmost column C3) and group T2 is D4. Figure 6A The distance between group T14 and group T2 is D3; the rightmost column C3 of the bit cell contains group T14 (in... Figure 6A The distance between group T16 (marked in the middle column) and group T4 is D3; group T16 in the middle column C2 (in the middle column) Figure 6A The distance D3 between the middle marker and group T5; and the distance D3 between group T17 in the rightmost column C3 (in Figure 6A The distance D3 between the marker in the middle and group T6.

[0076] In some embodiments, the arrangement of fins (FNs) is determined at least based on fin gates (FNs) or active regions used to form transistor gate structures. Thus, the distance between fins (FNs) in bit cells and fins (FNs) in logic cells along a row is associated at least with the fin pitch or polysilicon pitch, which in some embodiments is referred to as the minimum distance between two adjacent gate structures. For example, refer to... Figure 6BThe distance D1 is basically equal to one polysilicon spacing; the distance D2 is basically equal to twice the polysilicon spacing (i.e., D2≈2*polysilicon spacing); the distance D3 is basically in the range of four to seven times the polysilicon spacing (i.e., D3=4*polysilicon spacing to 7*polysilicon spacing); and the distance D4 is basically in the range of seven to ten times the polysilicon spacing (i.e., D4=7*polysilicon spacing to 10*polysilicon spacing).

[0077] For illustrative purposes, the above-described structure of layout diagram ML1 is provided. Various embodiments of layout diagram ML1 are within the scope of this invention.

[0078] In some methods, when fins are arranged in logic cells, each fin is arranged on a fin grid. Thus, the active region gap between two adjacent fin groups is limited to an integer multiple of the fin pitch, and this also affects the active region density of the memory device. Furthermore, because the active region gap is constrained, it does not allow for customized arrangements of fins formed within the active regions.

[0079] Compared with the methods described above, in embodiments of the present invention, for example, referring to... Figure 4 , Figure 6A or Figure 6B In a logic cell, at least one fin (FN) is arranged outside the fin grid (FN'). Therefore, the active region gap between two adjacent groups (TN) of fins (FN) is not limited by fin pitch constraints. Similarly, it can provide a compact active region density for the memory device, and can also provide [specific features] within the corresponding active region ([specific features]). Figure 3 Custom arrangement of fins FN formed in the active region AA shown.

[0080] Now for reference Figures 7A-7B . Figures 7A-7B Each of these is an embodiment of the present invention. Figure 3 The layout diagram ML1 of the storage device MC1 is shown. In some embodiments, Figures 7A-7B The layout diagram ML1 shown is Figure 4 or Figures 6A-6B An optional embodiment of the layout diagram ML1 shown. Refer to... Figure 3 , Figure 4 , Figure 6A and Figure 6B The embodiments are provided for ease of understanding. Figures 7A-7B Similar elements in the reference numerals are assigned the same reference numerals. For simplicity, refer to... Figure 3 , Figure 4 , Figure 6A and Figure 6B The embodiments are provided for ease of understanding. Figures 7A-7B Some components are not labeled with the exact same component.

[0081] and Figure 4 Compared to the illustrated embodiment, layout ML1 further includes conductive rails disposed in a zero metal (M0) layer, and the M0 layer is disposed above the fin FN. The conductive rails include power rails 711, 713, 715, 717 and 719 and signal rails 712, 714, 716 and 718 disposed in the bit cells, and also include power rails 731, 737, 743 and 749 and signal rails 732, 733, 734, 735, 736, 738, 739, 740, 741, 742, 744, 745, 746, 747 and 748 disposed in the logic cells. For simplicity, each of power rails 711, 713, 715, 717, 719, 731, 737, 743, and 749 is referred to PG below for illustrative purposes, since each of power rails 711, 713, 715, 717, 719, 731, 737, 743, and 749 operates in a similar manner in some embodiments. For simplicity, each of signal rails 732, 733, 734, 735, 736, 738, 739, 740, 741, 742, 744, 745, 746, 747, and 748 is referred to SL below for illustrative purposes, since each of signal rails 732, 733, 734, 735, 736, 738, 739, 740, 741, 742, 744, 745, 746, 747, and 748 operates in a similar manner in some embodiments.

[0082] refer to Figures 7A-7B In a bit cell or logic cell, the power rails PG are separated from each other along the column. The signal rails SL in a bit cell or logic cell are located between the power rails PG and are separated from each other along the column. Both the power rails PG and the signal rails SL are parallel to each other and extend along the row.

[0083] In some embodiments, the power rail PG and signal rail SL in a bit cell are uniformly separated from each other. Alternatively, in a bit cell, the distance between any two adjacent rails of the power rail PG and signal rail SL is the same. For example, refer to... Figures 7A to 7B The distance between power rail 711 and signal rail 712 is equal to the distance between signal rail 712 and power rail 713, power rail 713 and signal rail 714, etc. In some other embodiments, in a bit cell, at least one distance between power rail PG and signal rail SL is different from other distances therebetween. For example, refer to Figures 7A-7BThe distance between power rail 711 and signal rail 712, or between signal rail 714 and power rail 715, or between power rail 715 and signal rail 716, or between signal rail 718 and power rail 719, is equal to the first rail gap. The distance between signal rail 712 and power rail 713, or between power rail 713 and signal rail 714, or between signal rail 716 and power rail 717, or between power rail 717 and signal rail 718, is equal to the second rail gap. The first rail gap is also represented as... Figure 7B The distance S11 shown is represented as the second track gap. Figure 7B The distance S12 is shown. The first rail gap is different from the second rail gap.

[0084] In some embodiments, the power rail PG and signal rail SL in the logic unit are uniformly separated from each other. Alternatively, in the logic unit, the distance between any two adjacent rails of the power rail PG and signal rail SL is the same. For example, refer to... Figures 7A-7B The distance between power rail 731 and signal rail 732 is equal to the distance between signal rails 732 and 733, signal rails 733 and 734, signal rails 734 and 735, signal rails 735 and 736, and the distance between signal rail 736 and power rail 737, etc. This distance between two adjacent rails of power rail PG and signal rail SL is also expressed as... Figure 7B The distance S13 is shown. In some other embodiments, in a bit cell, at least one distance between the power rail PG and the signal rail SL is different from the other distances therebetween. For example, refer to Figures 7A-7B The distance between power rail 731 and signal rail 732 is equal to the third rail gap, and the distance between signal rails 732 and 733 is equal to the fourth rail gap. The third rail gap is different from the fourth rail gap.

[0085] In order to Figure 7A The description indicates that, in the bit cell, in the layout view, power rail 711 is directly positioned above the top edge of the bit cell. In the layout view, power rail 715 is directly positioned above the intersection edge between two adjacent bit cells, while power rail 719 is directly positioned above the bottom edge of the bit cell. Signal rail 712 is positioned between power rails 711 and 713. Signal rail 712 is also positioned above the fin FN containing fin 412. Furthermore, signal rail 714 is positioned between power rails 713 and 715. Signal rail 714 is also positioned above the fin FN containing fin 415. Moreover, signal rail 716 is positioned between power rails 715 and 717. Signal rail 716 is also positioned above the fin FN containing fin 432. Signal rail 718 is positioned between power rails 717 and 719. Signal rail 718 is also positioned above the fin FN containing fin 435.

[0086] In some embodiments, power rail 711 is connected via a through-hole (not shown) to a transistor formed in a fin FN containing fin 411. Signal rail 712 is connected via a through-hole to a transistor formed in a fin FN containing fins 411 and 412. Power rail 713 is connected via a through-hole to a transistor formed in a fin FN containing fins 413 and 414. Signal rail 714 is connected via a through-hole to a transistor formed in a fin FN containing fins 415 and 416. Power rail 715 is connected via a through-hole to a transistor formed in a fin FN containing fins 416 and 431. Signal rail 716 is connected via a through-hole to a transistor formed in a fin FN containing fins 431 and 432. Power rail 717 is connected via a through-hole to a transistor formed in a fin FN containing fins 433 and 434. Signal rail 718 is connected via a through-hole to a transistor formed in a fin FN containing fins 435 and 436. Power rail 719 is connected via a through-hole to a transistor formed in a fin FN containing fin 436.

[0087] Continue to refer to Figure 7A In the layout view, within the logic cell, power rail 731 is directly positioned above the top edge of the logic cell, and power rail 749 is directly positioned above the bottom edge of the bit cell. Signal rail 732 is partially positioned above fin 421. Alternatively, in the layout view, signal rail 732 partially overlaps with fin 421. Furthermore, in the layout view, signal rail 733 partially overlaps with fin 422. Signal rail 734 does not overlap with fin FN. Alternatively, signal rail 734 overlaps with a group (i.e., Figure 4 The fin 422 of group T1 shown and another adjacent group (i.e., Figure 4 The fin 423 of group T2 shown is separated. In the layout view, signal rail 735 directly overlaps with fin 423. In the layout view, signal rail 736 substantially overlaps completely with fin 424. Or, signal rail 736 is substantially positioned above fin 424. Moreover, power rail 737 does not overlap with fin FN. Or, power rail 737 is separated from a group (i.e., Figure 4 The fins 424 of group T2 shown and another adjacent group (i.e., Figure 4 The fin 425 of group T3 shown is separated.

[0088] In some embodiments, power rails 731, signal rails 732, 733, 734, 735, and 736, and power rail 737 are represented as a set of conductive rails for supplying power to a device unit (i.e., Figure 4The device unit DU1 shown provides signals. In some other embodiments, power rail 731 is connected via a via (not shown) to transistors formed in fins 421 and 422, and power rail 737 is connected via a via (not shown) to transistors formed in fins 423 and 424. Alternatively, power rails 731 and 737 are connected to a device unit containing two different types of transistors formed in adjacent fins FN comprising fins 421, 422, 423, and 424. In various embodiments, signal rails 732, 733, 734, 735, and 736 are connected via vias (not shown) to transistors formed in fins 421, 422, 423, and 424. Alternatively, signal rails 732, 733, 734, 735, and 736 are connected to a device unit that is further connected to power rails 731 and 737.

[0089] Furthermore, in the layout view, signal rail 738 partially overlaps with fin 425. Signal rail 739 is substantially positioned above fin 426. Signal rail 740 is positioned directly above the cross edge between two adjacent logic cells. In the layout view, signal rail 741 directly overlaps with fin 441. In the layout view, signal rail 742 directly overlaps with fin 442. Moreover, power rail 743 does not overlap with fin FN. Or rather, power rail 743 overlaps with a group (i.e., Figure 4 The fin 442 of group T4 shown and another adjacent group (i.e., Figure 4 Fin 443 of group T5 shown is separated.

[0090] In some embodiments, power rails 737, signal rails 738, 739, 740, 741, and 742, and power rail 743 are represented as a set of conductive rails for supplying power to a device unit (i.e., Figure 4 The device unit DU2 shown provides signals. In some other embodiments, power rail 737 is connected via a via (not shown) to transistors formed in fins 425 and 426, and power rail 743 is connected via a via (not shown) to transistors formed in fins 441 and 442. Alternatively, power rails 737 and 743 are connected to a device unit containing two different types of transistors formed in adjacent fins FN comprising fins 425, 426, 441, and 442. In various embodiments, signal rails 738, 739, 740, 741, and 742 are connected via vias (not shown) to transistors formed in fins 425, 426, 441, and 442. Alternatively, signal rails 738, 739, 740, 741, and 742 are connected to a device unit that is further connected to power rails 737 and 743.

[0091] Furthermore, in the layout view, signal rail 744 partially overlaps with fin 443. Signal rail 745 is essentially positioned above fin 444. Signal rail 746 does not overlap with fin FN. In other words, signal rail 746 is associated with a group (i.e., Figure 4 The fins 444 of group T5 shown and another adjacent group (i.e., Figure 4 Fin 445 of group T6 shown is separated. In the layout view, signal rail 747 directly overlaps with fin 445. In the layout view, signal rail 748 directly overlaps with fin 446.

[0092] In some embodiments, power rails 743, signal rails 744, 745, 746, 747, and 748, and power rail 749 are represented as a set of conductive rails for supplying power to a device unit (i.e., Figure 4 The device unit DU3 shown provides signals. In some other embodiments, power rail 743 is connected via a via (not shown) to transistors formed in fins 443 and 444, and power rail 749 is connected via a via (not shown) to transistors formed in fins 445 and 446. Alternatively, power rails 743 and 749 are connected to a device unit containing two different types of transistors formed in adjacent fins FN comprising fins 443, 444, 445, and 446. In various embodiments, signal rails 738, 739, 740, 741, and 742 are connected via vias (not shown) to transistors formed in fins 435, 436, 441, and 442. Alternatively, signal rails 744, 745, 746, 747, and 748 are connected to a device unit that is further connected to power rails 743 and 749.

[0093] In some embodiments, the power rail PG is made of metal. In other embodiments, the power rail PG is connected via a via (not shown) to at least one power circuit (not shown, e.g., a current source or voltage source) disposed in a metal layer (e.g., metal layer M1) above the M0 layer for receiving power signals. In various embodiments, the power rail PG disposed between the fin FN and the M0 layer is connected via a via to a fin FN disposed below the M0 layer for providing power signals to corresponding transistors formed in the fin FN. In some embodiments, at least one power rail PG is configured to provide a signal having a first voltage, and at least one power rail PG is configured to provide a signal having a second voltage, wherein the first voltage is higher than the second voltage. The power rail PG having the first voltage is represented as a power line, and the power rail having the second voltage is represented as a ground line. For example, in some embodiments, reference... Figure 7AThe power rails 713 and 717 in the bit cells and the power rails 731 and 743 in the logic cells are called power lines. The power rails 711, 715, and 719 in the bit cells and the power rails 737 and 749 in the logic cells are called ground lines. The power lines and ground lines are arranged to cross each other.

[0094] In some embodiments, the signal rail SL is made of metal. In other embodiments, the signal rail SL is connected via a via (not shown) to at least one data circuit (not shown) disposed in layer M1 for receiving data signals. In various embodiments, the signal rail SL is connected via a via (not shown) to fin FN for providing data signals to corresponding transistors formed in fin FN.

[0095] In some embodiments, signal tracks SL in a bit cell are configured to provide signals having bit data, and these signal tracks SL are represented as bit lines. For example, in some embodiments, reference... Figure 7A Signal rails 712, 714, 716, and 718 in the bit cell are referred to as bit lines. Each of signal rails 712, 714, 716, and 718 is disposed between one of power rails 713 and 717, which are power metal rails, and one of power rails 711, 715, and 719, which are ground rails. In some embodiments, signal rails 712 and 714 are connected to a memory device ( Figure 4 The bit line pairs of one row of the memory device MC1. Similarly, signal rails 716 and 718 are connected to the memory device ( Figure 4 Another line pair in another row of the storage device MC1).

[0096] In some embodiments, signal rails SL in a logic unit are configured to provide signals for operating logic functions, and these signal rails SL are represented as signal lines. For example, in some embodiments, reference... Figure 7A Signal rails 732, 733, 734, 735, and 736, located between one of the power rails 731 (which serves as a power supply metal rail) and one of the power rails 737 (which serves as a ground rail), are referred to as signal lines. Similarly, signal rails 738, 739, 740, 741, and 742 in the logic unit are referred to as signal lines, and these signal lines are located between one of the power rails 737 (which serves as a ground wire) and one of the power rails 743 (which serves as a power supply line). Signal rails 744, 745, 746, 747, and 748 in the logic unit are referred to as signal lines, and these signal lines are located between one of the power rails 743 (which serves as a power supply line) and one of the power rails 749 (which serves as a ground wire).

[0097] refer to Figure 7B For simplicity, only the settings shown are displayed. Figure 7AThe components in layer M0 are shown. The width of a power rail PG in a bit cell is represented as width W1. The width of a signal rail SL in a bit cell is represented as width W2. The width of another power rail PG in a bit cell is represented as width W3. The width of a power rail PG in a logic cell is represented as width W4. The width of a signal rail SL in a logic cell is represented as width W5. For simplicity, as... Figure 7B As shown, only a few power rails PG or signal rails SL are marked with widths W1-W5.

[0098] In some embodiments, reference Figure 7B In the bit unit, power rails 711, 715, and 719 are represented as ground lines, and each of them has a width W1. In the bit unit, power rails 713 and 717 are represented as power lines, and each of them has a width W2. In the bit unit, signal rails 712, 714, 716, and 718 are represented as bit lines, and each of them has a width W3.

[0099] In some embodiments, reference Figure 7B In the logic unit, power rails 731 and 743 are represented as power lines, and each of them has a width W4. In the logic unit, power rails 737 and 749 are represented as ground lines, and each of them also has a width W4. In the logic unit, signal rails 732, 733, 734, 735, 736, 738, 739, 740, 741, 742, 744, 745, 746, 747, and 748 are represented as signal lines, and each of them has a width W5.

[0100] In some embodiments, widths W1-W5 are different from each other. In other embodiments, width W1 is substantially equal to width W2 or width W4. In various embodiments, width W1 is less than or greater than width W2, and width W1 is less than or greater than width W4. In some embodiments, width W4 is greater than width W5.

[0101] In some embodiments, the width W4 is greater than the width of the fin FN. The width of the fin FN is also referred to as... Figure 4 and Figure 6A The fin width P is shown. In various embodiments, the width W5 is greater than the fin width P. In alternative embodiments, the width W5 is substantially equal to the fin width P. In some embodiments, the width W4 is less than or equal to the distance between two adjacent groups TN in the logic cell (e.g., Figure 4 (The distance between groups T1 and T2 shown). In some other embodiments, the width W4 is substantially equal to the distance between two adjacent groups TN in the logic cell. In various embodiments, the width W5 is less than the distance between two adjacent groups TN in the logic cell.

[0102] For reference Figure 8A . Figure 8A It is for generating according to some embodiments of the present invention Figure 2 The storage device MC0 or shown Figure 3 A flowchart of method 800A for laying out an integrated circuit (IC) diagram of the memory device MC1 shown. In some embodiments, the layout diagram generated by method 800A corresponds to... Figure 4 , Figures 6A to 6B or Figures 7A to 7B The layout diagram ML1 is shown. In some other embodiments, the layout diagram generated by method 800A corresponds to... Figure 5 The layout diagram ML2 is shown. In order to... Figure 8A The description states that method 800A includes operations S810a, S820a, and S830a. (See reference...) Figure 4 or Figures 6A to 6B The layout diagram in the middle, Figure 8A The following description of method 800A contains exemplary operations. However, Figure 8A The operations described herein may not be performed in the order shown. In other words, in accordance with the spirit and scope of various embodiments of the invention, operations may be appropriately added, substituted, changed in order, and / or canceled.

[0103] In operation S810a, fin regions that are separate from each other and extend along rows are arranged in logic cells. The logic cells are positioned adjacent to memory cells, and both the logic cells and memory cells are contained within memory devices. For illustration, as... Figure 3 As shown, the active regions AA1-AA3, which are separated from each other and extend along the row, are arranged in logic cells 320 and 340, which are located adjacent to bit cells 310 and 330 contained in the memory device MC1.

[0104] In some embodiments, method 800A further includes the following operation: determining the distance between two adjacent fins. For illustration, as... Figure 6A As shown, the distance between two adjacent fins FN in group T1 is determined as distance S3. In some other embodiments, the distance between two adjacent fins is determined based on the fin grid in the layout view, with each fin grid separated from the fin spacing. For further illustration, as... Figure 6A As shown, the distance S3 is determined based on the fin grid FN' and the fin spacing between each fin grid FN'.

[0105] In operation S820a, the fin region is divided into fin groups. Alternatively, the fin region is grouped or divided into several rows of arranged groups. For illustration, as... Figure 3 As shown, the active regions AA1-AA3 are divided into groups T1-T6, which are used to generate the corresponding transistors.

[0106] In operation S830a, fins are generated and positioned within the fin region. Fins for corresponding transistors are then constructed within the fin region. Therefore, transistors can be further generated based on the arrangement of the fin region. For illustration, as... Figure 3 As shown, fins 321-326 and 341-346 are generated accordingly in the active regions AA1-AA3.

[0107] In some embodiments, method 800A further includes the following operation: In the logic cell, conductive rails including power rails and signal rails are arranged in a metal layer above the fin region. In the logic cell, in a layout view, the power rails are separated from the fins. For illustration, as... Figure 7A As shown, in the logic cell, conductive rails including power rail PG and signal rail SL are arranged in the M0 layer above the active region. Figure 7A It is also shown that in the logic cell, in the layout view, the power rail PG is separated from the fin FN.

[0108] In some embodiments, method 800A further includes the following operation: In a logic cell, in a layout view, at least one signal rail partially overlaps with a fin. For illustration, as... Figure 7A As shown, in the logic unit, in the layout view, for example, at least one signal rail SL containing signal rail 732 partially overlaps with fin FN.

[0109] Figure 8B According to some embodiments of the present invention, it is used for manufacturing containing Figure 2 The storage device MC0 or shown Figure 3 The flowchart shows the method 800B for the integrated circuit (IC) of the memory device MC1. In order to... Figure 8B The description states that method 800B includes operations S810b, S820b, S830b, and S840b. See below for reference. Figure 4 , Figures 6A-6B or Figures 7A-7B Storage devices and their layout diagrams in Figure 8B The description of method 800B includes exemplary operation diagrams. However, Figure 8B The operations described herein may not be performed in the order shown. In other words, in accordance with the spirit and scope of various embodiments of the invention, operations may be appropriately added, substituted, changed in order, and / or canceled.

[0110] In operation S810b, a fin region is formed in a logic cell where adjacent bit cells are located. The fin regions are separated from each other and extend along the row direction. In some embodiments, the fin regions correspond to... Figure 3 The active regions AA1-AA3 are shown. In some embodiments, the logic unit corresponds to... Figure 3 The logic unit shown is 320 or 340, and the bit unit corresponds to Figure 3The bit unit shown is 310 or 330.

[0111] In operation S820b, the fin region is divided into fin groups. In some embodiments, the fin groups correspond to... Figure 3 Groups T1-T6 are shown. In some embodiments, the distance between at least two adjacent fin groups is different from the distance between another two adjacent fin groups.

[0112] In operation S830b, a fin is generated in the fin region. In some embodiments, the fin corresponds to... Figure 3 The fins shown are 321-326 or 341-346. In some embodiments, the distance between the fins is greater than or equal to the interfin spacing.

[0113] In operation S840b, a transistor is generated. The transistor includes a fin formed in operation S830b. In some embodiments, the transistor corresponds to... Figure 3 Transistors T1-T6 are shown.

[0114] For reference Figure 9 . Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 for designing integrated circuit layout designs according to some embodiments of the present invention. The EDA system 900 is configured to implement... Figure 8A Method 800 or disclosed in the middle Figure 8B One or more operations of the method disclosed in 800B, and in combination Figure 3-4 , Figures 6A-6B and Figures 7A-7B Further explanation. In some embodiments, the EDA system 900 includes an Automatic Placement and Routing (APR) system.

[0115] In some embodiments, the EDA system 900 is a general-purpose computing device that includes a hardware processor 920 and a non-transitory computer-readable storage medium 960. The storage medium 960, among other uses, stores, i.e., computer program code (instructions) 961, i.e., a set of executable instructions. Execution of the instructions 961 by the hardware processor 920 represents (at least partially) some or all of an implementation of an EDA tool, such as methods 800A and 800B.

[0116] Processor 920 is electrically coupled to computer-readable storage medium 960 via bus 950. Processor 920 is also electrically coupled to input / output (I / O) interface 910 and manufacturing tool 970 via bus 950. Network interface 930 is also electrically connected to processor 920 via bus 950. Network interface 930 is connected to network 940, thereby enabling processor 920 and estimation machine-readable storage medium 960 to be connected to external components via network 940. Processor 920 is configured to execute computer program code 961 encoded in computer-readable storage medium 960 to make EDA system 900 available for performing some or all of the described processes and / or methods. In one or more embodiments, processor 920 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0117] In one or more embodiments, the computer-readable storage medium 960 is an electronic, magnetic, fiber-optic, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 960 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 960 includes optical disc read-only memory (CD-ROM), optical disc read / write memory (CD-R / W), and / or digital video optical disc (DVD).

[0118] In one or more embodiments, the storage medium 960 storing computer program code 961 is configured such that an EDA system 900 (where such execution represents (at least partially) EDA tools) can be used to perform part or all of the described process and / or method. In one or more embodiments, the storage medium 960 also stores some or all of the information that helps perform the described process and / or method. In one or more embodiments, the storage medium 960 stores a standard cell library 962, which includes such standard cells disclosed herein, for example, those included in the above references. Figure 4 The memory cells in the cell arrays 410-440 discussed.

[0119] EDA system 900 includes an I / O interface 910. The I / O interface 910 is connected to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 920.

[0120] EDA system 900 also includes a network interface 930 connected to processor 920. Network interface 930 allows EDA system 900 to communicate with network 940, which connects to one or more other computer systems. Network interface 930 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is performed in two or more EDA systems 900.

[0121] The EDA system 900 also includes a manufacturing tool 970 connected to the processor 920. The manufacturing tool 970 is configured to manufacture integrated circuits based on design files processed by the processor 920 and / or the IC layout design as described above. The integrated circuits comprise, for example, components made of... Figure 1 The semiconductor device 100 shown implements a memory device MC0 or MC1.

[0122] EDA system 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 920. The information is transferred to processor 920 via bus 950. EDA system 900 is also configured to receive UI-related information via I / O interface 910. This information is stored as a user interface (UI) 963 on computer-readable medium 960.

[0123] In some embodiments, part or all of the described processes and / or methods are executed as a standalone software application executed by a processor. In some embodiments, part or all of the described processes and / or methods are executed as a software application that is part of an additional software application. In some embodiments, part or all of the described processes and / or methods are executed as a plug-in to a corresponding software application. In some embodiments, part or all of the described processes and / or methods are executed as a software application that is part of an EDA tool. In some embodiments, part or all of the described processes and / or methods are executed as a software application used by an EDA system 900. In some embodiments, tools, such as those available from global electronic design companies, are used. Alternatively, another suitable layout generation tool can be used to generate a layout diagram containing standard cells.

[0124] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (such as digital video discs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), etc.

[0125] Figure 10 This is a block diagram of an IC manufacturing system 1000 and an associated IC manufacturing process according to some embodiments of the present invention; in some embodiments, based on the layout diagram, the IC manufacturing system 1000 is used to manufacture at least one of the following two: (A) one or more semiconductor masks, or (B) at least one element in a semiconductor integrated circuit layer.

[0126] exist Figure 10 In this IC manufacturing system 1000, entities such as design room 1010, mask room 1020, and IC fabrication / manufacturing plant (“fab”) 1030 interact with each other in the design, R&D, and manufacturing cycles and / or services related to the manufacture of IC devices 1040. The entities in the IC manufacturing system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, a single, larger company owns two or more of the design room 1010, mask room 1020, and IC fabrication plant 1030. In some embodiments, two or more of the design room 1010, mask room 1020, and IC fabrication plant 1030 coexist in common facilities and use common resources.

[0127] Design studio (or design team) 1010 generates IC design layout 1011. IC design layout 1011 includes IC device 1040 (e.g., referred to above). Figure 3 The discussion covers various geometries of the storage device MC1) design, for example, Figure 4 , Figure 5 , Figures 6A-6B and / or Figures 7A-7BThe IC layout design is depicted in the diagram. The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1040 to be manufactured. Various layers are combined to form various IC components. For example, a portion of the IC layout diagram 1011 includes various IC components to be formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, such as interlayer interconnect fins, gate electrodes, source and drain electrodes, conductive portions, or vias. The design room 1010 performs appropriate design processes to form the IC layout diagram 1011. The design processes include one or more of logic design, physical design, or placement and routing. The IC layout diagram 1011 exists in one or more data files containing information about the geometric pattern. For example, the IC layout diagram 1011 may be presented in GDSII file format or DFII file format.

[0128] Mask chamber 1020 includes mask data preparation 1021 and mask fabrication 1022. Mask chamber 1020 uses an IC design layout 1011 to fabricate one or more masks 1023 for fabricating various layers of an IC device 1040 according to the IC design layout 1011. Mask chamber 1020 performs mask data preparation 1021, where the IC design layout 1011 is translated into a representative data file (“RDF”). Mask data preparation 1021 provides the RDF to mask fabrication 1022. Mask fabrication 1022 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1023 or a semiconductor wafer 1033. The IC design layout 1011 is manipulated by mask data preparation 1021 to comply with the specific performance requirements of the mask writer and / or the needs of the IC fabrication plant 1030. Figure 10 In this design, data preparation 1021 and mask manufacturing 1022 are shown as separate elements. In some embodiments, data preparation 1021 and mask manufacturing 1022 may be collectively referred to as mask data preparation.

[0129] In some embodiments, mask data preparation 1021 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image distortions, such as those caused by diffraction, interference, and other process effects. OPC adjusts the IC design layout as shown in Figure 1011. In some embodiments, data preparation 1021 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assistance, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, where ILT treats OPC as an inverse imaging problem.

[0130] In some embodiments, data preparation 1021 includes a mask rule checker (MRC), which examines the IC design layout 1011, which has undergone the process in the OPC, using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient space, to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 1011 to compensate for constraints in the mask manufacturing process 1022, which may undo the improved portions performed by the OPC to meet the mask creation rules.

[0131] In some embodiments, data preparation 1021 includes a lithography process check (LPC), an LPC simulation performed by an IC manufacturing plant 1030 to manufacture an IC device 1040. The LPC simulates this process based on an IC design layout 1011 to create a simulated manufactured device, such as IC device 1040. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1011.

[0132] It should be understood that the above description of data preparation 1021 has been simplified for clarity. In some embodiments, data preparation 1021 includes additional components, such as logic operations (LOPs), to modify the IC design layout 1011 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1011 during data preparation 1021 can be performed in various different sequences.

[0133] Following data preparation 1021 and during mask fabrication 1022, a mask 1023 or a set of masks 1023 is fabricated based on the modified IC design layout 1011. In some embodiments, mask fabrication 1022 includes performing one or more photolithographic exposures based on the IC design layout 1011. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 1023 based on the modified IC design layout 1011. The mask 1023 can be formed using various techniques. In some embodiments, a binary lithography technique is used to form the mask 1023. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary intermediate mask version of mask 1023 comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 1023. In the phase-shifting mask (PSM) version of mask 1023, various components in the pattern formed on the phase-shifting mask are configured to have suitable phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be a decaying PSM or an alternating PSM. The mask produced by mask fabrication 1022 is used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1033, in etching processes to form various etched regions in semiconductor wafer 1033, and / or in other suitable processes.

[0134] IC manufacturing plant 1030 includes wafer fabrication 1032. IC manufacturing plant 1030 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 1030 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging integrated circuit products, and a third manufacturing facility can provide other services for the foundry operation.

[0135] IC manufacturing plant 1030 uses one or more masks 1023 manufactured by mask chamber 1020 to manufacture IC device 1040. Therefore, IC manufacturing plant 1030 uses IC design layout 1011 at least indirectly to manufacture IC device 1040. In some embodiments, IC manufacturing plant 1030 uses one or more masks 1023 to manufacture semiconductor wafer 1033 to form IC device 1040. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1011. Semiconductor wafer 1033 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon. Semiconductor wafer 1033 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0136] In some embodiments, a semiconductor device is disclosed. The semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed adjacent to the at least one memory cell and includes a plurality of fins. The plurality of fins are divided into a plurality of fin groups for forming transistors. The distance between two adjacent groups of the plurality of fin groups is different from the distance between another two adjacent groups of the plurality of fin groups.

[0137] In some embodiments, a plurality of fins extend along a first direction extending from a plurality of fin gates, wherein there is a fin spacing between every two adjacent fin gates of the plurality of fin gates. At least one of the plurality of fins is not aligned with the plurality of fin grids.

[0138] In some embodiments, at least one of the plurality of fins is aligned with at least one memory fin of at least one memory cell, or at least one of the plurality of fins is not aligned with the memory fin of at least one memory cell.

[0139] In some embodiments, at least one memory cell includes a plurality of memory fins. The plurality of memory fins extend toward and are separate from the plurality of fins. At least one of the plurality of memory fins is not aligned with the plurality of fins.

[0140] In some embodiments, the plurality of fin groups include a first fin group, a second fin group, and a third fin group for forming corresponding transistors. The second fin group is disposed between the first fin group and the third fin group. At least one of the distances between the first fin group and the second fin group, or between the second fin group and the third fin group, is not an integer multiple of the fin pitch.

[0141] In some embodiments, at least one logic unit further includes a plurality of first conductive rails and a plurality of second conductive rails. The plurality of first conductive rails are disposed in a first conductive layer above the plurality of fins. The plurality of second conductive rails are disposed in the first conductive layer and between the plurality of first conductive rails. In a layout view, the plurality of first conductive rails are separated from the plurality of fins, and in a layout view, at least one of the plurality of second conductive rails partially overlaps with the plurality of fins.

[0142] A semiconductor device is also disclosed, comprising a memory cell and a logic cell. The memory cell has a cell height and includes a plurality of first fins extending along a first direction. The logic cell is adjacent to the memory cell and also has a cell height. The logic cell includes a plurality of second fins. The plurality of second fins extend along the first direction based on the cell height and a plurality of fin grids extending along the first direction. A fin spacing is present between each pair of adjacent fin grids. At least one of the plurality of second fins is substantially aligned with at least one of the plurality of first fins, and at least one of the plurality of second fins is not aligned with the plurality of fin grids.

[0143] In some embodiments, the plurality of second fins are divided into a plurality of fin groups for forming transistors, and the plurality of fin groups include a first fin group and a second fin group adjacent to the first fin group. The distance between the top edge of the first fin in the first fin group and the top edge of the second fin adjacent to the first fin in the second fin group is not an integer multiple of the fin pitch.

[0144] In some embodiments, the plurality of fin groups further includes a third fin group. A first fin group is configured to form a first transistor, a second fin group is configured to form a second transistor, and a third fin group is configured to form a third transistor. A second fin group is disposed between the first and third fin groups. The distance between the first and second fin groups is different from the distance between the second and third fin groups.

[0145] In some embodiments, the plurality of second fins are divided into a plurality of fin groups for forming respective transistors. The distance between the top edge of the first fin in the first fin group of the plurality of fin groups and the top edge of the second fin adjacent to the first fin in the second fin group of the plurality of fin groups is greater than an integer multiple of the fin pitch.

[0146] In some embodiments, in a layout view, at least one of the plurality of first fins is aligned with at least one of the plurality of fin grids. The plurality of first fins are separated from the plurality of second fins along a first direction. The distance between one of the plurality of first fins and one of the plurality of second fins is different from the distance between another of the plurality of first fins and another of the plurality of second fins.

[0147] In some embodiments, the logic unit further includes a plurality of first conductive rails and a plurality of second conductive rails. The plurality of first conductive rails are disposed in a first conductive layer above the plurality of first fins and the plurality of second fins and extend along a first direction. The plurality of second conductive rails are disposed in the first conductive layer, disposed between the plurality of first conductive rails and extending along the first direction. In a layout view, the plurality of first conductive rails are separated from the plurality of second fins, and in the layout view, at least one of the plurality of second conductive rails partially overlaps with the plurality of second fins.

[0148] In some embodiments, the plurality of second fins are divided into a plurality of fin groups for forming a transistor. The width of the plurality of first conductive rails is less than or equal to the distance between two adjacent fin groups in the plurality of fin groups. The width of the plurality of second conductive rails is greater than or equal to the width of one of the plurality of second fins.

[0149] In some embodiments, the plurality of second fins are divided into a plurality of fin groups. The plurality of second conductive rails are divided into a plurality of rail groups, and adjacent pairs in the plurality of rail groups are separated from each other by one of the plurality of first conductive rails. In a layout view, the plurality of fin groups and the plurality of rail groups overlap, and the number of the plurality of fin groups is equal to the number of the plurality of rail groups.

[0150] In some embodiments, the memory cell further includes a plurality of third conductive rails. The plurality of third conductive rails are disposed in the first conductive layer and extend along a first direction. In a layout view, the plurality of third conductive rails partially overlap with the plurality of first fins. The plurality of third conductive rails are not aligned with at least one of the plurality of first conductive rails and the plurality of second conductive rails.

[0151] A method is also disclosed, comprising the following operations: In a logic cell adjacent to a memory cell, within the cell height of a logic cell equal to the cell height of a memory cell in a layout view, at least three fin groups, separated from each other and extending along a first direction, are formed for forming corresponding transistors in an integrated circuit.

[0152] In some embodiments, forming at least three fin groups includes at least one of the following two operations: forming at least one fin in the at least three fin groups that is aligned with at least one memory fin of a memory cell; or forming at least one fin in the at least three fin groups that is not aligned with a memory fin of a memory cell.

[0153] In some embodiments, at least three fin groups include a first fin group, a second fin group, and a third fin group. In a layout view, the second fin group is disposed between the first fin group and the third fin group. The distance between the top edge of the first fin in the first fin group and the top edge of the second fin adjacent to the first fin in the second fin group is not an integer multiple of the fin spacing between every two adjacent fin spacings.

[0154] In some embodiments, the method further includes the following operations: In an integrated circuit, in a logic cell, a plurality of first conductive rails are formed in a first conductive layer above at least three fin groups. In the logic cell, a plurality of second conductive rails are formed in the first conductive layer. In a layout view, the plurality of second conductive rails are disposed between the plurality of first conductive rails.

[0155] In some embodiments, in a layout view, the plurality of fins of the logic cells are separate from the plurality of memory fins of the memory cells formed in the integrated circuit. The plurality of memory fins extend toward the plurality of fins. In the layout view, at least one of the plurality of fins is not aligned with the plurality of memory fins.

[0156] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art will understand that the invention can be readily used as a basis for designing or modifying other processes or structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device comprising: at least one memory cell; and at least one logic cell disposed proximate to the at least one memory cell, comprising: a plurality of fins, wherein the plurality of fins are divided into a plurality of fin groups for forming transistors, wherein a distance between two adjacent groups of the plurality of fin groups is different from a distance between two other adjacent groups of the plurality of fin groups, wherein the plurality of fins extend along a first direction in which a plurality of fin grids extend, wherein there is a fin pitch between each adjacent two of the plurality of fin grids, at least one of the plurality of fin groups completely overlaps a respective one of the fin grids, and at least one of the plurality of fin groups does not overlap a respective one of the fin grids, the plurality of fin grids are arranged in parallel and extend across an area of the at least one memory cell and the at least one logic cell.

2. The semiconductor device of claim 1, wherein at least one of the plurality of fins is not aligned with the plurality of fin grids.

3. The semiconductor device of claim 1, wherein at least one of the plurality of fins is aligned with at least one memory fin of the at least one memory cell, or at least one of the plurality of fins is not aligned with the memory fins of the at least one memory cell.

4. The semiconductor device of claim 1, wherein the at least one memory cell comprises a plurality of memory fins, the plurality of memory fins extend toward and are separate from the plurality of fins, and at least one of the plurality of memory fins is not aligned with the plurality of fins.

5. The semiconductor device of claim 1, wherein the plurality of fin groups comprises a first fin group, a second fin group, and a third fin group for forming respective transistors, the second fin group is disposed between the first fin group and the third fin group, and at least one of a distance between the first fin group and the second fin group or a distance between the second fin group and the third fin group is not an integer multiple of the fin pitch.

6. The semiconductor device of claim 1, wherein, the at least one logic cell further comprises: a plurality of first conductive tracks disposed in a first conductive layer above the plurality of fins; and a plurality of second conductive tracks disposed in the first conductive layer and disposed between the plurality of first conductive tracks, wherein, in a layout view, the plurality of first conductive tracks are separate from the plurality of fins, and in the layout view, at least one of the plurality of second conductive tracks partially overlaps the plurality of fins.

7. A semiconductor device comprising: a memory cell having a cell height, comprising: a plurality of first fins extending along a first direction; and a logic cell adjoining the memory cell and having the cell height, comprising: a plurality of second fins extending along the first direction and a plurality of fin grids extending along the first direction based on the cell height, wherein there is a fin pitch between each adjacent two of the plurality of fin grids, wherein at least one of the plurality of second fins is substantially aligned with at least one of the plurality of first fins, and at least one of the plurality of second fins is not aligned with the plurality of fin grids, wherein the plurality of second fins are divided into a plurality of fin groups for forming transistors, and the plurality of fin groups include a first fin group and a second fin group adjacent to the first fin group, the first fin group completely overlaps with a corresponding one of the fin grids, and the second fin group does not overlap with a corresponding one of the fin grids, the plurality of fin grids are arranged in parallel and extend across a region of the memory cells and the logic cells.

8. The semiconductor device of claim 7, wherein, a distance between a top edge of a first fin in the first fin group and a top edge of a second fin adjacent to the first fin in the second fin group is not an integer multiple of the fin pitch.

9. The semiconductor device of claim 8, wherein, the plurality of fin groups further include a third fin group, and the first fin group is configured for forming a first transistor, the second fin group is configured for forming a second transistor, and the third fin group is configured for forming a third transistor, the second fin group is disposed between the first fin group and the third fin group, and a distance between the first fin group and the second fin group is different from a distance between the second fin group and the third fin group.

10. The semiconductor device of claim 7, wherein, the plurality of second fins are divided into a plurality of fin groups for forming respective transistors, a distance between a top edge of a first fin in a first fin group of the plurality of fin groups and a top edge of a second fin adjacent to the first fin in a second fin group of the plurality of fin groups is greater than an integer multiple of the fin pitch.

11. The semiconductor device of claim 7, wherein, in a layout view, at least one of the plurality of first fins is aligned with at least one of the plurality of fin grids, the plurality of first fins are separated from the plurality of second fins along the first direction, and a distance between one of the plurality of first fins and one of the plurality of second fins is different from a distance between another one of the plurality of first fins and another one of the plurality of second fins.

12. The semiconductor device of claim 7, wherein, the logic cells further include: a plurality of first conductive tracks disposed in a first conductive layer above the plurality of first fins and the plurality of second fins and extending along the first direction; and a plurality of second conductive tracks disposed in the first conductive layer and between the plurality of first conductive tracks and extending along the first direction, wherein, in a layout view, the plurality of first conductive tracks are separated from the plurality of second fins, and in a layout view, at least one of the plurality of second conductive tracks partially overlaps with the plurality of second fins.

13. The semiconductor device of claim 12, wherein, the plurality of second fins are divided into a plurality of fin groups for forming transistors, a width of the plurality of first conductive tracks is less than or equal to a distance between two adjacent ones of the plurality of fin groups, and a width of the plurality of second conductive tracks is greater than or equal to a width of one of the plurality of second fins.

14. The semiconductor device of claim 12, wherein, the plurality of second fins are divided into a plurality of fin groups, the plurality of second conductive tracks are divided into a plurality of track groups, and adjacent two of the plurality of track groups are separated from each other by one of the plurality of first conductive tracks, and in a layout view, the plurality of fin groups and the plurality of track groups overlap, and a number of the plurality of fin groups is equal to a number of the plurality of track groups.

15. The semiconductor device of claim 12, wherein, The memory cell further includes: a plurality of third conductive tracks disposed in the first conductive layer and extending along the first direction, wherein, in a layout view, the plurality of third conductive tracks partially overlap the plurality of first fins, and the plurality of third conductive tracks are not aligned with at least one of the plurality of first conductive tracks and the plurality of second conductive tracks.

16. A method of fabricating an integrated circuit, comprising: in a logic cell disposed proximate to a memory cell, within a cell height of the logic cell equal to a cell height of the memory cell in a layout view, forming at least three fin groups of a plurality of fins separated from each other and extending along a first direction for forming respective transistors in the integrated circuit, wherein the plurality of fins extend along a first direction in which a plurality of fin grids extend, wherein each adjacent two of the plurality of fin grids have a fin pitch therebetween, at least one of the at least three fin groups completely overlaps a respective one of the fin grids, and at least one of the at least three fin groups does not overlap a respective one of the fin grids, the plurality of fin grids are arranged in parallel and extend across an area of the memory cell and the logic cell.

17. The method of claim 16, wherein, the forming the at least three fin groups includes at least one of: forming at least one fin in the at least three fin groups that is aligned with at least one memory fin of the memory cell; or forming at least one fin in the at least three fin groups that is not aligned with the memory fin of the memory cell.

18. The method of claim 16, wherein: the at least three fin groups include a first fin group, a second fin group, and a third fin group, in a layout view, the second fin group is disposed between the first fin group and the third fin group, and a distance between a top edge of a first fin in the first fin group and a top edge of a second fin adjacent to the first fin in the second fin group is not an integer multiple of the fin pitch between each adjacent two of the fin pitch.

19. The method of claim 16, further comprising: in the logic cell, forming a plurality of first conductive tracks in a first conductive layer over the at least three fin groups in the integrated circuit; and forming a plurality of second conductive tracks in the first conductive layer, wherein, in a layout view, the plurality of second conductive tracks are disposed between the plurality of first conductive tracks. in a layout view, 20. The method of claim 16, wherein, a plurality of fins of the logic cell are separated from a plurality of memory fins of the memory cell formed in the integrated circuit, wherein the plurality of memory fins extend toward the plurality of fins, and at least one of the plurality of fins is not aligned with the plurality of memory fins. ​

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