Integrated circuit and method of forming the same

Abstract

Integrated circuits are disclosed. The integrated circuits include a conductive track, a signal track, at least one first via, and at least one first conductive portion. The at least one first via is disposed between a first conductive layer and a second conductive layer and couples a first signal track of the signal track to at least one of the conductive track. The first signal track is configured to transmit a supply signal through the at least one first via and the at least one of the conductive track to at least one element of the integrated circuit. The at least one first conductive portion is disposed between the first conductive layer and the second conductive layer. The at least one first conductive portion is coupled to the at least one of the conductive track and is separate from the first signal track. Embodiments of the invention also relate to methods of forming integrated circuits.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated circuits and methods of forming the same. BACKGROUND

[0002] Integrated circuits (ICs) have experienced exponential growth. The design of ICs has produced generations of products with smaller size and more complex circuitry. The increasingly dense ICs have brought advantages in speed, functionality, and cost, but also increasingly difficult design and manufacturing problems. SUMMARY

[0003] According to an aspect of embodiments of the present invention, there is provided an integrated circuit, comprising: a plurality of conductive tracks disposed in a first conductive layer; a plurality of signal tracks disposed in a second conductive layer above the first conductive layer; at least one first via disposed between the first conductive layer and the second conductive layer and coupling a first signal track of the plurality of signal tracks to at least one of the plurality of conductive tracks, wherein the first signal track is configured to transmit a supply signal through the at least one first via and the at least one of the plurality of conductive tracks to at least one element of the integrated circuit; and at least one first conductive section disposed between the first conductive layer and the second conductive layer, wherein the at least one first conductive section is coupled to the at least one of the plurality of conductive tracks and is separate from the first signal track.

[0004] According to another aspect of embodiments of the present invention, there is provided an integrated circuit, comprising: a first plurality of conductive tracks disposed in a first conductive layer and extending in a first direction, wherein the first plurality of conductive tracks is configured to transmit a power signal to at least one element of the integrated circuit; a second plurality of conductive tracks disposed in the first conductive layer and extending in the first direction, wherein, in a layout, the second plurality of conductive tracks is disposed between the first plurality of conductive tracks and is separate from each other, wherein the second plurality of conductive tracks is configured to transmit a data signal to the at least one element of the integrated circuit; at least one first via disposed between the first conductive layer and a second conductive layer above the first conductive layer and coupling one of the first plurality of conductive tracks to a power track disposed in the second conductive layer; and at least one first conductive section disposed between the first conductive layer and the second conductive layer above the first conductive layer, wherein, in the layout, the at least one first conductive section at least partially overlaps at least two adjacent conductive tracks of the second plurality of conductive tracks, and the at least one first conductive section contacts the at least two adjacent conductive tracks of the second plurality of conductive tracks and is separate from a signal track disposed in the second conductive layer and immediately adjacent to the power track.

[0005] According to yet another aspect of embodiments of the application, there is provided a method of forming an integrated circuit, comprising: forming a plurality of conductive tracks; forming a film structure over the plurality of conductive tracks; patterning the film structure to form a first pattern; filling the first pattern with a conductive material to form a first conductive structure, the first conductive structure comprising at least one first conductive portion contacting at least one first track of the plurality of conductive tracks; forming a dielectric structure covering the at least one first conductive portion; and removing portions of the film structure and portions of the dielectric structure to expose portions of a second track of the plurality of conductive tracks; and filling the removed portions of the film structure and the removed portions of the dielectric structure with a conductive material to form a second conductive structure, the second conductive structure comprising a first via contacting the exposed portions of the second track and a signal track contacting the first via. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read with the accompanying drawings. It is noted that the components of the various embodiments illustrated are not necessarily drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A-1B is a layout of an integrated circuit (IC) according to some embodiments of the application.

[0008] Figure 2 is a cross-sectional schematic of a layout corresponding to Figure 1A or Figure 1B according to some embodiments of the application.

[0009] Figures 3A-3C is a layout of an IC according to some embodiments of the application.

[0010] Figure 4 is a layout of an IC according to some embodiments of the application.

[0011] Figures 5A-5C is a cross-sectional schematic of a layout corresponding to Figure 4 according to some embodiments of the application.

[0012] Figure 6 is a flowchart of a method for manufacturing an IC according to some embodiments of the application.

[0013] Figures 7A-7G is a schematic of various processes of a method according to some embodiments of the application, shown in a cross-sectional view of a portion of an IC corresponding to Figure 4 . Figure 6

[0014] Figure 8 is a layout of an IC according to some embodiments of the application.

[0015] ​Figures 9A-9C This corresponds to some embodiments of the present invention. Figure 8 A cross-sectional schematic diagram of the layout diagram.

[0016] Figures 10A-10C According to some embodiments of the present invention, in the corresponding Figure 8 The cross-sectional view of the IC portion is shown Figures 5A-5C A schematic diagram of the various processes of the method.

[0017] Figure 11A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0018] Figure 11B This corresponds to some embodiments of the present invention. Figure 11A The layout diagram of the IC.

[0019] Figure 12A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0020] Figure 12B This corresponds to some embodiments of the present invention. Figure 12A The layout diagram of the IC.

[0021] Figure 13A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0022] Figure 13B This corresponds to some embodiments of the present invention. Figure 13A The layout diagram of the IC.

[0023] Figure 14A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0024] Figure 14B This corresponds to some embodiments of the present invention. Figure 14A The layout diagram of the IC.

[0025] Figure 15A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0026] Figure 15B This corresponds to some embodiments of the present invention. Figure 15A The layout diagram of the IC.

[0027] Figure 16A This is a circuit diagram of an IC according to some embodiments of the present invention.

[0028] Figure 16B This corresponds to some embodiments of the present invention. Figure 16A The layout diagram of the IC.

[0029] Figure 17A is a circuit diagram of an IC according to some embodiments of the application.

[0030] Figures 17B-17E is a layout diagram of an IC of an IC corresponding to Figure 17A according to some embodiments of the application.

[0031] Figure 18A is a circuit diagram of an IC according to some embodiments of the application.

[0032] Figure 18B is a layout diagram of an IC of an IC corresponding to Figure 18A according to some embodiments of the application.

[0033] Figure 19A is a circuit diagram of an IC according to some embodiments of the application.

[0034] Figure 19B is a layout diagram of an IC of an IC corresponding to Figure 19A according to some embodiments of the application.

[0035] Figure 20 is a flowchart of a method for manufacturing an IC according to some embodiments of the application.

[0036] Figure 21 is a block diagram of a system for designing an IC layout design according to some embodiments of the application.

[0037] Figure 22 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments, or examples, for implementing different components of the provided subject matter. Each of the following embodiments can be implemented alone or in combination with one another. For simplicity, the following description of a particular embodiment can not include a detailed description of features that are not relevant to that embodiment. However, where the features are relevant to an embodiment, a detailed description of those features will be set forth in the description of that embodiment. Moreover, although the drawings represent embodiments of the application, the drawings and the associated descriptions are samples only and do not limit the scope of the application. It is understood that when a particular feature is described as being formed on or over another feature, the particular feature can be formed directly on or over the other feature or intervening features can also be present. In addition, the drawings are not necessarily drawn to scale.

[0039] The terms used in this specification have their common meanings in the art and in the specific text in which each term is used. The use of examples in this specification, including instances of any terms discussed herein, is illustrative only and is not intended to limit the scope or meaning of the invention or any exemplary terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0040] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish different elements. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0041] In this specification, the term "coupling" may also be referred to as "electrical coupling," and the term "connection" may be referred to as "electrical connection." "Coupling" and "connection" may also be used to indicate that two or more elements cooperate with or interact with each other.

[0042] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. Structures may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0043] As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, within which any approximation varies according to the respective fields to which it pertains, and whose range is subject to the broadest interpretation understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, the given value or range should generally be within 20%, preferably within 10%, and more preferably within 5%. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred, or imply other approximations.

[0044] Now for reference Figure 1A and Figure 1B . Figure 1A This is a layout diagram 100A of an integrated circuit (IC) according to some embodiments of the present invention, and Figure 1Ais a layout diagram 100B of an IC. For simplicity of illustration of the layout diagram 100A or diagram 100B, only a few patterns disposed in one metal layer, e.g., in some embodiments, the metal layer is a zero metal (M0) layer hereinafter, are shown.

[0045] For illustration in Figure 1A , the layout diagram 100A contains conductive tracks P01, P02, S01, S02, S03 and S04, conductive portions 111, 112, 121, 122 and 123, and cut portions CT. For simplicity, each of the conductive tracks S01, S02, S03 and S04 is referred to as S0 hereinafter for illustration, as each of the conductive tracks S01, S02, S03 and S04 operates in a similar manner in some embodiments.

[0046] The conductive tracks P01, P02 and S0 are disposed in the same metal layer, which is the M0 layer in some embodiments and are separated from each other in the layout diagram. In the layout diagram, the conductive tracks S0 are disposed between the conductive tracks P10 and P20. The conductive portion 111 is disposed on the conductive track P01, and the conductive portion 112 is disposed on the conductive track P02. The conductive portions 121-123 are disposed on and between at least two adjacent conductive tracks S0. Specifically, the conductive portion 121 is disposed on and between the conductive tracks S03 and S04. The conductive portion 122 is disposed on and between the conductive tracks S02 and S03. The conductive portion 123 is disposed on and between the conductive tracks S01 and S02. Optionally, in the layout diagram, the conductive portion 121 partially overlaps the conductive tracks S03 and S04; the conductive portion 122 partially overlaps the conductive tracks S02 and S03; and the conductive portion 123 partially overlaps the conductive tracks S01 and S02. Each of the cut portions CT is disposed across one of the conductive tracks S0. For example, referring to Figure 1A , the cut portion CT with the label is disposed across the conductive track S02.

[0047] In some embodiments, the conductive tracks P01 and P02 are configured to receive a power supply signal (which is at least discussed with reference to Figure 4 and Figures 5A-5C ), which is disposed in another metal layer, e.g., in some embodiments, the metal layer is a first metal (M1) layer hereinafter. The M1 layer is disposed above the M0 layer in which the conductive tracks P01 and P02 are disposed. In various embodiments, the conductive tracks P01 and P02 are denoted as power supply conductive tracks to transmit a power supply signal, which contains, for example, a power voltage signal (which is denoted as VDD discussed with reference to Figure 4 ) or a reference voltage signal (which is denoted as VSS discussed with reference to Figure 4 ). In some other embodiments, the conductive tracks P01 and P02 are referred to as a pair of power supply conductive tracks and are configured to transmit power supply signals with different voltages from each other.

[0048] In some embodiments, the conductive tracks S0 are configured to receive data signals disposed in the same metal layer (i.e., M0 layer) in which the conductive tracks P01 and P02 are disposed. In various embodiments, the conductive tracks S0 are denoted as signal conductive tracks to transmit data signals containing, for example, signals (denoted as D1 and D2 shown in Figure 4 In some other embodiments, at least two of the conductive tracks S0 are coupled to each other to transmit the same data signal.

[0049] In some embodiments, each of the cutouts CT is configured to cut at least one pattern in the layout 100A to divide this pattern into two parts. In various embodiments, the cutouts CT are removed prior to generating the layout for manufacturing the IC.

[0050] In some embodiments, the conductive portions 111 and 112 are shaped as extended tracks similar to the conductive tracks P01 and P02. In various embodiments, the conductive portion 111 is coupled to the conductive track P01 and spaced apart from a power signal disposed in the M1 layer and coupled to the conductive track P01. In another embodiment, the conductive portion 111 contacts the conductive track P01. Similarly, the conductive portion 112 is coupled to the conductive track P02 and spaced apart from a power signal disposed in the M1 layer and coupled to the conductive track P02. In another embodiment, the conductive portion 112 contacts the conductive track P02. In various embodiments, the conductive portions 111 and 112 are denoted as "V0 tracks" to form additional conductive portions / tracks / paths / patterns on the conductive tracks P01 and P02. Optionally, the height of the conductive tracks P01 or P02 in the M0 layer is increased by disposing the conductive portions 111 or 112 on and above the conductive tracks P01 or P02. In some other embodiments, the conductive tracks P01 and P02 and the conductive portions 111 and 112 are made of the same metal material as each other.

[0051] In some embodiments, the conductive portions 121, 122, and 123 are shaped as blocks. In various embodiments, the conductive portion 121 is coupled between the conductive tracks S03 and S04 and spaced apart from a data signal disposed in the M1 layer (refer to at least Figure 4 and Figures 5A-5CIn another embodiment, the conductive portion 121 contacts the conductive tracks S03 and S04. Similarly, the conductive portion 122 is coupled between the conductive tracks S02 and S03, and the conductive portion 123 is coupled between the conductive tracks SOI and S02. Each of the conductive portions 122 and 123 is spaced apart from the data signal provided in the Ml layer. In another embodiment, the conductive portion 122 contacts the conductive tracks S02 and S03, and the conductive portion 123 contacts the conductive tracks SOI and S02. In various embodiments, the conductive portions 121, 122, and 123 are denoted as "M0 jumpers" to form additional conductive portions / traces / tracks / patterns on the conductive tracks SO and disposed across at least two adjacent conductive tracks SO. Optionally, the height of the conductive tracks SO in the M0 layer is increased by disposing the conductive portions 121, 122, or 123 on and above the conductive tracks SO. In some other embodiments, the conductive tracks SO and the conductive portions 121, 122, and 123 are made of the same metal material as each other.

[0052] The structure of the layout 100B of the IC is similar to that of the layout 100A of the IC as shown in Figure 1A , and thus the similar detailed description is omitted. In comparison with Figure 1A , the layout 100B as shown in Figure 1B contains the conductive portion 124 disposed on the conductive tracks SO instead of the conductive portions 121-123. The conductive portion 124 is disposed on and between the conductive tracks S02 and S03. Optionally, in the layout, the conductive portion 124 partially overlaps with the conductive tracks S02 and S03. In some embodiments, the conductive portion 124 has a structure or arrangement similar to that of the conductive portions 121-123 as shown in Figure 1A .

[0053] Figure 1A and Figure 1B the number and arrangement of the conductive portions or conductive tracks as shown in Figure 1A are for illustration purposes. Various numbers and arrangements of the conductive portions or conductive tracks for implementing the layout 100A in Figure 1B or the layout 100B in Figure 1A are within the contemplation of the present disclosure. For example, in some embodiments, in addition to the conductive portions 121, 122, and 123 or the conductive tracks P01, P02, and SO as shown in , the layout 100A contains a conductive track disposed between the conductive tracks P01, P02 and immediately adjacent to the conductive tracks SO in the layout.

[0054] Figure 2 Reference is now made to Figure 2 . Figure 1A is a layout 100A or Figure 1BFig. 2 is a cross-sectional schematic view of a layout 200 of the layout 100B of Fig. 1B. For ease of understanding, elements of the layout 200 of embodiments of Figure 1A or Figure 1B Fig. 1A are designated with the same reference numbers as in Figure 2

[0055] For ease of understanding, each of the layouts 300A, 300B, and 300C of embodiments of Figure 2 Fig. 1A or Fig. 1B is illustrated in Figure 1A and Figure 1B Fig. 2, as discussed with respect to the embodiments illustrated in Figures 1A-1B Fig. 2. The conductive portion 213 is disposed across the conductive tracks P01 and P02 and the conductive track S0. As illustrated in

[0056] Reference is now made to Figures 3A-3C . Figures 3A-3C Figs. 3A, 3B, and 3C are layouts 300A, 300B, and 300C, respectively, of an IC according to some embodiments of the application. The structure of each of the layouts 300A, 300B, and 300C of the IC is similar to the structure of the layout 100A of the IC as illustrated in Figure 1A Fig. 1A or the layout 100B of the IC as illustrated in Figure 1B Fig. 1B, and therefore similar detailed descriptions are omitted. For ease of understanding, each of the layouts 300A, 300B, and 300C of embodiments of Figure 1A or Figure 1B Fig. 1A are designated with the same reference numbers as in Figures 3A-3C In contrast to

[0057] or Figure 1A Fig. 1A, each of the layouts 300A, 300B, and 300C illustrated in Figure 1B Fig. 3A, 3B, and 3C, respectively, further includes gate portions 311 and 312 disposed across the conductive tracks P01 and P02 and the conductive track S0. As illustrated in Figures 3A-3C Fig. 3A, 3B, and 3C, respectively, further includes gate portions 311 and 312 disposed across the conductive tracks P01 and P02 and the conductive track S0. As illustrated in Figures 3A-3C Fig. 3A, 3B, and 3C, respectively, further includes gate portions 311 and 312 disposed across the conductive tracks P01 and P02 and the conductive track S0. As illustrated in

[0058] In some embodiments, the gate portions 311 and 312 are formed in an active region below the M0 layer to form gate terminals of transistors included in the IC. In various embodiments, the gate portions 311 and 312 include polysilicon (PO) and are formed by a gate formation process, also referred to as a "PO process" using a polysilicon mask.

[0059] ​In some embodiments, the distance between two adjacent gates, e.g., referring to Figures 3A-3C The gate sections 311 and 312 are denoted as gate pitch Dl. The gate pitch Dl is also referred to as polysilicon pitch Dl hereinafter. In some other embodiments, the distance between two adjacent conductive tracks, e.g., referring to Figures 3A-3C The track sections S01 and S02 are denoted as M0 pitch D2. In alternative embodiments, at least one of the polysilicon pitch Dl or the M0 pitch D2 is limited by a design rule in a layout map to an IC, and the design rule is associated with a manufacturing process or technology of the IC.

[0060] To illustrate in Figure 3A , the layout map 300A includes the conductive sections 121, 122, and 123 shaped as blocks and disposed on and between the conductive tracks S0. The layout map 300A also includes a pair of conductive sections 111 and 112 shaped as extended tracks and disposed on a pair of conductive tracks P01 and P02, respectively. For each of the conductive sections 121, 122, and 123, it is shaped as a square, and the width of each of the conductive sections 121, 122, and 123 is approximately equal to one M0 pitch D2. Alternatively, the size of each of the conductive sections 121, 122, and 123 is approximately equal to the square of the M0 pitch D2 (i.e., M0 pitch D2*M0 pitch D2).

[0061] The distance between the corresponding corners of two adjacent conductive sections is approximately in the range of half of the polysilicon pitch Dl to one polysilicon pitch Dl (i.e., 0.5*polysilicon pitch Dl ~ 1*polysilicon pitch Dl). As shown in Figure 3A , the corner of the conductive section 121 is separated from the corresponding corner of the conductive section 122 by a distance C1, and the distance C1 is approximately in the above range.

[0062] In addition, the width of each of the conductive sections 111 and 112 is substantially equal to or less than the width of each of the conductive tracks P01 and P02. In some embodiments, the length of each of the conductive sections 111 and 112 is also substantially equal to or less than the length of each of the conductive tracks P01 and P02.

[0063] In some embodiments, the distance between one conductive section denoted as a V0 track and one conductive section denoted as an M0 jumper is approximately in the range of half of the polysilicon pitch Dl to 1.2 times of the polysilicon pitch Dl (i.e., 0.5*polysilicon pitch Dl ~ 1.2*polysilicon pitch Dl). As shown in Figure 3A , the conductive section 111 is denoted as a V0 track disposed on one of the conductive tracks P01 and P02. The conductive section 123 is denoted as an M0 jumper disposed on at least two adjacent conductive tracks S0. The conductive section 111 is separated from the conductive section 123 disposed adjacent to the conductive section 111 by a distance C2. The C2 distance is approximately in the range discussed above.

[0064] In comparison to the embodiment shown in FIG. 3A, the layout 300B further includes one conductive portion 124 shaped as a rail block and disposed on and between the conductive tracks S0. In some embodiments, the conductive portion 124 is shaped as a rectangular block, and the length LI of the conductive portion 124 is greater than twice the polysilicon pitch Dl (i.e., LI > 2* polysilicon pitch Dl). Figure 3A In some embodiments, the distance between one conductive portion representing a V0 track and another conductive portion representing an M0 jumper in the layout 300C is not limited. For example, referring to FIG. 3C, the distance between the conductive portion 111 representing a V0 track and the conductive portion 124 representing an M0 jumper can be less than 0.5* polysilicon pitch Dl.

[0065] Figure 3B In some embodiments, the distance between one conductive portion representing a V0 track and another conductive portion representing an M0 jumper in the layout 300C is not limited. For example, referring to FIG. 3C, the distance between the conductive portion 111 representing a V0 track and the conductive portion 124 representing an M0 jumper can be less than 0.5* polysilicon pitch Dl.

[0066] In comparison to the embodiment shown in FIG. 3A, the layout 300B further includes one conductive portion 124 shaped as a rail block and disposed on and between the conductive tracks S0. In some embodiments, the conductive portion 124 is shaped as a rectangular block, and the length LI of the conductive portion 124 is greater than twice the polysilicon pitch Dl (i.e., LI > 2* polysilicon pitch Dl). Figure 3A In comparison to the embodiment shown in FIG. 3A, the layout 300B further includes one conductive portion 124 shaped as a rail block and disposed on and between the conductive tracks S0. In some embodiments, the conductive portion 124 is shaped as a rectangular block, and the length LI of the conductive portion 124 is greater than twice the polysilicon pitch Dl (i.e., LI > 2* polysilicon pitch Dl).

[0067] In some embodiments, the conductive portions 121, 122, and 123 are each shaped as a square, and the width thereof is approximately equal to one M0 pitch D2. Alternatively, the size of each of the conductive portions 121, 122, and 123 is approximately equal to the square of the M0 pitch D2 (i.e., M0 pitch D2*M0 pitch D2). Similar to the embodiment shown in FIG. 3A, the length of each of the conductive portions 121, 122, and 123 is approximately equal to the length of the conductive tracks P01 and P02. Figure 3A Figure 3C In some embodiments, the distance between one conductive portion representing a V0 track and another conductive portion representing an M0 jumper in the layout 300C is not limited. For example, referring to FIG. 3C, the distance between the conductive portion 111 representing a V0 track and the conductive portion 124 representing an M0 jumper can be less than 0.5* polysilicon pitch Dl.

[0068] In some embodiments, the distance between one conductive portion representing a V0 track and another conductive portion representing an M0 jumper in the layout 300C is not limited. For example, referring to FIG. 3C, the distance between the conductive portion 111 representing a V0 track and the conductive portion 124 representing an M0 jumper can be less than 0.5* polysilicon pitch Dl. Figure 3C

[0069] ​​​In some embodiments, layout diagram 300C is generated from at least one mask (this references...). Figure 22 (To be discussed). For example, conductive portions 111 and 112 are patterned using a first mask. The remaining conductive portions 121, 122, and 123 are patterned using a second mask. Therefore, layout 300C has fewer design constraints compared to layouts 300A or 300B that are patterned using a single mask.

[0070] Figures 3A-3C The structures and arrangements of layout diagrams 300A, 300B, and 300C shown are given for illustrative purposes. Various structures and arrangements of layout diagrams 300A, 300B, and 300C for implementing ICs are within the scope of this invention. For example, in some embodiments, in the layout diagrams, at least one of conductive portions 121, 122, 123, or 124 is disposed on, between, or across three or more conductive rails S0.

[0071] For reference Figure 4 . Figure 4 This is a layout diagram 400 of an IC according to some embodiments of the present invention. For ease of understanding, regarding... Figure 1A or Figure 1B Layout diagram 400 of the embodiment, as shown Figure 4 The components in the document are assigned the same reference number.

[0072] In order to Figure 4 As illustrated, layout diagram 400 includes conductive rails P01, P02, and P03 disposed in layer M0 and extending along the row direction, as well as conductive rails S01, S02, S03, and S04. In some embodiments, for simplicity of illustration, conductive rails S01, S02, S03, and S04 are referred to as S0 hereinafter. In the layout diagram, conductive rails P01 and P02 are separated from each other by conductive rail S0, and conductive rails P02 and P03 are separated by... Figure 4 The additional conductive rails, not shown, are separate from each other. In some embodiments, conductive rail P01 is identical to conductive rail P03. The structure of conductive rails P01, P02, and S0 in layout figure 400 is similar to that shown below. Figure 1A The layout diagram shown is structural, and therefore similar detailed descriptions are omitted.

[0073] The layout 400 also includes conductive portions 411a, 411b, 412a, 412b, and 421 disposed on the conductive tracks P01, P02, and S0, signal tracks P11, P12, S11, and S12 disposed in the M1 layer, and vias 431, 432, 433, and 434 disposed between the M0 layer and the M1 layer. In the layout, the signal tracks P11, P12, S11, and S12 are separated from each other and extend in the column direction. Optionally, in the layout, the signal tracks P11, P12, S11, and S12 are disposed above and across the conductive tracks P01, P02, P03, and S0. In the layout, the vias 431, 432, 433, and 434 overlap at least two of the conductive tracks P01, P02, and S0 and the signal tracks P11, P12, S11, and S12. Specifically, in the layout, the via 431 overlaps the conductive track P01 and the signal track P11; the via 434 overlaps the conductive track P02 and the signal track P12; the via 432 overlaps the conductive track S01 and the signal track S11; and the via 433 overlaps the conductive track S03 and the signal track S12.

[0074] In the layout, the conductive portions 411a and 411b are disposed on the conductive track P01 and separated from each other. In the layout, the via 431 is disposed between the conductive portions 411a and 411b. Optionally, one conductive portion, denoted as a V0 track, is disposed on the conductive track P01. Such a conductive portion includes several separated portions, including, for example, the conductive portions 411a and 411b, as referenced in Figure 4 . Further, in the layout, at least one via is disposed between the separated portions. As referenced in Figure 4 , in the layout, the via 431 is disposed between the separated portions that are the conductive portions 411a and 411b. Similarly, in the layout, the conductive portions 412a and 412b are disposed on the conductive track P02 and separated from each other. In the layout, the via 434 is disposed between the conductive portions 412a and 412b.

[0075] The conductive portion 421 is disposed on and between the conductive tracks S02 and S03. The conductive portion 421 is shaped as a track block and extends in the row direction. Optionally, at least one conductive portion, denoted as an M0 jumper, extends parallel to the conductive track S0. In some embodiments, in the layout, such a conductive portion is disposed on and between the conductive track S0 and separated from another conductive portion, denoted as a V0 track. For example, in the layout, the conductive portion 421, denoted as an M0 jumper, is separated from the conductive portion 411b or 412b, denoted as a V0 track.

[0076] In some embodiments, signal tracks P11 and P12 are configured to provide power signals to conductive tracks P01 and P02. In various embodiments, signal track P11 is configured to provide a voltage signal different from that of signal track P12. For example, signal track P11 is configured to provide a voltage VDD to a power voltage signal, and signal track P12 is configured to provide a voltage VSS to a reference voltage signal. Voltage VDD is higher than voltage VSS, which in some embodiments is referred to as ground. In alternative embodiments, signal tracks P11 and P12 are denoted as power tracks to provide power signals (e.g., VDD or VSS) to power conductive tracks including, for example, conductive tracks P01, P02, and P03.

[0077] In some embodiments, signal tracks S11 and S12 are configured to provide data signals to conductive track S0. In various embodiments, signal track S11 is configured to provide a data signal different from that of signal track S12. For example, signal track S11 is configured to provide a control signal for controlling a first transistor, and signal track S12 is configured to provide another control signal for controlling a second transistor. In alternative embodiments, signal tracks S11 and S12 are denoted as data tracks to provide data signals to signal conductive tracks including, for example, conductive tracks S01 to S04.

[0078] Reference is now made to Figures 5A-5C . Figure 5A is a cross-sectional schematic view of layout 500A corresponding to layout 400 of Figure 4 , taken along line A-A', in accordance with some embodiments of the present application; Figure 5B is a cross-sectional schematic view of layout 500B corresponding to layout 400 of Figure 4 , taken along line B-B', in accordance with some embodiments of the present application; Figure 5C is a cross-sectional schematic view of layout 500C corresponding to layout 400 of Figure 4 , taken along line C-C', in accordance with some embodiments of the present application. For ease of understanding, with respect to layouts 500A to 500C of embodiments of Figure 4 , elements as in Figures 5A-5C are designated with the same reference numbers.

[0079] For illustration in Figure 5A , signal track P11 extends along line A-A' and across conductive track P01, S0 to conductive track P02. Via 431 is disposed between conductive track P01 and signal track P11 without additional spacing. Conductive portion 412a is disposed on conductive track P02 and is spaced apart from signal track P11. With the above structure, the height of conductive portion 412a is less than the height of via 431.

[0080] In some embodiments, the conductive track P01 is coupled to the signal track P11 through the via 431 to receive the power voltage signal with the voltage VDD. With the above structure, the conductive portion 412a or the conductive track P02 is not coupled to or in contact with the signal track P11 since the conductive portion 412a is separated from the signal track P11. In various embodiments, both the conductive portion 412a and the conductive track P02 are coupled to ground by being separated from the signal track P11. In addition, the conductive track P02 is not coupled to any signal track disposed in the M1 layer and represents a ground track. Similarly, the conductive tracks S0 are not coupled to the signal track P11 since the conductive tracks S0 are separated from the signal track P11.

[0081] To illustrate in Figure 5B , the signal track S11 extends along the line B-B' and across the conductive tracks P01, S0 to the conductive track P02. The conductive portion 411b is disposed on the conductive track P01 and is spaced apart from the signal track S11. Similarly, the conductive portion 412b is disposed on the conductive track P02 and is spaced apart from the signal track S11. The conductive portion 421 is disposed on two adjacent conductive tracks S02 and S03 and is also spaced apart from the signal track S11. Optionally, each of the conductive portions 411b, 412b and 421 is spaced apart from the signal track S11 along a vertical direction perpendicular to the line B-B'. Figure 5B In addition, the via 432 is disposed between the conductive track S01 and the signal track S11 without additional spacing. With the above structure, the height of the conductive portion 411b, 421 or 412b is less than the height of the via 432.

[0082] In comparison with the embodiment shown in Figure 5A , the layout 500B also shows the conductive portions 511 and 512 and the vias 521 and 522. The conductive portions 511 and 512 are disposed in the active region (not shown) below the M0 layer and the vias 521 and 522 are disposed between the active region and the M0 layer. Specifically, the via 521 is disposed between the conductive portion 511 and the conductive track S01 without additional spacing. The via 522 is disposed between the conductive portion 512 and the conductive track S03 without additional spacing.

[0083] In some embodiments, the conductive portion 511 is coupled to the conductive track S01 through the via 521. The conductive track S01 is also coupled to the signal track S11 through the via 432 to receive the data signal provided to the conductive portion 511. In addition, the conductive portion 512 is coupled to the conductive track S03 through the via 522 and the conductive track S03 is also coupled to the conductive track S02 through the conductive portion 421. Optionally, at least two adjacent conductive tracks including, for example, the conductive tracks S02 and S03 are coupled together through a conductive portion including, for example, the conductive portion 421, which represents an M0 jumper.

[0084] In some embodiments, the conductive portions 511 and 512 are disposed in the active region to form a source terminal or a drain terminal of a transistor included in the IC. In various embodiments, the conductive portions 511 and 512 are hereinafter referred to as metal-like defined (MD) portions. In alternative embodiments, the vias 521 and 522 coupled from the MD portions 511 and 512 to other elements of the IC are hereinafter referred to as via defined (VD) vias.

[0085] In some embodiments, the MD portions include a portion of at least one metal layer, e.g., copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or one or more of another metal or material suitable for providing a low resistance electrical connection between elements included in the IC, i.e., a resistance level lower than a predetermined threshold corresponding to one or more tolerance levels based on resistance affecting circuit performance. In some other embodiments, the MD portions include a portion of a doped semiconductor substrate and / or an epitaxial layer, e.g., based on an implantation process, having a doping level sufficient for the portion to have a low resistance level. In various embodiments, the doped MD portions include silicon (Si), SiGe, silicon carbide (SiC), boron (B), phosphorus (P), arsenic (As), gallium (Ga), a metal as discussed above, or one or more of another material suitable for providing a low resistance level. In some embodiments, the MD portions include a dopant having a doping concentration of about 1*1016per cubic centimeter (cm -3 ) or greater.

[0086] To illustrate in Figure 5C , the signal track S12 extends along the line C-C' and across the conductive track P01, S0 to the conductive track P02. The conductive portion 411b is disposed on the conductive track P01 and spaced apart from the signal track S12. Similarly, the conductive portion 412b is disposed on the conductive track P02 and spaced apart from the signal track S12. Optionally, each of the conductive portions 411b and 412b is separated from the signal track S12 in a vertical direction perpendicular to the line C-C' as shown in Figure 5C . Further, the via 433 is disposed between the conductive track S03 and the signal track S12 without additional spacing. With the above structure, the height of the conductive portion 411b or 412b is less than the height of the via 433.

[0087] In some embodiments, the conductive track S03 is coupled to the signal track S12 through the via 433 to receive a data signal provided to the conductive track S03. The conductive track P01 or P02 is not coupled to the signal track P11 to receive a signal equivalently represented as ground.

[0088] With Figure 5AThe layout 500C also shows the MD sections 513 and 514 and the VD vias 523 and 524 compared to the embodiment shown in FIG. 5. The via 523 is disposed between the MD section 513 and the conductive track S01 without additional spacing, and the via 524 is disposed between the MD section 514 and the conductive track P02 without additional spacing. Correspondingly, as shown in FIG. 5B, the conductive tracks P01 and S0 are coupled together through the MD sections 513 and 514 and the VD vias 523 and 524, respectively. Figure 5B As shown in FIG. 5, the structures of the MD sections 513 and 514 or the vias 523 and 524 are similar to those of the MD sections 511 and 512 or the vias 521 and 522, and thus the similar detailed descriptions are omitted.

[0089] In some approaches, no other conductive sections are disposed on the conductive tracks in the M0 layer. With such a structure, the resistance coupling between the conductive tracks in the M1 layer and the signal tracks is substantially contributed by the height of the conductive tracks and the size of the vias coupling between the M0 layer and the M1 layer. The resistance affects the IR drop issue and also reduces the working speed of the IC.

[0090] Compared to the above approaches, in the M0 layer, an additional conductive section, e.g., the conductive section 412a, is disposed on the conductive track, e.g., the conductive track P02. This additional conductive section 412a is spaced apart from the M1 layer to increase the height of the conductive track P02 in the M0 layer without changing the cell height of the corresponding layout 400. Thus, the resistance of the conductive track P02, also referred to as the power conductive track, is reduced. The resistance is reduced by disposing the conductive section 412a, denoted as the V0 track, on the top surface of the conductive track P02.

[0091] Further, an additional conductive section, e.g., the conductive section 421, is disposed on and between at least two adjacent conductive tracks, e.g., the conductive tracks S02 and S03. This additional conductive section 421 is also spaced apart from the M1 layer to couple the two adjacent conductive tracks S02 and S03 together as a local interconnect. Thus, the routing for coupling more than two conductive tracks S0 is reduced by disposing the conductive section 421, denoted as the M0 jumper. This also improves the electromagnetic bottleneck and the IC performance of the data signals transmitted in these conductive tracks S0.

[0092] Reference is now made to Figure 6 and Figures 7A-7G . Figure 6 is a method for fabricating an IC including Figure 4 the conductive tracks P01, P02 and S0, the conductive sections 411a, 411b, 412a, 412b and 421, and the vias 431-434 shown in FIG. 4, or Figures 7A-7G a flowchart of the method 600 of fabricating the IC shown in FIG. 4. Figures 7A-7G is a cross-sectional view of a portion of an IC 700 of an IC according to some embodiments of the application, along the line Figure 4 as shown in FIG. 7A. Figure 4The column direction shown indicates Figure 6 The diagram illustrates various processes of method 600. It can be considered that... Figure 6 and Figures 7A-7G Additional operations are provided before, during, and after the illustrated process, and some of the operations described below may be replaced or deleted for additional embodiments of the method. The order of operations / processes may be interchanged. In the various figures and illustrative embodiments, reference numerals are used to denote, for example, elements.

[0093] exist Figure 6 In operation S610, multiple conductive rails are formed within the M0 layer of IC 700. The conductive rails include... Figure 4 The conductive rails P01, P02 and S0 shown are shown, as well as the dielectric material stack between these conductive rails.

[0094] In operation S620, a film structure is formed on the conductive rails. Therefore, the film structure is formed on the MO layer of IC 700. Optionally, the film is deposited on the MO layer. Operations S610-S620 are as follows. Figure 7A The execution is shown in the figure.

[0095] To illustrate, such as Figure 7A As shown, IC 700 includes conductive rails P02, SO2, SO3, and SO4 formed in the M0 layer, a dielectric structure 710, and a film structure 720 formed on the M0 layer. The conductive rails P02, SO2, SO3, and SO4 are separated from each other by the dielectric structure 710. In some embodiments, the material of the dielectric structure 710 is different from the material of the film structure 720. In various embodiments, the dielectric structure 710 and the film structure 720 are isolated from each other. In an optional embodiment, the thickness of the film structure 720 is substantially equal to the distance between the M0 layer and the M1 layer (which is at least...). Figure 7E (as shown in the image).

[0096] In operation S630, the film structure is patterned to form a pattern. In some embodiments, the patterning operation utilizes photolithography and etching to space specific patterns in the film structure. Operation S630 is as follows: Figure 7B The process is as shown in the diagram.

[0097] To illustrate, such as Figure 7BAs shown, patterns 731 and 732 are formed in the membrane structure 720. Specifically, pattern 731 is formed in the membrane structure 720 and above and between conductive rails S03 and S04. At the surface of the MO layer and the bottom of the membrane structure 720, portions of conductive rails S03 and S04, as well as portions of the membrane structure 720, are removed to form pattern 731. Furthermore, pattern 732 is formed in the membrane structure 720 and above and between conductive rails P02. Similarly, around the surface of the MO layer, portions of the membrane structure 720 are removed to form pattern 732.

[0098] In operation S640, a pattern is filled with a conductive material to form a first conductive structure, which includes a first conductive portion that contacts a first conductive rail. In some embodiments, the first conductive portion corresponds to... Figure 4 At least one of the conductive portions 411a or 411b shown, and the first conductive rail corresponds to Figure 4 The conductive rail P01 is shown. In other embodiments, the first conductive portion corresponds to... Figure 4 At least one of the conductive portions 412a or 412b shown, and the first conductive rail corresponds to Figure 4 The conductive rail P02 is shown. Processing operation S640, as follows... Figures 7C-7D As shown in the figure.

[0099] In some embodiments, the filling operation in S640 is also referred to as a multi-metal gap filling process. In various embodiments, the pattern is filled with a conductive material to form an interconnect structure between two adjacent metal layers, such as M0 layer and M1 layer.

[0100] To illustrate, such as Figure 7C As shown, conductive structure 740 is formed on film structure 720 and is also filled in patterns 731 and 732.

[0101] In some embodiments, the material of the conductive structure 740 is the same as the material of the conductive portions S02 to S04 and P02 formed in the MO layer. Optionally, the material of pattern 731 or 732 is the same as the material of the conductive portions S04 or P02. In various embodiments, if the conductive structure 740 physically contacts the conductive portions S02 to S04 and P02 formed in the MO layer, the conductive structure 740 and the conductive portions S02 to S04 and P02 are coupled to each other. In optional embodiments, the conductive material is copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), graphene, or any other suitable conductive material.

[0102] To illustrate, such as Figure 7D As shown, conductive portions 751 and 752 are formed. In some embodiments, conductive portion 752 corresponds to... Figure 4at least one of the contact conductive tracks P01 or P02 as shown in FIG. 7B. As such, the conductive portion 752 is able to form a first conductive portion that contacts the first conductive track as discussed in operation S640. In other embodiments, the conductive portion 751 corresponds to contacting Figure 4 a conductive portion 421 of two adjacent conductive tracks S0 as shown in FIG. 7B.

[0103] As shown in FIG. 7B, the conductive portion 751 is formed on the M0 layer and on portions of the conductive tracks S03 and S04. Optionally, the conductive portion 751 is formed on and between the conductive tracks S03 and S04. Further, the conductive portion 752 is formed on the M0 layer and also on the conductive track P02. Further, the conductive portions 751 and 752 and the film structure 720 have a same surface that is substantially parallel to the surface of the M0 layer. Optionally, all of the conductive portions 751 and 752 and the film structure 720 form a substantially flat surface above the M0 layer. In some embodiments, the conductive portions 751 and 752 are made of the same conductive material as the conductive structure 740. Figure 7D In some embodiments, operation S640 further includes the following operations. The pattern of the conductive material and the film structure is polished. In some other embodiments, the polishing operation in S640 is performed by chemical mechanical polishing (CMP) to remove the extra conductive material on the top of the surface. In various embodiments, portions of the structure are removed in conjunction with the CMP and dry etching.

[0104] In operation S650, a dielectric structure is formed that covers the first conductive portion. In some embodiments, the dielectric structure is formed and stacked on the remaining structure after performing operation S640. In other embodiments, the M1 layer is created by forming the dielectric structure on the film structure and as shown in FIG. 7C.

[0105] Figure 7E As shown in FIG. 7C, the dielectric structure 760 is created by forming on the film structure 720 and the conductive portions 751 and 752. In some embodiments, the material of the dielectric structure 710 is the same as the material of the dielectric structure 760. In various embodiments, the thickness of the dielectric structure 760 is substantially equal to the distance between the M1 layer and a second metal layer (M2, not shown) above the M1 layer.

[0106] To illustrate, as shown in FIG. 7C, the dielectric structure 760 is created by forming on the film structure 720 and the conductive portions 751 and 752. In some embodiments, the material of the dielectric structure 710 is the same as the material of the dielectric structure 760. In various embodiments, the thickness of the dielectric structure 760 is substantially equal to the distance between the M1 layer and a second metal layer (M2, not shown) above the M1 layer. Figure 7E In operation S660, portions of the film structure and portions of the dielectric structure are removed to expose portions of a second conductive track of the conductive tracks. In some embodiments, the second conductive track corresponds to one of the conductive tracks S0 as shown in FIG. 7B.

[0107] Figure 4 In operation S660, portions of the film structure and portions of the dielectric structure are removed to expose portions of a second conductive track of the conductive tracks. In some embodiments, the second conductive track corresponds to one of the conductive tracks S0 as shown in FIG. 7B.

[0108] ​​In operation S670, the removed portions of the film structure and the dielectric structure are filled with a conductive material to form a second conductive structure that includes a via that contacts the exposed portion of the second conductive track and a signal track that contacts the via. In some embodiments, the via included in the second conductive structure corresponds to the via 432 shown in Figure 4 and the signal track included in the second conductive structure corresponds to the data track Sll shown in Figure 4 Operation S660-S670 are processed as shown in Figures 7F-7G

[0109] To illustrate, as shown in Figure 7F portions of the film structure 720 and the dielectric structure 760 are removed and expose a structure 781. Further, the removed structures 720 and 760 are filled with a conductive material (not shown) to form a via 771 and the structure 781 that corresponds to a signal track. In some embodiments, the via 771 and the structure 781 are in contact with each other and correspond to the via 432 and the signal track Sll, respectively, as shown in Figure 4 Likewise, as shown in Figure 7G portions of the film structure 720 and the dielectric structure 760 are removed and expose a structure 782. Further, the removed structures 720 and 760 are filled with a conductive material (not shown) to form a via 772 and the structure 782 that corresponds to a signal track. The via 772 and the structure 782 are in contact with each other.

[0110] As shown in Figure 7F the IC 700 also includes the via 771 formed on the M0 layer and connected to the structure 781 formed in the Ml layer. One end of the via 771 is formed on the conductive track S02 and the other end of the via 771 is formed in the Ml layer. With the above operations, the height of the via 771 is substantially equal to or slightly greater than the distance between the conductive track S02 and the structure 781. Alternatively, the height of the via 771 is substantially equal to or slightly greater than the distance between the M0 layer and the Ml layer.

[0111] In some embodiments, the via 771 is configured to couple between the conductive track S02 formed in the Ml layer and the structure 781. In various embodiments, the structure 781 is a signal track configured to provide a data signal. In some other embodiments, the via 771 is coupled between the conductive track S02 and the data track Sll and corresponds to the via 432 shown in Figure 4 or Figure 5B

[0112] ​​Furthermore, as discussed above, the conductive portion 751 is formed on the M0 layer and separated from the M1 layer by the dielectric structure 760. Optionally, the conductive portion 751 is spaced apart from the M1 layer. Using the operation discussed above, the height of the conductive portion 751 is less than the height of the via 771. Similar to the structure of the conductive portion 751, the conductive portion 752 is formed on the M0 layer and spaced apart from the M1 layer. Moreover, the height of the conductive portion 752 is less than the height of the via 771.

[0113] In some embodiments, the conductive portion 751 is coupled between conductive rails S03 and S04. In some other embodiments, the conductive portion 751 is referred to as an M0 jumper and corresponds to... Figure 4 or Figure 5B The conductive portion 421 is shown. In various embodiments, the conductive portion 752 is coupled to the conductive rail P02. In some other embodiments, the conductive portion 752 is referred to as the V0 rail and corresponds to... Figure 4 or Figure 5A The conductive part 412a shown.

[0114] In some embodiments, the operation of forming conductive portions 751 and 752 and via 771 using the above arrangement between layers M0 and M1 is referred to as a dual damascene process. This establishes a connection between the conductive portions 751 and 752 in layer M1 and structure 781. In some other embodiments, the operation of forming conductive portions 751 and 752 and via 771 using the above arrangement between layers M0 and M1 is referred to as a single damascene process. The via 771 formed by the single damascene process has a greater height compared to embodiments performed by the dual damascene process.

[0115] To illustrate, such as Figure 7G As shown, IC 700 includes a via 772 formed on layer M0 and connected to structure 782 formed in layer M1. One end of via 772 is formed on conductive rail P02, and the other end is formed in layer M1. Using the above operation, similar to the structure of via 771, the height of via 772 is substantially equal to or slightly greater than the distance between conductive rail P02 and structure 782.

[0116] In some embodiments, via 772 is configured to couple between conductive rail P02 formed in layer M1 and structure 782. In various embodiments, structure 782 is a power rail configured to provide a power signal. In some other embodiments, via 772 is coupled between conductive rail P02 and power rail P11, and corresponds to Figure 4 or Figure 5A The through hole 431 shown.

[0117] As mentioned above, the integrated circuit in the present application is provided with conductive parts formed on the M0 layer and spaced apart from the M1 layer. The conductive parts denoted as V0 tracks are provided on the power conductive tracks, and the conductive parts denoted as M0 jumpers are provided on at least two signal conductive tracks. Thus, the routing between the M0 layer and the M1 layer is reduced, and the resistance of the power conductive tracks or the signal conductive tracks is also reduced by the additional arrangement of the conductive parts.

[0118] Figures 7A-7G The structure of the layout diagram 800 is given for illustration purposes. The above description of the various structures of the elements mentioned in the Figures 7A-7G is within the contemplation of the present application.

[0119] Reference is now made to Figure 8 . Figure 8 is a layout diagram 800 of an IC according to some embodiments of the present application. The structure of the layout diagram 800 is similar to the structure of the layout diagram 400 as shown in Figure 4 , and thus a similar detailed description is omitted. For ease of understanding, the patterns shown in the layout diagram 800 with respect to the embodiments of Figure 4 are designated with the same reference numbers as the elements in Figure 8 .

[0120] Compared to the embodiments shown in Figure 4 , the layout diagram 800 contains conductive parts 811 and 812 provided on the conductive tracks P01 and P02, respectively. The layout diagram 800 also contains a conductive part 821 provided on and between the conductive tracks S02 and S03. The layout diagram 800 also contains vias 831, 832 and 433 provided between the M0 layer and the M1 layer. Specifically, in the layout diagram, the via 831 overlaps the conductive track P01, the conductive part 811 and the signal track P11; the via 832 overlaps the conductive track S02', the conductive track S03, the conductive part 821 and the signal track S11; and the via 433 has a similar structure as shown in Figure 4 .

[0121] In some embodiments, the conductive part 811 corresponds to the conductive part 411a or 411b shown in Figure 4 . Compared to the conductive part 411a or 411b of Figure 4 , the conductive part 811 is not divided into multiple parts. Similarly, the conductive part 812 corresponds to the conductive part 412a or 412b shown in Figure 4 . In various embodiments, the conductive part 811 has a similar structure / arrangement as the conductive part 812. In some other embodiments, the conductive part 821 corresponds to the conductive part 421 shown in Figure 4 , and has a similar structure / arrangement as the conductive part 421.

[0122] Reference is now made to Figures 9A-9C .Figure 9A is a cross-sectional view of layout 900A of layout 800 corresponding to Figure 8 Figure 9B is a cross-sectional view of layout 900B of layout 800 corresponding to Figure 8 Figure 9C is a cross-sectional view of layout 900C of layout 800 corresponding to Figure 8 Figure 5A The structure of layout 900A is similar to that of layout 500A as shown in Figure 5B Figure 5C The structure / arrangement of layout 900C is similar to that of layout 500C as shown in Figure 8 Figures 9A-9C For ease of understanding, with respect to layouts 900A to 900C of embodiments of

[0123] For illustration in Figure 9A , conductive portion 811 is disposed on conductive track P01. Via 831 is disposed between conductive portion 811 and signal track P11 without additional spacing. Conductive portion 812 is disposed on conductive track P02 and is spaced apart from signal track P11.

[0124] In some embodiments, conductive track P01 is coupled to conductive portion 811 and is also coupled to signal track P11 through via 831 to receive a power voltage signal having voltage VDD. With the above structure, since conductive portion 812 is separated from signal track P11, conductive portion 812 or conductive track P02 is not coupled to signal track P11.

[0125] For illustration in Figure 9B , conductive portion 811 is disposed on conductive track P01 and is spaced apart from signal track S11. Conductive portion 812 is disposed on conductive track P02 and is spaced apart from signal track S11. Conductive portion 821 is disposed on two adjacent conductive tracks S02 and S03. In addition, via 832 is disposed between conductive portion 821 and signal track S11 without additional spacing.

[0126] Compared to the embodiment shown in Figure 9A , layout 900B also shows conductive portions 911 and 912 and vias 921 and 922. In some embodiments, conductive portions 911 and 912 correspond to Figure 5B ​​​​​MD portions 511 and 512, and through holes 921 and 922 respectively correspond to Figure 5B The VD vias 521 and 522 are shown in the diagram. Conductive portions 911 and 912 are referred to as MD portions in the following text, and vias 921 and 922 are referred to as VD vias in the following text.

[0127] refer to Figure 9B VD through hole 921 is provided between MD part 911 and conductive rail S01 without any additional gap. VD through hole 922 is provided between MD part 912 and conductive rail S03 without any additional gap.

[0128] In some embodiments, the MD section 911 is coupled to the conductive rail S01 via a VD through-hole 921. Furthermore, the MD section 912 is coupled to the conductive rail S03 via a VD through-hole 922. The conductive rail S03 is also coupled to the conductive section 821 and further coupled to the signal rail S11 via a through-hole 832 to receive data signals provided to the conductive rail S03 and also to the MD section 911. On the other hand, the conductive rail S03 is also coupled to the conductive rail S02 via the conductive section 821. Therefore, the conductive rail S02 is also configured to receive data signals transmitted from the signal rail S11.

[0129] In order to Figure 9C As described, conductive portions 913 and 914, as well as through holes 923 and 924, are disposed below conductive rails P01, P02, and S0. In some embodiments, conductive portions 913 and 914 respectively correspond to Figure 5C The MD portions 513 and 514 are in the middle, and the through holes 923 and 924 correspond to respectively Figure 5C VD through holes 523 and 524 in the middle.

[0130] Now for reference Figures 10A-10C And return to reference Figure 6 . Figures 10A-10C According to some embodiments of the present invention, in the corresponding Figure 8 In the cross-sectional view of IC 1000, along as... Figure 8 The column direction shown indicates Figure 6 A schematic diagram of some processes of the method. Figure 10A It shows Figure 6 The operation S650 in the middle, and has the same as Figure 7E The structure shown is similar to the one described above. Figure 10B It shows Figure 6 The operations S660-S670 in the middle, and have the same as Figure 7F and 7G The structure shown is similar to the structure shown below, and similar detailed descriptions are omitted.

[0131] like Figure 10AAs shown, conductive portion 1051 is disposed on portions of conductive rail S03, film structure 720, and conductive rail S04, and is disposed on and above layer M0. Conductive portion 1052 is disposed on conductive rail P02 and is disposed on and above layer M0. Similar to Figure 7E The conductive portions 751 and 752, conductive portions 1051 and 1052, and film structure 720 shown form a substantially flat surface above the MO layer. In some embodiments, conductive portion 1052 corresponds to a contact of conductive portion 811 or 812. Figure 8 At least one of the conductive rails P01 or P02 shown. In other embodiments, the conductive portion 1051 corresponds to a contact. Figure 8 The conductive portion 821 of the two adjacent conductive rails S0 shown.

[0132] To explain Figure 6 The operation shown is as follows: Figure 10A As shown, conductive rail P02 corresponds to the first conductive rail, and conductive portion 1052 corresponds to the first conductive portion that contacts the first conductive rail. (Reference) Figure 6 and Figure 10A In operation S650, a dielectric structure 760 is formed and covers the conductive portion 1052. The dielectric structure 760 also covers the conductive portion 1051.

[0133] about Figure 6 and Figure 10B In operations S660-S670, a portion of the structure is removed and filled with conductive material, forming a through-hole 771 and a structure 781 corresponding to the signal rail, as shown in the reference. Figure 6 and Figures 7F-7G As discussed. In some embodiments, through-hole 771 and structure 781 correspond to through-hole 832 and signal rail S11, respectively, as Figure 8 As shown. Figure 10B As shown, via 771 is formed on layer M0 and connected to structure 781 formed in layer M1, which is similar to Figure 7F The embodiment shown.

[0134] In some embodiments, the conductive portion 1051 is referred to as an M0 jumper, and corresponds to Figure 8 or Figure 9B The conductive portion 821 is shown. In some other embodiments, the conductive portion 1052 is referred to as the V0 rail, and corresponds to... Figure 8 or Figure 9B The conductive portion 812 is shown. In various embodiments, the through hole 771 corresponds to... Figure 8 or Figure 9C The through hole 433 is shown.

[0135] In some embodiments, the method further includes the following operation: The dielectric structure is further patterned to form patterns other than the pattern formed in operation S630. These patterns are then filled with a conductive material to form through-holes that contact the first conductive portion formed in operation S640. Such through-holes contact the first conductive portion and a power rail disposed adjacent to the second conductive rail. Figure 10C As explained in the description, in some embodiments, the first conductive part corresponds to the conductive part 1052, and the power rail corresponds to the structure 782 corresponding to the power rail. Thus, the through hole corresponds to the through hole 1072 that contacts the first conductive part and the power rail.

[0136] like Figure 10C As shown, a through-hole 1072 is formed on the conductive portion 1052 and connected to the structure 782 formed in the M1 layer. One end of the through-hole 1072 is formed on the conductive portion 1052, and the other end of the through-hole 1072 is formed in the M1 layer. Using this operation, the height of the through-hole 1072 is less than the distance between the conductive rail P02 and the structure 782. Furthermore, the height of the through-hole 1072 is less than... Figure 7F , Figure 7G or Figure 10B The height of at least one of the through holes 771 shown.

[0137] In some embodiments, via 1072 is configured to couple between conductive portion 1052 formed in layer M1 and structure 782. In various embodiments, structure 782 is referred to as a power rail to provide a power signal. Conductive portion 1052 is referred to as V0 rail and corresponds to... Figure 9A The conductive portion 811 is shown. Furthermore, the through-hole 1072 corresponds to... Figure 9A The through-hole 831 is shown. Therefore, the through-hole 1072 is coupled to... Figure 8 or Figure 9A The conductive part 1052 shown is between the power rail P11.

[0138] Figure 10A , Figure 10B and Figure 10C The structure is given for illustrative purposes. The above... Figure 10A , Figure 10B and Figure 10C Various structures of the elements mentioned herein are within the scope of consideration of this invention.

[0139] In order to implement various devices, such as those mentioned above Figure 1A , Figure 1B , Figure 2 , Figures 3A-3C , Figure 4 , Figures 5A-5C , Figure 8 and Figures 9A-9C The layout diagrams discussed are used or modified for use, as described below.Figures 11A-19B The non-limiting examples discussed are shown below. In the various embodiments discussed below, the IC of the present invention is used by... Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A The layout diagrams depicted in the diagrams are used for implementation, and these diagrams correspond to... Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figures 17B-17E , Figure 18B and Figure 19B The circuit diagrams depicted are shown below. To indicate the correspondence between given layout components formed based on given layout components, the same reference indicators are used in each of the layout diagrams and structural depictions, as discussed below.

[0140] For reference Figure 11A . Figure 11A This is a circuit diagram of IC 1100A according to some embodiments of the present invention. To illustrate IC 1100A, the gate terminal of a p-type metal-oxide-semiconductor (PMOS) transistor P1 is coupled to the gate terminal of an n-type metal-oxide-semiconductor (NMOS) transistor N1. The source / drain terminals of PMOS transistor P1 are coupled to the source / drain terminals of PMOS transistor P2 at node A1. The source / drain terminals of NMOS transistor N1 are coupled to the source / drain terminals of NMOS transistor N2 at node B1. Node A1 is also coupled to node B1, as... Figure 11A The connection ZA shown is indicated. To implement the IC 1100A including the connection ZA between nodes A1 and B1 in an embodiment of the present invention, embodiments of layout design and / or structure are provided and discussed below, as referenced... Figure 11B As shown.

[0141] In some embodiments, IC 1100A is used as a unit or unit circuit, wherein the unit or unit circuit can be used as part of a basic unit or device or circuit to implement various devices or circuits. Optionally, in some embodiments, IC 1100A is implemented in various devices or circuits, including, for example, inverters, NAND gates, AND-OR-NOT (AOI) logic gates, flip-flops, etc.

[0142] Figure 11B This corresponds to some embodiments of the present invention. Figure 11AThe layout diagram 1100B of IC 1100A is shown. To simplify the description of layout diagram 1100B, only the implementation diagram is shown. Figure 11A Part of the layout diagram of IC 1100A.

[0143] exist Figure 11B In the description, gates 1111, 1112, and 1113 are arranged in an active region (not shown) and extend along the column direction. In some embodiments, gates 1111, 1112, and 1113 correspond to Figures 3A to 3C The gate portions 311 and 312 are shown. In various embodiments, gates 1111, 1112, and 1113 are patterned as follows: Figure 11B The term "polycrystalline silicon" is shown. Conductive portions 1121, 1122, 1123, 1124, and 1125 extend along the column direction and are hereinafter referred to as MD portions. In various embodiments, conductive portions 1121, 1122, 1123, 1124, and 1125 are patterned as follows: Figure 11B The “MD” shown.

[0144] MD portions 1121 and 1122 are arranged in the active region, serving as the source / drain of PMOS transistors P1 and P2. Gate 1112 and MD portions 1121 and 1122 together correspond to PMOS transistor P1. Gate 1113, MD portion 1122, and another MD portion (not shown) arranged adjacent to MD portion 1112 together correspond to PMOS transistor P2. In this embodiment, PMOS transistors P1 and P2 share MD portion 1122, which corresponds to PMOS transistors P1 and P2 sharing the MD portion 1122 as described above. Figure 11A Coupled at node A1. MD portions 1123, 1124, and 1125 are arranged in the active region, serving as the source / drain of NMOS transistors N1 and N2. Gate 1111 and MD portions 1123 and 1124 together correspond to NMOS transistor N1. Gate 1112 and MD portions 1124 and 1125 together correspond to NMOS transistor N2. In this embodiment, NMOS transistors N1 and N2 share MD portion 1124, which corresponds to NMOS transistors N1 and N2 being coupled as described above regarding... Figure 11A The coupling is located at node B1.

[0145] Vias 1131 and 1132 are disposed between the active region and the M0 layer. In various embodiments, vias 1131 and 1132 are patterned as follows: Figure 11B The "VD" shown. Through holes 1131 and 1132 are also referred to below as VD through holes, which are mentioned above at least in reference to... Figure 5B The discussion focuses on coupling between the MD portions 1121-1125 in the active region and the conductive rails 1141-1143 in the M0 layer. Figure 11BIn the layout 1100A, the VD via 1131 is arranged between the MD portion 1122 and the conductive track 1141, and the VD via 1132 is arranged between the MD portion 1124 and the conductive track 1142. The VD via 1131 couples the MD portion 1122 to the conductive track 1141. The VD via 1132 couples the MD portion 1124 to the conductive track 1142.

[0146] In some embodiments, the layout 1100B further includes a data track (not shown) arranged in the Ml layer, above the M0 layer, and the data track extends in the column direction and is coupled to the conductive track 1141. With such a structure, a data signal provided from the data track is transmitted through the conductive track 1141, and is also transmitted through the via 1131 to the MD portion 1122. In such embodiments, as discussed above with respect to Figure 11A The node Al is also coupled to the data track to receive the data signal at the node Al.

[0147] The conductive tracks 1141, 1142, and 1143 are arranged in the M0 layer above the active region and extend along the row direction. In some embodiments, the conductive tracks 1141, 1142, and 1143 are patterned as "M0" shown in Figure 11B In some other embodiments, the conductive tracks 1141, 1142, and 1143 are also referred to as signal conductive tracks, which are discussed above at least with respect to Figure 4

[0148] The conductive portion 1151 is arranged in the M0 layer and below the Ml layer. In various embodiments, the conductive portion 1151 is patterned as "M01" shown in Figure 11B In some embodiments, the conductive portion 1151 is shaped as a block and is also referred to as an M0 jumper corresponding to the conductive portions 121-124 as shown in Figures 3A-3C In the layout, the conductive portion 1151 partially overlaps with the conductive tracks 1141 and 1142, the gate 1111, and the VD via 1132. The conductive portion 1151 couples the conductive tracks 1141 and 1142 together. Thus, the MD portion 1122 is coupled to the conductive track 1141 through the VD via 1131, and the conductive track 1141 is also coupled to the conductive track 1142 through the conductive portion 1151. The conductive track 1142 is coupled to the MD portion 1124 through the VD via 1132. With the above structure, the MD portions 1122 and 1124 are together coupled to the conductive portion 1151, which is coupled between the nodes Al and Bl as discussed above with respect to the connection ZA. Figure 11A

[0149] Reference is now made to Figure 12A . Figure 12A ​​is a circuit diagram of an IC 1200A according to some embodiments of the present application. To illustrate the IC 1200A, a gate terminal of a PMOS transistor P1 is coupled to a gate terminal of an NMOS transistor N1; a gate terminal of a PMOS transistor P2 is coupled to a gate terminal of an NMOS transistor N2; a gate terminal of a PMOS transistor P3 is coupled to a gate terminal of an NMOS transistor N3; and a gate terminal of a PMOS transistor P4 is coupled to a gate terminal of an NMOS transistor N4.

[0150] A source / drain terminal of the PMOS transistor P1 is coupled to a node Al; a source / drain terminal of the PMOS transistor P1 is coupled to a source / drain terminal of the PMOS transistor P2 at a node A2; a source / drain terminal of the PMOS transistor P2 is coupled to a source / drain terminal of the PMOS transistor P3 at a node A3; a source / drain terminal of the PMOS transistor P3 is coupled to a source / drain terminal of the PMOS transistor P4 at a node A4; and a source / drain terminal of the PMOS transistor P4 is coupled to a node A5, which is also coupled to the nodes Al and A3.

[0151] Further, a source / drain terminal of the NMOS transistor N1 is coupled to a node Bl; a source / drain terminal of the NMOS transistor N1 is coupled to a source / drain terminal of the NMOS transistor N2; a source / drain terminal of the NMOS transistor N2 is coupled to a source / drain terminal of the NMOS transistor N3 at a node B2; a source / drain terminal of the NMOS transistor N3 is coupled to a source / drain terminal of the NMOS transistor N4; and a source / drain terminal of the NMOS transistor N4 is coupled to a node B3. The node A3 is also coupled to a power rail referred to as VDD. Each of the nodes Bl and B3 is also coupled to another power rail referred to as VSS, and the voltage of the power rail VSS is lower than the voltage of the power rail VDD. The node A4 is also coupled to the node B2, as shown by the connection ZN. Figure 12A To implement the IC 1200A containing the connection ZN between the nodes A4 and B2 in embodiments of the present application, embodiments of layout designs and / or structures are provided and discussed below, as referenced by Figure 12B .

[0152] Figure 12B is a layout diagram 1200B of an IC corresponding to the IC 1200A of Figure 12A according to some embodiments of the present application.

[0153] In the illustration of Figure 12B , the gates 1211, 1212, 1213, and 1214 are arranged as Figure 12Agate terminals of the PMOS transistors P1-P4 or the NMOS transistors N1-N4 in the PMOS transistor P1 and the NMOS transistor N1. The MD sections 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, and 1229 are arranged as Figure 12A source / drain of the PMOS transistors P1-P4 or the NMOS transistors N1-N4 in the PMOS transistor P1 and the NMOS transistor N1.

[0154] The gate 1211 and the MD sections 1220 and 1221 together correspond to the PMOS transistor P1. The gate 1212 and the MD sections 1221 and 1222 together correspond to the PMOS transistor P2. The gate 1213 and the MD sections 1222 and 1223 together correspond to the PMOS transistor P3. The gate 1214 and the MD sections 1223 and 1224 together correspond to the PMOS transistor P4. In such embodiments, the PMOS transistors P1 and P2 share the MD section 1221, which corresponds to the PMOS transistors P1 and P2 being coupled at the node A2 shown in Figure 12A Figure 12A Figure 12A

[0155] Furthermore, the gate 1211 and the MD sections 1225 and 1226 together correspond to the NMOS transistor N1. The gate 1212 and the MD sections 1226 and 1227 together correspond to the NMOS transistor N2. The gate 1213 and the MD sections 1227 and 1228 together correspond to the NMOS transistor N3. The gate 1214 and the MD sections 1228 and 1229 together correspond to the NMOS transistor N4. In such embodiments, the NMOS transistors N2 and N3 share the MD section 1227, which corresponds to the NMOS transistors N2 and N3 being coupled at the node B2 shown in Figure 12A

[0156] ​​​​Conductive tracks 1241, 1242, 1243, 1244, 1245, 1246, 1247, 1248, and 1249 are arranged. Conductive tracks 1242, 1243, 1244, 1245, 1246, 1248, and 1249 are arranged between conductive tracks 1241 and 1247. The width of conductive tracks 1242, 1243, 1244, 1245, 1246, 1248, or 1249 is smaller than the width of conductive tracks 1241 or 1247. In some embodiments, conductive tracks 1242, 1243, 1244, 1245, 1246, 1248, and 1249 are referred to as signal conductive tracks, and conductive tracks 1241 and 1247 are referred to as power conductive tracks, which power conductive tracks are discussed above at least with reference to Figure 4 .

[0157] VD vias 1231, 1232, 1233, 1234, 1235, 1236, 1237, and 1238 are arranged. VD via 1231 couples MD portion 1220 to conductive track 1242. VD via 1232 couples MD portion 1221 to conductive track 1241, which conductive track is also coupled to a power rail (not shown) arranged in the M1 layer. MD portion 1221 and conductive track 1241 together are coupled to the power rail, which corresponds to node A3 being coupled to the power rail VDD as discussed above with respect to Figure 12A . VD via 1233 couples MD portion 1222 to conductive track 1242. VD via 1234 couples MD portion 1223 to conductive track 1244. VD via 1235 couples MD portion 1224 to conductive track 1242. With such a structure, MD portions 1220, 1222, and 1224 are coupled together, which corresponds to nodes A1, A3, and A5 being coupled together as discussed above with respect to Figure 12A .

[0158] Furthermore, VD via 1236 couples MD portion 1225 to conductive track 1247, which conductive track is also coupled to another power rail (not shown) arranged in the M1 layer. MD portion 1225 and conductive track 1247 together are coupled to the power rail, which corresponds to node B1 being coupled to the power rail VSS as discussed above with respect to Figure 12A . VD via 1237 couples MD portion 1227 to conductive track 1245. VD via 1238 couples MD portion 1229 to conductive track 1247, which conductive track is also coupled to the same power rail as the power rail coupled to MD portion 1225. MD portion 1229 and conductive track 1247 together are coupled to the power rail, which corresponds to node B3 being coupled to the power rail VSS as discussed above with respect to Figure 12A .

[0159] VG vias 1251, 1252, 1253, and 1254 are arranged. VG via 1251 couples gate 1211 to conductive rail 1243. VG via 1252 couples gate 1212 to conductive rail 1246. VG via 1253 couples gate 1213 to conductive rail 1249. VG via 1254 couples gate 1214 to conductive rail 1248.

[0160] Conductive portions 1261, 1262, and 1263 are arranged. Conductive portion 1261 is also referred to as an M0 jumper, and in some embodiments corresponds to, for example... Figure 3A or Figure 3C The conductive portions 121, 122, or 123 are shown. Conductive portion 1261 couples conductive rails 1244 and 1245 together. Using this structure, MD portions 1223 and 1227 are coupled together, corresponding to nodes A4 and B2 being coupled as described above. Figure 12A The connection between ZN is discussed.

[0161] Furthermore, conductive portions 1262 and 1263 are also referred to as V0 rails, and correspond to, for example... Figures 3A-3C The conductive portions 111 and 112 are shown. As discussed above with reference to VD vias 1231-1238, conductive portion 1262 is coupled to both conductive rail 1241 and MD portion 1221, which is also coupled to power rail VDD. Conductive portion 1263 is coupled to both conductive rail 1247 and MD portions 1225 and 1229, which are also coupled to power rail VSS.

[0162] For reference Figure 13A . Figure 13A This is a circuit diagram of IC 1300A according to some embodiments of the present invention. In some embodiments, IC 1300A is used as a unit / circuit for implementing two different logic functions, and the unit / circuit is also represented as a two-level unit. To illustrate IC 1300A, the gate terminal of PMOS transistor P1 is coupled to the gate terminal of NMOS transistor N1 at node E1; the gate terminal of PMOS transistor P2 is coupled to the gate terminal of NMOS transistor N2; and the gate terminal of PMOS transistor P3 is coupled to the gate terminal of NMOS transistor N3.

[0163] Furthermore, a source / drain terminal of PMOS transistor P1 is coupled to node Al; a source / drain terminal of PMOS transistor P1 is coupled to a source / drain terminal of PMOS transistor P2 at node A2; a source / drain terminal of PMOS transistor P2 is coupled to a source / drain terminal of PMOS transistor P3 at node A3; and a source / drain terminal of PMOS transistor P3 is coupled to node A4. A source / drain terminal of NMOS transistor N1 is coupled to node Bl; a source / drain terminal of NMOS transistor N1 is coupled to a source / drain terminal of NMOS transistor N2 of node B2; a source / drain terminal of NMOS transistor N2 is coupled to a source / drain terminal of NMOS transistor N3; and a source / drain terminal of NMOS transistor N3 is coupled to node B3. Nodes A2 and A4 are also coupled to a power rail referred to as VDD. Node B2 is also coupled to another power rail referred to as VSS. Reference is made to Figure 13A Node Al is also coupled to node Bl, as shown by connection Z. Node A3 is also coupled to node El at node E2, as shown by connection ZE. Node A3 is also coupled to node B3, as shown by connection ZN. To implement IC 1300A in embodiments of the invention that include connection Z between nodes Al and Bl, connection ZE between nodes El and E2, and connection ZN between nodes A3 and B3, embodiments of layout designs and / or structures are provided and discussed below, as shown in Figure 13B .

[0164] Figure 13B is an IC 1300A of an IC according to some embodiments of the invention. Figure 13A .

[0165] In the description of Figure 13B , gates 1311, 1312, and 1313 are arranged as gate terminals of PMOS transistors P1-P3 or NMOS transistors N1-N3 in Figure 13A . MD portions 1321, 1322, 1323, 1324, 1325, 1326, and 1327 are arranged as source / drain of PMOS transistors P1-P3 or NMOS transistors N1-N3 in Figure 13A .

[0166] Gates 1311 and MD portions 1321 and 1322 together correspond to PMOS transistor P1. Gates 1312 and MD portions 1322 and 1333 together correspond to PMOS transistor P2. Gates 1313 and MD portions 1323 and 1324 together correspond to PMOS transistor P3. In such embodiments, PMOS transistors P1 and P2 share MD portion 1322, which corresponds to PMOS transistors P1 and P2 sharing a common source / drain in Figure 13AThe PMOS transistor P2 and the NMOS transistor N2 share the MD part 1325, which corresponds to the PMOS transistor P2 and the NMOS transistor N2 being coupled at the node B2 shown in Figure 13A The PMOS transistor P3 and the NMOS transistor N3 share the MD part 1327, which corresponds to the PMOS transistor P3 and the NMOS transistor N3 being coupled at the node C2 shown in

[0167] Furthermore, the gate 1311 and the MD parts 1321 and 1325 together correspond to the NMOS transistor N1. The gate 1312 and the MD parts 1325 and 1326 together correspond to the NMOS transistor N2. The gate 1313 and the MD parts 1326 and 1327 together correspond to the NMOS transistor N3. In such embodiments, the NMOS transistors N1 and N2 share the MD part 1325, which corresponds to the NMOS transistors N1 and N2 being coupled at the node B2 shown in Figure 13A The PMOS transistor P1 and the NMOS transistor N1 share the MD part 1321, which corresponds to the PMOS transistor P1 and the NMOS transistor N1 being coupled at the node A1 and B1 being coupled together. The MD part also corresponds to the connection Z shown in Figure 13A between the nodes A1 and B1 being coupled together.

[0168] The conductive tracks 1341, 1342, 1343, 1344, 1345, 1346 and 1347 are arranged. In some embodiments, the conductive tracks 1342, 1343, 1344, 1345 and 1346 are referred to as signal conductive tracks, and the conductive tracks 1341 and 1347 are referred to as power conductive tracks, which power conductive tracks are discussed above at least with reference to Figure 4

[0169] The VD vias 1331, 1332, 1333, 1334, 1335 and 1336 are arranged. The VD via 1331 couples the MD part 1321 to the conductive track 1344. The VD via 1332 couples the MD part 1322 to the conductive track 1341, which also couples to a power rail (not shown) arranged in the M1 layer. The MD part 1322 and the conductive track 1341 together couple to the power rail, which corresponds to the node A2 coupling to the power rail VDD as discussed above with reference to Figure 13A The VD via 1333 couples the MD part 1323 to the conductive track 1343. The VD via 1334 couples the MD part 1324 to the conductive track 1341. Similarly, the MD part 1324 and the conductive track 1341 together couple to the power rail, which corresponds to the node A4 coupling to the power rail VDD as discussed above with reference to Figure 13A The VD via 1335 couples the MD part 1325 to the conductive track 1347, which also couples to another power rail (not shown) arranged in the M1 layer. The MD part 1325 and the conductive track 1347 together couple to the power rail, which corresponds to the node B2 coupling to the power rail VDD as discussed above with reference to Figure 13A ​The power rail VSS discussed. The VG via 1351 couples the MD portion 1327 to the conductive rail 1346.

[0170] The VG vias 1352 and 1353 are arranged. The VG via 1352 couples the gate 1312 to the conductive rail 1345. With such a configuration, the gate 1312 is also coupled to the MD portion 1324 through the conductive rail 1345, which corresponds to the connection ZE discussed above with respect to Figure 13A The VG via 1353 couples the gate 1313 to the conductive rail 1342.

[0171] The conductive portions 1361, 1362, and 1363 are arranged. The conductive portion 1361 is also referred to as the M0 jumper, and in some embodiments corresponds to the conductive portion 121, 122, or 123 shown in Figure 3A or Figure 3C The conductive portion 1361 couples the conductive rails 1343 and 1346 together. With such a structure, the MD portions 1323 and 1327 are coupled together, which corresponds to the nodes A3 and B3 being coupled between the connections ZN discussed above with respect to Figure 13A .

[0172] Furthermore, the conductive portions 1362 and 1363 are also referred to as the V0 rails, and correspond to the conductive portions 111 and 112 shown in Figures 3A-3C The conductive portion 1362 is coupled to both the conductive rail 1341 and the MD portions 1322 and 1324, which are also coupled to the power rail VDD, as discussed above with respect to the VD vias 1331-1336. The conductive portion 1263 is coupled to both the conductive rail 1347 and the MD portion 1325, which is also coupled to the power rail VSS.

[0173] Reference is now made to Figure 14A . Figure 14A is a circuit diagram of an IC 1400A in accordance with some embodiments of the present application. To illustrate the IC 1400A, the gate terminal of the PMOS transistor PI is coupled to the gate terminal of the NMOS transistor Nl, as shown by the connection I. In some embodiments, the connection I is denoted as an input terminal to provide a control signal to both the PMOS transistor PI and the NMOS transistor Nl.

[0174] Furthermore, the source / drain terminal of PMOS transistor P1 is coupled to node Al. The source / drain terminal of PMOS transistor P1 is coupled to node A2. The source / drain terminal of NMOS transistor N1 is coupled to node Bl. The source / drain terminal of NMOS transistor N2 is coupled to node B2. Node Al is also coupled to a power rail referred to as VDD. Node Bl is also coupled to another power rail referred to as VSS. Node A2 is also coupled to node B2 as shown by connection ZN. To implement IC 1400A in embodiments of the invention that include connection ZN between nodes A2 and B2, embodiments of layout designs and / or structures are provided and discussed below as referenced by Figure 14B .

[0175] Figure 14B is an IC 1400A of an IC according to some embodiments of the invention. Figure 14A .

[0176] In the description of Figure 14B , gate 1411 is arranged as Figure 14A the gate terminal of PMOS transistor P1 and NMOS transistor N1 in Figure 14A . MD portions 1421, 1422, and 1423 are arranged as the source / drain of PMOS transistor P1 or NMOS transistor N1 in

[0177] . Figure 14A Gate 1411 and MD portions 1421 and 1422 together correspond to PMOS transistor P1. Gate 1411 and MD portions 1423 and 1422 together correspond to NMOS transistor N1. In such embodiments, PMOS transistors P1 and P2 share MD portion 1422, which corresponds to PMOS transistor P1 being coupled together at nodes A2 and B2 shown in Figure 14A . That MD portion also corresponds to the connection between nodes A2 and B2 being coupled in .

[0178] Conductive tracks 1441, 1442, 1443, 1444, 1445, and 1446 are arranged. In some embodiments, conductive tracks 1442, 1443, 1444, and 1445 are referred to as signal conductive tracks, and conductive tracks 1441 and 1446 are referred to as power conductive tracks, as discussed above at least with reference to Figure 4 .

[0179] VG vias 1431, 1432, and 1433 are arranged. VD via 1431 couples MD portion 1421 to conductive track 1441, which is also coupled to a power rail (not shown) arranged in the M1 layer. MD portion 1421 and conductive track 1441 together are coupled to the power rail, which corresponds to node Al being coupled to a power rail as discussed above with reference to Figure 14A The power rail VDD is discussed. The VD via 1432 couples the MD portion 1422 to the conductive rail 1444. The VD via 1433 couples the MD portion 1423 to the conductive rail 1423, which is also coupled to another power rail (not shown) arranged in the Ml layer. The MD portion 1423 and the conductive rail 1446 together are coupled to the power rail, which corresponds to the node B1 being coupled to the power rail as discussed above with respect to Figure 14A The power rail VSS is discussed.

[0180] The VG via 1451 is arranged. The VG via 1451 couples the gate 1411 to the conductive rail 1445, which is also coupled to a signal rail (not shown) arranged in the Ml layer. The gate 1411 and the conductive rail 1445 together are coupled to the signal rail, which corresponds to the gate of the PMOS transistor PI or the NMOS transistor Nl being coupled to the signal rail as discussed above with respect to Figure 14A The connection I between is discussed.

[0181] The conductive portions 1461, 1462, and 1463 are arranged. The conductive portion 1461 is also referred to as an M0 jumper and in some embodiments corresponds to the conductive portion 121, 122, or 123 as shown in Figure 3A or Figure 3C The conductive portion 1461 couples the conductive rails 1443 and 1444 together.

[0182] Furthermore, the conductive portions 1462 and 1463 are also referred to as V0 rails and in some embodiments correspond to the conductive portions 111 and 112 as shown in Figures 3A-3C The conductive portion 1462 is coupled to both the conductive rail 1441 and the MD portion 1421, which is also coupled to the power rail VDD, as discussed above with respect to the VD vias 1431-1433. The conductive portion 1463 is coupled to both the conductive rail 1446 and the MD portion 1423, which is also coupled to the power rail VSS.

[0183] Reference is now made to Figure 15A . Figure 15A is a circuit diagram of the IC 1500A in accordance with some embodiments of the present application. To illustrate the IC 1500A, the gate terminal of the PMOS transistor PI is coupled to the gate terminal of the NMOS transistor Nl as shown by the connection I. The gate terminal of the PMOS transistor P2 is coupled to the gate terminal of the NMOS transistor N2 also as shown by the connection I. In some embodiments, the structure / arrangement of the connection I is similar to the structure / arrangement of the connection I as shown in Figure 14A .

[0184] Furthermore, a source / drain terminal of PMOS transistor P1 is coupled to node Al; a source / drain terminal of PMOS transistor P1 is coupled to a source / drain terminal of PMOS transistor P2 at node A2; and a source / drain terminal of PMOS transistor P2 is coupled to node A3. A source / drain terminal of NMOS transistor N1 is coupled to node Bl; a source / drain terminal of NMOS transistor N1 is coupled to a source / drain terminal of NMOS transistor N2 at node B2; and a source / drain terminal of NMOS transistor N2 is coupled to node B3. Nodes Al and A3 are also coupled to a power rail referred to as VDD. Nodes Bl and B3 are also coupled to another power rail referred to as VSS. Node A2 is also coupled to node B2, as shown by connection ZN. Figure 15A To implement IC 1500A containing connection ZN between nodes A2 and B2 in embodiments of the invention, embodiments of layout designs and / or structures are provided and discussed below, as referenced to Figure 15B .

[0185] Figure 15B is a layout view 1500B of an IC corresponding to Figure 15A IC 1500A according to some embodiments of the invention.

[0186] In the description of Figure 15B , gates 1511 and 1512 are arranged as gate terminals of PMOS transistors P1-P2 or NMOS transistors N1-N2 in Figure 15A . MD portions 1521, 1522, 1523, 1524, and 1525 are arranged as source / drain terminals of PMOS transistors P1-P2 or NMOS transistors N1-N2 in Figure 15A .

[0187] Gates 1511 and MD portions 1521 and 1522 together correspond to PMOS transistor P1. Gates 1512 and MD portions 1522 and 1523 together correspond to PMOS transistor P2. In such embodiments, PMOS transistors P1 and P2 share MD portion 1522, which corresponds to PMOS transistors P1 and P2 being coupled at node A2 as shown in Figure 15A . Gates 1511 and MD portions 1524 and 1522 together correspond to NMOS transistor N1. Gates 1512 and MD portions 1522 and 1525 together correspond to NMOS transistor N2. In such embodiments, NMOS transistors N1 and N2 share MD portion 1522, which corresponds to NMOS transistors N1 and N2 being coupled at node B2 as shown in Figure 15A . Also, NMOS transistors N1 / N2 and PMOS transistors P1 / P2 share MD portion 1522, which corresponds to nodes A2 and B2 being coupled at Figure 15A The connections ZN are coupled between the nodes shown in the middle.

[0188] The conductive tracks 1541, 1542, 1543, 1544, 1545 and 1546 are arranged. In some embodiments, the conductive tracks 1542, 1543, 1544 and 1545 are referred to as signal conductive tracks, and the conductive tracks 1541 and 1546 are referred to as power conductive tracks, which are discussed above at least with reference to Figure 4 .

[0189] The VD vias 1531, 1532, 1533, 1534 and 1535 are arranged. The VD via 1531 couples the MD part 1521 to the conductive track 1541, which is further coupled to a power rail (not shown) arranged in the M1 layer. The MD part 1521 and the conductive track 1541 together are coupled to the power rail, which corresponds to the node A1 being coupled to the power rail VDD as discussed above with reference to Figure 15A . Figure 15A The VD via 1532 couples the MD part 1522 to the conductive track 1543. The VD via 1533 couples the MD part 1523 to the conductive track 1541. Similarly, the MD part 1523 and the conductive track 1541 together are coupled to the power rail, which corresponds to the node A3 being coupled to the power rail VDD as discussed above with reference to .

[0190] Furthermore, the VD via 1534 couples the MD part 1524 to the conductive track 1546, which is further coupled to another power rail (not shown) arranged in the M1 layer. The MD part 1524 and the conductive track 1546 together are coupled to the power rail, which corresponds to the node B1 being coupled to the power rail VSS as discussed above with reference to Figure 15A . Figure 15A The VD via 1535 couples the MD part 1525 to the conductive track 1546. Similarly, the MD part 1525 and the conductive track 1546 together are coupled to the power rail, which corresponds to the node B3 being coupled to the power rail VSS as discussed above with reference to .

[0191] The VG vias 1551 and 1552 are arranged. The VG via 1551 couples the gate 1511 to the conductive track 1545, which is further coupled to a signal rail (not shown) arranged in the M1 layer. Moreover, the VG via 1552 couples the gate 1512 to the conductive track 1545. The gate 1511 and the conductive track 1545 together are coupled to the signal rail, which corresponds to the gate of the PMOS transistor P1 or the NMOS transistor N1 being coupled to the signal rail VDD as discussed above with reference to Figure 15AThe connection I is discussed between. Similarly, the gate 1512 and the conductive track 1545 are coupled together to the same signal track that is also coupled to the gate 1511, which corresponds to the gate coupling of the PMOS transistor P2 or the NMOS transistor N2 between the connections that are also denoted as the connection I.

[0192] The conductive portions 1561, 1562, and 1563 are arranged. The conductive portion 1561 is also referred to as the M0 jumper, and in some embodiments corresponds to the conductive portion 124 as shown in Figure 3B or Figure 3C . The conductive portion 1561 couples the conductive tracks 1542 and 1543 together.

[0193] Further, the conductive portions 1562 and 1563 are also referred to as the V0 tracks, and in some embodiments correspond to the conductive portions 111 and 112 as shown in Figures 3A-3C . As discussed above with reference to the VD vias 1531-1535, the conductive portion 1562 is coupled to both the conductive track 1541 and the MD portions 1521 and 1523, which are also coupled to the power supply track VDD. The conductive portion 1563 is coupled to both the conductive track 1546 and the MD portions 1524 and 1525, which are also coupled to the power supply track VSS.

[0194] Reference is now made to Figure 16A . Figure 16A is a circuit diagram of the IC 1600A according to some embodiments of the present application. To illustrate the IC 1600A, the gate terminal of the PMOS transistor P1 is coupled to the gate terminal of the NMOS transistor N1 as shown by the connection I1. The gate terminal of the PMOS transistor P2 is coupled to the gate terminal of the NMOS transistor N2 as shown by the connection I2; and the gate terminal of the PMOS transistor P3 is coupled to the gate terminal of the NMOS transistor N3 as shown by the connection I3. In some embodiments, the structure / arrangement of the connections I1, I2, or I3 is similar to the structure / arrangement of the connections I as shown in Figure 14A . In some other embodiments, the connections I1, I2, and I3 are also coupled to different signal tracks (not shown) from each other to transmit different data signals. For example, the connection I1 is coupled to a first signal track; the connection I2 is coupled to a second signal track; and the connection I3 is coupled to a third signal track.

[0195] Furthermore, a source / drain terminal of PMOS transistor P1 is coupled to node Al; a source / drain terminal of PMOS transistor P1 is coupled to a source / drain terminal of PMOS transistor P2 at node A2; a source / drain terminal of PMOS transistor P2 is coupled to a source / drain terminal of PMOS transistor P3 at node A3. A source / drain terminal of PMOS transistor P3 is coupled to node A4. A source / drain terminal of NMOS transistor N1 is coupled to node Bl; a source / drain terminal of NMOS transistor N1 is coupled to a source / drain terminal of NMOS transistor N2; a source / drain terminal of NMOS transistor N2 is coupled to a source / drain terminal of NMOS transistor N3; and a source / drain terminal of NMOS transistor N3 is coupled to node B2. Nodes Al and A3 are also coupled to a power rail referred to as VDD. Node B2 is also coupled to another power rail referred to as VSS. Node A2 is also coupled to node A4. Node A2 is also coupled to node Bl as shown by connection ZN as shown in Figure 16A To implement IC 1600A containing connection ZN between nodes A2 and Bl in embodiments of the invention, embodiments of layout designs and / or structures are provided and discussed below as referenced to Figure 16B .

[0196] Figure 16B is a layout diagram 1600B of an IC corresponding to Figure 16A IC 1600A according to some embodiments of the invention.

[0197] In the description of Figure 16B , gates 1611, 1612, and 1613 are arranged as gate terminals of PMOS transistors P1-P3 or NMOS transistors N1-N3 in Figure 16A . MD portions 1621, 1622, 1623, 1624, 1625, 1626, 1627, and 1628 are arranged as source / drain terminals of PMOS transistors P1-P3 or NMOS transistors N1-N3 in Figure 16A .

[0198] Gates 1611 and MD portions 1621 and 1622 together correspond to PMOS transistor P1. Gates 1612 and MD portions 1622 and 1623 together correspond to PMOS transistor P2. In such embodiments, PMOS transistors P1 and P2 share MD portion 1622, which corresponds to PMOS transistors P1 and P2 being coupled at node A2 as shown in Figure 16A . Gates 1613 and MD portions 1623 and 1624 together correspond to PMOS transistor P3. In such embodiments, PMOS transistors P2 and P3 share MD portion 1623, which corresponds to PMOS transistors P2 and P3 being coupled at node A3 as shown in Figure 16A The gate 1611 and the MD portions 1625 and 1626 together correspond to the NMOS transistor N1. The gate 1612 and the MD portions 1626 and 1627 together correspond to the NMOS transistor N2. The gate 1613 and the MD portions 1627 and 1628 together correspond to the NMOS transistor N3.

[0199] The conductive tracks 1641, 1642, 1643, 1644, 1645, 1646 and 1647 are arranged. In some embodiments, the conductive tracks 1642, 1643, 1644, 1645 and 1646 are referred to as signal conductive tracks, and the conductive tracks 1641 and 1647 are referred to as power conductive tracks, which power conductive tracks are referred to above at least with reference to Figure 4 .

[0200] The VD vias 1631, 1632, 1633, 1634, 1635 and 1636 are arranged. The VD via 1631 couples the MD portion 1621 to the conductive track 1641, which conductive track is further coupled to a power rail (not shown) arranged in the M1 layer. The MD portion 1621 and the conductive track 1641 together couple to the power rail, which corresponds to the node A1 coupling to the power rail VDD as discussed above with reference to Figure 16A . The VD via 1632 couples the MD portion 1622 to the conductive track 1643. The VD via 1633 couples the MD portion 1623 to the conductive track 1641, which conductive track is further coupled to a power rail. Similarly, the MD portion 1623 and the conductive track 1641 together couple to the power rail, which corresponds to the node A3 coupling to the power rail VDD as discussed above with reference to Figure 16A . The VD via 1634 couples the MD portion 1624 to the conductive track 1643. With such a structure, the MD portions 1622 and 1624 are coupled together, which corresponds to the nodes A2 and A4 coupling together as discussed above with reference to Figure 16A .

[0201] Further, the VD via 1635 couples the MD portion 1625 to the conductive track 1644. The VD via 1636 couples the MD portion 1628 to the conductive track 1647, which conductive track is further coupled to another power rail (not shown) arranged in the M1 layer. The MD portion 1628 and the conductive track 1647 together couple to the power rail, which corresponds to the node B2 coupling to the power rail VSS as discussed above with reference to Figure 16A .

[0202] VG vias 1651, 1652, and 1653 are arranged. VG via 1651 couples gate 1611 to a conductive track 1645 that is also coupled to a first signal track (not shown) arranged in the M1 layer. Gate 1611 and conductive track 1645 together couple to the first signal track, which in some embodiments corresponds to connection I1 coupled to the first signal track as discussed above with respect to Figure 16A VG via 1652 couples gate 1612 to a conductive track 1642 that is also coupled to a second signal track (not shown) arranged in the M1 layer. Gate 1612 and conductive track 1642 together couple to the second signal track, which in some embodiments corresponds to connection I2 coupled to the second signal track as discussed above with respect to Figure 16A VG via 1653 couples gate 1613 to a conductive track 1646 that is also coupled to a third signal track (not shown) arranged in the M1 layer. Gate 1613 and conductive track 1646 together couple to the third signal track, which in some embodiments corresponds to connection I3 coupled to the third signal track as discussed above with respect to Figure 16A .

[0203] Conductive portions 1661, 1662, and 1663 are arranged. In some embodiments, conductive portion 1661 is shaped as a rail block and is also referred to as an M0 jumper corresponding to conductive portion 124 as shown in Figure 3B or Figure 3C Conductive portion 1661 couples conductive tracks 1643 and 1644 together. With such a structure, MD portions 1625 and 1622 are coupled together, which corresponds to nodes B1 and A2 being coupled between connections ZN as discussed above with respect to Figure 16A In addition, MD portions 1625, 1622, and 1624 are also coupled together, which corresponds to nodes B1, A2, and A4 being coupled to each other as discussed above with respect to Figure 16A

[0204] In addition, conductive portions 1662 and 1663 are also referred to as V0 rails and in some embodiments correspond to conductive portions 111 and 112 as shown in Figures 3A-3C Conductive portion 1662 is coupled to both conductive track 1641 and MD portion 1621 and 1623, which is also coupled to power rail VDD, as discussed above with respect to VD vias 1631-1636. Conductive portion 1663 is coupled to both conductive track 1647 and MD portion 1628, which is also coupled to power rail VSS.

[0205] Reference is now made to Figure 17A . Figure 17A ​is a circuit diagram of IC 1700A according to some embodiments of the application. To illustrate IC 1700A, PMOS transistor P1 includes a gate terminal A1, a drain (D) terminal, and a source (S) terminal. NMOS transistor N1 includes a gate terminal B2, a D terminal, and an S terminal. The S terminal of PMOS transistor P1 is coupled to the D terminal of NMOS transistor N1 to form a first transistor pair. PMOS transistor P2 includes a gate terminal B1, a D terminal, and an S terminal. NMOS transistor N2 includes a gate terminal A2, a D terminal, and an S terminal. The D terminal of PMOS transistor P2 is coupled to the S terminal of NMOS transistor N2 to form a second transistor pair.

[0206] The gate terminal A1 of PMOS transistor P1 is coupled to the gate terminal A2 of NMOS transistor N2. The gate terminal B1 of PMOS transistor P2 is coupled to the gate terminal B2 of NMOS transistor N1. The S terminal of PMOS transistor P1 and the D terminal of NMOS transistor N1 are coupled to the D terminal of PMOS transistor P2 and the S terminal of NMOS transistor N2 to represent connection Z as shown in Figure 17A The S terminal of PMOS transistor P1 and the D terminal of NMOS transistor N1 are coupled to the D terminal of PMOS transistor P2 and the S terminal of NMOS transistor N2 to represent connection Z as shown in Figure 17B 、 17C or 17D discussed in more detail below with reference to

[0207] Reference is now made to Figure 17B and Figure 17C . Figure 17B and Figure 17C are layout diagrams 1700B and 1700C of an IC of IC 1700A according to some embodiments of the application corresponding to Figure 17A To simplify the illustration of layout diagrams 1700B or 1700C, only portions of the layout diagrams are shown for implementing IC 1700A of Figure 17A .

[0208] In some embodiments, layout diagrams 1700B or 1700C illustrate a cell pattern, where the cell pattern can be fabricated as a basic cell or portion of an apparatus or circuit including a transmission gate as discussed above with respect to Figure 17A to implement various layout diagrams of devices or circuits including transmission gates. Alternatively, in some embodiments, layout diagrams 1700B or 1700C are implemented in various layout diagrams for implementing devices or circuits including transmission gates.

[0209] As Figure 17BAs shown, the layout 1700B includes gates 1711 and 1712, MD portions (not labeled), conductive tracks 1741, 1742, and 1743, VG vias 1751 and 1752, a conductive portion 1761, and cut portions 1771 and 1772.

[0210] The cut portions 1771 and 1772 are arranged in the active area and extend in the row direction, in Figure 17B are patterned as "CT" to cut the conductive portions in the layout 1700B. For example, the cut portion 1771 is configured to cut the gate 1711, and the cut portion 1772 is configured to cut the gate 1712. Optionally, the cut portions 1771 and 1772 are configured to divide one gate 1711 or 1712 into two separate portions. In some embodiments, the cut portions 1771 and 1772 correspond to the cut portions CT shown in Figure 1A .

[0211] The VG via 1751 couples the gate 1711 with the VG via 1751 to the conductive track 1743, and the VG via 1752 couples the gate 1712 with the VG via 1752 to the conductive track 1741.

[0212] The conductive portion 1761 partially overlaps the gate 1711, the cut portion 1771, the conductive tracks 1741 and 1743, and the VG via 1751. The conductive portion 1761 is also referred to as an M0 jumper, and in some embodiments corresponds to the conductive portions 121, 122, or 123 as shown in Figure 3A or Figure 3C . The conductive portion 1761 couples the conductive tracks 1741 and 1743 together.

[0213] In the description of Figure 17B , the polysilicon pitch D1 refers to the distance between two adjacent gates 1711 and 1712. The M0 pitch D2 refers to the distance between two adjacent conductive tracks 1741 and 1742. In some embodiments, the polysilicon pitch D1 corresponds to the polysilicon pitch D1 shown in Figures 3A to 3C , and the M0 pitch D2 corresponds to the M0 pitch D2 shown in Figures 3A to 3C .

[0214] The cut portions 1771 and 1772 are separated by a distance D3 in the column direction. The distance D3 is referred to as the jog spacing between two adjacent edges of the two adjacent cut portions 1771 and 1772, as shown in Figure 17BAs shown in the diagram. Furthermore, the gate 1711 is separated from the cut portion 1772 by a distance D4 in the row direction. The cut portion 1772 is arranged without crossing the gate 1711 and is arranged immediately adjacent to the gate 1711. The distance D4 is referred to as the interval between the edge of the cut portion 1772 and the edge of the gate 1711. The edges of the cut portion 1772 and the edges of the gate 1711 are arranged immediately adjacent to each other.

[0215] In some embodiments, the minimum distance D3 is approximately in the range of 0.3 times to 0.6 times the M0 spacing D2 (i.e., 0.3 * M0 spacing D2 to 1 * M0 spacing D2). In various embodiments, the distance D4 is approximately in the range of 0.4 times to 0.6 times the polysilicon spacing D1 (i.e., 0.3 * polysilicon spacing D1 to 1 * polysilicon spacing D1).

[0216] like Figure 17C As shown, layout diagram 1700C includes gates 1713, 1714 and 1715, MD section (not labeled), conductive rails 1744 and 1745, VG via 1753, conductive section 1762, and cut sections 1773 and 1774.

[0217] Cut-off portion 1773 partially overlaps with gate 1713 and is configured to cut off gate 1713. Cut-off portion 1774 partially overlaps with gate 1715 and is configured to cut off gate 1715. In some embodiments, cut-off portions 1773 and 1774 correspond to at least... Figure 1A The CT cut section is shown in the image.

[0218] VG via 1753 overlaps with gate 1713 and conductive rail 1745 to couple gate 1713 having VG via 1753 to conductive rail 1745. VG via 1752 overlaps with gate 1715 and conductive rail 1744 to couple gate 1715 having VG via 1754 to conductive rail 1744.

[0219] The conductive portion 1762 partially overlaps with the gate 1715, the cut portion 1774, the conductive rails 1744 and 1745, and the VG via 1754. The conductive portion 1762 is also referred to as an M0 jumper, and in some embodiments corresponds to, for example... Figure 3A or Figure 3C The conductive portions 121, 122, or 123 are shown. The conductive portion 1762 couples the conductive rails 1744 and 1745 together.

[0220] exist Figure 17C In the description, the polysilicon spacing D1 and M0 spacing D2 correspond to Figure 17Bpolysilicon pitch D1 and the M0 pitch D2 shown in FIG. 17A. The cut 1773 and the cut 1774 are separated by a distance D5 in the column direction. The distance D5 is referred to as the jog spacing between two adjacent edges of the two adjacent cuts 1773 and 1774, as shown in FIG. 17B. Figure 17C The gate 1714 is separated by a distance D6 from the cut 1774 in the row direction. The cut 1775 is not disposed across the gate 1714 and is disposed immediately adjacent to the gate 1714. The distance D6 is referred to as the spacing between two adjacent edges of the cut 1774 and the gate 1714.

[0221] In some embodiments, the distance D5 corresponds to the distance D3 shown in FIG. 17A and has a similar range. In some other embodiments, the distance D6 corresponds to the distance D4 shown in FIG. 17A and has a similar range. Figure 17B In some embodiments, the distance D5 corresponds to the distance D3 shown in FIG. 17A and has a similar range. In some other embodiments, the distance D6 corresponds to the distance D4 shown in FIG. 17A and has a similar range. Figure 17B In some embodiments, the distance D5 corresponds to the distance D3 shown in FIG. 17A and has a similar range. In some other embodiments, the distance D6 corresponds to the distance D4 shown in FIG. 17A and has a similar range.

[0222] Reference is now made to Figure 17D . Figure 17D Layout diagram 1700D of an IC corresponding to IC 1700A according to some embodiments of the present application. Figure 17A In the description of

[0223] , the gates 1711 and 1712 are disposed as gate terminals of PMOS transistors P1-P2 or NMOS transistors N1-N2 in FIG. 17A. The MD portions 1721, 1722, 1723, 1724, and 1725 are disposed as source / drain terminals of the PMOS transistors P1-P2 or the NMOS transistors N1-N2 in FIG. 17A. Figure 17D Figure 17A In the description of Figure 17A , the gates 1711 and 1712 are disposed as gate terminals of PMOS transistors P1-P2 or NMOS transistors N1-N2 in FIG. 17A. The MD portions 1721, 1722, 1723, 1724, and 1725 are disposed as source / drain terminals of the PMOS transistors P1-P2 or the NMOS transistors N1-N2 in FIG. 17A.

[0224] The cuts 1771 and 1772 are disposed and will be removed to manufacture the layout diagram 1700D. The cut 1771 is disposed across the gate 1711 to divide the gate 1711 into two portions including the gate 1711 with VG 1751 and the gate 1711 with VG 1753. The cut 1771 partially overlaps the conductive track 1743 and the gate 1711. The cut 1772 is disposed across the gate 1712 to divide the gate 1712 into two portions including the gate 1712 with VG 1752 and the gate 1712 with VG 1754. The cut 1772 partially overlaps the conductive track 1744 and the gate 1712.

[0225] ​The gate 1711 with VG 1751 and the MD parts 1721 and 1722 together correspond to the PMOS transistor P1. The gate 1712 with VG 1752 and the MD parts 1722 and 1723 together correspond to the PMOS transistor P2. The gate 1711 with VG 1753 and the MD parts 1724 and 1722 together correspond to the NMOS transistor N1. The gate 1712 with VG 1754 and the MD parts 1722 and 1725 together correspond to the NMOS transistor N2. In such embodiments, the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 share the MD part 1722, which corresponds to the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 being coupled together between the connections Z as shown in Fig. 1. Figure 17A

[0226] The conductive tracks 1741, 1742, 1743, 1744, 1745 and 1746 are arranged. In some embodiments, the conductive tracks 1741, 1742, 1743, 1744, 1745 and 1746 are also referred to as signal conductive tracks, which are discussed above at least with reference to Figure 4

[0227] The VD via 1731 is arranged. The VD via 1731 couples the MD part 1722 to the conductive track 1746, which is further coupled to a signal track (not shown) arranged in the M1 layer. In some embodiments, the signal track represents an output terminal for transmitting the signal transmitted from the connection Z, as discussed above with reference to Figure 17A

[0228] The VG vias 1751, 1752, 1753 and 1754 are arranged. The VG via 1751 couples the gate 1711 with the VG via 1751 to the conductive track 1741, which is further coupled to a first signal track (not shown) arranged in the M1 layer. The VG via 1752 couples the gate 1712 with the VG via 1752 to the conductive track 1743, which is further coupled to a second signal track (not shown) arranged in the M1 layer. The VG via 1753 couples the gate 1711 with the VG via 1753 to the conductive track 1744, which is further coupled to the second signal track. The VG via 1754 couples the gate 1712 with the VG via 1754 to the conductive track 1745, which is further coupled to the first signal track. In such a structure, this corresponds to the gate terminal Al of the PMOS transistor P1 and the gate terminal A2 of the NMOS transistor N2 being coupled together to receive a first signal transmitted from the first signal track, as discussed above with reference to Figure 17A ​​​The above discussion. Similarly, this corresponds to the gate terminal B1 of PMOS transistor P2 and the gate terminal N2 of NMOS transistor B2 being coupled together to receive the second signal transmitted from the second signal rail, as mentioned above. Figure 17A The subject of discussion.

[0229] A conductive portion 1761 is arranged. In some embodiments, the conductive portion 1761 is formed as a block and is also referred to as corresponding to, for example... Figure 3A or Figure 3C The M0 jumper of conductive portions 121, 122, or 123 shown. Conductive portion 1761 partially overlaps with gate 1711, cut portion 1771, two adjacent conductive rails 1743 and 1744, and VG via 1753. Conductive portion 1761 couples conductive rails 1743 and 1744 together. As discussed above, through the arrangement with conductive portion 1761, conductive rails 1743 and 1744 are also coupled to a second signal rail.

[0230] For reference Figure 17E . Figure 17E This corresponds to some embodiments of the present invention. Figure 17A The layout diagram of IC 1700A is shown in IC 1700E.

[0231] exist Figure 17E In the explanation, with Figure 17D Compared to the embodiment described above, the cut portion 1771 partially overlaps with the conductive rail 1744 and the gate 1711, and the cut portion 1772 partially overlaps with the conductive rail 1745' and the gate 1712. The VG via 1753 couples the MD portion 1722 to the conductive rail 1743, which is also coupled to a signal rail (not shown) serving as an output rail, to transmit signals from the above-mentioned... Figure 17A The discussed connection Z transmits the signal. VG via 1752 couples the gate 1712 having VG via 1752 to conductive rail 1744, which is also coupled to the second signal rail. VG via 1753 couples the gate 1711 having VG via 1753 to conductive rail 1744, which is also coupled to the second signal rail. VG via 1754 couples the gate 1712 having VG via 1754 to conductive rail 1745, which is also coupled to the first signal rail. In this type of structure, this also corresponds to... Figure 17A The connections shown are as referenced. Figure 17D The conductive portion 1761 partially overlaps with the gate 1711, the cut portion 1771, the two adjacent conductive rails 1744 and 1745, and the VG via 1753.

[0232] For reference Figure 18A . Figure 18A It is equivalent to some embodiments of the present invention. Figure 17AThe circuit diagram of IC 1800A, which is the transmission gate circuit of IC 1700A. Figure 18A In the explanation, with Figure 17A In comparison, IC 1800A also includes a PMOS transistor P3 and an NMOS transistor N3. The gate terminal of PMOS transistor P1 is coupled to node A1; the gate terminal of PMOS transistor P2 is coupled to node B1; the gate terminal of PMOS transistor P3 is coupled to the gate of NMOS transistor N2. The gate terminal of NMOS transistor N1 is coupled to node B2; the gate terminal of NMOS transistor N3 is coupled to the gate of PMOS transistor P2; the gate terminal of NMOS transistor N2 is coupled to node A2. Node A2 is also coupled to the gate terminal of PMOS transistor P3. Node B1 is also coupled to node B2, as via... Figure 18A The connection ZN is shown. To implement the IC 1800A containing the connection Z between nodes B1 and B2 in embodiments of the present invention, embodiments of layout design and / or structure are provided and discussed below, as referenced. Figure 18B As shown.

[0233] Furthermore, the source / drain terminals of PMOS transistor P1 are coupled at node S1 to the source / drain terminals of PMOS transistor P2; the source / drain terminals of PMOS transistor P2 are coupled at node S2 to the source / drain terminals of PMOS transistor P3; and the source / drain terminals of PMOS transistor P3 are coupled to node S2'. The source / drain terminals of NMOS transistor N1 are coupled at node S3 to the source / drain terminals of NMOS transistor N3; and the source / drain terminals of NMOS transistor N3 are coupled at node S3' to the source / drain terminals of NMOS transistor N2. Node S1 is also coupled to node S3, as if via... Figure 18A The connection Z' is shown. To implement the IC 1800A including the connection Z' between nodes S1 and S3 in embodiments of the present invention, embodiments of layout design and / or structure are provided and discussed below, as referenced. Figure 18B As shown.

[0234] Node S2 is also coupled to node S2', corresponding to the source and drain terminals of the coupled PMOS transistor P3. The source and drain terminals of PMOS transistor P3 are coupled together in a short-circuit structure, rendering PMOS transistor P3 inactive. Furthermore, node S3 is also coupled to node S3', corresponding to the source and drain terminals of the coupled NMOS transistor N3. The source and drain terminals of NMOS transistor N3 are coupled together in a short-circuit structure, rendering NMOS transistor N3 inactive. Utilizing the connection between PMOS transistor P3 and NMOS transistor N3, as... Figure 18A As shown, IC 1800A can be used as a... Figure 17A The equivalent circuit operation of the 1700A transmission gate circuit in the diagram.

[0235] Figure 18B This corresponds to some embodiments of the present invention. Figure 18A The layout diagram of IC 1800A and IC 1800B.

[0236] exist Figure 18B In the description, gates 1811, 1812, and 1813 are arranged as follows: Figure 18A The gate terminals of PMOS transistors P1-P3 or NMOS transistors N1-N3 in the circuit. MD sections 1821, 1822, 1823, 1824, 1825, 1826 and 1827 are arranged as follows: Figure 18A The source / drain terminals of PMOS transistors P1-P3 or NMOS transistors N1-N3 in the circuit.

[0237] A dicing portion 1871 is arranged and will be removed to manufacture IC 1800A. The dicing portion 1871 is arranged across the gate 1811 to divide the gate 1811 into two parts, including a gate 1811 having VG 1851 and a gate 1811 having VG 1853.

[0238] Gate 1811 and MD portions 1821 and 1822, having VG 1851, together correspond to PMOS transistor P1. Gate 1812 and MD portions 1822 and 1823 together correspond to PMOS transistor P2. In this type of embodiment, PMOS transistors P1 and P2 share MD portion 1822, which corresponds to PMOS transistors P1 and P2 in... Figure 18A Coupled at node S1 shown. Gate 1813 and MD portions 1823 and 1824 together correspond to PMOS transistor P3. In this type of embodiment, PMOS transistors P2 and P3 share MD portion 1823, which corresponds to PMOS transistors P2 and P3 being coupled at node S1. Figure 18A Coupled at node S2 shown. Gate 1811 with VG 1853 and MD portions 1825 and 1822 together correspond to NMOS transistor N1. Gate 1812 and MD portions 1822 and 1826 together correspond to NMOS transistor N3. In this embodiment, NMOS transistors N1 and N3 share MD portion 1822, which corresponds to NMOS transistors N1 and N3 in... Figure 18A Coupled at node S3 as shown. Furthermore, PMOS transistors P1 and P2, and NMOS transistors N1 and N3 share the MD section 1822, which corresponds to the coupling of PMOS transistors P1 and P2 and NMOS transistors N1 and N3 at... Figure 18Abetween the connections Z' shown in Fig. 1 1 1. The gate 1813 and the MD parts 1826 and 1827 together correspond to the NMOS transistor N2. In such embodiments, the NMOS transistors N3 and N2 share the MD part 1826, which corresponds to the NMOS transistors N3 and N2 being coupled at the nodes S3 and S3' as shown in Fig. 1 1 1. Figure 18A at the node S3' shown in Fig. 1 1 1.

[0239] The conductive tracks 1841, 1842, 1843, 1844, 1845, 1846, 1847 and 1848 are arranged. In some embodiments, the conductive tracks 1842, 1843, 1844, 1846, 1847 and 1848 are referred to as signal conductive tracks, and the conductive tracks 1841 and 1845 are referred to as power conductive tracks, which are discussed above at least with reference to Figure 4 .

[0240] The VD vias 1831, 1832, 1833, 1834 and 1835 are arranged. The VD via 1831 couples the MD part 1822 to the conductive track 1842. The VD via 1832 couples the MD part 1823 to the conductive track 1846, and the VD via 1833 couples the MD part 1824 to the conductive track 1846. In such embodiments, the source terminal of the PMOS transistor P3 and the drain terminal of the PMOS transistor P3 are coupled together, which corresponds to the source / drain terminals of the PMOS transistor P3 being coupled at the nodes S2 and S2' as shown in Fig. 1 1 1. Figure 18A . Similarly, the VD via 1834 couples the MD part 1822 to the conductive track 1845, and the VD via 1835 couples the MD part 1826 to the conductive track 1846. In such embodiments, the source terminal of the NMOS transistor N2 and the drain terminal of the NMOS transistor N2 are coupled together, which corresponds to the source / drain terminals of the NMOS transistor N2 being coupled at the nodes S3 and S3' as shown in Fig. 1 1 1. Figure 18A .

[0241] The VG vias 1851, 1852, 1853 and 1854 are arranged. The VG via 1851 couples the gate 181 1 with the VG via 1851 to the conductive track 1841, which is also coupled to a first signal track (not shown) arranged in the M1 layer. This corresponds to the PMOS transistor P1 being coupled at the node A1 in Fig. 1 1 1. Figure 18A . The VG via 1852 couples the gate 1812 to the conductive track 1843. The VG via 1853 couples the gate 1812 and the VG 1853 to the conductive track 1844. The VG via 1854 couples the gate 1813 to the conductive track 1847, which is also coupled to a second signal track (not shown) arranged in the M1 layer. This corresponds to the NMOS transistor N2 being coupled at the node A2 in Fig. 1 1 1. Figure 18A .

[0242] A conductive portion 1861 is arranged and partially overlaps the cut portion 1871, the gate 1811, the conductive tracks 1843 and 1844, and the VG via 1853. In some embodiments, the conductive portion 1861 is shaped as a block and is also referred to as an M0 jumper corresponding to the conductive portion 121, 122, or 123 as shown in FIGS. 12A, 12B, and 12C, respectively. Figure 3A or Figure 3C The conductive portion 1861 couples the conductive tracks 1843 and 1844 together. With such a structure, the gate 1811 with the VG via 1853 and the gate 1812 are coupled together, which corresponds to the nodes B1 and B2 being coupled between the connections Z as discussed above with respect to FIGS. 12A, 12B, and 12C. Figure 18A

[0243] Reference is now made to Figure 19A . Figure 19A is a circuit diagram of an IC 1900A equivalent to the transmission gate circuit 1700A in Figure 17A . In the description of Figure 19A , the IC 1900A further includes PMOS transistors P3, P4, P5, and P6, and NMOS transistors N3, N4, N5, and N6, as compared to Figure 17A . The gate terminal of the PMOS transistor P1 is coupled to the gate terminal of the NMOS transistor N1 at node C1; the gate terminal of the PMOS transistor P2 is coupled to the gate terminal of the NMOS transistor N2 as shown by connection I1; the gate terminal of the PMOS transistor P3 is coupled to node SB1; the gate terminal of the PMOS transistor P4 is coupled to the gate terminal of the NMOS transistor N4 as shown by connection I2; the gate terminal of the PMOS transistor P5 is coupled to node S1; the gate terminal of the PMOS transistor P6 is coupled to the gate terminal of the NMOS transistor N6 as shown by connection S2; the gate terminal of the NMOS transistor N3 is coupled to node S3; and the gate terminal of the NMOS transistor N5 is coupled to node SB3.

[0244] In some embodiments for illustrating Figure 19A and Figure 19B , the nodes SB1, SB2, and connection SB3 are further coupled to a first signal track (not shown) denoted as SB to receive a first signal transmitted from the first signal track. The nodes S1, S2, and S3 are further coupled to a second signal track (not shown) denoted as S to receive a second signal transmitted from the signal track in addition to the first signal. The connection I1 is further coupled to a third signal track (not shown) denoted as I1 to receive a third signal transmitted from the third signal track. The connection I2 is further coupled to a fourth signal track (not shown) denoted as I2 to receive a fourth signal transmitted from the fourth signal track. ​

[0245] In addition, a source / drain terminal of PMOS transistor P1 is coupled to node Al; a source / drain terminal of PMOS transistor P1 is coupled to a source / drain terminal of PMOS transistor P2 at node A2; a source / drain terminal of PMOS transistor P2 is coupled to a source / drain terminal of PMOS transistor P3; a source / drain terminal of PMOS transistor P3 is coupled to a source / drain terminal of PMOS transistor P4 at node A3; a source / drain terminal of PMOS transistor P4 is coupled to a source / drain terminal of PMOS transistor P5; a source / drain terminal of PMOS transistor P5 is coupled to a source / drain terminal of PMOS transistor P6 at node A4; and a source / drain terminal of PMOS transistor P6 is coupled to node A5. A source / drain terminal of NMOS transistor N1 is coupled to node Bl; a source / drain terminal of NMOS transistor N1 is coupled to a source / drain terminal of NMOS transistor N2 at node B2; a source / drain terminal of NMOS transistor N2 is coupled to a source / drain terminal of NMOS transistor N3; a source / drain terminal of NMOS transistor N3 is coupled to a source / drain terminal of NMOS transistor N4 at node B3; a source / drain terminal of NMOS transistor N4 is coupled to a source / drain terminal of NMOS transistor N5; a source / drain terminal of NMOS transistor N5 is coupled to a source / drain terminal of NMOS transistor N6 at node B4; and a source / drain terminal of NMOS transistor N6 is coupled to node B5.

[0246] Nodes A2 and B5 are also coupled to a power rail referred to as VDD. Nodes B2 and B4 are also coupled to a power rail referred to as VDD. Node C2 is also coupled to node Cl. Node Al is also coupled to node Bl, as shown by connection Z. Node A3 is also coupled to node B3 at node C2. Node C2 is also coupled to node Cl, as shown by connection S4. Node A5 is also coupled to node B5, as shown by connection SB2. To implement IC 1900A in embodiments of the application that include connection Z between nodes Al and Bl, connection S4 between nodes Cl and C2, and connection SB2 between nodes A5 and B5, embodiments of layout designs and / or structures are provided and discussed below, as referenced to Figure 19B .

[0247] Figure 19B is a layout diagram 1900B of an IC corresponding to IC 1900A according to some embodiments of the application. In comparison to layout 1800B in Figure 19A , fewer conductive rails are arranged in layout diagram 1900B. Figure 18B

[0248] In Figure 19B ​In the illustration, the gates 1911, 1912, 1913, 1914, 1915, and 1916 are arranged as Figure 18A the gate terminals of the PMOS transistors P1-P6 or the NMOS transistors N1-N6 in the illustration. The MD sections 1920, 1920', 1921, 1922, 1923, 1924, 1925, 1926, 1927, 1928, and 1929 are arranged as Figure 19A the source / drain terminals of the PMOS transistors P1-P6 or the NMOS transistors N1-N6 in the illustration. The cut sections 1971 and 1972 are arranged. The cut section 1971 is arranged across the gate 1913 to divide the gate 1913 into two parts comprising the gate 1913 with VG 1953 and the gate 1913 with VG 1954. The cut section 1972 is arranged across the gate 1915 to divide the gate 1915 into two parts comprising the gate 1915 with VG 1956 and the gate 1915 with VG 1957.

[0249] The gate 1911 and the MD sections 1920 and 1921 together correspond to the PMOS transistor P1. The gate 1912 and the MD sections 1921 and 1922 together correspond to the PMOS transistor P2. In such embodiments, the PMOS transistors P1 and P2 share the MD section 1921, which corresponds to the PMOS transistors P1 and P2 being coupled at the node A2 shown in Figure 19A The gate 1913 with VG 1953 and the MD sections 1922 and 1923 together correspond to the PMOS transistor P3. The gate 1914 and the MD sections 1923 and 1924 together correspond to the PMOS transistor P4. In such embodiments, the PMOS transistors P3 and P4 share the MD section 1923, which corresponds to the PMOS transistors P3 and P4 being coupled at the node A3 shown in Figure 19A The gate 1915 with VG 1956 and the MD sections 1924 and 1925 together correspond to the PMOS transistor P5. The gate 1916 and the MD sections 1925 and 1926 together correspond to the PMOS transistor P6. In such embodiments, the PMOS transistors P5 and P6 share the MD section 1925, which corresponds to the PMOS transistors P5 and P6 being coupled at the node A4 shown in Figure 19A The gate 1916 and the MD sections 1925 and 1926 together correspond to the PMOS transistor P6. In such embodiments, the PMOS transistors P5 and P6 share the MD section 1925, which corresponds to the PMOS transistors P5 and P6 being coupled at the node A4 shown in

[0250] Furthermore, the gate 1911 and the MD sections 1920 and 1927 together correspond to the NMOS transistor N1. In such embodiments, the NMOS transistor N1 and the PMOS transistor P1 share the MD section 1920, which corresponds to the NMOS transistor N1 and the PMOS transistor P1 being coupled at the node A1 shown in Figure 19Abetween the connections Z shown in FIG. 19. Gate 1912 and MD portions 1927 and 1928 together correspond to NMOS transistor N2. In such embodiments, NMOS transistors N1 and N2 share MD portion 1927, which corresponds to NMOS transistors N1 and N2 being coupled at node B2 in FIG. 19. Figure 19A Gate 1913 and MD portions 1928 and 1923 together correspond to NMOS transistor N3. Gate 1914 and MD portions 1923 and 1929 together correspond to NMOS transistor N4. In such embodiments, NMOS transistors N3-N4 and PMOS transistors P3-P4 share MD portion 1923, which corresponds to NMOS transistors N3-N4 and PMOS transistors P3-P4 being coupled between nodes A3 and B3 in FIG. 19. Figure 19A Gate 1915 with VG 1957 and MD portions 1929 and 1920' together correspond to NMOS transistor N5. Gate 1916 and MD portions 1920' and 1926 together correspond to NMOS transistor N6. In such embodiments, NMOS transistors N5 and N6 share MD portion 1920', which corresponds to NMOS transistors N5 and N6 being coupled at node B4 in FIG. 19. Figure 19A Furthermore, NMOS transistor N6 and PMOS transistor P6 share MD portion 1926, which corresponds to NMOS transistor N6 and PMOS transistor P6 being coupled between nodes A5 and B5 in FIG. 19. Figure 19A

[0251] Conductive tracks 1940, 1940', 1941, 1942, 1943, 1944, 1945, 1946, 1947, 1948, and 1949 are arranged. In some embodiments, conductive tracks 1940, 1940', 1942, 1943, 1944, 1945, 1947, 1948, and 1949 are referred to as signal conductive tracks, and conductive tracks 1941 and 1946 are referred to as power conductive tracks, which are discussed above at least with reference to Figure 4

[0252] VD vias 1931, 1932, 1933, 1934, 1935, 1936, and 1937 are arranged. VD via 1931 couples MD portion 1920 to conductive track 1942. VD via 1932 couples MD portion 1921 to conductive track 1941, which is also coupled to a power rail (not shown) arranged in the M1 layer. MD portion 1921 and conductive track 1941 together are coupled to the power rail, which corresponds to node A2 being coupled to a power rail as discussed above with reference to Figure 19A ​​The power rail VDD discussed. The VD via 1933 couples the MD portion 1923 to the conductive rail 1944. The VD via 1934 couples the MD portion 1925 to the conductive rail 1941. Together, the MD portion 1925 and the conductive rail 1941 are coupled to a power rail, which corresponds to the node A4 being coupled to the power rail VSS, as discussed above with respect to Figure 19A The power rail VDD discussed.

[0253] Furthermore, the VD via 1935 couples the MD portion 1927 to the conductive rail 1946, which is also coupled to another power rail (not shown) arranged in the M1 layer. Together, the MD portion 1927 and the conductive rail 1946 are coupled to such a power rail, which corresponds to the node B2 being coupled to the power rail VD VSS, as discussed above with respect to Figure 19A The power rail VDD discussed. The VD via 1936 couples the MD portion 1920' to the conductive rail 1946, which is also coupled to the same power rail (not shown) as the power rail to which the conductive rail 1946 is coupled. Together, the MD portion 1920' and the conductive rail 1946 are coupled to such a power rail, which corresponds to the node B4 being coupled to the power rail VD VSS, as discussed above with respect to Figure 19A The power rail VDD discussed. The VD via 1937 couples the MD portion 1926 to the conductive rail 1940, which is also coupled to a first signal rail (not shown) arranged in the M1 layer.

[0254] VG vias 1951, 1952, 1953, 1954, 1955, 1957, 1958, and 1959 are arranged. The VG via 1951 couples the gate 1911 to the conductive rail 1944, which is also coupled to a signal rail (not shown) arranged in the M1 layer. This corresponds to the PMOS transistor P1 and the NOMS transistor N1 being coupled at a node C11 in Figure 19A In such a structure, the MD portion 1923 coupled to the conductive rail 1944 is also coupled to the gate 1911. This corresponds to the nodes C1 and C2, which are also coupled to the nodes A3 and B3, being coupled between the connection S4 in Figure 19A The VG via 1952 couples the gate 1912 to the conductive rail 1945, which is also coupled to a third signal rail (not shown) arranged in the M1 layer. This corresponds to the PMOS transistor P2 and the NOMS transistor N2 being coupled between the connection I1 in Figure 19A The VG via 1953 couples the gate 1913 with the VG via 1953 to the conductive rail 1949, which is also coupled to the first signal rail. This corresponds to the PMOS transistor P3 being coupled at a node SB1 in Figure 19A The VG via 1954 couples the gate 1913 with the VG via 1954 to the conductive rail 1940', which is also coupled to a second signal rail (not shown) arranged in the M1 layer. This corresponds to the NMOS transistor N3 being coupled at a node SB2 in Figure 19A at node S3 in

[0255] Furthermore, in some embodiments, the VG via 1955 couples the gate 1914 to a conductive track 1947 which is also coupled to a fourth signal track (not shown) arranged in the M1 layer. This corresponds to the connection I2 between the PMOS transistor P4 and the NOMS transistor N4 being coupled at node S3 in Figure 19A Figure 19A Figure 19A Figure 19A

[0256] Conductive portions 1961, 1962, 1963 and 1964 are arranged. In some embodiments, the conductive portion 1961 is shaped as a rail block and is also referred to as a MO jumper corresponding to the conductive portion 124 as shown in Figure 3B or Figure 3C . The conductive portion 1961 couples the conductive tracks 1942 and 1943 together.

[0257] Furthermore, in some embodiments, the conductive portion 1962 is shaped as a block and is also referred to as a MO jumper corresponding to the conductive portion 121, 122 or 123 as shown in Figure 3A or Figure 3C . The conductive portion 1962 partially overlaps the gate 1915, the cut portion 1972, the conductive tracks 1949 and 1940 and the VG via 1957. The conductive portion 1962 couples the conductive tracks 1949 and 1940 together. With such a configuration, the gate 1913, the gate 1915 with the VG via 1957 and the MD portion 1926 are coupled together which corresponds to the PMOS transistor P3, the NMOS transistor N5 and the nodes B1 and A2 coupled between the connections SB2 being coupled to the same signal track, which in some embodiments is the first signal track as discussed above in relation to Figure 19A .

[0258] ​​​​Furthermore, conductive portions 1963 and 1964 are also referred to as V0 rails, and in some embodiments correspond to, for example... Figures 3A-3C The conductive portions 111 and 112 are shown. As discussed above with reference to VD vias 1931-1937, conductive portion 1963 is coupled to both conductive rail 1941 and MD portions 1921 and 1925, which are also coupled to the power rail VDD. Conductive portion 1964 is coupled to both conductive rail 1946 and MD portions 1927 and 1920', which are also coupled to the power rail VSS.

[0259] If passed Figures 1A-19B As described in the above-discussed non-limiting examples, the various embodiments include conductive portions formed on conductive rails and disposed above the M0 layer and below the M1 layer, thereby increasing wiring flexibility compared to methods lacking these conductive portions.

[0260] For reference Figure 20 . Figure 20 This is a flowchart of a method 2000 for manufacturing an IC according to some embodiments of the present invention. In some embodiments, the IC is manufactured based on an IC layout drawing, the IC layout drawing including elements corresponding to the above-mentioned... Figures 1A-19B The layout diagram of the IC structure under discussion (e.g., one of IC 700 or 1000) is one of 100A, 100B, 200, 300A-300C, 400, 500A-500C, 800, 1100B, 1200B, 1300B, 1400B, 1500B, 1600B, 1700B-1700E, 1800B, or 1900B. In some embodiments, the operation of method 2000 is as follows: Figure 20 The described sequential execution. In some embodiments, the operations of method 2000 are performed simultaneously and / or in addition to Figure 20 Execution in a sequence other than that described. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 2000.

[0261] At operation 2010, conductive rails are formed in the first metal layer. In some embodiments, the conductive rails correspond to the above-mentioned... Figures 1A-19B The conductive rails P01, P02, and SO1-S04 are discussed. The first metal layer corresponds to the above regarding... Figures 1A-19B The M0 layer under discussion.

[0262] In some embodiments, the conductive rail includes a pair of first conductive rails. In various embodiments, this pair of first conductive rails corresponds to conductive rails P01 and P02, which are also represented as described above regarding... Figures 1A-19B The power supply rails under discussion.

[0263] At operation 2020, signal rails are formed in a second metal layer above the first metal layer. In some embodiments, the signal rails correspond to signal rails P11, P12, and S11-S4 or more. Figures 1A-19B The orbitals discussed are not shown. The second metal layer corresponds to the above regarding... Figures 1A-19B The M1 layer under discussion.

[0264] At operation 2030, a first conductive portion is formed between the first metal layer and the second metal layer and spaced apart from the signal rails. In some embodiments, in the layout diagram, the first conductive portion overlaps with a pair of first conductive rails. In some embodiments, the first conductive portion corresponds to the above regarding... Figures 1A-19B The conductive portion discussed is represented as the V0 rail. For example, the first conductive portion corresponds to... Figure 1A , Figure 1B , Figures 3A-3C The conductive part 111 or 112 shown Figure 4 , Figures 5A-5C Conductive parts 411a, 411b, 412a, and 412b in the example.

[0265] In some embodiments, method 2000 further includes the following operation: A second conductive portion is also formed between the first metal layer and the second metal layer and is also spaced apart from the signal rails. In a layout diagram, the second conductive portion overlaps with at least two adjacent conductive rails between a pair of first conductive rails. In some embodiments, the second conductive portion corresponds to the above-mentioned... Figures 1A-19B The conductive portion represented by the M0 jumper discussed. For example, the second conductive portion corresponds to... Figure 1A , Figure 1B , Figures 3A-3C The conductive parts 121, 122, 123 or 124 shown are... Figure 4 , Figures 5A-5C The conductive portion 421 is mentioned above. In various embodiments, the adjacent conductive rail disposed together with the second conductive portion corresponds to the conductive rail S0, which is also represented as described above regarding... Figures 1A-19B The signal conduction rails under discussion.

[0266] For reference Figure 21 . Figure 21 This is a block diagram of an electronic design automation (EDA) system 2100 for designing layout designs of integrated circuits according to some embodiments of the present invention. The EDA system 2100 is configured to implement... Figure 6 Method 600 disclosed in the document and Figure 20 The method disclosed in 2000 includes one or more operations, and also incorporates... Figures 1A-5C and Figures 7A-19B This will be explained. In some embodiments, the EDA system 2100 includes an APR system.

[0267] In some embodiments, the EDA system 2100 is a general purpose computing device that includes a hardware processor 2120 and a non-transitory computer readable storage medium 2160. The storage medium 2160, among other uses, stores computer program code (instructions) 2161, i.e., a set of executable instructions, encoded thereupon. Execution of the instructions 2161 by the hardware processor 2120 represents (at least in part) an electronic design automation tool that implements, for example, part or all of the methods 600 and 2000.

[0268] The processor 2120 is electrically coupled to the computer readable storage medium 2160 via bus 2150. The processor 2120 is also electrically coupled to an input / output (I / O) interface 2110 and a fabrication tool 2170 via bus 2150. A network interface 2130 is also electrically coupled to the processor 2120 via bus 2150. The network interface 2130 is connected to a network 2140, thereby enabling the processor 2120 and the computer readable storage medium 2160 to communicate with external entities via the network 2140. The processor 2120 is configured to execute the computer program code 2161 encoded in the computer readable storage medium 2160, to cause the EDA system 2100 to be operable for part or all of the processes and / or methods described. In one or more embodiments, the processor 2120 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0269] In one or more embodiments, the computer readable storage medium 2160 is an electronic, magnetic, fiber optic, electromagnetic, infrared, and / or semiconductor system (or apparatus) or device. For example, the computer readable storage medium 2160 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc and / or an optical disc. In one or more embodiments using optical discs, the computer readable storage medium 2160 includes a compact disc - read only memory (CD-ROM), a compact disc - read / write (CD-R / W) and / or a digital video disc (DVD).

[0270] In one or more embodiments, the storage medium 2160 storing the computer program code 2161 is configured to cause the EDA system 2100 (where such execution represents (at least in part) an electronic design automation tool) to be operable to perform part or all of the processes and / or methods described. In one or more embodiments, the storage medium 2160 also stores information that assists in performing part or all of the processes and / or methods described. In one or more embodiments, the storage medium 2160 stores a library 2162 of standard cells that includes such standard cells as disclosed herein, for example, including the standard cells described above with respect to FIG. 6. Figure 1AThe unit of the conductive part 111, 112 or 121-123 in question.

[0271] The EDA system 2100 includes an I / O interface 2110. The I / O interface 2110 is coupled to external circuits. In one or more embodiments, the I / O interface 2110 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touchscreen, and / or cursor direction keys for communicating information and commands to the processor 2120.

[0272] The EDA system 2100 also includes a network interface 2130 coupled to the processor 2120. The network interface 2130 allows the EDA system 2100 to communicate with a network 2140 connected to one or more other computer systems. The network interface 2130 includes a wireless network interface, such as Bluetooth, Wireless Local Area Network (WIFI), Access Control (WIMAX), General Packet Radio Service (GPRS), or Mobile Communications (WCDMA), or a limited network interface, such as Ethernet, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the processes and / or methods described are implemented in two or more systems 2100.

[0273] The EDA system 2100 also includes a manufacturing tool 2170 coupled to the processor 2120. The manufacturing tool 2170 is configured to manufacture an integrated circuit based on a design file and / or an IC layout design processed by the processor 2120, including, for example, the integrated circuit 700 shown in FIG. 7 or the integrated circuit 1000 shown in FIG. 10. Figures 7A-7G Figures 10A-10C

[0274] The EDA system 2100 is configured to receive information through the input / output interface 2110. The information received through the I / O interface 2110 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 2120. The information is transferred to the processor 2120 through the bus 2150. The EDA system 2100 is configured to receive information related to a user interface (UI) through the I / O interface 2110. This information is stored in the computer readable medium 2160 as a user interface (UI) 2163.

[0275] ​​In some embodiments, portions or all of the described processes and / or methods are performed as a separate software application executed by a processor. In some embodiments, portions or all of the described processes and / or methods are performed as part of an additional software application. In some embodiments, portions or all of the described processes and / or methods are performed as a plug-in to a software application. In some embodiments, portions or all of the described processes and / or methods are performed as a software application that is part of an EDA tool. In some embodiments, portions or all of the described processes and / or methods are performed as a software application that is part of an EDA system 2100. In some embodiments, the described processes and / or methods are performed using a tool such as the VERICLAD® tool available from GLOBALFOUNDRIES® or another suitable place-and-route tool, to generate a layout map containing standard cells.

[0276] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, e.g., optical discs such as digital video discs, magnetic discs such as hard discs, semiconductor memories such as read-only memories, random access memories, and memory cards, and the like.

[0277] Figure 22 is a block of an IC manufacturing system 2200 and an IC manufacturing flow related thereto according to some embodiments. In some embodiments, based on a layout map, the IC manufacturing system 2200 is used to manufacture at least one of (A) one or more semiconductor masks, or (B) at least one element of a semiconductor integrated circuit layer.

[0278] In Figure 22In overview, the IC fabrication system 2200 includes entities such as a design house 2210, a mask house 2220, and an IC manufacturer / foundry ("fab") 2230 that interact in the design, development, and manufacturing cycle and / or services related to fabrication of IC devices 2240. The entities of the IC fabrication system 2200 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is various different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or accepts services from one or more other entities. In some embodiments, a single larger company owns two or more of the design house 2210, the mask house 2220, and the IC fab 2230. In some embodiments, two or more of the design house 2210, the mask house 2220, and the IC fab 2230 coexist in a common facility and use common resources.

[0279] The design house (or design group) 2210 generates an IC design layout 2211. The IC design layout 2211 contains various geometric patterns, e.g., lines, curves, and / or polygons, that are depicted in a format that is suitable for use in the fabrication of the IC devices 2240, e.g., as described above with respect to Figures 1A-1B 、 Figure 2 、 Figures 3A-3C 、 Figure 4 、 Figures 5A-5C 、 Figure 8 、 Figures 9A-9C 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B and / or Figure 19B the IC layout design depicted in the IC design layout 2211 is designed for the IC devices 2240, e.g., as described above with respect to Figures 7A-7G and / or Figures 10A-10CThe integrated circuits 700 and 1000 are discussed. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various elements of the IC device 2240 to be fabricated. The various layer combinations form the various IC components. For example, portions of the IC design layout 2211 contain the various IC components to be formed on a semiconductor substrate, such as a silicon wafer, such as active areas for interconnects, gate electrodes, source and drain, conductive or vias, and various metal layers disposed on the semiconductor substrate. The design room 2210 performs appropriate design procedures to form the IC design layout 2211. The design procedures include one or more of logic design, physical design, or layout and routing. The IC design layout 2211 exists in one or more data files with information of the geometric patterns. For example, the IC design layout 2211 can be expressed in a GDSII file format or a DFII file format.

[0280] The mask room 2220 includes data preparation 2221 and mask fabrication 2222. The mask room 2220 uses the IC design layout 2211 to fabricate one or more masks 2223 for fabricating the various layers of the IC device 2240 according to the IC design layout 2211. The mask room 2220 performs mask data preparation 2221 in which the IC design layout 2211 is translated into a representative data file ("RDF"). The mask data preparation 2221 provides the representative data file to the mask fabrication 2222. The mask fabrication 2222 contains a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 2223 or a semiconductor wafer 2233. The IC design layout 2211 is manipulated by the mask data preparation 2221 to comply with the specific capabilities of the mask writer and / or the requirements of the IC fab 2230. In some embodiments, the data preparation 2221 and the mask fabrication 2222 are shown as a single element. In some embodiments, the data preparation 2221 and the mask fabrication 2222 can be collectively referred to as mask data preparation. Figure 22

[0281] In some embodiments, the data preparation 2221 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image distortions, such as those caused by diffraction, interference, and other process effects, among others. The OPC adjusts the IC design layout 2211. In some embodiments, the data preparation 2221 also includes resolution enhancement techniques (RET), such as off-axis illumination, resolution assist

[0282] ​In some embodiments, data preparation 2221 includes creating a mask rule checker (MRC) that checks the IC design layout 2211 for mask creation rules, such as certain geometric constraints and / or connectivity constraints to ensure sufficient space, account for variability in the semiconductor manufacturing process, and so on, with a set of mask creation rules. In some embodiments, the MRC modifies the IC design layout 2211 to compensate for limitations during mask fabrication 2222, which can undo portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0283] In some embodiments, data preparation 2221 includes a lithography process check (LPC) that simulates the processing to be performed by the IC fab 2230 to fabricate the IC device 2240. The LPC simulates the processing based on the IC design layout 2211 to create a simulated fabricated device, such as the IC device 2240. The processing parameters in the LPC simulation can include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the fabrication process. The LPC accounts for various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), and other suitable factors, and so on or combinations thereof. In some embodiments, if the simulated fabricated device after having been created by the LPC does not sufficiently closely meet the design rules, then the OPC and / or the MRC are repeated to further refine the IC design layout 2211.

[0284] It should be appreciated that the foregoing description of data preparation 2221 has been simplified for brevity. In some embodiments, data preparation 2221 includes additional components, such as a logic operation (LOP), to modify the IC design layout 2211 according to fabrication rules. Furthermore, the processes applied to the IC design layout 2211 during data preparation 2221 can be performed in various different orders.

[0285] After data preparation 2221 and during mask manufacturing 2222, a mask 2223 or a set of masks 2223 is manufactured based on the IC design layout 2211. In some embodiments, mask manufacturing 2222 includes performing one or more photolithography exposures based on the IC design layout 2211. In some embodiments, an e-beam or multiple e-beams mechanism is used to form a pattern on a mask (photomask or intermediate mask) 2223 based on the modified IC design layout 2211. The mask 2223 can be formed in various techniques. In some embodiments, the mask 2223 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary intermediate mask version of the mask 2223 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 2223 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 2223, various components in the pattern formed on the phase shift mask are configured to have suitable phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask or masks generated by mask manufacturing 2222 are used in various processes. For example, such mask or masks are used in ion implantation processes to form various doped regions in a semiconductor wafer 2233, in etching processes to form various etched regions in the semiconductor wafer 2233, and / or in other suitable processes.

[0286] The IC fab 2230 includes wafer fabrication 2232. The IC fab 2230 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC fab 2230 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0287] IC fab 2230 uses one or more masks 2223 manufactured using mask room 2220 to manufacture IC devices 2240. Thus, IC fab 2230 uses, at least indirectly, integrated circuit design layout 2211 to manufacture IC devices 2240. In some embodiments, IC fab 2230 uses one or more masks 2223 to manufacture a semiconductor wafer 2233 to form IC devices 2240. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based, at least indirectly, on IC design layout 2211. Semiconductor wafer 2233 includes a silicon substrate or other suitable substrate having a plurality of material layers formed thereon. Semiconductor wafer 2233 also includes one or more of various doped regions, dielectric components, and multilayer interconnects, among others (formed in subsequent fabrication steps).

[0288] Further, various circuits or devices for implementing the transistors in the foregoing embodiments are within the contemplation of the present disclosure. In some embodiments of the present document, at least one of the transistors is implemented with at least one MOS transistor, at least one bipolar junction transistor (BJT), or the like, or a combination thereof. Various circuits or devices for implementing the transistors in the foregoing embodiments are within the contemplation of the present disclosure.

[0289] In some embodiments, an integrated circuit is disclosed. The integrated circuit includes a plurality of conductive tracks, a plurality of signal tracks, at least one first via, and at least one first conductive portion. The plurality of conductive tracks is disposed in a first conductive layer. The plurality of signal tracks is disposed in a second conductive layer above the first conductive layer. The at least one first via is disposed between the first conductive layer and the second conductive layer and couples a first signal track of the plurality of signal tracks to at least one of the plurality of conductive tracks. The first signal track is configured to transmit a supply signal through the at least one first via and the at least one of the plurality of conductive tracks to at least one element of the integrated circuit. The at least one first conductive portion is disposed between the first conductive layer and the second conductive layer. The at least one first conductive portion is coupled to the at least one of the plurality of conductive tracks and is separate from the first signal track.

[0290] In some embodiments, the integrated circuit further includes at least one second conductive portion. The at least one second conductive portion is disposed between the first conductive layer and the second conductive layer. In a layout, the at least one second conductive portion is disposed over and couples at least two adjacent conductive tracks of the plurality of conductive tracks to each other and is separate from the plurality of signal tracks.

[0291] In some embodiments, the integrated circuit further includes at least one second via. The at least one second via is disposed between the first conductive layer and the second conductive layer. The at least one second conductive portion is coupled to the plurality of signal tracks through the at least one second via. A height of the at least one second via is less than a height of the at least one first via.

[0292] In some embodiments, the at least one first conductive portion includes a separate portion, and in the layout, the at least one first via is disposed between the separate portion. In the layout, the at least one first via and the separate portion are disposed directly above at least one of the plurality of conductive tracks.

[0293] In some embodiments, the integrated circuit further includes a plurality of second vias. The plurality of second vias is disposed between the first conductive layer and the second conductive layer. The at least one first conductive portion includes a pair of conductive portions. Each of the pair of conductive portions is disposed on two separate conductive tracks of the plurality of conductive tracks and is coupled to the plurality of signal tracks through one of the plurality of second vias.

[0294] In some embodiments, a width of the at least one first conductive portion is less than or equal to a width of one of the plurality of conductive tracks. A length of the at least one first conductive portion is less than or equal to a length of one of the plurality of conductive tracks.

[0295] In some embodiments, an integrated circuit is also disclosed. The integrated circuit includes a first plurality of conductive tracks, a second plurality of conductive tracks, at least one first via, and at least one first conductive portion. The first plurality of conductive tracks is disposed in a first conductive layer and extends along a first direction. The first plurality of conductive tracks is configured to transmit a power signal to at least one element of the integrated circuit. The second plurality of conductive tracks is disposed in the first conductive layer and extends along the first direction. In a layout, the second plurality of conductive tracks is disposed between the first plurality of conductive tracks and is separated from each other. The second plurality of conductive tracks is configured to transmit a data signal to the at least one element of the integrated circuit. The at least one first via is disposed between the first conductive layer and a second conductive layer above the first conductive layer and couples one of the first plurality of conductive tracks to a power track disposed in the second conductive layer. The at least one first conductive portion is disposed between the first conductive layer and the second conductive layer above the first conductive layer. In the layout, the at least one first conductive portion at least partially overlaps at least two adjacent conductive tracks of the second plurality of conductive tracks, and the at least one first conductive portion contacts the at least two adjacent conductive tracks of the second plurality of conductive tracks and is separated from a signal track disposed in the second conductive layer and immediately adjacent to the power track.

[0296] In some embodiments, the integrated circuit further includes a plurality of second conductive portions. The plurality of second conductive portions is disposed between the first conductive layer and the second conductive layer. In the layout, the plurality of second conductive portions extends along the first direction and is disposed directly above the first plurality of conductive tracks. In the layout, the plurality of second conductive portions does not exceed the first plurality of conductive tracks and is separated from the second conductive layer.

[0297] In some embodiments, one of the plurality of second conductive portions includes a separate portion, and in the layout, the at least one first via is disposed between the separate portion.

[0298] In some embodiments, the integrated circuit further includes at least one second via. The at least one second via is disposed between the first conductive layer and the second conductive layer. One of the plurality of second conductive portions is coupled to the power rail through the at least one second via. The height of the at least one first via is different from the height of the at least one second via.

[0299] In some embodiments, the integrated circuit further includes a third conductive portion and a fourth conductive portion. The third conductive portion is disposed over the active region below the first conductive layer and extends in the second direction to form a first transistor. In the layout view, the third conductive portion overlaps a first conductive track of the second plurality of conductive tracks. The fourth conductive portion is disposed over the active region and extends in the second direction to form a second transistor coupled to the first transistor. In the layout view, the fourth conductive portion overlaps a second conductive track of the second plurality of conductive tracks. In the layout view, the first conductive track and the second conductive track are immediately adjacent to each other, and the first conductive track, the second conductive track, and the at least one first conductive portion partially overlap each other.

[0300] In some embodiments, the integrated circuit further includes at least one via. The at least one via is disposed below the first conductive layer. In the layout view, the at least one second via overlaps at least the second plurality of conductive tracks. In the layout view, the at least one first conductive portion overlaps the at least one second via, at least two adjacent conductive tracks of the second plurality of conductive tracks, and a cut portion of the at least two adjacent conductive tracks.

[0301] In some embodiments, the integrated circuit further includes at least one third conductive portion. The at least one third conductive portion is disposed over the active region below the first conductive layer and extends in the second direction to form a gate terminal. In the layout view, the at least one third conductive portion is disposed across the second plurality of conductive tracks. The at least one third conductive portion is coupled to one of the second plurality of conductive tracks through the at least one second via.

[0302] In some embodiments, the at least one third conductive portion includes a plurality of third conductive portions. The plurality of third conductive portions are separated from each other in the first direction. A length of the at least one first conductive portion is substantially equal to or greater than a distance between two adjacent third conductive portions of the plurality of third conductive portions.

[0303] In some embodiments, the integrated circuit further includes a plurality of third conductive portions and at least one second via. The plurality of third conductive portions are disposed over the active region below the first conductive layer and extend in the second direction to form a transistor. The at least one second via is disposed below the first conductive layer. One of the plurality of third conductive portions is coupled to one of the second plurality of conductive tracks through the at least one second via, which is coupled to one of the power rails through the at least one first via. A height of the at least one first via is greater than a height of the at least one first conductive portion.

[0304] In some embodiments, methods are also disclosed. The methods include operations. A plurality of conductive tracks is formed. A film structure on the plurality of conductive tracks is formed. The film structure is patterned to form a first pattern. The first pattern is filled with a conductive material to form a first conductive structure including at least one first conductive portion contacting at least one first track of the plurality of conductive tracks. A dielectric structure covering the at least one first conductive portion is formed. Portions of the film structure and portions of the dielectric structure are removed to expose portions of a second track of the plurality of conductive tracks. The conductive material is filled in the removed portions of the film structure and the removed portions of the dielectric structure to form a second conductive structure including a first via contacting the exposed portions of the second track and a signal track contacting the first via.

[0305] In some embodiments, the methods further include operations. The dielectric structure is patterned to form a second pattern. The second pattern is filled with a conductive material to form a second via contacting the at least one first conductive portion. The second via contacts the at least one first conductive portion and a power track disposed immediately adjacent to the second track.

[0306] In some embodiments, the methods further include operations. At least one third conductive structure contacting at least two adjacent tracks of the plurality of conductive tracks is formed. The at least one third conductive structure is separated from the plurality of conductive tracks.

[0307] In some embodiments, the methods further include operations. A second via contacting the first track and a power track disposed immediately adjacent to the signal track is formed. The at least one first conductive portion includes separated portions. The second via is disposed between the separated portions of the at least one first conductive portion.

[0308] In some embodiments, a height of the first via is greater than a height of the at least one first conductive portion. A width of the first via is substantially equal to or less than a width of the at least one first conductive portion.

[0309] The foregoing is a summary of components of several embodiments, so that those skilled in the art can better understand aspects of the present application. Those of ordinary skill in the art will appreciate that the present application can be readily used as a basis for the designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present application, and that they will be obvious to those skilled in the art from this disclosure. Numerous changes, substitutions and alterations can be made to the embodiments disclosed herein without departing from the spirit and scope of the present application.

Claims

1. An integrated circuit comprising: a plurality of conductive tracks disposed in a first conductive layer; a plurality of signal tracks disposed in a second conductive layer above the first conductive layer; at least one first via disposed between the first conductive layer and the second conductive layer and coupling a first signal track of the plurality of signal tracks to at least one of the plurality of conductive tracks, wherein the first signal track is configured to transmit a supply signal through the at least one first via and the at least one of the plurality of conductive tracks to at least one element of the integrated circuit; and at least one first conductive portion disposed between the first conductive layer and the second conductive layer, wherein the at least one first conductive portion is disposed on and in direct contact with the at least one of the plurality of conductive tracks and is separate from the first signal track.

2. The integrated circuit of claim 1, further comprising: at least one second conductive portion disposed between the first conductive layer and the second conductive layer, wherein, in a layout, the at least one second conductive portion is disposed over and couples at least two adjacent conductive tracks of the plurality of conductive tracks to each other and is separate from the plurality of signal tracks.

3. The integrated circuit of claim 2, further comprising: at least one second via disposed between the first conductive layer and the second conductive layer, wherein the at least one second conductive portion is coupled to the plurality of signal tracks through the at least one second via, wherein a height of the at least one second via is less than a height of the at least one first via.

4. The integrated circuit of claim 1, wherein, in a layout, the at least one first conductive portion comprises separate portions and the at least one first via is disposed between the separate portions, and the at least one first via and the separate portions are disposed directly above the at least one of the plurality of conductive tracks.

5. The integrated circuit of claim 1, further comprising: a plurality of second vias disposed between the first conductive layer and the second conductive layer, wherein the at least one first conductive portion comprises a pair of conductive portions, wherein each of the pair of conductive portions is disposed on two separate conductive tracks of the plurality of conductive tracks and is coupled to the plurality of signal tracks through one of the plurality of second vias.

6. The integrated circuit of claim 1, wherein: a width of the at least one first conductive portion is less than or equal to a width of one of the plurality of conductive tracks, and a length of the at least one first conductive portion is less than or equal to a length of one of the plurality of conductive tracks.

7. An integrated circuit comprising: a first plurality of conductive tracks disposed in a first conductive layer and extending in a first direction, wherein the first plurality of conductive tracks is configured to transmit a power supply signal to at least one element of the integrated circuit; a second plurality of conductive tracks disposed in the first conductive layer and extending along the first direction, wherein, in a layout view, the second plurality of conductive tracks is disposed between the first plurality of conductive tracks and separated from each other, wherein the second plurality of conductive tracks is configured to transmit a data signal to the at least one element of the integrated circuit; at least one first via disposed between the first conductive layer and a second conductive layer above the first conductive layer and coupling one of the first plurality of conductive tracks to a power track disposed in the second conductive layer; and at least one first conductive portion disposed between the first conductive layer and the second conductive layer above the first conductive layer, wherein, in a layout view, the at least one first conductive portion at least partially overlaps at least two adjacent conductive tracks of the second plurality of conductive tracks and the at least one first conductive portion contacts the at least two adjacent conductive tracks of the second plurality of conductive tracks and is separated from a signal track disposed in the second conductive layer and immediately adjacent to the power track.

8. The integrated circuit of claim 7, further comprising: a plurality of second conductive portions disposed between the first conductive layer and the second conductive layer, wherein, in a layout view, the plurality of second conductive portions extends along the first direction and is disposed directly above the first plurality of conductive tracks, wherein, in a layout view, the plurality of second conductive portions does not exceed the first plurality of conductive tracks and is separated from the second conductive layer.

9. The integrated circuit of claim 8, wherein, one of the plurality of second conductive portions includes separated portions and, in a layout view, the at least one first via is disposed between the separated portions.

10. The integrated circuit of claim 9, further comprising: at least one second via disposed between the first conductive layer and the second conductive layer, wherein one of the plurality of second conductive portions is coupled to the power track through the at least one second via, and a height of the at least one first via is different from a height of the at least one second via.

11. The integrated circuit of claim 7, further comprising: a third conductive portion disposed above an active region below the first conductive layer and extending along a second direction to form a first transistor, wherein, in a layout view, the third conductive portion overlaps a first conductive track of the second plurality of conductive tracks; and a fourth conductive portion disposed above the active region and extending along the second direction to form a second transistor coupled to the first transistor, wherein, in a layout view, the fourth conductive portion overlaps a second conductive track of the second plurality of conductive tracks, wherein, in a layout view, the first conductive track and the second conductive track are immediately adjacent to each other and the first conductive track, the second conductive track, and the at least one first conductive portion partially overlap together.

12. The integrated circuit of claim 7, further comprising: at least one second via disposed below the first conductive layer, wherein, in a layout view, the at least one second via overlaps at least the second plurality of conductive tracks, wherein, in a layout view, the at least one first conductive portion overlaps the at least one second via, the at least two adjacent conductive tracks of the second plurality of conductive tracks, and the cut portions of the at least two adjacent conductive tracks.

13. The integrated circuit of claim 12, further comprising: at least one third conductive portion disposed over an active region underlying the first conductive layer and extending in a second direction to form a gate terminal, wherein, in a layout view, the at least one third conductive portion is disposed across the second plurality of conductive tracks, and the at least one third conductive portion is coupled to one of the second plurality of conductive tracks through the at least one second via.

14. The integrated circuit of claim 13, wherein, the at least one third conductive portion comprises: a plurality of third conductive portions separated from each other in the first direction, wherein a length of the at least one first conductive portion is substantially equal to or greater than a distance between two adjacent third conductive portions of the plurality of third conductive portions.

15. The integrated circuit of claim 7, further comprising: a plurality of third conductive portions disposed over an active region underlying the first conductive layer and extending in a second direction to form a transistor; and at least one second via disposed below the first conductive layer, wherein one of the plurality of third conductive portions is coupled to one of the second plurality of conductive tracks through the at least one second via, the one of the second plurality of conductive tracks is coupled to the power rail through the at least one first via, and a height of the at least one first via is greater than a height of the at least one first conductive portion.

16. A method of forming an integrated circuit, comprising: forming a plurality of conductive tracks; forming a film structure over the plurality of conductive tracks; patterning the film structure to form a first pattern; filling the first pattern with a conductive material to form a first conductive structure, the first conductive structure including at least one first conductive portion contacting at least one first conductive track of the plurality of conductive tracks; forming a dielectric structure covering the at least one first conductive portion; removing portions of the film structure and portions of the dielectric structure to expose portions of a second conductive track of the plurality of conductive tracks; and filling the conductive material in the removed portions of the film structure and the removed portions of the dielectric structure to form a second conductive structure, the second conductive structure including a first via contacting the exposed portions of the second conductive track and a signal track contacting the first via; forming at least one third conductive structure contacting at least two adjacent conductive tracks of the plurality of conductive tracks.

17. The method of claim 16, further comprising: patterning the dielectric structure to form a second pattern; and filling the second pattern with the conductive material to form a second via contacting the at least one first conductive portion, wherein the second via contacts the at least one first conductive portion and a power rail disposed immediately adjacent to the second conductive track.

18. The method of claim 16, further comprising: patterning the dielectric structure to form a second pattern; and filling the second pattern with the electrically conductive material to form a second via that contacts the at least one first electrically conductive portion.

19. The method of claim 16, further comprising: forming a second via that contacts the first electrically conductive track and a power supply track disposed proximate to the signal track, wherein the at least one first electrically conductive portion comprises separate portions and the second via is disposed between the separate portions of the at least one first electrically conductive portion.

20. The method of claim 16, wherein, a height of the first via is greater than a height of the at least one first electrically conductive portion and a width of the first via is substantially equal to or less than a width of the at least one first electrically conductive portion.

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