Dual conversion gain image sensor and method for manufacturing the same

Abstract

The present invention provides a dual-conversion-gain image sensor. The dual-conversion-gain image sensor includes a semiconductor substrate, which includes a first active region and a second active region that are isolated from each other; a floating diffusion region is disposed in the first active region; an auxiliary capacitor is disposed in the second active region for adjusting the conversion gain of the floating diffusion region; wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, the inner surface of the trench is covered with a dielectric layer, the upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each trench, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor. Filling each trench with the upper electrode plate of the auxiliary capacitor can increase the capacitance value of the auxiliary capacitor, so as to meet the requirements of a larger pixel full well capacity of the image sensor and improve the dynamic range of the image sensor. The present invention also provides a manufacturing method of the dual-conversion-gain image sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a dual conversion gain image sensor and a manufacturing method thereof. Background Art

[0002] Dynamic range is a key factor in the imaging quality of an image sensor (Contact Image Sensor, CIS). A large dynamic range can output scene image information within a wider light intensity range, presenting richer image details. Generally, the dynamic range output by an image sensor is about 60 db - 70 db, and in general natural environment applications, the dynamic range required to simultaneously capture image information of high light and shadow parts is about 100 db.

[0003] Currently, in the field of image sensors, dual conversion gain (DCG) is applied to the pixel circuit of an image sensor to increase the conversion gain with a smaller integration capacitor under low illumination conditions to improve the sensitivity of the image sensor; under high illumination conditions, the stored charge is increased with a larger integration capacitor, and the conversion gain is reduced to increase the dynamic range. In an image sensor with a DCG structure, an auxiliary capacitor is connected in parallel to the FD capacitor in the floating diffusion (FD) region, so that the floating diffusion region has a first conversion gain through the combination of the auxiliary capacitor and the FD capacitor. When the connection between the FD capacitor and the auxiliary capacitor is disconnected by a switching element, the floating diffusion region has a second conversion gain. Currently, when manufacturing an image sensor with a DCG structure, this auxiliary capacitor is often implemented using a planar MOS capacitor, a MIM (metal insulator metal) capacitor, or a MOM (metal oxid metal) capacitor. However, due to the limitation of chip area, the capacitance value of the auxiliary capacitor constructed with these types of capacitors is small and cannot meet the requirement of increasing the full well capacity (FWC) of the pixels of the image sensor, which is not conducive to the image sensor obtaining a larger dynamic range. Summary of the Invention

[0004] The present invention provides a dual conversion gain image sensor, which can increase the capacitance value of the auxiliary capacitor without increasing the chip area, thereby helping the image sensor to meet the requirement of a larger full well capacity of the pixels, and further facilitating the increase of the dynamic range of the image sensor. The present invention also provides a manufacturing method of an image sensor.

[0005] To achieve the above object, on the one hand, the present invention provides a dual-conversion gain image sensor. The dual-conversion gain image sensor includes a semiconductor substrate, the semiconductor substrate includes a first active region and a second active region, and a shallow trench isolation structure is provided between the first active region and the second active region; a floating diffusion region is disposed in the first active region for receiving stored charges from a photosensitive device; an auxiliary capacitor is disposed in the second active region for adjusting the conversion gain of the floating diffusion region. Wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, and the inner surface of the trenches is covered with a dielectric layer; the upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each trench, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor.

[0006] Optionally, the plurality of trenches are parallel to each other.

[0007] Optionally, the width of each trench is less than 0.2 micrometers, the depth is greater than 0.1 micrometers, and the distance between adjacent trenches is less than 0.2 micrometers.

[0008] Optionally, the number of trenches filled with the upper electrode plate of the auxiliary capacitor is more than three.

[0009] Optionally, the floating diffusion region has an FD capacitor, and the auxiliary capacitor is connected in parallel with the FD capacitor.

[0010] Optionally, the first active region is further provided with the photosensitive device, a transfer transistor, a switching transistor and a reset transistor; wherein, the output end of the photosensitive device is connected to the first source-drain region of the transfer transistor, the second source-drain region of the transfer transistor is connected to the first source-drain region of the switching transistor and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source-drain region of the switching transistor is connected to the first source-drain region of the reset transistor and the upper electrode plate of the auxiliary capacitor, the lower electrode plate of the auxiliary capacitor is grounded, and the second source-drain region of the reset transistor is connected to a power supply voltage.

[0011] Optionally, the first active region is further provided with a source follower transistor and a row selection transistor, the gate, the first source-drain region and the second source-drain region of the source follower transistor are respectively connected to the second source-drain region of the transfer transistor, a power supply voltage and the first source-drain region of the row selection transistor, and the second source-drain region of the row selection transistor is a signal output end.

[0012] On the other hand, the present invention further provides a manufacturing method of a dual-conversion gain image sensor. The manufacturing method includes:

[0013] Providing a semiconductor substrate, the semiconductor substrate includes a first active region and a second active region isolated from each other, and the first active region is used to form a photosensitive device and a floating diffusion region for receiving stored charges from the photosensitive device;

[0014] An auxiliary capacitor is formed in the second active region, and the auxiliary capacitor is used to adjust the conversion gain of the floating diffusion region. Wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, the inner walls of the trenches are covered with a dielectric layer, and the trenches are filled with an electrode material layer covering the dielectric layer. The electrode material layer serves as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor.

[0015] Optionally, the method for forming the photosensitive device, the floating diffusion region and the auxiliary capacitor includes:

[0016] Performing ion implantation in the first active region to form the photosensitive device;

[0017] Etching the semiconductor substrate of the second active region to form a plurality of the trenches;

[0018] Forming a dielectric layer and an electrode material layer covering the dielectric layer on the semiconductor substrate in sequence. The dielectric layer covers the inner surface of the trenches and the upper surface of the semiconductor substrate, and the electrode material layer fills the trenches and is located on the semiconductor substrate;

[0019] Etching the electrode material layer to form the gates of a plurality of functional transistors in the first active region and form the upper electrode plate of the auxiliary capacitor in the second active region;

[0020] Performing ion implantation to form the first source / drain regions, the second source / drain regions and the floating diffusion region of a plurality of the functional transistors in the first active region;

[0021] Forming an interconnect structure on the semiconductor substrate to form electrical interconnection between the first active region and the second active region.

[0022] Optionally, after forming a plurality of the trenches and before forming the dielectric layer, the manufacturing method includes:

[0023] Forming an oxide layer on the semiconductor substrate, and the oxide layer covers the inner surface of the trenches and the upper surface of the semiconductor substrate;

[0024] Injecting dopant ions into a plurality of the trenches to suppress dark current caused by defects on the inner surfaces of the trenches; and

[0025] Removing the oxide layer.

[0026] The dual-conversion gain image sensor of the present invention includes a semiconductor substrate, which includes a first active region and a second active region; a floating diffusion region is disposed in the first active region for receiving stored charges from a photosensitive device; the auxiliary capacitor is disposed in the second active region for adjusting the conversion gain of the floating diffusion region; wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, the inner surface of the trenches is covered with a dielectric layer, the upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each trench, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor. That is to say, a part of the upper electrode plate of the auxiliary capacitor is located above a plurality of the trenches and another part fills the plurality of trenches. Without increasing the chip area, the surface area of the auxiliary capacitor electrode plate can be increased, and the capacitance value of the auxiliary capacitor can be increased, which helps the image sensor to meet the requirements of a larger pixel full well capacity, and further facilitates improving the dynamic range of the image sensor.

[0027] In the manufacturing method of the dual-conversion gain image sensor of the present invention, a plurality of trenches are formed in the semiconductor substrate of the second active region, the inner wall of the trenches is covered with a dielectric layer and filled with an electrode material layer covering the dielectric layer. The electrode material layer serves as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor. In this way, a part of the upper electrode plate of the auxiliary capacitor can be located above a plurality of trenches and another part fills the plurality of trenches. The surface area of the auxiliary capacitor electrode plate can be increased, and the capacitance value of the auxiliary capacitor can be increased, which helps the image sensor to meet the requirements of a larger pixel full well capacity, and further facilitates improving the dynamic range of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the architecture of the dual-conversion gain image sensor according to an embodiment of the present invention.

[0029] Figure 2 It is a schematic plan view of the dual-conversion gain image sensor according to an embodiment of the present invention.

[0030] Figure 3 is Figure 2 A schematic cross-sectional view of the dual-conversion gain image sensor shown along line AA.

[0031] Figures 4 to 6 It is a schematic diagram of the manufacturing process of the dual-conversion gain image sensor according to an embodiment of the present invention.

[0032] Explanation of the reference numerals: 10 - semiconductor substrate; 100 - first active region; 101 - photosensitive device; 102 - floating diffusion region; 200 - second active region; 201 - trench; 202 - upper plate; 300 - shallow trench isolation structure; 401 - first oxide layer; 402 - hard mask layer; 403 - dielectric layer; 404 - electrode material layer; 500 - contact plug. DETAILED DESCRIPTION

[0033] The dual conversion gain image sensor and its manufacturing method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] In order to improve the dynamic range of the image sensor, this embodiment provides a dual conversion gain image sensor. Figure 1 FIG. 4 shows the architecture of the dual conversion gain image sensor of this embodiment. Figure 2 FIG. 4 shows the planar layout of the dual conversion gain image sensor of this embodiment. Figure 3 for Figure 2 The cross-sectional diagram of the dual conversion gain image sensor along line AA is shown in FIG. Figures 1 to 3 As shown, the dual conversion gain image sensor includes a semiconductor substrate 10, and the semiconductor substrate 10 includes a first active area 100 and a second active area 200, and a shallow trench isolation structure 300 is arranged between the first active area 100 and the second active area 200. A floating diffusion region 102 (Floating Diffusion, FD) is arranged in the first active area 100, and is used to receive the stored charge from the photosensitive device 101, or to receive the charge generated and stored by the photosensitive device 101 under illumination conditions. The photosensitive device 101 is, for example, a photodiode (Photo-Diode, PD). The auxiliary capacitor (C 辅 ) is arranged in the second active area 200 and is used to adjust the conversion gain of the floating diffusion area 102.

[0035] Among them, a plurality of trenches 201 are formed in the semiconductor substrate of the second active region 200. The inner surface of the trench 201 is covered with a dielectric layer 403. The upper plate 202 of the auxiliary capacitor covers the dielectric layer 403 in the trench 201 and fills (completely fills) each trench 201. The semiconductor substrate 10 opposite to the upper plate 202 of the auxiliary capacitor serves as the lower plate of the auxiliary capacitor. That is to say, a part of the upper plate 202 of the auxiliary capacitor is located above a plurality of trenches 201 and another part is filled in a plurality of trenches 201. Without increasing the chip area, the surface area of the upper plate 202 of the auxiliary capacitor can be increased, and the capacitance value of the auxiliary capacitor can be increased, which helps the image sensor to meet the requirement of a larger pixel full well capacity, and further facilitates improving the dynamic range of the image sensor.

[0036] In this embodiment, the floating diffusion region 102 has an FD capacitor (corresponding to Figure 1 C in FD ), and the auxiliary capacitor is connected in parallel with the FD capacitor. Specifically, when the auxiliary capacitor works, it is in a parallel relationship with the FD capacitor. It should be noted that the floating diffusion region 102 is formed by implanting dopant ions in the semiconductor substrate 10 and can receive the stored charge from the photosensitive device 101. That is, the floating diffusion region 102 is an FD capacitor, and moreover, the floating diffusion region 102 can also be called a floating diffusion node.

[0037] A plurality of trenches 201 can be parallel to each other so as to fabricate more trenches 201 under the condition of the same chip area, which helps to increase the capacitance value of the auxiliary capacitor. As an example, as Figure 2 and Figure 3 shown, the number of trenches 201 filled with the upper plate 202 of the auxiliary capacitor is three. However, it is not limited thereto. In other embodiments, a plurality of trenches 201 may not be parallel, and the number of trenches 201 filled with the upper plate 202 may also be two or more than three.

[0038] When the width of the trench 201 and the spacing between two adjacent trenches 201 are small, more trenches 201 can be provided under the condition of the same chip area, which can increase the density of the trenches 201, contribute to increasing the surface area of the upper plate 202 of the auxiliary capacitor, and further increase the capacitance value of the auxiliary capacitor. Therefore, in this embodiment, the width of each trench 201 can be less than 0.2 microns, and the spacing between two adjacent trenches can be less than 0.2 microns. The depth of the trench 201 can be greater than 0.1 microns, and when allowed by the process window, increasing the depth of the trench 201 can increase the surface area of the upper plate 202. As an example, the width of the trench 201 is 0.13 microns, and the spacing between two adjacent trenches 201 is 0.13 microns. Thus, the trench 201 can be fabricated by a process with Trench W / S = 0.13 microns / 0.13 microns. However, it is not limited thereto, and the width, depth, and spacing between two adjacent trenches of the trench 201 can be adjusted as needed.

[0039] Through experimental comparison, it is found that when the chip areas are all 10 microns × 10 microns, the capacitance value of the planar MOS capacitor is about 320 fF, the capacitance value of the MIM capacitor is about 200 fF, the capacitance value of the MOM capacitor is about 238 fF, while the capacitance value of the auxiliary capacitor in this embodiment can reach 3840 fF. It can be seen that in this embodiment, by providing a plurality of trenches 201 in the semiconductor substrate of the second active region 200 of the auxiliary capacitor and filling the upper plate 202 of each trench 201 with the auxiliary capacitor, the surface area of the upper plate 202 can be effectively increased, and further the capacitance value of the auxiliary capacitor can be effectively increased.

[0040] Reference Figures 1 to 3 , the first active region 100 may further be provided with the photosensitive device 101, transfer transistor Tx, switching transistor Sx, and reset transistor Rx. Among them, the output end of the photosensitive device 101 may be connected to the first source-drain region of the transfer transistor Tx, the second source-drain region of the transfer transistor Tx may be connected to the first source-drain region of the switching transistor Sx and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source-drain region of the switching transistor Sx may be connected to the first source-drain region of the reset transistor Rx and the upper plate 202 of the auxiliary capacitor (C 辅 ), the lower plate of the auxiliary capacitor is grounded (i.e., the semiconductor substrate 10 is grounded), and the second source-drain region of the reset transistor Rx is connected to the power supply voltage (VDD).

[0041] It should be noted that the transfer transistor Tx can be used to transfer the charge generated and stored by the photosensitive device 101 from the photosensitive device 101 to the floating diffusion region 102. The switching transistor Sx can be used to control the parallel relationship between the FD capacitor and the auxiliary capacitor. As an example, under high illumination conditions (e.g., greater than or equal to a first set value), the switching transistor Sx is connected so that the auxiliary capacitor is in parallel with the FD capacitor to adjust the conversion gain of the floating diffusion region 102 (i.e., the floating diffusion region 102 has a first conversion gain), thereby helping the image sensor to meet the requirement of a larger pixel full well capacity; under low illumination conditions (e.g., less than the first set value), the switching transistor Sx is turned off so that the auxiliary capacitor is disconnected from the FD capacitor, and the floating diffusion region 102 has a second conversion gain. The first set value can be specifically set according to actual situations, and this embodiment does not make a limitation. The reset transistor Rx can be used to introduce a reset voltage (slightly less than the power supply voltage) into the floating diffusion region 102 through the power supply voltage to reset the voltage of the floating diffusion region 102. Among them, when the reset transistor Rx resets the floating diffusion region 102, the switching transistor Sx is connected and the transfer transistor Tx is turned off.

[0042] In this embodiment, the first active region 100 may further be provided with a source follower transistor SF and a row selection transistor RS. Among them, the gate of the source follower transistor SF may be connected to the second source-drain region of the transfer transistor Tx (i.e., the gate of the source follower transistor SF is connected to the floating diffusion region 102), the first source-drain region of the source follower transistor SF may be connected to the power supply voltage (VDD), the second source-drain region of the source follower transistor SF may be connected to the first source-drain region of the row selection transistor RS, and the second source-drain region of the row selection transistor RS is the signal output terminal.

[0043] It should be noted that the source follower transistor SF can be used to receive the voltage of the floating diffusion region 102 and provide an amplified voltage at the second source-drain region of the source follower transistor SF (e.g., at the source of the source follower transistor SF). The row selection transistor RS can be used to receive the amplified voltage and output the amplified voltage, for example, provide the amplified voltage to the bit line.

[0044] In this embodiment, the gates of the transfer transistor Tx, the switching transistor Sx, the reset transistor Rx, and the row selection transistor RS are all connected to the corresponding control circuit, and the control circuit controls the gate voltage of the corresponding functional transistor (referring to the transfer transistor Tx, the switching transistor Sx, the reset transistor Rx, or the row selection transistor RS) to turn on or off the corresponding functional transistor.

[0045] The transfer transistor Tx, the switching transistor Sx, the reset transistor Rx, the source follower transistor SF, and the row selection transistor RS may be arranged in sequence along a set direction (i.e., arranged in a row), and the trench 201 may extend along the set direction, so that the chip area can be effectively utilized.

[0046] To save chip area, as Figure 2 shown, the second source-drain region of the transfer transistor Tx and the first source-drain region of the switch transistor Sx can share the same source-drain region, the second source-drain region of the switch transistor Sx and the first source-drain region of the reset transistor Rx can share the same source-drain region, the second source-drain region of the reset transistor Rx and the first source-drain region of the source follower transistor SF can share the same source-drain region, and the second source-drain region of the source follower transistor SF and the first source-drain region of the row selection transistor RS can share the same source-drain region.

[0047] In this embodiment, as Figure 2 shown, an interconnect structure may be formed on the semiconductor substrate 10, and the interconnect structure may include a plurality of contact plugs 500 and a plurality of conductive lines. The plurality of contact plugs 500 may be respectively connected to the source-drain regions (collectively referred to as the first source-drain region and the second source-drain region) or the gates of the respective functional transistors. Through the plurality of contact plugs 500 and the plurality of conductive lines, the photosensitive device 101, the floating diffusion region 102, the transfer transistor Tx, the switch transistor Sx, the reset transistor Rx, the source follower transistor SF, the row selection transistor RS, and the auxiliary capacitor can achieve the electrical connection relationship as Figure 1 shown.

[0048] The dual conversion gain image sensor of this embodiment includes a semiconductor substrate 10, and the semiconductor substrate 10 includes a first active region 100 and a second active region 200; a floating diffusion region 102 is disposed in the first active region 100 for receiving stored charges from the photosensitive device 101; the auxiliary capacitor (C 辅 ) is disposed in the second active region 200 for adjusting the conversion gain of the floating diffusion region 102; wherein, a plurality of trenches 201 are formed in the semiconductor substrate of the second active region 200, the inner surface of the trenches 201 is covered with a dielectric layer 403, the upper electrode plate 202 of the auxiliary capacitor covers the dielectric layer 403 in the trenches and fills each of the trenches 201, and the semiconductor substrate opposite to the upper electrode plate 202 of the auxiliary capacitor is the lower electrode plate of the auxiliary capacitor. That is to say, a part of the upper electrode plate 202 of the auxiliary capacitor is located above the plurality of trenches 201 and another part extends vertically into the trenches 201. Without increasing the chip area, the surface area of the auxiliary capacitor electrode plate can be increased, and the capacitance value of the auxiliary capacitor can be increased, which helps the image sensor to meet the requirements of a larger pixel full well capacity, and further facilitates improving the dynamic range of the image sensor.

[0049] This embodiment also provides a manufacturing method of a dual conversion gain image sensor, and the above dual conversion gain image sensor can be manufactured by using this manufacturing method.

[0050] The manufacturing method of the dual conversion gain image sensor includes:

[0051] A semiconductor substrate is provided, which includes a first active region and a second active region that are isolated from each other. The first active region is used to form a photosensitive device and a floating diffusion region for receiving stored charges from the photosensitive device;

[0052] An auxiliary capacitor is formed in the second active region. The auxiliary capacitor is used to adjust the conversion gain of the floating diffusion region. Wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region. The inner walls of the trenches are covered with a dielectric layer and the trenches are filled with an electrode material layer covering the dielectric layer (the electrode material layer fills the trenches). The electrode material layer serves as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor.

[0053] Figures 4 to 6 It is a schematic diagram of the manufacturing process of a dual-conversion gain image sensor according to an embodiment of the present invention. The following combines Figures 1 to 6 to illustrate the manufacturing method of the dual-conversion gain image sensor of this embodiment.

[0054] Refer to Figure 3 and Figure 4 , the semiconductor substrate 10 includes a first active region 100 and a second active region 200 that are isolated from each other. The first active region 100 is used to form a photosensitive device 101 and a floating diffusion region 102 for receiving stored charges from the photosensitive device 101. The first active region 100 and the second active region 200 can be isolated by a shallow trench isolation structure 300. The shallow trench isolation structure 300 is formed before the photosensitive device 101 and the floating diffusion region 102 are formed, and the shallow trench isolation structure 300 can define the first active region 100 and the second active region 200.

[0055] The semiconductor substrate 10 can be various semiconductor materials well-known to those skilled in the semiconductor art. As an example, the semiconductor substrate 10 can be single-crystalline or polycrystalline silicon or silicon germanium (SiGe); it can also be silicon or silicon germanium containing doped ions such as N-type or P-type doping; it can also include compound semiconductor structures such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, gallium nitride, aluminum nitride or indium nitride alloy semiconductors, or a combination thereof; it can also be silicon on insulator (SOI); it can also be strained silicon, strained silicon germanium or other strained materials. The semiconductor substrate can be a blank semiconductor material substrate, or a semiconductor substrate on which various semiconductor structures, devices and circuits have been formed.

[0056] In this embodiment, the method for forming the photosensitive device 101, the floating diffusion region 102, and the auxiliary capacitor may include the following sub-steps S01 to S06.

[0057] Sub-step S01, as Figure 4 shown, after forming the shallow trench isolation structure 300, ion implantation is performed in the first active region 100 to form the photosensitive device 101. Specifically, two ion implantations may be performed in the semiconductor substrate of the first active region 100 to sequentially form the N-doped region of the photosensitive device 101 and the P+-doped region located above the N-doped region, where the boundary of the N-doped region extends beyond the boundary of the P+-doped region.

[0058] Sub-step S02, as Figure 5 shown, etch the semiconductor substrate of the second active region 200 to form a plurality of trenches 201. Specifically, after forming the photosensitive device 101 in the first active region 100, a first oxide layer 401 and a hard mask layer 402 are sequentially deposited on the semiconductor substrate 10. The first oxide layer 401 covers the upper surface of the semiconductor substrate 10, and the hard mask layer 402 covers the upper surface of the first oxide layer 401; the hard mask layer 402 is subjected to patterning to form a patterned hard mask layer, and the first oxide layer 401 and the semiconductor substrate 10 are sequentially etched using the patterned hard mask layer as a mask and stopped in the semiconductor substrate 10 to form a plurality of trenches 201 in the semiconductor substrate of the second active region 200.

[0059] After forming a plurality of the trenches 201, sub-step S02 may further include: forming a second oxide layer (not shown in the figure) on the semiconductor substrate 10, and the second oxide layer may cover the inner surface of the trenches 201 and the upper surface of the semiconductor substrate 10; then implanting dopant ions into the plurality of trenches 201, and the dopant ions penetrate the second oxide layer in the trenches 201 and enter the semiconductor substrate corresponding to the inner surface of the trenches 201, so that a doped region is formed on the surface layer of the semiconductor substrate corresponding to the inner surface of the trenches 201 to suppress the dark current caused by defects on the inner surface of the trenches 201; then, removing the second oxide layer, the hard mask layer 402, and the first oxide layer 401. The first oxide layer 401 and the second oxide layer may be silicon oxide layers. The hard mask layer 402 may be a silicon nitride layer.

[0060] After performing sub-step S02, perform sub-step S03, as Figure 6As shown, a dielectric layer 403 and an electrode material layer 404 covering the dielectric layer 403 are sequentially formed on the semiconductor substrate 10. The dielectric layer 403 covers the inner surface of the trench 201 and the upper surface of the semiconductor substrate 10. The electrode material layer 404 fills (completely fills) the trench 201 and is located on the semiconductor substrate 10. The dielectric layer 403 can be a silicon oxide layer. The electrode material layer 404 can be a polysilicon layer. However, it is not limited thereto, and the dielectric layer 403 and the electrode material layer 404 can be selected according to needs. The dielectric layer 403 and the electrode material layer 404 can be formed by deposition methods well-known in the art, which are not limited herein.

[0061] Perform sub-step S04, refer to Figure 2 and Figure 3 , etch the electrode material layer 404 to form gates of several functional transistors in the first active region 100 and form the upper plate 202 of the auxiliary capacitor in the second active region 200. The several functional transistors can include a transfer transistor Tx, a switching transistor Sx, a reset transistor Rx, a source follower transistor SF, and a row selection transistor RS.

[0062] Perform sub-step S05, perform ion implantation to form a first source / drain region, a second source / drain region, and a floating diffusion region 102 of several of the functional transistors in the first active region 100.

[0063] As an example, both the first source / drain region and the second source / drain region can include an N-doped region and an N+-doped region. Refer to Figure 3 , sub-step S05 can specifically include: after forming gates of several of the functional transistors and the upper plate 202 of the auxiliary capacitor, perform ion implantation to form an N-doped region of the source / drain region (a collective term for the first source / drain region and the second source / drain region) in the semiconductor substrate on both sides of the gate; then, form sidewalls on both sides of the gate, and the sidewalls can cover partial edges of the N-doped region of the source / drain region; then, continue ion implantation in the semiconductor substrate on the side of the sidewalls to form an N+-doped region of the source / drain region above the N-doped region of the source / drain region. Among them, after forming the N-doped region of the source / drain region and before forming the sidewalls, a part of the dielectric layer 403 on the upper surface of the semiconductor substrate 10 can be removed, and the dielectric layer 403 under each gate and the upper plate 202 of the auxiliary capacitor can be retained.

[0064] It should be noted that in this embodiment, the N-doped region of the photosensitive device 101 overlaps with the gate portion of the transfer transistor Tx. The photosensitive device 101 can serve as the first source-drain region of the transfer transistor Tx, that is, in sub-step S05, it is not necessary to fabricate the first source-drain region of the transfer transistor Tx on the side of the gate of the transfer transistor Tx. A P-doped region is further formed below the N-doped region of the second source-drain region of the transfer transistor Tx. This P-doped region can be formed before the N-doped region is formed, and the second source-drain region of the transfer transistor Tx serves as the floating diffusion region 102 of the dual conversion gain image sensor.

[0065] The above introduction to the manufacturing method of the dual conversion gain image sensor is described by taking the semiconductor substrate 10 as P-type as an example. In other embodiments, the semiconductor substrate can also be N-type. Correspondingly, the types of dopant ions in each doped region of the source-drain regions of several functional transistors can also be adaptively changed.

[0066] In this embodiment, the gates of several functional transistors can be arranged in sequence along a set direction (i.e., arranged in rows). In order to save chip area, as Figure 2 shown, the second source-drain region of the transfer transistor Tx and the first source-drain region of the switch transistor Sx can share the same source-drain region, the second source-drain region of the switch transistor and the first source-drain region of the reset transistor Rx can share the same source-drain region, the second source-drain region of the reset transistor Rx and the first source-drain region of the source follower transistor SF can share the same source-drain region, and the second source-drain region of the source follower transistor SF and the first source-drain region of the row selection transistor RS can share the same source-drain region.

[0067] After sub-step S05 is completed, sub-step S06 is executed to form an interconnect structure on the semiconductor substrate 10 to form an electrical interconnection between the first active region 100 and the second active region 200. Specifically, referring to Figure 1 and Figure 2 , the interconnect structure can include contact plugs 500 and conductive lines. Through the contact plugs 500 and conductive lines, the upper plate 202 of the auxiliary capacitor (C 辅 ) can be electrically connected to the second source-drain region of the switch transistor Sx, the gate of the source follower transistor SF can be electrically connected to the floating diffusion region 102 (FD), the second source-drain region of the reset transistor Rx and the first source-drain region of the source follower transistor SF are both electrically connected to the power supply voltage (VDD), and the gates of the transfer transistor Tx, the reset transistor Rx, the switch transistor Sx, and the row selection transistor RS are respectively connected to the corresponding control circuits.

[0068] It should be understood that the specific embodiments described in this application are only used to explain this application and are not used to limit this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in this application without creative efforts belong to the scope of protection of this application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in this application, some design, manufacturing, or production changes based on the technical content disclosed in this application are only conventional technical means and should not be understood as insufficient disclosure of the content of this application.

[0069] In this application, the mention of "embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The phrase appears in various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

[0070] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the ordinary meaning understood by those of ordinary skill in the technical field to which this application belongs. The words such as "a", "one", "a kind of", "the" and the like involved in this application do not indicate a quantity limitation and can represent a singular or plural number. The terms "including", "comprising", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. The "multiple" involved in this application means greater than or equal to two. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. The terms "first", "second", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects. The "connection" and "coupling" mentioned in this application, unless otherwise specified, both include direct and indirect connection (coupling). The orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", etc. involved in this application is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation to this application.

[0071] In this application, unless otherwise clearly defined and specified, when a first feature is "on" or "under" a second feature, it may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature is to describe that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature is to describe that the horizontal height of the first feature is lower than that of the second feature.

[0072] It should be noted that the embodiments in this specification are described in a progressive manner. The key points of the manufacturing method of the dual conversion gain image sensor described later mainly illustrate the differences from the dual conversion gain image sensor described earlier. The same and similar parts between each part can be referred to each other. For the dual conversion gain image sensor disclosed in the embodiments, since it corresponds to the manufacturing method of the dual conversion gain image sensor disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.

[0073] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A dual conversion gain image sensor, characterized in that, it includes: A semiconductor substrate, the semiconductor substrate includes a first active region and a second active region, and a shallow trench isolation structure is provided between the first active region and the second active region; A floating diffusion region, the floating diffusion region is disposed in the first active region for receiving stored charges from a photosensitive device; An auxiliary capacitor, the auxiliary capacitor is disposed in the second active region for adjusting the conversion gain of the floating diffusion region; Wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, and the inner surface of the trenches is covered with a dielectric layer; The upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each trench, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor; the floating diffusion region has an FD capacitor, and the first active region is further provided with the photosensitive device, a transfer transistor, a switching transistor and a reset transistor. Among them, the output end of the photosensitive device is connected to the first source-drain region of the transfer transistor, the second source-drain region of the transfer transistor is connected to the first source-drain region of the switching transistor and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source-drain region of the switching transistor is connected to the first source-drain region of the reset transistor and the upper electrode plate of the auxiliary capacitor, the lower electrode plate of the auxiliary capacitor is grounded, and the second source-drain region of the reset transistor is connected to a power supply voltage.

2. The dual conversion gain image sensor according to claim 1, characterized in that, A plurality of the trenches are parallel to each other.

3. The dual conversion gain image sensor according to claim 2, characterized in that, The width of each trench is less than 0.2 microns, the depth is greater than 0.1 microns, and the distance between adjacent two trenches is less than 0.2 microns.

4. The dual conversion gain image sensor according to claim 1, characterized in that, The number of trenches filled with the upper electrode plate of the auxiliary capacitor is more than three.

5. The dual conversion gain image sensor according to claim 1, characterized in that, The auxiliary capacitor is connected in parallel with the FD capacitor.

6. The dual conversion gain image sensor according to claim 1, characterized in that, The first active region is further provided with a source follower transistor and a row selection transistor; wherein, the gate, the first source-drain region and the second source-drain region of the source follower transistor are respectively connected to the second source-drain region of the transfer transistor, a power supply voltage and the first source-drain region of the row selection transistor, and the second source-drain region of the row selection transistor is a signal output end.

7. A manufacturing method of a dual conversion gain image sensor, characterized in that, it includes: Providing a semiconductor substrate, the semiconductor substrate includes a first active region and a second active region isolated from each other, and the first active region is used to form a photosensitive device and a floating diffusion region for receiving stored charges from the photosensitive device; An auxiliary capacitor is formed in the second active region, and the auxiliary capacitor is used to adjust the conversion gain of the floating diffusion region. Wherein, a plurality of trenches are formed in the semiconductor substrate of the second active region, the inner walls of the trenches are covered with a dielectric layer, and the trenches are filled with an electrode material layer covering the dielectric layer. The electrode material layer serves as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor serves as the lower electrode plate of the auxiliary capacitor; The floating diffusion region has an FD capacitor. The first active region is further provided with the photosensitive device, the transfer transistor, the switch transistor and the reset transistor. Wherein, the output end of the photosensitive device is connected to the first source-drain region of the transfer transistor, the second source-drain region of the transfer transistor is connected to the first source-drain region of the switch transistor and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source-drain region of the switch transistor is connected to the first source-drain region of the reset transistor and the upper electrode plate of the auxiliary capacitor, the lower electrode plate of the auxiliary capacitor is grounded, and the second source-drain region of the reset transistor is connected to the power supply voltage.

8. The manufacturing method of the dual-conversion gain image sensor according to claim 7, characterized in that, The method for forming the photosensitive device, the floating diffusion region and the auxiliary capacitor includes: Performing ion implantation in the first active region to form the photosensitive device; Etching the semiconductor substrate of the second active region to form a plurality of the trenches; Successively forming a dielectric layer and an electrode material layer covering the dielectric layer on the semiconductor substrate. The dielectric layer covers the inner surface of the trenches and the upper surface of the semiconductor substrate, and the electrode material layer fills the trenches and is located on the semiconductor substrate; Etching the electrode material layer to form the gate electrodes of a plurality of functional transistors in the first active region and form the upper electrode plate of the auxiliary capacitor in the second active region; Performing ion implantation to form the first source-drain regions, the second source-drain regions of a plurality of the functional transistors and the floating diffusion region in the first active region; Forming an interconnect structure on the semiconductor substrate to form electrical interconnection between the first active region and the second active region.

9. The manufacturing method of the image sensor according to claim 8, characterized in that, Before forming the dielectric layer after forming a plurality of the trenches, the manufacturing method includes: Forming an oxide layer on the semiconductor substrate, and the oxide layer covers the inner surface of the trenches and the upper surface of the semiconductor substrate; Injecting dopant ions into a plurality of the trenches to suppress dark current caused by defects on the inner surface of the trenches; and Removing the oxide layer.

Images