A chip and an integrated chip

Abstract

The chip and the integrated chip are used to solve the problem that the upper and lower chips in the existing packaging chip need to be interconnected through the TSV mode, resulting in high warping risk, complex design and difficult manufacturing process in the structure of the lower chip. The integrated chip comprises an interconnection layer, a first chip, a second chip and a first vertical interconnection structure arranged on the interconnection layer. The second chip comprises a first part and a second part, the first part is arranged on the top surface of the first chip, and the second part protrudes from the side of the first chip; the first vertical interconnection structure is arranged on the side of the first chip, and the second part of the second chip is electrically connected to the interconnection layer through the first vertical interconnection structure, that is, the first chip and the second chip are arranged staggered, the first vertical interconnection structure and the second part of the second chip are arranged on the same side of the first chip, the second part of the second chip bypasses the first chip, and is electrically connected to the interconnection layer through the first vertical interconnection structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and in particular to a chip and an integrated chip. BACKGROUND

[0002] With the development of semiconductor technology, the position of chip packaging technology in the electronic device industry chain has become more and more important. Among them, the package on package (POP) technology in the chip packaging technology is relatively mature, and has high feasibility, which can greatly improve the integration of chip packaging and has high benefits.

[0003] At present, the upper chip and the lower chip in the integrated chip packaged by the package on package technology are interconnected through solder balls, wiring layers, vertical interconnection structures and substrates, etc., and the interconnection traces are relatively long, which leads to a small bandwidth of the chip formed after the package on package.

[0004] The common structure of the integrated chip using the package on package technology is shown in FIG. 1, wherein the upper chip is located above the lower chip, and the upper chip is electrically interconnected with the lower chip through solder balls, interconnection layers (wiring layers or substrates), vertical interconnection structures, fanout redistribution layers (FO-RDL) and copper studs. Figure 1 Among them, the upper chip can be a dynamic random access memory (DRAM) chip, and the lower chip can be a system on chip (SOC). The DRAM chip is usually a packaged DRAM package directly purchased from a memory manufacturer. The multiple memory bare dies in the packaged memory are interconnected between different layers of bare dies through wire bonding (WB) or through silicon via (TSV) technology, and the package is formed by plastic packaging.

[0005] As shown in FIG. 1, the upper chip is electrically interconnected with the lower chip through solder balls, interconnection layers (wiring layers or substrates), vertical interconnection structures, fanout redistribution layers (FO-RDL) and copper studs. Figure 1It can be known that the upper chip and the lower chip are electrically connected through the solder balls, the interconnection layer, the vertical interconnection structure, the fan-out wiring layer and the small copper pillars, the interconnection path is long, and the bandwidth of the packaged integrated chip is small. With the rapid development of semiconductor technology, considering the needs of heat dissipation and power distribution, the lower chip also has the demand of multi-chip integration. In order to improve the working efficiency of the SOC, a storage chip will be packaged in the lower chip for the SOC. In this way, the data with high transmission rate requirement required by the SOC can be stored in the storage chip in the lower chip, without the need to access the DRAM chip in the upper layer. The packaging of the SOC and the storage chip in the lower chip usually also adopts a stacking manner, such as arranging the SOC on the top of the storage chip, the active surface of the SOC is attached to the silicon layer of the storage chip, and then the TSV is punched in the silicon layer of the storage chip to realize the interconnection of the active surfaces of the SOC and the storage chip.

[0006] In this scenario, since the TSV needs to be formed in the storage chip in the lower chip, the volume of the storage chip in the lower chip needs to be increased, especially the lateral area, thereby increasing the warping risk in the structure of the lower chip. At the same time, it also increases the design complexity of the lower chip and the difficulty of the manufacturing process. SUMMARY

[0007] The present application provides a chip and an integrated chip to solve the problem that the upper and lower chips in the packaged chip need to be interconnected through the TSV, which leads to high warping risk, design complexity and manufacturing process difficulty in the structure of the lower chip.

[0008] In a first aspect, the present application provides an integrated chip, which includes an interconnection layer, a first chip, a second chip and a first vertical interconnection structure arranged on the interconnection layer. The second chip includes a first part and a second part, the first part is arranged on the top surface of the first chip, and the second part protrudes from the side of the first chip; the first vertical interconnection structure is arranged on the side of the first chip, and the second part of the second chip is electrically connected to the interconnection layer through the first vertical interconnection structure. That is, the first chip and the second chip are arranged staggered, the first vertical interconnection structure and the second part of the second chip are arranged on the same side of the first chip, and the second part of the second chip bypasses the first chip and is electrically connected to the interconnection layer through the first vertical interconnection structure.

[0009] Through the above scheme, the second chip in the integrated chip is electrically connected with the first chip arranged on the interconnection layer through the first vertical interconnection structure, so that the interconnection path between the second chip and the first chip can be shortened as much as possible, so as to improve the data transmission rate of the integrated chip, that is, to improve the bandwidth of the integrated chip. Moreover, the second part of the second chip bypasses the first core and is electrically connected with the interconnection layer through the first vertical interconnection structure, so that the TSV does not need to be made in the first chip and the second chip, which can reduce the complexity of design and processing of the integrated chip, and the risk of stress and warping.

[0010] In the embodiments of the present application, the first chip and the second chip can be any combination of processor chips and memory chips, such as the first chip being a processor chip and the second chip being a memory chip, or the first chip being a memory chip and the second chip being a processor chip. In alternative embodiments, the first chip and the second chip can also be any combination of other types of chips.

[0011] In addition, the structure of the integrated chip is a common stacked package structure, which has low technical risk, high technical feasibility, good package integration performance, and is easy to package other chips together.

[0012] In one possible implementation, the first vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of mold encapsulation through holes TMV, or a plurality of dielectric layer through holes TDV, or a plurality of insulating layer through holes TIV. One end of the first vertical interconnection structure is directly connected to the bottom of the second part of the second chip, and the other end of the first vertical interconnection structure is directly connected to the conductive layer in the interconnection layer.

[0013] In one possible implementation, the second chip is provided with data transmission pins, and all the signal transmission pins on the second chip are arranged at the bottom of the second part of the second chip, so as to shorten the data transmission path between the first chip and the second chip, thereby improving the bandwidth of the integrated chip.

[0014] Further, the pins in the first chip for connecting with the pins of the second chip can be arranged on the side of the first chip close to the second part of the second chip, so as to shorten the interconnection path between the first chip and the second chip to the greatest extent, thereby improving the bandwidth of the integrated chip.

[0015] In one possible implementation, the second chip is further provided with power supply pins, and the power supply pins on the second chip are arranged at the bottom of the second part of the second chip.

[0016] In a possible implementation, the data transmission pins and the power supply pins of the second chip are arranged in an array to form a first pin array. In the first pin array, the types of the pins in any column are the same, and the types of the pins in any two adjacent columns are different, that is, in any two adjacent columns of the first pin array, one column is composed of signal transmission pins, and the other column is composed of power supply pins. Alternatively, in the first pin array, the types of the pins in any row are the same, and the types of the pins in any two adjacent rows are different, that is, in any two adjacent rows of the first pin array, one row is composed of signal transmission pins, and the other row is composed of power supply pins.

[0017] Compared with the power supply pins of the chip, the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and the power supply pins of the second chip are arranged in rows or columns to reduce the area occupied by the pins in the second chip, and to increase the number of pins in a unit area of the second chip, thereby meeting the requirement of high integration of the chip. Meanwhile, the signal transmission pins and the power supply pins of the second chip are arranged in rows or columns to separate the signal transmission pins in different columns, reduce the mutual influence between the signal transmission pins, and improve the signal transmission quality.

[0018] In a possible implementation, the first chip can be a processor chip, and the second chip can be a memory chip.

[0019] In a possible implementation, the first part of the second chip is fixed on the top surface of the first chip by using a bonding material. The bonding material can be a chip adhesive or silver paste.

[0020] In a possible implementation, the integrated chip includes at least two first chips, or at least two second chips, or at least two first chips and at least two second chips.

[0021] In a possible implementation, the integrated chip further includes a third chip and a second vertical interconnection structure. The third chip includes a third part and a fourth part, the third part is fixed on the top surface of the second chip, and the fourth part protrudes from the side of the second chip. The second vertical interconnection structure is arranged on the side of the second chip, and the fourth part of the third chip is electrically connected to the interconnection layer through the second vertical interconnection structure.

[0022] In a possible implementation, the second vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of mold encapsulation through holes TMVs, or a plurality of dielectric layer through holes TDVs, or a plurality of insulating layer through holes TIVs. One end of the second vertical interconnection structure is directly connected to the bottom of the fourth part of the third chip, and the other end of the second vertical interconnection structure is directly connected to the conductive layer in the interconnection layer.

[0023] In one possible implementation, the third chip is provided with data transmission pins, and all the signal transmission pins on the third chip are arranged at the bottom of the fourth part of the third chip, so as to shorten the data transmission path between the first chip and the third chip, and thus to improve the bandwidth of the integrated chip.

[0024] Further, the pins on the first chip for connecting with the pins of the third chip can be arranged on the side of the first chip close to the fourth part of the third chip, so as to shorten the interconnection path between the first chip and the third chip to the greatest extent, and to improve the bandwidth of the integrated chip.

[0025] In one possible implementation, the third chip is further provided with power supply pins, and all the power supply pins on the third chip are arranged at the bottom of the fourth part of the second chip.

[0026] In one possible implementation, the data transmission pins and the power supply pins on the third chip are arranged in an array to form a second pin array. In the second pin array, the types of all the pins in any column are the same, and the types of the pins in any two adjacent columns are different, that is, in any two adjacent columns, one column is composed of signal transmission pins, and the other column is composed of power supply pins; or in the second pin array, the types of all the pins in any row are the same, and the types of the pins in any two adjacent rows are different, that is, in any two adjacent rows, one row is composed of signal transmission pins, and the other row is composed of power supply pins.

[0027] Compared with the power supply pins of a chip, the signal transmission pins of a chip have a larger area, and therefore, the signal transmission pins and the power supply pins on the third chip are arranged in an array or in a row, so as to reduce the area occupied by the pins on the third chip, and thus to increase the number of pins per unit area of the third chip, and to meet the requirement of high integration of a chip. Meanwhile, the signal transmission pins and the power supply pins on the third chip are arranged in an array or in a row, so as to separate the signal transmission pins in different columns, to reduce the mutual influence between the signal transmission pins, and to improve the signal transmission quality.

[0028] In one possible implementation, in order to provide stable structure and electrical performance, the integrated chip is further provided with an insulating material, which wraps the first chip, the vertical interconnection structure and the second chip. With the top of the first chip as a horizontal boundary, the insulating material can be divided into a first insulating material and a second insulating material arranged in an upper and lower manner, and at this time, the first insulating material wraps the first chip and the vertical interconnection structure, and the second insulating material wraps the second chip.

[0029] In a second aspect, the present application provides another integrated chip, which comprises a first interconnection layer, a first chip disposed on the first interconnection layer, a second interconnection layer disposed on a top surface of the first chip, a second chip disposed on a top surface of the second interconnection layer, and a first vertical interconnection structure. The second chip comprises a first part and a second part, the first part coincides with a projection of the first chip on the second interconnection layer, and the second part protrudes from the first part to a side of the first chip along the second interconnection layer. The first vertical interconnection structure is disposed on the side of the first chip, and the first chip and the second chip are connected to the first interconnection layer by bypassing the first chip through the second interconnection layer and the first vertical interconnection structure.

[0030] Through the above scheme, the second part of the second chip in the integrated chip is electrically connected to the first chip disposed on the first interconnection layer through the vertical interconnection structure, which can shorten the interconnection path between the second part of the second chip and the first chip as much as possible, thereby improving the data transmission rate of the integrated chip, i.e., improving the bandwidth of the integrated chip, and making the second part of the second chip bypass the first chip and be electrically connected to the first interconnection layer through the first vertical interconnection structure, thereby making neither the first chip nor the second chip need to be made of TSV, which can reduce the complexity of design and processing of the integrated chip, and the risk of stress and warping. Moreover, the second interconnection layer can not only fan out the pins at the bottom of the first part of the second chip from other edges of the second chip to increase the pitch of the pins, thereby facilitating the interconnection of the pins of the second chip and the first chip, but also serve as a stress buffer layer to reduce the stress generated when the second chip is interconnected with the vertical interconnection structure.

[0031] In addition, the structure of the integrated chip is a common stacked package structure, which has low technical risk, high technical feasibility, good package integration performance, and is easy to package other chips together.

[0032] In one possible implementation, the first vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of mold encapsulation through holes TMV, or a plurality of dielectric layer through holes TDV, or a plurality of insulating layer through holes TIV. One end of the first vertical interconnection structure is connected to the bottom of the second part of the second chip through the second interconnection layer, and the other end of the first vertical interconnection structure is directly connected to a conductive layer in the first interconnection layer.

[0033] In one possible implementation, the second chip is provided with signal transmission pins, and all the second signal transmission pins on the second chip are disposed at the bottom (active surface) of the second part of the second chip, which can shorten the data transmission path between the first chip and the second chip, thereby improving the bandwidth of the integrated chip.

[0034] Furthermore, the pins in the first chip used for connection with the pins of the second chip can be located on the side of the first chip closer to the second part of the second chip, so as to minimize the interconnection path between the first chip and the second chip and improve the bandwidth of the integrated chip.

[0035] In one possible implementation, the second chip is further provided with power supply pins, some or all of which are located at the bottom of the second part of the second chip.

[0036] In one possible implementation, the signal transmission pins and power supply pins on the second chip are arranged in an array to form a first pin array. All pins in any column of the first pin array are of the same type, and the pins in any two adjacent columns of the first pin array are of different types; or, all pins in any row of the first pin array are of the same type, and the pins in any two adjacent rows of the first pin array are of different types.

[0037] Compared to the power supply pins of a chip, the signal transmission pins of a chip have a larger area. Therefore, in the above scheme, the signal transmission pins and power supply pins of the second chip are distributed in rows or columns, which can reduce the area occupied by the pins in the second chip, thereby increasing the number of pins per unit area of ​​the second chip, meeting the requirements of high chip integration. At the same time, the distribution of the signal transmission pins and power supply pins of the second chip in rows or columns can separate the signal transmission pins in different columns, reduce the mutual interference between signal transmission pins, and improve the signal transmission quality.

[0038] In one possible implementation, a high-speed signal pin is provided at the bottom of the second part of the second chip. This high-speed signal pin is used to transmit high-speed signals (highly sensitive signals), so that the high-speed signal pin of the second chip is directly electrically connected to the first interconnect layer through the first vertical interconnect structure. This can shorten the interconnect path between the high-speed signal pin in the second chip and the first chip. Since the high-speed signal transmitted in the high-speed signal pin is the main factor affecting the bandwidth of the integrated chip, placing the high-speed signal pin at the bottom of the second part of the second chip can effectively improve the bandwidth of the integrated chip.

[0039] In one possible implementation, the integrated chip includes at least two first chips; or, the integrated chip includes at least two second chips; or, the integrated chip includes at least two first chips and at least two second chips.

[0040] In one possible implementation, the first chip is a processor chip and the second chip is a memory chip.

[0041] In one possible implementation, the integrated chip further includes a third interconnect layer disposed on the top surface of the second chip and a third chip disposed on the top surface of the third interconnect layer. The third chip includes a third portion and a fourth portion, the third portion coinciding with the projection of the second chip onto the third interconnect layer, and the fourth portion protruding from the third portion along the side of the second chip along the third interconnect layer. A second vertical interconnect structure is disposed on the side of the second chip, and the third chip, through the third interconnect layer and the second vertical interconnect structure, bypasses the first chip and is connected to the first interconnect layer.

[0042] In one possible implementation, the second vertical interconnect structure is a plurality of solder balls, a plurality of copper pillars, a plurality of through-hole vias (TMVs), a plurality of dielectric layer vias (TDVs), or a plurality of insulating layer vias (TIVs). One end of the second vertical interconnect structure is connected to the bottom of the fourth portion of the third chip through a third interconnect layer, and the other end of the second vertical interconnect structure is directly connected to the conductive layer in the first interconnect layer.

[0043] In one possible implementation, the third chip is provided with signal transmission pins, and all the second signal transmission pins on the third chip are located at the bottom (active surface) of the fourth part of the second chip, which can shorten the data transmission path between the first chip and the third chip, thereby improving the bandwidth of the integrated chip.

[0044] Furthermore, the pins in the first chip used for connection with the third chip can be located on the side of the first chip near the fourth part of the third chip, so as to minimize the interconnection path between the first chip and the third chip and improve the bandwidth of the integrated chip.

[0045] In one possible implementation, the third chip is provided with data transmission pins, and all signal transmission pins on the third chip are located at the bottom of the fourth part of the third chip, which can shorten the data transmission path between the first chip and the third chip, thereby improving the bandwidth of the integrated chip.

[0046] Furthermore, the pins in the first chip used for connection with the third chip can be located on the side of the first chip near the fourth part of the third chip, so as to minimize the interconnection path between the first chip and the third chip and improve the bandwidth of the integrated chip.

[0047] In one possible implementation, the third chip is further provided with power supply pins, some or all of which are located at the bottom of the fourth part of the third chip.

[0048] In one possible implementation, the data transmission pins and power supply pins of the third chip are arranged in an array to form a second pin array. In this array, all pins in any column are of the same type, and the pin types in any two adjacent columns are different; that is, in any two adjacent columns, one column consists entirely of signal transmission pins, and the other column consists entirely of power supply pins. Alternatively, all pins in any row of the second pin array are of the same type, and the pin types in any two adjacent rows are different; that is, in any two adjacent rows, one row consists entirely of signal transmission pins, and the other row consists entirely of power supply pins.

[0049] Compared to the power supply pins of a chip, the signal transmission pins of a chip have a larger area. Therefore, distributing the signal transmission pins and power supply pins of a third chip in rows or columns can reduce the area occupied by the pins in the third chip, thereby increasing the number of pins per unit area and meeting the requirements of high chip integration. At the same time, distributing the signal transmission pins and power supply pins in rows or columns can separate signal transmission pins in different columns, reducing mutual interference between signal transmission pins and improving signal transmission quality.

[0050] In one possible implementation, a high-speed signal pin is provided at the bottom of the fourth part of the third chip. This high-speed signal pin is used to transmit high-speed signals (highly sensitive signals), so that the high-speed signal pin of the third chip is directly electrically connected to the first interconnect layer through the second vertical interconnect structure. This can shorten the interconnect path between the high-speed signal pin in the third chip and the first chip. Since the high-speed signal transmitted in the high-speed signal pin is the main factor affecting the bandwidth of the integrated chip, placing the high-speed signal pin at the bottom of the fourth part of the third chip can effectively improve the bandwidth of the integrated chip.

[0051] In one possible implementation, to provide stable structural and electrical performance, the integrated chip is further encased in an insulating material that surrounds the first chip, the vertical interconnect structure, and the second chip. Specifically, using the second interconnect layer as a horizontal interface, the insulating material can be further divided into a first insulating material and a second insulating material arranged vertically. In this case, the first insulating material surrounds the first chip and the vertical interconnect structure, and the second insulating material surrounds the second chip.

[0052] Thirdly, this application also provides a chip comprising a first part and a second part, wherein the first part is provided with a first type of pin for transmitting a first type of signal, and the second part is provided with a second type of pin for transmitting a second type of signal, wherein the transmission rate of the first type of signal is greater than the transmission rate of the second type of signal.

[0053] The above scheme divides the chip pins into a first type of pin and a second type of pin according to the different transmission rates of the signals transmitted by the pins. The first type of pin and the second type of pin are respectively set in the first part and the second part of the chip. This allows the first type of pin of the chip to be connected to other chips through the shortest possible interconnection path when the chip is packaged with other chips, thereby improving the bandwidth of the packaged chip.

[0054] In one possible implementation, the first type of signal includes at least one of a differential signal, an interrupt signal, a clock signal, and a reset signal. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the stacked packaging integration structure in the prior art;

[0056] Figure 2 This is one of the structural schematic diagrams of an integrated chip provided in this application;

[0057] Figure 3 This is a schematic diagram of the chip structure provided in this application;

[0058] Figure 4 This is the second schematic diagram of an integrated chip structure provided in this application;

[0059] Figure 5a This is the third schematic diagram of an integrated chip structure provided in this application;

[0060] Figure 5b This is the fourth schematic diagram of an integrated chip structure provided in this application;

[0061] Figure 6 A schematic diagram of the pin distribution of a first chip and a second chip in an integrated chip provided in this application;

[0062] Figure 7a One of the pin layout diagrams for the second chip provided in this application;

[0063] Figure 7b The second schematic diagram of the pin distribution of the second chip provided in this application;

[0064] Figure 8a This is one of the pin connection diagrams of the first chip and the second chip provided in this application;

[0065] Figure 8b The second schematic diagram of the pin connection between the first chip and the second chip provided in this application;

[0066] Figure 9 This is the fifth schematic diagram of an integrated chip structure provided in this application;

[0067] Figure 10 This application provides a schematic diagram of the structure of an integrated chip, number six.

[0068] Figure 11a This application provides a schematic diagram of the structure of an integrated chip, number seven.

[0069] Figure 11b This application provides an eighth schematic diagram of the structure of an integrated chip.

[0070] Figure 12a One of the schematic diagrams of the structure of an integrated chip packaged with other chips provided in this application;

[0071] Figure 12b A second schematic diagram of the structure of an integrated chip packaged with other chips, provided in this application;

[0072] Figure 13 One of the structural schematic diagrams of another integrated chip provided in this application;

[0073] Figure 14 This is a second schematic diagram of the structure of another integrated chip provided in this application;

[0074] Figure 15a This is the third schematic diagram of another integrated chip structure provided in this application;

[0075] Figure 15b Fourth schematic diagram of another integrated chip structure provided in this application;

[0076] Figure 16 A schematic diagram of the pin distribution of the first chip and the second chip in another integrated chip provided in this application;

[0077] Figure 17 Fifth schematic diagram of another integrated chip structure provided in this application;

[0078] Figure 18 Sixth schematic diagram of another integrated chip structure provided in this application;

[0079] Figure 19a Seventh schematic diagram of another integrated chip structure provided in this application;

[0080] Figure 19b This is the eighth schematic diagram of another integrated chip structure provided in this application;

[0081] Figure 20a One of the schematic diagrams of the structure of another integrated chip packaged with other chips provided in this application;

[0082] Figure 20bAnother schematic diagram of the structure of an integrated chip packaged with other chips provided in this application;

[0083] Figure 21 This application provides a schematic diagram of the structure of a chip;

[0084] Figure 22 A schematic flowchart illustrating a chip packaging method provided in this application;

[0085] Figure 23 This is a schematic flowchart of a chip packaging method provided in a specific embodiment of this application. Detailed Implementation

[0086] To address the problems in the prior art, this application proposes a chip and an integrated chip.

[0087] It should be noted that the "multiple" mentioned in the embodiments of this application refers to two or more. Furthermore, it should be understood that in the description of the embodiments of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0088] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0089] like Figure 2 As shown, this application embodiment provides an integrated chip 200, which includes: an interconnect layer 210, a first chip 220 disposed on the interconnect layer 210, a first vertical interconnect structure 230, and a second chip 240. Figure 2 As can be seen, a portion of the second chip 240 is disposed on the top surface of the first chip 220, and another portion extends from the top of the first chip 220 outward to the side of the first chip 220. Therefore, in this embodiment, the second chip 240 can be considered to include two parts: a first part and a second part. The first part is attached to the top surface of the first chip 220. The second part extends from one end of the top of the first chip 220 near the second chip 240 towards the side of the first chip 220 near the first vertical interconnect structure 230. The first vertical interconnect structure 230 and the second part are disposed on the same side of the first chip 220. The second part is electrically connected to the interconnect layer 210 through the first vertical interconnect structure 230, thereby enabling the second chip 240 to be electrically connected to the first chip 220 through the first vertical interconnect structure 230 and the interconnect layer 210.

[0090] In other words, the first chip 220 and the second chip 240 are staggered, with the first part of the second chip 240 supported by the first chip 220. The second part of the second chip 240 protrudes from the side of the first chip 220 and connects to the first vertical interconnect structure 230, which is also located on the side of the first chip 220. That is, the second chip 240 bypasses the first chip 220 through the first vertical interconnect structure 230 and is electrically connected to the interconnect layer 210. The first chip 220 and the second chip 240 transmit signals to each other through the interconnect layer 210. Of course, the bottom of the interconnect layer 210 also has an external interface, through which the first chip 220 and the second chip 240 also transmit and receive signals with the external components of the integrated chip 200.

[0091] like Figure 3 As shown, a chip typically consists of semiconductor material and circuit layers disposed on the semiconductor material. The semiconductor material forms semiconductor devices such as transistors, and the circuit layers contain multiple layers of circuits, typically including various functional circuits. These circuits are coupled to the semiconductor devices on the semiconductor material, thus forming a complete chip circuit structure. The surface of the chip containing the circuit layers is called the active surface, and the surface of the chip containing the semiconductor material (the opposite surface to the active surface) is called the passive surface. In integrated chip 200, the bottom of the first chip 220, i.e., the active surface 221 of the first chip 220, faces the interconnect layer 210, and the bottom of the second chip 240, i.e., the active surface 241 of the second chip 240, faces the interconnect layer 210. The second part of the active surface 241 of the second chip 240 is attached to the passive surface of the first chip 220 (i.e., the top of the first chip 220). Since the active surfaces 221 of the first chip 220 and 241 of the second chip 240 both face the interconnect layer 210, and the second part of the second chip 240 bypasses the first chip 220 and is electrically connected to the interconnect layer 210 through the first vertical interconnect structure 230, the first chip 220 does not need to provide a signal transmission channel to the second chip 240 through TSV, which reduces the risk of stress and warping of the integrated chip 200, as well as the difficulty and cost of the processing technology.

[0092] In this embodiment, the first portion of the second chip 240 is disposed on the top surface of the first chip 220, meaning that the first portion is directly attached to the top of the first chip 220 without the support of other support structures such as solder balls or copper pillars. In practical implementation, to ensure the reliability of the second chip 240 attached to the top surface of the first chip 220, an adhesive material can be applied between the first portion of the second chip 240 and the top surface of the first chip 220. Specifically, such as... Figure 4As shown, the first portion of the second chip 240 is fixed to the top of the first chip 220 by an adhesive material 250; that is, the active surface 241 of the first portion of the second chip 240 is fixed to the passive surface of the first chip 220 by the adhesive material 250. The adhesive material 250 can be a die-attach epoxy (DAF) or silver plating, etc. Furthermore, considering that the first chip 220 and the second chip 240 will generate heat during operation, a thermally conductive or insulating material can be filled between the first portion of the second chip 240 and the first chip 220 to improve or prevent heat conduction between them. The adhesive material 250, thermally conductive material, or thermally insulating material described above can all be considered auxiliary means required to fix the first portion of the second chip 240 to the top surface of the first chip 220.

[0093] In a broad sense, interconnect layer 210 can be what is commonly referred to as a substrate. In specific implementations, interconnect layer 210 can also be a redistribution layer (RDL) or a silicon substrate (also known as an interposer). Interconnect layer 210 internally includes multiple dielectric layers 211 and conductive layers 212 sandwiched between the dielectric layers 211. Circuit wiring is provided on the conductive layers 212, and dielectric vias are provided in the dielectric layers 211 to connect circuit wiring on different layers. Furthermore, interconnect layer 210 can be configured such as... Figure 5a The small copper pillar 260 shown, or as... Figure 5b The solder ball 270 shown is electrically connected to the first chip 220. The solder ball 270 and the small copper pillar 260 are connected to the circuit wiring on the conductive layer 212 through dielectric vias.

[0094] Compared to the thickness of the silicon substrate, the thickness of the RDL is smaller. Therefore, using the RDL for the interconnect layer 210 can reduce the thickness of the integrated chip 200. Furthermore, since the first chip 220 dissipates heat downwards, using a thinner RDL as the interconnect layer 210 is beneficial for the heat dissipation of the first chip 220.

[0095] In summary, the first vertical interconnect structure 230 is a dielectric layer formed around the first chip 220, or a signal channel in the molding compound connecting the second chip 220 and the interconnect layer 210. The first vertical interconnect structure 230 can be implemented in various ways. For example, it can be a copper pillar erected on the side of the first chip 220; it can also be a through-mold via (TMV), through-dielectric via (TDV), or through-insulator via (TIV) formed in the dielectric material on the side of the first chip 220, forming a signal path by plating or filling the via with metal; alternatively, the first vertical interconnect structure 230 can also be a solder ball formed between the second chip 220 and the interconnect layer 210 (see reference). Figure 5b Solder ball 230 in the middle).

[0096] One end of the first vertical interconnect structure 230 is directly connected to the bottom of the second part of the second chip 240, and the other end of the first vertical interconnect structure 230 is directly connected to the conductive layer in the interconnect layer 210.

[0097] In a specific implementation, the second chip 240 is provided with signal transmission pins (i.e., input / output pads, I / O pads). All signal transmission pins on the second chip 240 are located at the bottom of the second part of the second chip 240, that is, all signal transmission pins of the second chip 240 are located on the active surface 241 of the second part of the second chip 240. This can shorten the signal transmission path between the first chip 220 and the second chip 240, thereby improving the bandwidth of the integrated chip 200.

[0098] In addition, the second chip 240 may also be provided with power supply pins. All signal power supply pins on the second chip 240 are located at the bottom of the second part of the second chip 240, that is, all power supply pins of the second chip 240 are located on the active surface 241 of the second part of the second chip 240.

[0099] Correspondingly, the pins in the first chip 220 used for connection with the pins of the second chip 240 can also be located on the side of the first chip 220 near the second part of the second chip 240, such as... Figure 6 As shown ( Figure 6 (This is a top view of the integrated chip 200 from the top of the second chip 240 looking down) to minimize the interconnection path between the first chip 220 and the second chip 240 and increase the bandwidth of the integrated chip 200.

[0100] In practical implementation, the signal transmission pins and power supply pins on the second chip 240 can be arranged in an array to form the first pin array. For example, Figure 7a As shown ( Figure 7a for Figure 6 The diagram shows the pin distribution of the second chip 240. In any column of the first pin array, all pins are of the same type. In any two adjacent columns of the first pin array, the pin types are different; that is, in any two adjacent columns of the first pin array, one column consists entirely of signal transmission pins, and the other column consists entirely of power supply pins. Alternatively, as shown... Figure 7b ( Figure 7b for Figure 6 As shown in the schematic diagram of the pin distribution of the second chip 240, all pins in any row of the first pin array are of the same type, and the pins in any two adjacent rows of the first pin array are of different types. That is, in any two adjacent rows of the first pin array, one row consists of signal transmission pins and the other row consists of power supply pins.

[0101] Typically, the signal transmission pins of a chip have a larger area than its power supply pins. Therefore, distributing the signal transmission pins and power supply pins of the second chip 240 in rows or columns can reduce the area occupied by the pins in the second chip 240, thereby increasing the number of pins per unit area of ​​the second chip 240 to meet the requirements of high chip integration. At the same time, distributing the signal transmission pins and power supply pins of the second chip 240 in rows or columns can separate the signal transmission pins in different columns, reduce mutual interference between signal transmission pins, and improve signal transmission quality.

[0102] Correspondingly, the pins in the first chip 220 used for connection with the pins of the second chip 240 can also be arranged in an array corresponding to the pins of the second chip 240, such as... Figure 8a or Figure 8b As shown, Figure 8a as well as Figure 8b for Figure 6 The diagram shows the pin distribution of the first chip 220 and the second chip 240.

[0103] It should be noted that the embodiments of this application do not limit the shape of the array formed by the pins of the second chip 240, the number of pins in each row of the array, or the number of pins in each column of the array. The number of pins in each row of the array may be the same or different, and the number of pins in each column of the array may be the same or different.

[0104] In one specific implementation, the first chip 220 can be a logic die, such as a processor chip (e.g., an AP chip) or intellectual property (IP) cores, and the second chip 240 can be a memory (including static random-access memory (SRAM) and DRAM), a flip chip package, a passive device, an interposer, a micro-electro-mechanical system (MEMS) chip or package, etc.

[0105] To provide stable structural and electrical performance, integrated chips are typically surrounded by insulating material. In embodiments of this application, such as... Figure 9 As shown, insulating material 280 encapsulates the first chip 220, the first vertical interconnect structure 230, and the second chip 240. Using the top surface of the first chip 220 as a horizontal dividing interface, the insulating material 280 can be further divided into a first insulating material 281 and a second insulating material 282 arranged vertically. In this configuration, the first insulating material 281 encapsulates the first chip 220 and the first vertical interconnect structure 230, while the second insulating material 282 encapsulates the second chip 240.

[0106] Generally speaking, in order to protect the second chip 240, the thickness of the second insulating material 282 needs to be greater than or equal to the thickness of the second chip 240. From a heat dissipation perspective, the thinner the portion of the second insulating material 282 that extends above the top of the second chip 240, the better the heat dissipation of the second chip 240.

[0107] The first insulating material 281 and the second insulating material 282 may be the same or different. The first insulating material 281 and the second insulating material 282 may be silicon oxide, silicon nitride, or other epoxy resins.

[0108] Furthermore, such as Figure 10 As shown, the bottom of the interconnect layer 210 is also provided with a plurality of solder balls 270 for interconnecting the first chip 220 and the second chip 240 with the outside (such as a printed circuit board (PCB), other chips, etc.), so that the integrated chip 200 can be directly interconnected with the outside through the solder balls 270.

[0109] In specific implementations, the integrated chip 200 may include at least two first chips 220, or at least two second chips 240, or at least two first chips 220 and at least two second chips 240. For example, the integrated chip 200 includes two first chips 220 and one second chip 240. Both first chips 220 are disposed on the first interconnect layer 210, and the second chip 240 is disposed on top of and between the two first chips 220. That is, the second chip 240 includes two first portions and a second portion located between the two first portions. The two first portions of the second chip 240 are respectively disposed on the top surface of the two first chips 220. A first vertical interconnect structure 230 is located between the two first chips 220, with one end directly connected to the bottom of the second portion of the second chip 240, and the other end directly connected to the conductive layer 212 in the interconnect layer 210. For example, ... Figure 11a As shown, the integrated chip 200 includes a first chip 220 and two second chips 240, which are respectively disposed at both ends of the first chip 220.

[0110] In addition, such as Figure 11b As shown, the integrated chip 200 may further include a third chip 290 and a second vertical interconnect structure 300. The third chip 290, similar to the second chip 240, comprises two parts: a third part and a fourth part. The third part is fixed to the top surface of the second chip 240 (similar to the first part of the second chip 240), and the fourth part protrudes from the side of the second chip 240 (similar to the second part of the second chip 240). The second vertical interconnect structure 300 and the fourth part are disposed on the same side of the second chip 240. The fourth part is electrically connected to the interconnect layer 210 through the second vertical interconnect structure 300, thereby enabling the third chip 290 to be electrically connected to the first chip 220 through the second vertical interconnect structure 300 and the interconnect layer 210.

[0111] Similar to the second chip 240, the third portion of the third chip 290 is disposed on the top surface of the second chip 220. This means that the third portion is directly mounted on the top of the second chip 240 without the support of other support structures such as solder balls or copper pillars. In practice, to ensure the reliability of the third chip 290's attachment to the top surface of the second chip 240, an adhesive material can be applied between the first portion of the third chip 290 and the top surface of the second chip 240. Specifically, such as... Figure 11bAs shown, the third portion of the third chip 290 is fixed to the top surface of the second chip 240 by an adhesive material 250; that is, the active surface of the third portion of the third chip 290 is fixed to the passive surface of the second chip 240 by the adhesive material 250. Furthermore, considering that the third chip 290 and the second chip 240 will generate heat during operation, a thermally conductive or insulating material can be filled between the third portion of the third chip 290 and the second chip 240 to improve or prevent heat conduction between them. The adhesive material 250, thermally conductive material, or insulating material described above can all be considered auxiliary means required to fix the third portion of the third chip 290 to the top surface of the second chip 240.

[0112] The second vertical interconnect structure 300 is a signal channel formed in the dielectric layer surrounding the first chip 220 and the second chip 240, or in the molding compound, connecting the third chip 290 and the interconnect layer 210. The second vertical interconnect structure 300 can be implemented in various ways. For example, it can be a copper pillar erected on the side of the first chip 220; it can also be a TMV, TDV, or TIV formed in the dielectric material on the side of the first chip 220, with a signal path formed by plating or filling the holes with metal; alternatively, the second vertical interconnect structure 300 can also be a solder ball formed between the third chip 290 and the interconnect layer 210. One end of the second vertical interconnect structure 300 is directly connected to the bottom of the fourth portion of the third chip 290, and the other end is directly connected to the conductive layer in the interconnect layer 210.

[0113] In specific implementation, the third chip 290 is provided with signal transmission pins. All signal transmission pins on the third chip 290 are located at the bottom of the fourth part of the third chip 290. That is, all signal transmission pins of the third chip 290 are located on the active surface of the fourth part of the third chip 290, which can shorten the signal transmission path between the first chip 220 and the third chip 290, thereby improving the bandwidth of the integrated chip 200.

[0114] In addition, the third chip 290 may also be provided with power supply pins. All signal power supply pins on the third chip 290 are located at the bottom of the fourth part of the third chip 290, that is, all power supply pins of the third chip 290 are located on the active surface of the fourth part of the third chip 290.

[0115] Correspondingly, the pins in the first chip 220 used for connection with the pins of the third chip 290 can also be set on the side of the first chip 220 near the fourth part of the third chip 290, so as to shorten the interconnection path between the first chip 220 and the third chip 290 to the greatest extent and improve the bandwidth of the integrated chip 200.

[0116] In a specific implementation, the signal transmission pins and power supply pins on the third chip 290 can be arranged in an array to form a second pin array. In this second pin array, all pins in any column are of the same type, and the pin types in any two adjacent columns are different; that is, in any two adjacent columns, one column consists entirely of signal transmission pins, and the other column consists entirely of power supply pins. Alternatively, all pins in any row of the second pin array are of the same type, and the pin types in any two adjacent rows are different; that is, in any two adjacent rows, one row consists entirely of signal transmission pins, and the other row consists entirely of power supply pins.

[0117] Typically, the signal transmission pins of a chip have a larger area than its power supply pins. Therefore, distributing the signal transmission pins and power supply pins of the third chip 290 in rows or columns can reduce the area occupied by the pins in the third chip 290, thereby increasing the number of pins per unit area of ​​the third chip 290 to meet the requirements of high chip integration. At the same time, distributing the signal transmission pins and power supply pins of the third chip 290 in rows or columns can separate the signal transmission pins in different columns, reduce mutual interference between signal transmission pins, and improve signal transmission quality.

[0118] Correspondingly, the pins in the first chip 220 used for connection with the pins of the third chip 290 can also be arranged in an array corresponding to the pins of the third chip 290.

[0119] In practice, a fourth chip can be disposed on top of the third chip 290 in the same manner as the third chip 290 on the second chip 240. A portion of the fourth chip is fixed to the top surface of the third chip 290, while another portion protrudes from the side of the third chip 290. The bottom of this other portion is connected to the interconnect layer 210 via a third vertical interconnect structure. Similarly, a fifth chip, and so on, can be disposed on top of the fourth chip.

[0120] It should be noted that the number of the first chip 220, the second chip 240, and the third chip 290 in the integrated chip 200 is not limited in this embodiment. The number of the first chip 220, the second chip 240, and the third chip 290 in the integrated chip 200 is determined according to the specific performance requirements (such as bandwidth, area, processing speed, etc.) of the integrated chip 200. The chip type of the third chip 290 can be the same as or different from that of the second chip 240.

[0121] Through the above scheme, the second chip 240 in the integrated chip 200 is electrically connected to the first chip 220 disposed on the interconnect layer 210 through the first vertical interconnect structure 230. This minimizes the interconnect path between the second chip 240 and the first chip 220, thereby improving the data transmission rate of the integrated chip 200, i.e., increasing the bandwidth of the integrated chip 200. Furthermore, the active surfaces of both the first chip 220 and the second chip 240 in the integrated chip 200 face the interconnect layer 210. The second part of the second chip 240 bypasses the first chip 220 and is electrically connected to the interconnect layer 210 through the first vertical interconnect structure 230. This eliminates the need for TSV fabrication in either the first chip 220 or the second chip 240, reducing the design and fabrication complexity of the integrated chip 200, as well as the risks of stress and warpage.

[0122] Furthermore, the integrated chip 200 uses a common stacked packaging structure, which has low technical risk, high technical feasibility, and good packaging integration performance, making it easy to package with other chips. Specifically, the integrated chip 200 can be packaged with other chips using stacked packaging technology. For example, as... Figure 12a As shown, integrated chip 200 can be packaged with other chips using a FOPOP method, or integrated chip 200 can also be packaged with other chips using other POP methods, such as... Figure 12b As shown.

[0123] like Figure 13 As shown, this application embodiment also provides another integrated chip 1300, which includes: a first interconnect layer 1310, a first chip 1320 disposed on the first interconnect layer 1310, a first vertical interconnect structure 1330, a second interconnect layer 1340 disposed on the top surface of the first chip, and a second chip 1350 disposed on the top surface of the second interconnect layer 1340. Figure 13It is understood that a portion of the second chip 1350 is located on the second interconnect layer 1340 and coupled to the first chip 1320, while another portion of the second chip 1350 is located on the second interconnect layer 1340 extending laterally toward the first chip 1320. That is, the second chip 1350 comprises both a first portion and a second portion. The first portion coincides with the projection of the first chip 1320 onto the second interconnect layer 1340, and the second portion protrudes laterally from the first portion along the second interconnect layer 1340 toward the side of the first chip 1320. The first vertical interconnect structure 1330 is disposed on the side of the first chip 1320. The first chip 1320 and the second chip 1350 are electrically connected to the first interconnect layer 1310 via the second interconnect layer 1340 and the first vertical interconnect structure 1330, bypassing the first chip 1320. Of course, as mentioned above, the top surfaces of the second chip 1350 and the second interconnect layer 1340 can also be filled with an adhesive, thermally conductive, or thermally insulating material.

[0124] The second interconnect layer 1340 may or may not be provided at the bottom of the second part of the second chip 1350. That is, the second interconnect layer 1340 may extend to the bottom of the second part of the second chip 1350 or may only extend to the bottom of the first part of the second chip 1350. When the second interconnect layer 1340 is provided at the bottom of the second part of the second chip 1350, the portion of the second interconnect layer 1340 used to connect the second part of the second chip 1350 and the first vertical interconnect structure 1330 is also electrically connected through vertical interconnection. That is, when the second interconnect layer 1340 is provided at the bottom of the second part of the second chip 1350, the portion of the second interconnect layer 1340 used to connect the second part of the second chip 1350 and the first vertical interconnect structure 1330 is also part of the first vertical interconnect structure 1330. The second interconnect layer 1340 not only allows the pins at the bottom of the first portion of the second chip 1350 to fan out from the other sides of the second chip 1350, increasing the pin spacing to facilitate the interconnection between the second chip 1350 and the first chip 1320, but also serves as a stress buffer layer to reduce the stress generated when the second chip 1350 is interconnected with the first vertical interconnect structure 1330. Of course, the bottom of the first interconnect layer 1310 also has an external interface, through which the first chip 1320 and the second chip 1350 communicate with the outside of the integrated chip 1300 for signal transmission and reception.

[0125] The active surface 1321 of the first chip 1320 faces the first interconnect layer 1310, and the active surface 1351 of the second chip 1350 faces the second interconnect layer 1340. The first part of the second chip 1350 bypasses the first chip 1320 and is electrically connected to the first interconnect layer 1310 through the second interconnect layer 1340 and the first vertical interconnect structure 1330. The second part of the second chip 1350 is directly electrically connected to the first interconnect layer 1310 through the first vertical interconnect structure 1330. Therefore, the second chip 1350 does not need to provide a signal transmission channel by processing TSV, which reduces the stress and warpage risk of the integrated chip 1300, as well as the difficulty and cost of the processing technology.

[0126] In specific implementations, the first chip 1320 can be a logic chip, such as a processor or intellectual property core, and the second chip 1350 can be a memory (including SRAM and DRAM), flip chip package, passive device, adapter board, MEMS, or other chip or package.

[0127] Furthermore, such as Figure 14 As shown, the first chip 1320 can be fixed to the bottom of the second interconnect layer 1340 by an adhesive material 1360. The adhesive material 1360 can be a material such as DAF or silver paste.

[0128] In one specific embodiment, the first interconnect layer 1310 can be an RDL or a silicon substrate, and the second interconnect layer 1340 can also be an RDL or a silicon substrate. Taking the first interconnect layer 1310 as an example, the first interconnect layer 1310 can be constructed using, for example... Figure 15a The multiple small copper pillars 1370 shown are disposed on top of the first interconnect layer 1310 (i.e., the surface facing the active surface 1321 of the first chip 1320) or as shown in the figure. Figure 15b The multiple solder balls 1380 shown are electrically connected to the first chip 1320. The small copper pillars 1370 and solder balls 1380 are connected to the circuit wiring on the conductive layer of the first interconnect layer 1310 through dielectric vias. The method by which the second interconnect layer 1340 is electrically connected to the second chip 1350 is similar to the method by which the first interconnect layer 1310 is electrically connected to the first chip 1320, and will not be described further here.

[0129] Compared to a silicon substrate, the thickness of the RDL is smaller. Therefore, using RDL for the first interconnect layer 1310 and the second interconnect layer 1340 can reduce the thickness of the integrated chip 1300. Furthermore, since the first chip 1320 dissipates heat downwards, using a thinner RDL as the first interconnect layer 1310 is beneficial for the heat dissipation of the first chip 220.

[0130] In summary, the first vertical interconnect structure 1330 is a dielectric layer formed around the first chip 1320, or a signal channel in the molding compound connecting the second chip 1350 and the first interconnect layer 1310. The first vertical interconnect structure 1330 can be implemented in various ways. For example, it can be a copper pillar erected on the side of the first chip 1320; it can also be a TMV, TDV, or TIV formed in the dielectric material on the side of the first chip 1320, forming a signal path by plating or filling the holes with metal; alternatively, the first vertical interconnect structure 1330 can also be a solder ball formed between the second chip 1350 and the first interconnect layer 1310. One end of the first vertical interconnect structure 1330 is connected to the bottom of the second portion of the second chip 1350 through the second interconnect layer 1340, and the other end of the second vertical interconnect structure 1330 is directly connected to the conductive layer in the first interconnect layer 1310.

[0131] In one possible embodiment, the second chip 1350 is provided with signal transmission pins. All signal transmission pins on the second chip 1350 are located at the bottom of the second part of the second chip 1350, that is, all signal transmission pins of the second chip 1350 are located on the active surface of the second part of the second chip 1350. This can shorten the signal transmission path between the first chip 1320 and the second chip 1350, thereby improving the bandwidth of the integrated chip 1300.

[0132] In addition, the second chip 1350 may also be provided with power supply pins. All or some of the signal power supply pins on the second chip 1350 are located at the bottom of the second part of the second chip 1350, that is, all or some of the power supply pins of the second chip 1350 are located on the active surface of the second part of the second chip 1350.

[0133] Correspondingly, the pins in the first chip 1320 used for connection with the pins of the second chip 1350 can also be set on the side of the first chip 1320 near the second part of the second chip 1350, so as to shorten the interconnection path between the first chip 1320 and the second chip 1350 to the greatest extent and improve the bandwidth of the integrated chip 1300.

[0134] In another possible implementation, a high-speed signal pin is provided on the bottom (active surface) of the second portion of the second chip 1350, and a non-high-speed signal pin is provided on the bottom (active surface) of the first portion of the second chip 1350. The high-speed signal pin is used to transmit high-speed signals (highly sensitive signals), so that the high-speed signal pin of the second chip 1350 is directly electrically connected to the first interconnect layer 1310 through the first vertical interconnect structure 1330. This can shorten the interconnection path between the high-speed signal pin in the second chip 1350 and the first chip 1310. Since the high-speed signal transmitted in the high-speed signal pin is the main factor affecting the bandwidth of the integrated chip 1300, the bandwidth of the integrated chip 1300 can be improved by placing the high-speed signal pin on the bottom of the second portion of the second chip 1350. A signal is considered a high-speed signal if it meets any of the following conditions: a) the signal experiences severe skin effect and ionization loss during transmission along the transmission path; b) the signal's rising or falling edge is less than 50 ps; c) the length of the signal's transmission path is greater than 1 / 6λ, where λ is the signal's wavelength; d) the signal's frequency is greater than 50 MHz. Non-high-speed signals are any signals other than the high-speed signals mentioned above.

[0135] Accordingly, the pins in the first chip 1320 used for connecting to the high-speed signal pins of the second chip 1350 are located on the side of the first chip 1320 near the second part of the second chip 1350, such as... Figure 16 As shown, the interconnection path between the first chip 1320 and the second chip 1350 is shortened to the greatest extent possible, thereby increasing the bandwidth of the integrated chip 1300.

[0136] In practical implementation, the signal transmission pins and power supply pins on the second chip 1350 can be arranged in an array to form the first pin array. For example, Figure 7a As shown, all pins in any column of the first pin array are of the same type, while the pins in any two adjacent columns of the first pin array are of different types. That is, in any two adjacent columns of the first pin array, one column consists entirely of signal transmission pins, and the other column consists entirely of power supply pins. Or, as... Figure 7b As shown, all pins in any row of the first pin array are of the same type, while the pins in any two adjacent rows of the first pin array are of different types. That is, in any two adjacent rows of the first pin array, one row consists entirely of signal transmission pins, and the other row consists entirely of power supply pins. In other words, the different types of pins in the array formed by the pins of the second chip 1350 are distributed at row or column intervals. Correspondingly, the pins in the first chip 1320 used to connect to the pins of the second chip 1350 can also be arranged in an array corresponding to the pins of the second chip 1350.

[0137] Typically, the signal transmission pins of a chip have a larger area than its power supply pins. Therefore, distributing the signal transmission pins and power supply pins of the second chip 1350 in rows or columns can reduce the area occupied by the pins in the second chip 1350, thereby increasing the number of pins per unit area of ​​the second chip 1350 to meet the requirements of high chip integration. At the same time, distributing the signal transmission pins and power supply pins of the second chip 1350 in rows or columns can separate the signal transmission pins in different columns, reduce mutual interference between signal transmission pins, and improve signal transmission quality.

[0138] To provide stable structural and electrical performance, integrated chips are typically surrounded by insulating material. In embodiments of this application, such as... Figure 17 As shown, insulating material 1390 encapsulates the first chip 1320, the first vertical interconnect structure 1330, and the second chip 1350. Using the second interconnect layer 1340 as a horizontal interface, the insulating material 1390 can be further divided into a first insulating material 1391 and a second insulating material 1392 arranged vertically. In this case, the first insulating material 1391 encapsulates the first chip 1320 and the first vertical interconnect structure 1330, while the second insulating material 1392 encapsulates the second chip 1350.

[0139] Typically, to protect the second chip 1350, the thickness of the second insulating material 1392 needs to be greater than or equal to the thickness of the second chip 1350. However, from the perspective of chip heat dissipation, the closer the thickness of the second insulating material 1392 is to the thickness of the second chip 1350, the better it is for the heat dissipation of the second chip 1350. Furthermore, the first insulating material 1391 and the second insulating material 1392 can be the same or different. The first insulating material 1391 and the second insulating material 1392 can be silicon oxide, silicon nitride, or other epoxy resins.

[0140] Furthermore, such as Figure 18 As shown, the bottom of the first interconnect layer 1310 is also provided with a plurality of solder balls 1380 for interconnecting the first chip 1320 and the second chip 1350 with external components (such as PCB, other chips, etc.).

[0141] In a specific implementation, the integrated chip 1300 includes at least two first chips 1320, or at least two second chips 1350 (e.g., such as...). Figure 19a (as shown), or includes at least two first chips 1320 and at least two second chips 1350.

[0142] like Figure 19bAs shown, the integrated chip 1300 may further include a third interconnect layer 1400 disposed on the top surface of the second chip, a third chip 1410 disposed on the top surface of the third interconnect layer 1400, and a second vertical interconnect structure 1420. The third chip 1410 is similar to the second chip 1350, including a third portion and a fourth portion. The third portion coincides with the projection of the second chip 1350 onto the third interconnect layer 1400, and the fourth portion protrudes from the third portion along the third interconnect layer 1400 to the side of the second chip 1350. The second vertical interconnect structure 1420 is disposed to the side of the second chip 1350. The third chip 1410, through the third interconnect layer 1400 and the second vertical interconnect structure 1420, bypasses the first chip 1320 and is connected to the first interconnect layer 1310.

[0143] The bottom of the fourth part of the third chip 1410 may or may not have a third interconnect layer 1400. That is, the third interconnect layer 1400 may extend to the bottom of the fourth part of the third chip 1410, or it may only extend to the bottom of the fourth part of the third chip 1410. When the bottom of the fourth part of the third chip 1410 has a third interconnect layer 1400, the portion of the third interconnect layer 1400 used to connect the fourth part of the third chip 1410 to the second vertical interconnect structure 1420 is also electrically connected via a vertical interconnect. In other words, when the bottom of the fourth part of the third chip 1410 has a third interconnect layer 1400, the portion of the third interconnect layer 1400 used to connect the fourth part of the third chip 1410 to the second vertical interconnect structure 1420 is also part of the second vertical interconnect structure 1420. The third interconnect layer 1400 not only allows the pins at the bottom of the third portion of the third chip 1410 to fan out from the other sides of the third chip 1410, increasing the pin spacing to facilitate pin interconnection between the third chip 1410 and the first chip 1320, but also serves as a stress buffer layer to reduce the stress generated when the third chip 1410 is interconnected with the second vertical interconnect structure 1420. Additionally, a vertical interconnect structure may be provided at one end of the third interconnect layer 1400 near the first portion of the second chip 1350, allowing the first portion of the second chip 1350 to be electrically connected to the second interconnect layer 1340 through the third interconnect layer 1400 and this vertical interconnect structure.

[0144] In summary, the second vertical interconnect structure 1420 is a dielectric layer formed around the second chip 1350, or a signal channel in the molding compound connecting the third chip 1410 and the first interconnect layer 1310. The second vertical interconnect structure 1420 can be implemented in various ways. For example, it can be a copper pillar erected on the side of the second chip 1350; it can also be a TMV, TDV, or TIV formed in the dielectric material on the side of the second chip 1350, forming a signal path by plating or filling the holes with metal; alternatively, the second vertical interconnect structure 1420 can also be a solder ball formed between the third chip 1410 and the first interconnect layer 1310. One end of the second vertical interconnect structure 1420 is connected to the bottom of the fourth portion of the third chip 1410 through the third interconnect layer 1400, and the other end of the second vertical interconnect structure 1420 is directly connected to the conductive layer in the first interconnect layer 1310.

[0145] In one possible embodiment, the third chip 1410 is provided with signal transmission pins. All signal transmission pins on the third chip 1410 are located at the bottom of the fourth part of the third chip 1410, that is, all signal transmission pins of the third chip 1410 are located on the active surface of the fourth part of the third chip 1410. This can shorten the signal transmission path between the first chip 1320 and the third chip 1410, thereby improving the bandwidth of the integrated chip 1300.

[0146] In addition, the third chip 1410 may also be provided with power supply pins. All or some of the signal power supply pins on the third chip 1410 are located at the bottom of the fourth part of the third chip 1410, that is, all or some of the power supply pins of the third chip 1410 are located on the active surface of the fourth part of the third chip 1410.

[0147] Correspondingly, the pins in the first chip 1320 used for connection with the pins of the third chip 1410 can also be set on the side of the first chip 1320 near the fourth part of the third chip 1410, so as to shorten the interconnection path between the first chip 1320 and the third chip 1410 to the greatest extent and improve the bandwidth of the integrated chip 1300.

[0148] In practical implementation, the signal transmission pins and power supply pins on the third chip 1410 can be arranged in an array to form a second pin array. For example, Figure 7a As shown, all pins in any column of the second pin array are of the same type, while the pins in any two adjacent columns of the second pin array are of different types. That is, in any two adjacent columns of the second pin array, one column consists entirely of signal transmission pins, and the other column consists entirely of power supply pins. Or, as... Figure 7bAs shown, all pins in any row of the second pin array are of the same type, while the pins in any two adjacent rows of the first pin array are of different types. That is, in any two adjacent rows of the second pin array, one row consists entirely of signal transmission pins, and the other row consists entirely of power supply pins. Correspondingly, the pins in the first chip 1320 used for connection with the pins of the third chip 1410 can also be arranged in an array corresponding to the pins of the third chip 1410.

[0149] Typically, the signal transmission pins of a chip have a larger area than its power supply pins. Therefore, distributing the signal transmission pins and power supply pins of the third chip 1410 in rows or columns can reduce the area occupied by the pins in the third chip 1410, thereby increasing the number of pins per unit area of ​​the third chip 1410 to meet the requirements of high chip integration. At the same time, distributing the signal transmission pins and power supply pins of the third chip 1410 in rows or columns can separate the signal transmission pins in different columns, reduce mutual interference between signal transmission pins, and improve signal transmission quality.

[0150] In another possible implementation, a high-speed signal pin is provided on the bottom (active surface) of the fourth part of the third chip 1410, and a non-high-speed signal pin is provided on the bottom (active surface) of the third part of the third chip 1410. This allows the high-speed signal pin of the third chip 1410 to be directly electrically connected to the first interconnect layer 1310 through the second vertical interconnect structure 1420, which can shorten the interconnection path between the high-speed signal pin in the third chip 1410 and the first chip 1310. Since the high-speed signal transmitted in the high-speed signal pin is the main factor affecting the bandwidth of the integrated chip 1300, the bandwidth of the integrated chip 1300 can be improved by placing the high-speed signal pin at the bottom of the second part of the second chip 1350.

[0151] Accordingly, the pins in the first chip 1320 used for connecting to the high-speed signal pins of the third chip 1410 are located on the side of the first chip 1320 near the fourth part of the third chip 1410, so as to shorten the interconnection path between the first chip 1320 and the third chip 1410 to the greatest extent and improve the bandwidth of the integrated chip 1300.

[0152] In specific implementation, a fourth chip can be disposed on top of the third chip 1410 in the same manner as the third chip 1410 on the second chip 1350. A portion of the fourth chip overlaps with its projection onto the interconnect layer on the top surface of the third chip 1410, while another portion protrudes from this portion along the interconnect layer on the top surface of the third chip 1410, extending to the side of the third chip 1410. The bottom of this other portion is connected to the first interconnect layer 1310 via a third vertical interconnect structure. Similarly, a fifth chip, and so on, can be disposed on top of the fourth chip.

[0153] It should be noted that the number of the first chip 1320, the second chip 1350, and the third chip 1410 in the integrated chip 1300 is not limited in this embodiment. The number of the first chip 1320, the second chip 1350, and the third chip 1410 in the integrated chip 1300 is determined according to the specific performance requirements (such as bandwidth, area, processing speed, etc.) of the integrated chip 1300.

[0154] Through the above scheme, the second part of the second chip 1350 in the integrated chip 1300 is electrically connected to the first chip 1320 disposed on the first interconnect layer 1310 through the first vertical interconnect structure 1330. This can minimize the interconnection path between the second part of the second chip 1350 and the first chip 1320, thereby improving the data transmission rate of the integrated chip 1300. Furthermore, the second part of the second chip 1350 bypasses the first chip 1320 and is electrically connected to the first interconnect layer 1310 through the first vertical interconnect structure 1340. As a result, neither the first chip 1320 nor the second chip 1350 needs to be fabricated with TSVs, which can reduce the design and manufacturing complexity of the integrated chip 1300, as well as the risk of stress and warpage.

[0155] Furthermore, the integrated chip 1300 uses a common stacked packaging structure, which has low technical risk, high technical feasibility, and good packaging integration performance, making it easy to package with other chips. Specifically, the integrated chip 1300 can be packaged with other chips using stacked packaging technology. For example, as... Figure 20a As shown, integrated chip 1300 can be packaged with other chips in a FOPOP manner, or integrated chip 1300 can also be packaged with other chips in other POP manner, such as... Figure 20b As shown.

[0156] like Figure 21As shown, this application embodiment also provides a chip 2100, which includes a first part and a second part. The first part of the chip 2100 is provided with a first type pin 2110 for transmitting a first type of signal, and the second part of the chip 2100 is provided with a second type pin 2120 for transmitting a second type of signal. The transmission rate of the first type of signal is greater than the transmission rate of the second type of signal.

[0157] In specific implementations, chip 2100 can be a memory (including SRAM and DRAM), flip chip package, passive device, adapter board, MEMS, or other chip or package.

[0158] Furthermore, the first type of signal includes at least one of high-speed signals such as differential signals, interrupt signals, clock signals, and reset signals. It should be noted that the above description of the first type of signal is merely illustrative and does not constitute a limitation on the embodiments of this application.

[0159] Furthermore, the first type of pins 2110 are arranged in an array, including signal transmission pins and power supply pins (wherein the power supply pins are used to supply power to the signal transmission pins). All pins in any column of this array are of the same type, and the pin types in any two adjacent columns of this array are different, such as... Figure 7a As shown; or, all pins in any row of the array are of the same type, and the pins in any two adjacent rows of the array are of different types, such as... Figure 7b As shown. That is to say, in the array formed by the first type of pins 2110 of chip 2100, different types are distributed at row or column intervals.

[0160] Typically, the signal transmission pins of a chip have a larger area than its power supply pins. Therefore, the array distribution of the first type of pins 2110, with the signal transmission pins and power supply pins in the first type of pins 2110 arranged in rows or columns, can reduce the area occupied by the pins in the chip 2100. This can increase the number of pins per unit area in the chip 2100, meeting the requirements for high chip integration. At the same time, the arrangement of the signal transmission pins and power supply pins in the first type of pins 2110 in rows or columns can separate the signal transmission pins in different columns, reducing mutual interference between signal transmission pins and improving signal transmission quality.

[0161] Furthermore, the second type of pins 2120 can also be arranged in an array, including signal transmission pins and power supply pins. In this array, all pins in any column are of the same type, and the pin types in any two adjacent columns of the array are different, such as... Figure 7a As shown; or, all pins in any row of the array are of the same type, and the pins in any two adjacent rows of the array are of different types, such as...Figure 7b As shown. That is to say, in the array formed by the second type of pins 2120 of chip 2100, different types are distributed at row or column intervals.

[0162] According to the above scheme, the pins of chip 2100 are divided into a first type of pin 2110 and a second type of pin 2120 based on the different transmission rates of the signals transmitted by the pins. The first type of pin 2110 and the second type of pin 2120 are respectively set in the first part and the second part of chip 2100, so that when chip 2100 is packaged with other chips, the first type of pin 2110 of chip 2100 can be connected to other chips through the shortest possible interconnection path, thereby improving the bandwidth of the packaged chip.

[0163] like Figure 22 As shown in the figure, this application embodiment also provides a chip packaging method, which mainly includes the following steps:

[0164] S2201: A vertical interconnect structure is fabricated on the active surface of the first part of the first chip.

[0165] The vertical interconnect structure can be any one of copper pillars, TMV, TDV, TIV, or solder balls.

[0166] S2202: Attach the active surface of the second part of the first chip to the passive surface of the second chip.

[0167] Specifically, the active surface of the second part of the first chip can be adhered to the passive surface of the second chip using an adhesive material. This adhesive material can be DAF or silver paste, among other materials.

[0168] S2203: An interconnect layer is fabricated on the active surface of the vertical interconnect structure and the second chip. This interconnect layer can be a substrate or a wiring layer.

[0169] In step S2201, a vertical interconnect structure is fabricated on the active surface of the first portion of the first chip, specifically including the following steps: i. bonding the active surface of the first chip to a carrier; ii. preparing a first insulating material to form a first package, wherein the first insulating material encapsulates the first chip; iii. removing the carrier and fabricating the vertical interconnect structure on the active surface of the first portion within the first package. The carrier may include, but is not limited to, any one of silicon wafers and glass wafers, and a temporary bonding layer is provided between the carrier and the first chip to facilitate subsequent debonding.

[0170] At this point, in step S2202, the passive surface of the second chip is attached to the surface of the first package starting from the location of the second active surface.

[0171] After preparing the first insulating material and before removing the carrier, the process further includes thinning the first package. Specifically, the first package can be thinned to a predetermined thickness using processes including but not limited to grinding, polishing, or a combination of both. This predetermined thickness is determined based on the actual processing technology and processing costs. For example, when the thickness of the first chip is large, the first package can be thinned to the same thickness as the first chip.

[0172] In step 2203, the interconnect layer can be fabricated on the active surface of the vertical interconnect structure and the second chip using the following methods: 1. Prepare a second insulating material to form a second package, wherein the second insulating material encapsulates the vertical interconnect structure and the second chip; 2. Fabricate the interconnect layer on the surface of the active surface of the vertical interconnect structure and the second chip within the second package. The second insulating material can be the same as or different from the first insulating material.

[0173] The process includes, after preparing the second insulating material and before preparing the interconnect layer on the surface where the vertical interconnect structure and the active surface of the second chip are located in the second package, grinding the second package to expose small copper pillars on the active surface of the vertical interconnect structure and the second chip. The small copper pillars on the active surface of the second chip can be pre-processed on the active surface of the second chip.

[0174] Furthermore, after performing step S2203, solder balls can be prepared on the interconnect layer so that the chip obtained after packaging the first chip and the second chip can be connected to the outside through solder balls.

[0175] The following describes the encapsulation process as follows: Figure 5a Taking the integrated chip 200 shown as an example, the chip packaging method provided in this application will be described in detail. The first chip 220 is a processor chip, and the second chip 240 is an HBM-DRAM chip separated from a memory package purchased from a memory manufacturer. The separated DRAM chip has a bandwidth of up to 256Gbps, and its bit width is also higher than that of the DRAM package in a traditional stacked packaging structure, reaching 1024 bits.

[0176] Encapsulation formation as Figure 5a The integrated chip 200 shown mainly includes the following steps:

[0177] S2301: Temporarily bond the active face of the second chip 240 to the carrier. A temporary bonding layer is provided between the carrier and the second chip 240.

[0178] S2302: The second chip 240 bonded to the carrier is encapsulated using molding compound to obtain the first package.

[0179] S2303: Thinning treatment is performed on the first package.

[0180] S2304: Separate the carrier from the first package after thinning and remove the carrier (i.e., debond).

[0181] S2305: Copper pillars are fabricated on the active surface of the second portion of the second chip 240 in the first package after thinning.

[0182] S2306: Using adhesive material, the passive surface of the first chip 220 is adhered to the active surface of the first portion of the second chip 240 in the first package. The active surface of the first chip 220 has multiple small copper pillars.

[0183] S2307: The copper pillar and the first chip 220 are encapsulated using molding compound to obtain the second package.

[0184] S2308: The second package is ground to expose the copper pillars prepared on the first part of the second chip 240 and the small copper pillars on the active surface of the first chip 220.

[0185] S2309: RDL and solder balls are fabricated on the surface of the exposed copper pillars and small copper pillars on the second package.

[0186] The integrated chip 1300 can also be prepared using a method similar to the one described above. The subtle difference is that after molding the second chip 1350 to obtain the first package, the dielectric material and metal wiring of the second interconnect layer 1340 need to be generated on the surface of the first package by growth. Then, vertical interconnect structures such as copper pillars are fabricated or grown on the second interconnect layer 1340, and the first chip 1320 is attached.

[0187] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An integrated chip, characterized in that, include: Interconnect layer; The first chip disposed on the interconnect layer; The second chip includes a first part and a second part, the first part being fixed to the top surface of the first chip, and the second part protruding from the side of the first chip. A first vertical interconnect structure is disposed on the side of the first chip. The second part is electrically connected to the interconnect layer through the first vertical interconnect structure. The interconnect layer is a redistribution layer. The redistribution layer includes multiple dielectric layers and a conductive layer sandwiched between the dielectric layers. Circuit wiring is disposed on the conductive layer. Dielectric vias are disposed in the dielectric layer to connect circuit wiring on different layers. The first vertical interconnect structure is a plurality of through-hole vias (TMVs), or a plurality of through-hole vias (TDVs), or a plurality of through-hole vias (TIVs); one end of the first vertical interconnect structure is directly connected to the bottom of the second part of the second chip, and the other end of the first vertical interconnect structure is directly connected to the conductive layer in the interconnect layer. The second chip is provided with signal transmission pins, and all signal transmission pins on the second chip are located at the bottom of the second part; the second chip is also provided with power supply pins, and all signal power supply pins on the second chip are located at the bottom of the second part. The signal transmission pins and power supply pins on the second chip constitute a first pin array. Wherein, all pins in any column of the first pin array are of the same type, and the pins in any two adjacent columns of the first pin array are of different types; or, all pins in any row of the first pin array are of the same type, and the pins in any two adjacent rows of the first pin array are of different types.

2. The integrated chip as described in claim 1, characterized in that, The first chip is a processor chip, and the second chip is a memory chip.

3. The integrated chip as described in claim 1, characterized in that, The first part is fixed to the top surface of the first chip by adhesive material.

4. The integrated chip as described in claim 1, characterized in that, The integrated chip includes at least two of the first chips; and / or, the integrated chip includes at least two of the second chips.

5. The integrated chip as described in claim 1, characterized in that, The integrated chip also includes: The third chip includes a third part and a fourth part, the third part being fixed to the top surface of the second chip, and the fourth part protruding from the side of the second chip. A second vertical interconnect structure is disposed on the side of the second chip, and the fourth part is electrically connected to the interconnect layer through the second vertical interconnect structure.

6. The integrated chip as described in claim 5, characterized in that, The third chip is provided with signal transmission pins, and all signal transmission pins on the third chip are located at the bottom of the fourth part.

7. The integrated chip as described in claim 5 or 6, characterized in that, The second vertical interconnect structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of through-holes (TMVs), or a plurality of dielectric layer vias (TDVs), or a plurality of insulating layer vias (TIVs); One end of the second vertical interconnect structure is directly connected to the bottom of the fourth part, and the other end of the second vertical interconnect structure is directly connected to the conductive layer in the interconnect layer.

8. The integrated chip as described in claim 7, characterized in that, The third chip is also provided with power supply pins, and all signal power supply pins on the third chip are located at the bottom of the fourth part.

9. The integrated chip as described in claim 8, characterized in that, The signal transmission pins and power supply pins on the third chip constitute the second pin array; In this configuration, all pins in any column of the second pin array are of the same type, and the pins in any two adjacent columns of the second pin array are of different types; or, all pins in any row of the second pin array are of the same type, and the pins in any two adjacent rows of the second pin array are of different types.

10. An integrated chip, characterized in that, include: First interconnect layer; A first chip disposed on the first interconnect layer; A second interconnect layer disposed on the top surface of the first chip; A second chip disposed on the top surface of the second interconnect layer; The second chip includes a first part and a second part, wherein the first part coincides with the projection of the first chip on the second interconnect layer, and the second part protrudes from the first part along the second interconnect layer to the side of the first chip; A first vertical interconnect structure is disposed on the side of the first chip. The first chip and the second chip are connected to the first interconnect layer by bypassing the first chip through the second interconnect layer and the first vertical interconnect structure. The first interconnect layer and the second interconnect layer are redistribution layers. The redistribution layer includes multiple dielectric layers and conductive layers sandwiched between the dielectric layers. Circuit wiring is disposed on the conductive layers. Dielectric vias are disposed in the dielectric layers to connect circuit wiring on different layers. The first vertical interconnect structure is a plurality of through-holes (TMVs), or a plurality of dielectric layer through-holes (TDVs), or a plurality of insulating layer through-holes (TIVs); One end of the first vertical interconnect structure is connected to the bottom of the second part of the second chip through the second interconnect layer, and the other end of the first vertical interconnect structure is directly connected to the conductive layer in the first interconnect layer. The second chip has at least one signal transmission pin, and all signal transmission pins on the second chip are located at the bottom of the second part; the second chip also has power supply pins, and some or all of the power supply pins on the second chip are located at the bottom of the second part; the signal transmission pins and power supply pins on the second chip constitute a first pin array. Wherein, all pins in any column of the first pin array are of the same type, and the pins in any two adjacent columns of the first pin array are of different types; or, all pins in any row of the first pin array are of the same type, and the pins in any two adjacent rows of the first pin array are of different types.

11. The integrated chip as described in claim 10, characterized in that, The integrated chip includes at least two of the first chips; and / or, the integrated chip includes at least two of the second chips.

12. The integrated chip as described in claim 11, characterized in that, The integrated chip also includes: A third interconnect layer disposed on the top surface of the second chip; A third chip disposed on the top surface of the third interconnect layer; The third chip includes a third part and a fourth part. The third part coincides with the projection of the second chip onto the third interconnect layer, and the fourth part protrudes from the third part along the third interconnect layer to the side of the second chip. The second vertical interconnect structure is disposed to the side of the second chip. The third chip bypasses the first chip and is connected to the first interconnect layer through the third interconnect layer and the second vertical interconnect structure.

13. The integrated chip as described in claim 12, characterized in that, The third chip is provided with signal transmission pins, and all signal transmission pins on the third chip are located at the bottom of the fourth part.

14. The integrated chip as described in claim 12 or 13, characterized in that, The second vertical interconnect structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of through-holes (TMVs), or a plurality of dielectric layer vias (TDVs), or a plurality of insulating layer vias (TIVs); One end of the second vertical interconnect structure is connected to the bottom of the fourth part through the third interconnect layer, and the other end of the second vertical interconnect structure is connected to the conductive layer in the first interconnect layer.

15. The integrated chip as described in claim 13, characterized in that, The third chip is also provided with power supply pins, and some or all of the power supply pins on the third chip are located at the bottom of the fourth part.

16. The integrated chip as described in claim 13, characterized in that, The signal transmission pins and power supply pins on the third chip constitute a second pin array; In this configuration, all pins in any column of the second pin array are of the same type, and the pins in any two adjacent columns of the second pin array are of different types; or, all pins in any row of the second pin array are of the same type, and the pins in any two adjacent rows of the second pin array are of different types.

17. The integrated chip as described in claim 10, characterized in that, The first chip is a processor chip, and the second chip is a memory chip.

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