A Method, System, Device and Medium for Static Global Upgrade and Reconfiguration of Chip FPGA

Abstract

The present invention provides a method, system, device and medium for static global upgrade and reconstruction of a chip FPGA. Through the serial port of the PS side of the chip, without opening the product shell and using an emulator, it is possible to complete the online upgrade and reconstruction of the bit file in the PL segment on the chip, the FSBL on the PS side, and the user application program. The function of receiving commands from the host computer through the debug serial port is added by modifying the FSBL program. And by setting a timeout period, it is determined whether the modified FSBL program receives the command from the host computer within the timeout period, and then enters the upgrade program and the reconstruction program in sequence. The present invention uses a multi-serial port card and can simultaneously complete the online upgrade and reconstruction of software on multiple products. Compared with the traditional upgrade method, the production efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the fields of electronic engineering and computer science, and particularly to a method, system, device and medium for static global upgrade and reconstruction of an FPGA chip. Background Art

[0002] In the latest FPGAs of the current prior art, a multi-core heterogeneous architecture is usually adopted. That is, both a processor and an FPGA dedicated circuit are integrated in one chip. The processor is called the PS side, and the FPGA is called the PL side. The two are interconnected through the AXI4 bus. This heterogeneous architecture greatly increases the flexibility of use. Users can allocate functions to the PS or PL side according to needs. Even without changing the original peripheral hardware design, the program logic can be updated to change the functions provided by the system to the outside. This architecture poses new requirements for the upgrade and reconstruction of existing FPGA programs.

[0003] Generally, the method for upgrading and burning the program of the zynq7000 series chips probably includes the following process steps: First, develop an application program for the processor, that is, the PS side, to generate a corresponding elf file. On the FPGA side, that is, the PL side, develop the FPGA program to generate a bit file. Finally, generate an fsbl program according to the hardware platform configuration. This program mainly completes the configuration of the processor-side clock, cache, debugging serial port configuration, parsing the bit file, configuring the functions of the FPGA side according to the bit file, and loading the processor-side application program. Finally, through the development environment of xilinx, the elf file generated by the fsbl project, the bit file on the FPGA side, and the user executable file are packaged into a bin file and burned to the external spi Flash.

[0004] Under this process, any changes to the processor-side application program or the FPGA-side program by the user require re-packaging the latest bit file on the FPGA, the application program elf file on the processor side, and the elf file under the new fsbl project and then burning them again. The format of the bin file generated by the traditional method is as Figure 1 shown: It mainly includes five parts: boot ImageHeader, image Header Table, Partition Header Table, and partition. Moreover, the system needs to be powered on again to enable new functions. In practical applications, it is often impossible to directly burn with an emulator, but to update the user application program or the bit file on the FPGA side online through the external interface of the processor side such as the serial port. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a method, system, device and medium for static global upgrade and reconstruction of a chip FPGA, which effectively completes the online upgrade and reconstruction of user application programs on the chip FPGA.

[0006] The present invention is realized through the following technical solutions:

[0007] A method for static global upgrade and reconstruction of a chip FPGA includes the following steps:

[0008] Step 1, execute the read-only memory mirror rom program inside the chip, parse the bin file in Flash, load and run the FSBL program in Flash, and configure the PLL and cache on the processor side as well as the serial port used for upgrade; the FSBL program is the modified FSBL program;

[0009] Step 2, set a timeout period, and determine whether the modified FSBL program receives a command from the host computer within the timeout period; when the modified FSBL program does not receive a command from the host computer within the set timeout period, then transfer to the FPGA side configuration and enter the user application program loading stage, parse the bin file in Flash and load the bit file of the FPGA as well as parse the bin file in Flash to load the PS side application program until the work ends; when the modified FSBL program receives a command from the host computer within the set timeout period, enter the upgrade mode;

[0010] Step 3, after entering the upgrade mode, after receiving a file information packet, determine the program to be upgraded, receive a command packet for the file data to be upgraded, and enter the reconstruction mode after upgrading the corresponding program;

[0011] Step 4, after entering the reconstruction mode, determine whether to receive a command packet for reconstruction. If the command packet for reconstruction is not received, the work ends; if the command packet for reconstruction is received, execute the reconstruction process.

[0012] Preferably, after the FSBL program receives a command packet for file information to be upgraded sent by the host computer, it determines the type of the file to be upgraded through the information in the command packet for file information to be upgraded.

[0013] Preferably, the file data command packet to be upgraded includes an instruction field, a data field, a file type field, a length field, a check field, a sequence number field, and a file name field; the instruction field is filled with an upgrade instruction, and the data field includes the length of the file to be upgraded, the entry address of the file operation, and the loading address of the file in the memory; the file type to be upgraded is written in the file type field; the length of the data field is written in the length field; the information of the instruction field, the data field, and the length field is verified and written in the check field; the sequence number field is filled with the sequence number of the sent upgrade command packet; the file name field is written with the file name of the file to be upgraded; the length field is written with the effective length of the entire command packet.

[0014] Further, the file types to be upgraded include FSBL programs, PL-side programs, PS-side programs, and FPGA programs.

[0015] Preferably, after the FPGA program is upgraded, relevant fields of the partition header Partition Header structure corresponding to the FPGA program need to be modified, and the checksum of the partition header Partition Header structure is recalculated and written into the header checksum field Header Checksum of the partition header Partition Header structure, where the checksum algorithm is to accumulate the fields in the partition header Partition Header structure except the header checksum field Header Checksum, and the obtained accumulated sum is bitwise inverted.

[0016] Preferably, when executing the reconstruction command on the command packet to be reconstructed, after judging the file type field of the received command packet to be reconstructed, the reconstruction of the corresponding program to be reconstructed is executed; the programs to be reconstructed include FPGA programs, PS-side programs, and FSBL programs.

[0017] Further, the method for judging the type of the received command packet to be reconstructed is as follows:

[0018] When the file type field in the command packet to be reconstructed is an FPGA program, control the PCAP hardware peripheral to reconstruct the FPGA program and reload it into the reconstruction mode;

[0019] When the file type field in the command packet to be reconstructed is a PS-side program, load the PS-side program from the Flash into the internal static random access memory sram or double data rate synchronous dynamic random access memory DDR3 of the PS-side program, and jump to execute the PS program inside the static random access memory sram or double data rate synchronous dynamic random access memory DDR3;

[0020] When the file type field in the command packet to be reconstructed is an FSBL program, execute to reload the FSBL program into the reconstruction mode.

[0021] A chip FPGA static global upgrade and reconstruction system, comprising:

[0022] A first execution module, configured to execute the read-only memory image rom program inside the chip, parse the bin file in the Flash, load and run the FSBL program in the Flash, configure the PLL and cache in the processor side, and the serial port used for upgrade; the FSBL program is the modified FSBL program;

[0023] A first judgment module, configured to set a timeout period, and judge whether the modified FSBL program receives a command from the host computer within the timeout period; when the modified FSBL program does not receive a command from the host computer within the set timeout period, it transfers to the FPGA side configuration, enters the user application program loading stage, parses the bin file in the Flash, loads the bit file of the FPGA, and parses the bin file in the Flash to load the PS side application program until the work ends; when the modified FSBL program receives a command from the host computer within the set timeout period, it enters the upgrade mode;

[0024] A second execution module, configured to, after entering the upgrade mode, determine the program to be upgraded after receiving a file information packet, receive a command packet for the data of the file to be upgraded, and enter the reconstruction mode after upgrading the corresponding program;

[0025] A second judgment module, configured to, after entering the reconstruction mode, judge whether to receive a command packet to be reconstructed. If the command packet to be reconstructed is not received, the work ends; after receiving the command packet to be reconstructed, execute the reconstruction process.

[0026] A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the chip FPGA static global upgrade and reconstruction method as described above are implemented.

[0027] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the chip FPGA static global upgrade and reconstruction method as described above are implemented.

[0028] Compared with the prior art, the present invention has the following beneficial technical effects:

[0029] The present invention provides a method for static global upgrade and reconstruction of a chip FPGA. Through the serial port of the PS side of the chip, without opening the product shell and using an emulator, it is possible to complete the online upgrade and reconstruction of the bit file in the PL segment on the chip, the FSBL on the PS side, and the user application program. By modifying the FSBL program to add the function of receiving commands from the host computer through the debug serial port. And by setting a timeout period, it is determined whether the modified FSBL program receives a command from the host computer within the timeout period, and then enters the upgrade program and the reconstruction program in sequence. The present invention uses a multi-serial port card and can simultaneously complete the online upgrade and reconstruction of software on multiple products. Compared with the traditional upgrade method, the production efficiency is greatly improved.

[0030] A system for static global upgrade and reconstruction of a chip FPGA. The first execution module loads and runs the modified FSBL program to be upgraded and reconstructed, and the first judgment module determines whether the FSBL program receives a command from the host computer within a specified time. The second execution module executes the upgrade process for the command of the file data to be upgraded in the upgrade mode, and enters the reconstruction mode after executing the upgrade command. The second judgment module judges and executes the reconstruction process, which improves the systematization of the method for static global upgrade and reconstruction of the chip FPGA and facilitates the loading and running of the upgrade and reconstruction processes. Description of the Drawings

[0031] Figure 1 It is the bin file format in the prior art;

[0032] Figure 2 It is the flowchart of the method for static global upgrade and reconstruction of the chip FPGA in the present invention. Detailed Embodiments

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings:

[0036] The present invention provides a method for static global upgrade and reconstruction of a chip FPGA, which effectively completes the online upgrade and reconstruction of user application programs on the chip FPGA.

[0037] Specifically, as shown in Figure 2 the method for static global upgrade and reconstruction of the chip FPGA includes the following steps:

[0038] Step 1, execute the read-only memory mirror rom program inside the chip, parse the bin file in Flash, load and run the FSBL program in Flash, and configure the PLL and cache on the processor side and the serial port used for upgrade; the FSBL program is the modified FSBL program;

[0039] Step 2, set a timeout period, and determine whether the modified FSBL program receives a command from the host computer within the timeout period; when the modified FSBL program does not receive a command from the host computer within the set timeout period, it transfers to the FPGA side configuration and enters the user application program loading stage, parses the bin file in Flash and loads the bit file of the FPGA, and parses the bin file in Flash to load the PS side application program until the work ends; when the modified FSBL program receives a command from the host computer within the set timeout period, it enters the upgrade mode;

[0040] Step 3, after entering the upgrade mode, after receiving the file information packet, determine the program to be upgraded, receive the command packet for the file data to be upgraded, and enter the reconstruction mode after upgrading the corresponding program;

[0041] Step 4, after entering the reconstruction mode, determine whether to receive the command packet to be reconstructed. If the command packet to be reconstructed is not received, the work ends; after receiving the command packet to be reconstructed, execute the reconstruction process.

[0042] Specifically, in the upgrade mode, after the modified FSBL program receives the command packet of the file information to be upgraded sent by the host computer, it determines the type of the file to be upgraded through the information in the command packet of the file information to be upgraded.

[0043] Specifically, the command packet of the file data to be upgraded includes an instruction field, a data field, a file type field, a length field, a checksum field, a sequence number field, and a file name field; the upgrade instruction is filled in the instruction field, and the length of the file to be upgraded, the entry address of the file operation, and the loading address of the file in the memory are included in the data field; the type of the file to be upgraded is filled in the file type field; the length of the data field is written into the length field; the information of the instruction field, the data field, and the length field is verified and written into the checksum field; the sequence number of the sent upgrade command packet is filled in the sequence number field; the file name of the file to be upgraded is written into the file name field; the effective length of the entire command packet is written into the length field.

[0044] Among them, the types of files to be upgraded include the FSBL program, the PL-side program, the PS-side program, and the FPGA program.

[0045] Specifically, in the reconstruction mode, after the FPGA program is upgraded, relevant fields of the partition header Partition Header structure corresponding to the FPGA program need to be modified, and the checksum of the partition header Partition Header structure is recalculated and written into the header checksum field Header Checksum of the partition header Partition Header structure, where the checksum algorithm is to accumulate the fields in the partition header Partition Header structure except the header checksum field Header Checksum, and the obtained accumulated sum is bitwise inverted.

[0046] Specifically, when executing the reconstruction command on the command packet to be reconstructed, after determining the file type in the received command packet to be reconstructed, the reconstruction of the corresponding program to be reconstructed is executed; the programs to be reconstructed include the FPGA program, the PS-side program, and the FSBL program.

[0047] Specifically, the method for determining the type of the received command packet to be reconstructed is as follows:

[0048] When the file type field in the command packet to be reconstructed is the FPGA program, control the PCAP hardware peripheral to reconstruct the FPGA program and reload it into the reconstruction mode;

[0049] When the file type field in the command packet to be reconstructed is a PS-side program, the PS-side program is loaded from Flash into the internal static random access memory (sram) or double data rate synchronous dynamic random access memory (DDR3) of the PS-side program, and the PS program inside the sram or DDR3 is jumped to for execution;

[0050] When the file type field in the command packet to be reconstructed is an FSBL program, the FSBL program is reloaded to enter the reconstruction mode.

[0051] Embodiment

[0052] An online upgrade method for user application programs and FPGA programs on zynq7000 series chips. S1: Modify the fsbl project to add the function of receiving commands from the host computer through the debug serial port. After the system starts, the application program corresponding to the fsbl project is executed first, and it completes the following functions: configuring the PLL and cache on the processor side, and configuring the serial port used for upgrade.

[0053] Wait for the serial port to receive commands from the lower computer: If no command packet from the host computer is received within the set timeout period, it will transfer to the FPGA-side configuration and the user application program loading stage. The subsequent steps are the same as the function flow of the existing FSBL program.

[0054] If a command packet from the host computer (any agreed valid command) is received, enter the upgrade mode of the user application program and the FPGA program. At this time, the fsbl program loops to receive the command packets sent by the lower computer and enters the instruction processing branch specified by the protocol according to the instructions in the command packets.

[0055] S2: The software on the host computer reads the user application program or FPGA program to be upgraded, and first sends a command packet for the file information to be upgraded according to the preset communication protocol. In the instruction segment of this command packet, fill in the instruction for the file information to be upgraded. In the data segment, include the file length, the entry address where the file runs, and the loading address of the file in memory. Calculate the length of the data segment and write it into the length field of the command packet. Finally, calculate the checksum of the instruction field, data field, and length field information of the command packet and write it into the checksum segment of the command packet. Fill in the serial number segment of the command packet with the serial number of the upgrade command packet sent (this serial number starts from 1, and for each upgrade command packet sent, the serial number increases by 1). Write the file type to be upgraded (FSBL program, user application program, or FPGA program) into the file type segment, write the file name of the file to be upgraded into the file name segment, write the valid length of the entire command packet into the command packet length segment, and finally calculate the checksum of the command packet and write it into the checksum segment of the command packet. (For the convenience of writing, the above format is used as an example in this article. The method introduced in the present invention is not limited to the above command packet format.)

[0056] S3. After the modified FSBL program on the chip receives the command packet of the file information to be upgraded sent by the host computer, it determines the file type to be upgraded according to the information in the command packet. That is, the FSBL program, the user application program, or the FPGA program Bit file. In the aforementioned traditional method, the fsbl project elf file, the user application program elf file, and the FPGA program bit file have been packaged into a single bin file.

[0057] In this step, in order to upgrade the corresponding file, it is necessary to first parse the storage locations of the FSBL program, the user application program, or the FPGA program bit file corresponding to the original bin according to the bin file format burned into the spi Flash. For a specific FPGA chip, once the chip is selected, the generated bit file is always the same size during its development process and has nothing to do with the design. Therefore, when upgrading the bit file of the FPGA, the original bit file in the bin file can be directly overwritten. For the user program, the size of the generated elf file is related to the design. Therefore, the size of the original application program in the bin file may not be the same as the size of the user application program to be upgraded, so the elf file is placed at the end of the bin file.

[0058] S4. The bin file format generated by the traditional method is as Figure 1 shown: It mainly includes five parts: boot Image Header, image Header Table, Partition Header Table, and partition.

[0059] The starting address offset of the boot Image Header is an integer multiple of 32KB. Usually, multiple bin files can be included in Flash. When the chip is powered on, the program in the internal ROM will sequentially check whether the correct boot Image Header is included at the 32KB address offset. The basis for the search is the identifier 0x584C4E58 of the boot Image and the ASCII code 'XLNX'. And the boot image Header contains a field of Header checksum to verify whether the boot Image Header is valid. When the file to be upgraded is the FSBL program, the upgrade program is a bin file containing the new FSBL program. It is burned into a Flash sector that is 32KB byte-aligned and unused. Then erase the sector where the old bin file is located in Flash. Utilize the multiboot feature, that is, multiple bin files can exist in Flash simultaneously. After the chip is powered on and reset, the program in the internal ROM will sequentially search for valid bin programs in Flash. Since the old bin has been erased, parse the newly burned bin file for the FSBL program, move it to the internal OCM, and jump to the new fsbl to run. Update the fsbl program in this way.

[0060] S5, when the program to be upgraded is the FPGA bit file or the user application program. It is necessary to first find a valid boot image header. After finding a valid boot image header, add 0x8c0 to the offset address of the boot image header in Flash. This address offset is the Image header Table header. The format of the Image Headertable header is shown in Table 1:

[0061]

[0062] Table 1 Structure format of Image Header Table Header

[0063] The field at offset 0 is the Vesion field. For the entire zynq7000 series of chips and their corresponding bin files, this field is 0x01020000.

[0064] The field with an offset address of 4 is named count of Image headers. This field indicates the number of files packed in the bin file. Usually, this field is 3.

[0065] The field with an offset address of 8 is named: word offset to Partition Header. For a file packed in a bin, it usually corresponds to a partition. The partition identifies the image of the file in the memory. This field represents the offset address of the Partition Header structure specifying the partition - related information in the bin file within the bin file. Here, word means 4 bytes, so when addressing in bytes, the value of this field needs to be multiplied by 4.

[0066] The field at offset address 0xc is named: word offset to first Image Header. This field represents the offset of the Image Header, which is the description structure of the first file (i.e., the fsbl file) in the bin, within the bin file.

[0067] The field at offset address 0x10 is named: word offset to header authentication. This field represents the offset of the relevant authorization and authentication information, which is used in the encrypted bin file. This method does not involve encryption, and this field is usually 0 indicating that the field information is invalid.

[0068] Parse the Image Header table header structure to obtain the count of Image headers field and the word offset to first Image Header field.

[0069] S6, in the bin file, the Image Header structures are continuously distributed. Each Image Header field is 64 bytes. The Image Header structure is shown in Table 2;

[0070]

[0071] Table 2 Image Header structure format

[0072] The field at offset address 0 is named: word offset to Next Image Header. This field represents the offset of the next valid Image Header structure in the bin file.

[0073] The field at offset address 4 is named: Word offset to First Partition Header. This field represents the offset address of the partition Header structure of the file related to this Image Header in the bin file.

[0074] The field name at offset address 8 is: partition count. This field is invalid and its value length is 0.

[0075] The field name at offset address 0xc is: Image Name length. This field indicates how many partitions are required for the file described by this Image Header structure. Usually, a file only requires one partition. When the data or code addresses in the file are not continuous, a file requires multiple partitions. A partition represents a continuous block of code or data. Note that the field name does not match its actual meaning.

[0076] The field name at offset addresses 0x10 to N is: Image Name. This field represents the file name of the file described by the Image Header. The file name ends with 0. Each group of 4 bytes has its byte order reversed, and by recombining the characters represented by the bytes in each group, the file name string can be obtained.

[0077] Parse the Image Header structure successively according to the count of Image headers field and word offset to first Image Header field parsed according to S5. Multiple Image Header structures in the bin file form a linked list. Based on the first image Header structure and the number of Image Headers, all Image header structures can be traversed to parse the Image Name field in the Image Header structure. Compare whether it is the same as the file name specified in the upgrade command package. If not, further check the suffix of the Image Name and determine whether the file to be upgraded is a bit file or an elf file based on the suffix. If it is an elf file, further determine whether this Image Header is the first Image Header. If it is the first Image Header, the Image Header describes the FSBL program. If not, the Image Header describes the user application program. Determine the Image header structure corresponding to the program to be upgraded according to the file type in the received upgrade command.

[0078] S7. According to the Word offset to First Partition Header field in the Image Header structure, parse the partition header structure corresponding to the file to be upgraded. This structure is shown in Table 3;

[0079]

[0080]

[0081]

[0082] Table 3 Partition header structure format

[0083] The field name at offset address 0x0 is: Partition Data Word Length. This field represents the effective data length of the file after encryption encoding described by the Partition structure.

[0084] The field name at offset address 0x4 is: Extracted Data Word Length. This field represents the effective data length of the file before encryption described by the Partition structure.

[0085] The field name at offset address 0x8 is: Total Partition Word Length(Includes Authentication Certificate). This field represents the effective data length of the file after encryption encoding described by the Partition structure plus additional alignment supplement fields and encryption authentication information. Usually when not encrypted, the values of the above three fields are the same.

[0086] The field name at offset address 0xC is: Destination Load Address. This field represents the address when the file described by the Partition structure runs in the internal ram of the chip. If the file is an ELF file, then this address is related to the link script file in the project when generating the file (the file with the ld suffix). If it is a bit file, then this address is 0XFFFFFFFF.

[0087] The field name at offset address 0x10 is: Destination Execution Address. This field represents the entry address when the file described by the Partition structure runs in the internal ram of the chip. Execute the corresponding program and jump to this address to run the program.

[0088] The field name at offset address 0x14 is: Data Word offset in Image. This field represents the offset address of the file described by the Partition structure in the bin file.

[0089] The field name at the offset address 0x18 is: Attribute Bits. This field represents the attributes of the file described by the Partition structure. The specific meaning represented by each bit of this field is shown in Table 5.

[0090] The field name at the offset address 0x1c is: section count. This field is invalid. The value of this field is usually 1.

[0091] The field name at the offset address 0x20 is: Checksum Word Offset. This field is invalid. The value of this field is usually 0.

[0092] The field name at the offset address 0x24 is: Image Header Word Offset. This field represents the offset address of the corresponding Image Header structure of the file described by the Partition structure in the bin file.

[0093] The field name at the offset address 0x28 is: Authentication Certification Word offset. This field represents the offset address of the encryption authentication related information of the file described by the Partition structure in the bin file.

[0094] The field name at the offset addresses 0x2C - 0x3C is: unused. This field is not used and the value of this field is usually 0.

[0095] The field name at the offset address 0x3C is: Header Checksum. This field represents the checksum of all fields before this field in the partition header. The checksum algorithm is to accumulate all fields before this field in this partition header, and the calculated accumulated sum value is bitwise inverted. This field is used to verify the integrity of the partition header information.

[0096] If the bin file in the Flash is parsed according to the information in the command packet of the file to be upgraded in the above steps, and the checksum of the partition header corresponding to the file to be upgraded is calculated correctly. Then, fill the fields such as Total Partition Word Length, Destination Load Address, Destination Execution Address, and Data Word offset in Image in the current partition header, as well as the Image Name and other fields in the Image Header associated with this Partition header, into the data field of the response packet, and write 0xAAAAAAAA in the instruction execution result field (indicating that the command sent by the host computer is executed correctly). Calculate the length of the data field of the response packet and write it into the response packet length field. Calculate the checksum of the response packet and write it into the response packet checksum field. The FSBL program on the chip sends the response packet to the host computer and waits for the host computer to continue sending the command packet of the valid data of the program to be upgraded.

[0097] If the bin file in the Flash is parsed according to the information in the command packet of the file to be upgraded or the checksum of the partition header corresponding to the file to be upgraded is calculated incorrectly in the above steps, then write data other than 0xAAAAAAAA in the instruction execution result field (different result identifiers are defined according to specific errors). After receiving the response packet, the host computer parses the problem in the command execution process according to the identifier in the instruction execution result field and feedbacks it to the user.

[0098] S8. After the host computer receives the response packet returned by the fsbl program on the chip, calculate the checksum of the response packet and compare it with the checksum field in the response packet. If they are the same, further parse the response packet. If they are different, discard the response packet. If the instruction execution result field in the response packet returns the correct execution result. Then the host computer reads the valid data of the program to be upgraded, fills the data field of the command packet of the program to be upgraded, and at the same time writes the actual offset address burned into the Flash calculated according to the Data Word offset in Image information in the response packet and the offset of the currently read valid data in the file (actual offset address = (value of the Data Word offset in Image field) × 4 + offset of the valid data in the file) into the offset address field. Fill the current data segment data length in the length field. Calculate the checksum of the command packet of the program to be upgraded and write it into the checksum field of the command packet of the program to be upgraded.

[0099] S9. After the FSBL program on the chip receives the command packet of the program data to be upgraded, it calculates the checksum of the command packet and compares it with the checksum in the command packet field. If they are consistent, it further parses the command packet of the program data to be upgraded, and according to the length field, offset address field, and data field information in the command packet, erases the Flash sector where the offset address is located, and rewrites the data in the command packet of the program data to be upgraded to the corresponding offset address in the Flash. After the writing is completed, it returns the command packet of the program data to be upgraded to the host computer. The instruction execution result field in the command packet is written with different identifiers according to whether the writing process is normal.

[0100] S10. After the host computer receives the command packet returned by the fsbl program on the chip, it calculates the checksum of the command packet and compares it with the checksum field in the command packet. If they are consistent, it further parses the command packet; if they are inconsistent, it discards the command packet. If the instruction execution result field in the command packet indicates that the command execution of the program to be upgraded is normal, it continuously repeats steps S8 and S9 until the entire file to be upgraded is uploaded and written. If the execution result is abnormal, it repeats sending the command packet of the program data of the previous time. If it fails to execute successfully after multiple transmissions, the host computer will feedback the error to the user and stop the upgrade.

[0101] For reconstruction, it is mainly to reload the FPGA program for the PL side of the zynq7000 series of chips. In actual use, since the application program running on the PS side is closely related to the FPGA function on the PL side. Therefore, for the zynq7000 series of chips, after loading a new FPGA program on the PL side, it is also necessary to further load the PS side application program corresponding to the PL side function to complete the reconstruction of the entire chip function. The reconstruction process is as follows:

[0102] After the host computer completes the upgrade of the FPGA program and the user application program, it sends a reconstruction command. After the FSBL receives the correct reconstruction command, it completes the reconstruction through the PCAP hardware function component on the chip. The following steps are required:

[0103] L1. Write 1 to the devcfg.CTRL[PCAP_MODE] bit and the devcfg.CTRL[PCAP_PR] bit in the devcfg.CTRL register, indicating to start the reconstruction;

[0104] L2. Write 0xffffffff to the devcfg.INT_STS register to clear the interrupt flag;

[0105] L3. Write 1 to the devcfg.CTRL[PCFG_PROG_B] bit;

[0106] L4. Write 0 to the devcfg.CTRL[PCFG_PROG_B] bit;

[0107] L5, wait for the devcfg.STATUS[PCFG_INIT] bit to be 0;

[0108] L6, write 1 to the devcfg.CTRL[PCFG_PROG_B] bit;

[0109] L7, wait for the devcfg.STATUS[PCFG_INIT] bit to be 1;

[0110] L8, wait for the devcfg.STATUS[DMA_CMD_Q_F] bit to be 0;

[0111] L9, write 0 to the devcfg.MCTRL[INT_PCAP_LPBK] bit;

[0112] L10, when the FPGA file is encrypted, write 1 to devcfg.CTRL;

[0113] [QUARTER_PCAP_RATE_EN], otherwise write 0.

[0114] L11, configure the Source Address register of the DMA to the offset address of the FPGA file in Flash. This offset address value is obtained by calculating ((the value of the Data Word offset in Image field) × 4 + the offset address of the bin file in Flash) from the Data Word offset in Image field in the corresponding Partition Header structure of the user application and the offset address of the bin file in Flash. The Destination Address register is configured to 0xFFFFFFFF. Write the value of the Total Partition WordLength field in the corresponding Partition Header structure of the FPGA program to the SourceLength register. Write the same value as the Source Length register to the Destination Length register to start the DMA;

[0115] L12, wait for the devcfg.INT_STS[DMA_DONE_INT] bit to be 1, i.e., wait for the DMA transfer to complete;

[0116] L13, check the AXI_WERR_INT and AXI_RTO_INT of the devcfg.INI_STS register;

[0117] AXI_RERR_INT, RX_FIFO_OV_INT, DMA_CMD_ERR_INT, DMA_Q_OV_INT, P2D_LEN_ERR_INT, PCFG_HMAC_ERR_INT. Whether these bits are set, that is, whether an error has occurred.

[0118] L14, wait for the PCFG_DONE_INT bit in the devcfg.INT_STS register to be set to 1, indicating successful PL-side reconstruction;

[0119] Parse the bin file in Flash and load the user application to the PS side through DMA.

[0120] Configure the Source Address register of DMA to the offset address of the user application in Flash. It is obtained by calculating the Data Word offset in Image field in the Partition Header structure corresponding to the user application and the offset address of the bin file in Flash. The Destination Address register is configured with the value of the Destination Load Address field in the Partition Header structure corresponding to the user application. The Source Length register is written with the value of the Total Partition Word Length field in the Partition Header structure corresponding to the user application. The Destination Length register is written with the same value as the Source Length register to start DMA.

[0121] In addition to actively reconstructing the software by sending a reconstruction command from the host computer, the system can also be directly reset externally to load the upgraded FPGA program and user application. For the FPGA program, the relevant fields in the corresponding Partition Header structure in the bin file do not need to be changed after the upgrade. For the user application, information such as its corresponding load address, file length, and program entry address will change after the upgrade. Therefore, the relevant fields in its corresponding Partition Header structure need to be modified. And recalculate the checksum of this structure and write it to the HeaderChecksum field of the Partition Header structure. The checksum algorithm is to accumulate the fields in the Partition Header structure except the Header Checksum, and finally take the bitwise inverse of the obtained accumulated sum.

[0122] The present invention has been successfully applied to multiple embedded computer products that use the zynq7000 chip as a processor. During the overall machine joint debugging process, it is possible to complete the upgrade and reconstruction of the program on the zynq7000 chip in the product without opening the product shell, avoiding damage to the appearance of the product.

[0123] In summary, through the serial port on the PS side of the zynq7000 chip, the present invention can complete the online upgrade and reconstruction of the PL segment bit file, the FSBL on the PS side, and the user application program on the chip without opening the product shell and using an emulator. By using a multi-serial port card, the online upgrade and reconstruction of software on multiple products can be completed simultaneously. Compared with traditional upgrade methods, the production efficiency is greatly improved.

[0124] The following is an apparatus embodiment of the present invention, which can be used to execute the method embodiment of the present invention. For details not disclosed in the apparatus embodiment, please refer to the method embodiment of the present invention.

[0125] In another embodiment of the present invention, a chip FPGA static global upgrade and reconstruction system is provided, which can be used to implement the chip FPGA static global upgrade and reconstruction method described in the above embodiment. Specifically, it includes: a first execution module, which is used to execute the read-only memory mirror rom program inside the chip, parse the bin file in Flash, load and run the FSBL program in Flash, configure the PLL and cache on the processor side, and the serial port used for upgrade; the FSBL program is the modified FSBL program; a first judgment module, which is used to set a timeout period and judge whether the modified FSBL program receives a command from the host computer within the timeout period; when the modified FSBL program does not receive a command from the host computer within the set timeout period, it transfers to the FPGA side configuration and enters the user application program loading stage, parses the bin file in Flash, loads the bit file of the FPGA, and parses the bin file in Flash to load the PS side application program until the work ends; when the modified FSBL program receives a command from the host computer within the set timeout period, it enters the upgrade mode; a second execution module, which is used to, after entering the upgrade mode, determine the program to be upgraded after receiving the file information packet, receive the command packet for the data of the file to be upgraded, and enter the reconstruction mode after upgrading the corresponding program; a second judgment module, which is used to, when entering the reconstruction mode, judge whether to receive the command packet to be reconstructed. If the command packet to be reconstructed is not received, the work ends; after receiving the command packet to be reconstructed, execute the reconstruction process.

[0126] In another embodiment of the present invention, a computer device is provided. The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The computer program includes program instructions, and the processor is configured to execute the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is adapted to implement one or more instructions. Specifically, it is adapted to load and execute one or more instructions to implement the corresponding method flow or corresponding function. The processor described in the embodiments of the present invention can be used for the operation of the static global upgrade and reconstruction method of the chip FPGA.

[0127] In another embodiment of the present invention, a storage medium is also provided, specifically a computer-readable storage medium (Memory). The computer-readable storage medium is a memory device in a computer device and is used to store programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and, of course, the extended storage medium supported by the computer device. The computer-readable storage medium provides a storage space that stores the operating system of the terminal. And in this storage space, one or more instructions suitable for being loaded and executed by the processor are also stored. These instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. One or more instructions stored in the computer-readable storage medium can be loaded and executed by the processor to implement the corresponding steps of the static global upgrade and reconstruction method of the chip FPGA in the above embodiments.

[0128] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code.

[0129] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one or more of the processes Figure 1 or a plurality of processes and / or blocks

[0130] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one or more of the processes Figure 1 or a plurality of processes and / or blocks

[0131] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the processes Figure 1 or a plurality of processes and / or blocks

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: still can modify the specific implementation manners of the present invention or make equivalent replacements, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications or equivalent substitutions can still be made to the specific implementation manners of the present invention, and any modification or equivalent substitution that does not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A method for static global upgrade and reconstruction of a chip FPGA, characterized in that It includes the following steps: Step 1, execute the read-only memory mirror ROM program inside the chip, parse the bin file in Flash, load and run the FSBL program in Flash, configure the PLL and cache in the processor side, and the serial port for upgrade; the FSBL program is the modified FSBL program; Step 2, set the timeout time, and determine whether the modified FSBL program receives the command from the host computer within the timeout time; when the modified FSBL program does not receive the command from the host computer within the set timeout time, it transfers to the FPGA side configuration and enters the user application program loading stage, parses the bin file in Flash, loads the bit file of the FPGA, and parses the bin file in Flash to load the PS side application program until the work ends; when the modified FSBL program receives the command from the host computer within the set timeout time, it enters the upgrade mode; Step 3, after entering the upgrade mode, after receiving the file information packet, determine the program to be upgraded, receive the file data command packet to be upgraded, and enter the reconstruction mode after upgrading the corresponding program; Step 4, after entering the reconstruction mode, determine whether to receive the reconstruction command packet. If the reconstruction command packet is not received, the work ends; After receiving the reconstruction command packet, execute the reconstruction process.

2. The method for static global upgrade and reconstruction of a chip FPGA according to claim 1, characterized in that After the FSBL program receives the file information command packet to be upgraded sent by the host computer, it judges the file type to be upgraded through the information in the file information command packet to be upgraded.

3. A method for static global upgrade and reconstruction of a chip FPGA according to claim 1, characterized in that, The file data command packet to be upgraded includes an instruction field, a data field, a file type field, a length field, a checksum field, a sequence number field, and a file name field; the upgrade instruction is filled in the instruction field, the length of the file to be upgraded, the entry address of the file operation, and the loading address of the file in the memory are included in the data field; the file type to be upgraded is written in the file type field; the length of the data field is written in the length field; the information in the instruction field, the data field, and the length field is verified and written in the checksum field; the sequence number of the sent upgrade command packet is filled in the sequence number field; the file name of the file to be upgraded is written in the file name field; the valid length of the entire command packet is written in the length field.

4. A method for static global upgrade and reconstruction of a chip FPGA according to claim 3, characterized in that, The file types to be upgraded include the FSBL program, the PL side program, the PS side program, and the FPGA program.

5. A method for static global upgrade and reconstruction of a chip FPGA according to claim 1, characterized in that, After the FPGA program is upgraded, relevant fields of the partition header Partition Header structure corresponding to the FPGA program need to be modified, and the checksum of the partition header Partition Header structure is recalculated and written into the header checksum field Header Checksum of the partition header Partition Header structure, where the checksum algorithm is the accumulation of fields in the partition header Partition Header structure except the header checksum field Header Checksum, and the obtained accumulation sum is bitwise inverted.

6. A method for static global upgrade and reconstruction of a chip FPGA according to claim 1, characterized in that, When executing the reconstruction command for the received reconstruction command packet, the reconstruction process of the corresponding reconstruction program is executed after judging the file type field in the received reconstruction command packet to be reconstructed; the types of the programs to be reconstructed include FPGA programs, PS-side programs, and FSBL programs.

7. A method for static global upgrade and reconstruction of a chip FPGA according to claim 6, characterized in that, The method for judging the type of the received reconstruction command packet is as follows: When the type of the reconstruction command packet is an FPGA program, control the PCAP hardware peripheral to reconstruct the FPGA program and reload it into the reconstruction mode; When the file type field of the reconstruction command packet is a PS-side program, load the PS-side program from the Flash into the internal static random access memory sram or double data rate synchronous dynamic random access memory DDR3 of the PS-side program, and jump to execute the PS program inside the static random access memory sram or double data rate synchronous dynamic random access memory DDR3; When the file type field of the reconstruction command packet is an FSBL program, execute the reloading of the FSBL program into the reconstruction mode.

8. A chip FPGA static global upgrade and reconstruction system, characterized in that, It includes: A first execution module, which is used to execute the read-only memory mirror rom program inside the chip, parse the bin file in the Flash, load and run the FSBL program in the Flash, configure the processor-side PLL and cache, and upgrade the used serial port; the FSBL program is the modified FSBL program; A first judgment module, which is used to set a timeout period and judge whether the modified FSBL program receives a command from the upper computer within the timeout period; when the modified FSBL program does not receive a command from the upper computer within the set timeout period, it transfers to the FPGA-side configuration and enters the user application program loading stage, parses the bin file in the Flash, loads the bit file of the FPGA, and parses the bin file in the Flash to load the PS-side application program until the work ends; when the modified FSBL program receives a command from the upper computer within the set timeout period, it enters the upgrade mode; A second execution module, which is used to enter the upgrade mode, determine the program to be upgraded after receiving the file information packet, receive the command packet of the file data to be upgraded, and enter the reconstruction mode after upgrading the corresponding program; A second judgment module, which is used to enter the reconstruction mode and judge whether to receive the reconstruction command packet. If the reconstruction command packet is not received, the work ends; After receiving the reconstruction command packet, execute the reconstruction process.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip FPGA static global upgrade and reconstruction method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the chip FPGA static global upgrade and reconstruction method according to any one of claims 1 to 7.

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