Memory device and method of operating the same

Abstract

The present application discloses a memory device and an operation method thereof. The present disclosure relates to a memory device including a plurality of memory cells. The memory device further includes a peripheral circuit configured to perform a programming operation of storing data in the plurality of memory cells, the programming operation including a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected word line commonly connected to the plurality of memory cells and a verification operation of applying at least one verification voltage among a plurality of verification voltages corresponding to target programming states of the plurality of memory cells. The memory device further includes control logic configured to control the peripheral circuit such that during the programming operation, the at least one verification voltage increases according to the programming cycle among the plurality of programming cycles.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a storage controller that controls the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

[0003] A volatile memory device is a memory device that stores data when power is supplied and loses the stored data when the power is cut off. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0004] A non-volatile memory device is a memory device that does not lose data when the power is cut off. The non-volatile memory device may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a memory device having high reliability by improving a threshold voltage distribution and a method of operating the memory device.

[0006] A memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; a peripheral circuit configured to perform a programming operation of storing data in the plurality of memory cells, the programming operation including a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected word line commonly connected to the plurality of memory cells and a verification operation of applying at least one verification voltage among a plurality of verification voltages corresponding to target programming states of the plurality of memory cells; and a control logic configured to control the peripheral circuit such that the at least one verification voltage increases according to a programming cycle among the plurality of programming cycles during the programming operation.

[0007] A memory device according to an embodiment of the present disclosure may include: a memory cell array including a plurality of memory cells connected to a plurality of word lines; a peripheral circuit configured to perform a programming operation including a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected one of the plurality of word lines and a verification operation of applying some of a plurality of verification voltages corresponding to target programming states of the plurality of memory cells; and a control logic configured to control the peripheral circuit to determine voltage levels of the some verification voltages based on a number of target programming states corresponding to the some verification voltages and perform the programming operation using the determined some verification voltages.

[0008] A method of operating a memory device that performs a programming operation of storing data in a plurality of memory cells, the programming operation including a plurality of programming cycles, each programming cycle including a programming voltage application operation and a verification operation, the method includes the steps of: applying a programming voltage to a word line commonly connected to the plurality of memory cells; and applying, in the verification operation, verification voltages each increased by a step voltage from verification voltages applied in a verification operation of a previous programming cycle. The step voltage may be determined based on a number of target programming states corresponding to the verification voltages to be applied to the word line and voltage levels of the verification voltages applied in the verification operation of the previous programming cycle.

[0009] A memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; a peripheral circuit configured to perform a programming operation of storing data in the plurality of memory cells, the programming operation including a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected word line commonly connected to the plurality of memory cells and a verification operation of applying at least one of a plurality of verification voltages corresponding to target programming states of the plurality of memory cells; and a control logic configured to control the peripheral circuit such that, during the verification operation, some of at least two verification voltages applied to the selected word line have negative voltage levels and some have positive voltage levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram showing Figure 1 the structure of a memory device.

[0012] Figure 3 is a diagram showing Figure 2 a memory cell array.

[0013] Figure 4 is a diagram showing during a programming operationFigure 3 A diagram of the influence of adjacent bit lines among the first bit line BL1 to the m-th bit line BLm included in the memory cell array.

[0014] Figure 5 A diagram showing a programming cycle.

[0015] Figure 6 A timing diagram showing a programming method according to an embodiment.

[0016] Figure 7 A timing diagram showing a programming method according to an embodiment.

[0017] Figure 8 A timing diagram showing a programming method according to an embodiment.

[0018] Figure 9 A timing diagram showing a programming method according to an embodiment.

[0019] Figure 10 A timing diagram showing a programming method according to an embodiment.

[0020] Figure 11 A diagram showing according to an embodiment Figure 1 A flowchart of a programming voltage application operation and a verification operation included in a programming cycle of a memory device.

[0021] Figure 12 A diagram showing according to an embodiment Figure 2 A flowchart of a programming voltage application operation and a verification operation using a changed verification voltage included in a programming cycle of a memory device.

[0022] Figure 13 A flowchart of an operation of generating a changed verification voltage during a programming verification operation according to an embodiment.

[0023] Figure 14 A diagram showing the offset according to a count value during a programming verification operation.

[0024] Figure 15 A diagram showing Figure 2 An embodiment of a memory cell array.

[0025] Figure 16 A diagram showing Figure 1 Another embodiment of a storage controller.

[0026] Figure 17 A block diagram of a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0027] Figure 18is a block diagram showing a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0028] Figure 19 is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied. Detailed Embodiments

[0029] The advantages and features of the present disclosure and the methods for achieving these advantages and features will be described by the embodiments described in detail below together with the appended Figure 1 However, the present disclosure is not limited to the embodiments described herein and may be implemented in other specific forms. These embodiments are provided to describe in detail the technical spirit of the present disclosure to those skilled in the art to which the present disclosure pertains, so that those skilled in the art can implement the technical spirit of the present disclosure.

[0030] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0031] Referring to Figure 1 , the storage device 50 may include a memory device 100 and a storage controller 200 that controls the operation of the memory device. The storage device 50 is a device that stores data under the control of a host 400 (e.g., a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system).

[0032] According to the host interface as a communication method with the host 400, the storage device 50 may be manufactured as one of various types of storage devices. For example, the storage device 50 may be configured as any one of various types of storage devices, such as a multimedia card in the form of an SSD, MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a high-speed PCI (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0033] The storage device 50 may be manufactured as any one of various types of packages. For example, the storage device 50 may be manufactured as any one of various types of package types, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level package (WFP), and a wafer-level stack package (WSP).

[0034] The memory device 100 can store data. The memory device 100 operates under the control of the storage controller 200. The memory device 100 may include a memory cell array, and the memory cell array includes a plurality of memory cells that store data.

[0035] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that stores four data bits.

[0036] The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100.

[0037] A memory block may be a unit for erasing data. In an embodiment, the memory device 100 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory device.

[0038] The memory device 100 is configured to receive commands and addresses from the storage controller 200 and access a region selected by the address in the memory cell array. That is, the memory device 100 can perform an operation indicated by the command on the region selected by the address. For example, the memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 can program data into the region selected by the address. During the read operation, the memory device 100 can read data from the region selected by the address. During the erase operation, the memory device 100 can erase the data stored in the region selected by the address.

[0039] The storage controller 200 controls the overall operation of the storage device 50.

[0040] When power is applied to the storage device 50, the storage controller 200 may execute the firmware FW. When the memory device 100 is a flash memory device, the storage controller 200 may operate firmware such as a flash translation layer (FTL) to control communication between the host 400 and the memory device 100.

[0041] In an embodiment, the storage controller 200 may receive data and a logical block address (LBA) from the host 400 and convert the LBA into a physical block address (PBA) indicating an address of a memory cell in which the data included in the memory device 100 is to be stored.

[0042] The storage controller 200 may control the memory device 100 to perform a programming operation, a read operation, or an erase operation in response to a request from the host 400. During the programming operation, the storage controller 200 may provide a write command, a PBA, and data to the memory device 100. During the read operation, the storage controller 200 may provide a read command and a PBA to the memory device 100. During the erase operation, the storage controller 200 may provide an erase command and a PBA to the memory device 100.

[0043] In an embodiment, the storage controller 200 may generate commands, addresses, and data and send them to the memory device 100 regardless of a request from the host 400. For example, the storage controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a programming operation for wear leveling and a programming operation for garbage collection.

[0044] In an embodiment, the storage controller 200 may control at least two memory devices 100. In this case, the storage controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be an operation method that overlaps operation periods of at least two memory devices 100.

[0045] The host 400 may communicate with the storage device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0046] Figure 2 is a diagram showing Figure 1 the structure of the memory device.

[0047] Referring to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

[0048] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to an address decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a read / write circuit 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an implementation, the plurality of memory cells are non-volatile memory cells. The memory cells connected to the same word line among the plurality of memory cells are defined as one physical page. That is, the memory cell array 110 is configured by a plurality of physical pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between a drain select transistor and a memory cell and between a source select transistor and a memory cell.

[0049] Each memory cell of the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0050] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sense circuit 125.

[0051] The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a programming operation, a read operation, and an erase operation.

[0052] The address decoder 121 is connected to the memory cell array 110 through the row lines RL. The row lines RL may include a drain select line, a word line, a source select line, and a common source line. According to an embodiment of the present disclosure, the word line may include a normal word line and a dummy word line. According to an embodiment of the present disclosure, the row lines RL may further include a tube select line.

[0053] The address decoder 121 is configured to operate in response to the control of the control logic 130. The address decoder 121 receives an address ADDR from the control logic 130.

[0054] The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 121 may apply the operation voltage Vop supplied from the voltage generator 122 to the selected word line.

[0055] During a programming operation, the address decoder 121 may apply a programming voltage to the selected word line and apply a pass voltage having a level lower than the programming voltage to the unselected word lines. During a programming verification operation, the address decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage having a level higher than the verification voltage to the unselected word lines.

[0056] During a read operation, the address decoder 121 may apply a read voltage to the selected word line and apply a read pass voltage having a level higher than the read voltage to the unselected word lines.

[0057] According to an embodiment of the present disclosure, an erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input during the erase operation includes a block address. The address decoder 121 may decode the block address and select one memory block according to the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to the word lines input to the selected memory block.

[0058] According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode the column address of the transmitted address ADDR. The decoded column address may be transmitted to the read / write circuit 123. As an example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0059] The voltage generator 122 is configured to generate a plurality of operation voltages Vop using the external power supply voltage supplied to the memory device 100. The voltage generator 122 operates in response to the control of the control logic 130.

[0060] As an example, the voltage generator 122 may generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operation voltage of the memory device 100.

[0061] As an implementation, the voltage generator 122 may generate a plurality of operation voltages Vop using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may be configured to generate various voltages required for the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of dummy program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0062] To generate a plurality of operation voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal voltage and selectively enable the plurality of pumping capacitors in response to the control logic 130 to generate the plurality of operation voltages Vop.

[0063] The plurality of generated operation voltages Vop may be supplied to the memory cell array 110 through the address decoder 121.

[0064] The read / write circuit 123 includes a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm are respectively connected to the memory cell array 110 through a first bit line BL1 to an m-th bit line BLm. The first page buffer PB1 to the m-th page buffer PBm operate in response to the control of the control logic 130.

[0065] The first page buffer PB1 to the m-th page buffer PBm communicate data DATA with the data input / output circuit 124. During programming, the first page buffer PB1 to the m-th page buffer PBm receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0066] During a programming operation, when a program voltage is applied to a selected word line, the first page buffer PB1 to the m-th page buffer PBm may transfer the data DATA to be stored (i.e., the data DATA received through the data input / output circuit 124) to the selected memory cells through the bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transferred data DATA. The memory cells connected to the bit lines to which a program enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a program inhibit voltage (e.g., a power supply voltage) is applied may be maintained. During a program verification operation, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

[0067] During a read operation, the read / write circuit 123 may read the data DATA from the memory cells of a selected page through the bit line BL and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0068] During an erase operation, the read / write circuit 123 may float the bit lines BL. As an implementation, the read / write circuit 123 may include a column selection circuit.

[0069] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm through the data lines DL. The data input / output circuit 124 operates in response to the control of the control logic 130.

[0070] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) for receiving the input data DATA. During a programming operation, the data input / output circuit 124 receives the data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 outputs the data DATA transmitted from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0071] During a read operation or a verify operation, the sense circuit 125 may generate a reference current in response to the signal of the permission bit VRYBIT generated by the control logic 130, and may compare the sense voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.

[0072] The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code. The control logic 130 is connected to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, and the sense circuit 125. The control logic 130 may be configured to control all operations of the memory device 100. The control logic 130 operates in response to a command CMD transmitted from an external device.

[0073] The control logic 130 may generate various signals in response to the command CMD and the address ADDR to control the peripheral circuit 120. For example, the control logic 130 may generate an operation signal OPSIG, an address ADDR, a read / write circuit control signal PBSIGNALS, and a permission bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, output the address ADDR to the address decoder 121, output the read / write control signal to the read / write circuit 123, and output the permission bit VRYBIT to the sense circuit 125. In addition, the control logic 130 may determine whether the verify operation passes or fails in response to the pass signal PASS or the fail signal FAIL output by the sense circuit 125.

[0074] In an embodiment, the control logic 130 may further include a voltage level storage unit 131 and a programming operation controller 132.

[0075] In an embodiment, the voltage level storage unit 131 may store information about the level of the programming verification voltage applied to the selected word line during the programming verification operation of the selected memory cell.

[0076] Specifically, the information about the level of the programming verification voltage may include the level information of the programming verification voltage to be applied to the selected word line according to the corresponding programming cycle. Each of the multiple programming cycles included in the programming operation may include an operation of applying a programming voltage and a programming verification operation of applying a verification voltage.

[0077] The programming operation may execute multiple programming cycles for programming so that the selected memory cell has any one of multiple target programming states. Each of the multiple programming cycles may include a programming voltage application step of applying a programming voltage and a verification step of determining whether the memory cell is programmed by applying a verification voltage.

[0078] In an embodiment, according to the verification voltage level stored in the voltage level storage unit 131, for each programming cycle, the verification voltage applied to the word line selected in the programming verification operation included in each programming cycle may be different. As an embodiment, the verification voltage level stored in the voltage level storage unit 131 may be different according to the number of programmed states verified in each programming cycle included in the programming operation. The content of the voltage level storage unit 131 will be described in detail later.

[0079] In an embodiment, the programming operation controller 132 may control the peripheral circuit 120 to perform a programming operation and a programming verification operation on multiple memory cells based on the information Vfy_inf about the level of the programming verification voltage received from the voltage level storage unit 131.

[0080] In an embodiment, the control logic 130 may include a counter (not shown), and the counter counts the number of times the verification voltage corresponding to the target programming state of the multiple memory cells is applied to the selected word line as the multiple programming cycles proceed. According to the magnitude of the value of the counter, the voltage level storage unit 131 may include the information Vfy_inf about the level of the verification voltage.

[0081] In an embodiment, during the programming verification operation, the programming operation controller 132 may control the peripheral circuit 120 to apply different verification voltages to the selected word line for each programming cycle included in the programming operation of the selected memory cell. At this time, the different verification voltages applied to the selected word line may be determined based on the information Vfy_inf about the level of the verification voltage received from the voltage level storage unit 131.

[0082] In an embodiment, during a program verify operation included in a corresponding program cycle, the program operation controller 132 may control the peripheral circuit 120 to increase and apply a verify voltage corresponding to a target program state of each memory cell as the program cycle progresses. In an embodiment, for some of the verify voltages corresponding to the target program states of the respective memory cells, the program operation controller 132 may control the peripheral circuit 120 to apply the same verify voltage as the verify voltage applied to the selected word line during the program verify operation included in the previously executed program cycle. In an embodiment, for some of the verify voltages corresponding to the target program states during the program verify operation, the program operation controller 132 may control the peripheral circuit 120 to apply a verify voltage of a negative voltage and a verify voltage of a positive voltage to the selected memory cell.

[0083] Figure 3 is a diagram showing Figure 2 the memory cell array of.

[0084] Referring to Figure 3 , the first memory block BLK1 to the z-th memory block BLKz are commonly connected to the first bit line BL1 to the m-th bit line BLm. In Figure 3 , for convenience of description, elements included in the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz are shown, and elements included in each of the remaining memory blocks BLK2 to BLKz are omitted. It will be understood that each of the remaining memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

[0085] The memory block BLK1 may include a plurality of cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain select transistor DST, drain dummy memory cells DDMC connected in series, a plurality of memory cells MC1 to MCN (N is a positive integer) connected in series, source dummy memory cells SDMC connected in series, and a source select transistor SST.

[0086] The gate terminals of the drain select transistors DST included in each of the first cell strings CS1_1 to the m-th cell string CS1_m are connected to the drain select line DSL. The gate terminals of the drain dummy memory cells DDMC included in each of the first cell strings CS1_1 to the m-th cell string CS1_m are connected to the drain dummy word line DDWL. The gate terminals of the first memory cells MC1 to the N-th memory cells MCN included in each of the first cell strings CS1_1 to the m-th cell string CS1_m are connected to the first word line WL_1 to the N-th word line WL_N. The gate terminals of the source dummy memory cells SDMC included in each of the first cell strings CS1_1 to the m-th cell string CS1_m are connected to the source dummy word line SDWL, and the gate terminals of the source select transistors SST included in each of the first cell strings CS1_1 to the m-th cell string CS1_m are connected to the source select line SSL.

[0087] For convenience of description, the structure of the cell string is described based on the first cell string CS1_1 among the plurality of cell strings CS1_1 to CS1_m. However, it will be understood that each of the remaining cell strings CS1_2 to CS1_m is configured similarly to the first cell string CS1_1.

[0088] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the drain dummy memory cell DDMC included in the first cell string CS1_1. The first memory cells MC1 to the N-th memory cells MCN are connected in series with each other. The drain dummy memory cell DDMC and the N-th memory cell MCN are connected in series, and the first memory cell MC1 is connected in series to the source dummy memory cell SDMC. The drain terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the source terminal of the source dummy memory cell SDMC included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. As an implementation, the common source line CSL may be commonly connected to the first storage block BLK1 to the z-th storage block BLKz.

[0089] The drain select line DSL, the drain dummy word line DDWL, the first word line WL_1 to the N-th word line WL_N, the source dummy word line SDWL, and the source select line SSL are included in Figure 2In the row line RL. The drain select line DSL, the drain dummy word line DDWL, the first word line WL_1 to the Nth word line WL_N, the source dummy word line SDWL, and the source select line SSL are controlled by the address decoder 121. The common source line CSL is controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm are controlled by the read / write circuit 123.

[0090] Figure 4 is a diagram showing Figure 3 the influence of adjacent bit lines among the first bit line BL1 to the mth bit line BLm included in the memory cell array during a programming operation.

[0091] Figure 4 The first graph 401 of shows the magnitude of Itrip of the target bit line according to the cell current of the adjacent bit lines. Figure 4 The second graph 403 of shows the magnitude of the threshold voltage corresponding to the programming state of the memory cells included in the target bit line according to the cell current of the adjacent bit lines. As the programming cycle progresses, the possibility that the selected memory cells connected to the selected word line are in the programming state may increase. A smaller cell current flows through the bit line to which the memory cells in the programming state are connected compared to the bit line to which the memory cells in the erased state are connected.

[0092] For example, referring to Figure 3 , as the programming cycle progresses, the possibility that the memory cells connected to the bit lines BLm - 2 and BLm adjacent to the target bit line BLm - 1 are in the programming state may increase. Therefore, the cell current flowing through the adjacent bit lines BLm - 2 and BLm may decrease. As the cell current of the adjacent bit lines BLm - 2 and BLm decreases, the cell current of the target bit line BLm - 1 may also decrease.

[0093] Referring to Figure 4 the first graph 401 of, as the cell current flowing through the adjacent bit lines decreases, the Itrip of the target bit line may increase. Referring to the second graph 403, as the cell current flowing through the adjacent bit lines decreases, the threshold voltage corresponding to the programming state of the memory cells included in the target bit line may be affected and increase. Therefore, during the programming verification operation of the selected memory cells, the threshold voltage corresponding to the programming state of the selected memory cells that needs to be constant is affected by the adjacent bit lines BLm - 2 and BLm and increases, resulting in the phenomenon that the programming verification voltage seems to have changed. Therefore, the reliability of the data is reduced.

[0094] Figure 5 is a diagram showing the programming cycle.

[0095] Referring to Figure 5, the programming operation may include multiple programming loops Loop_1 to Loop_n (n is a natural number equal to or greater than 1). The memory device may execute multiple programming loops to program selected memory cells to have multiple target programming states.

[0096] Each of the multiple programming loops may include one of programming voltage application steps PGM_1 to PGM_n and one of verification steps VFY_1 to VFY_n.

[0097] In the programming voltage application step, a programming voltage application operation of applying a programming voltage to a selected word line connected to the selected memory cell may be executed. Each memory cell selected by the programming voltage application operation may be programmed to a target state among multiple states. The target state may be determined according to the data to be programmed into the selected memory cell.

[0098] In the verification step, a programming verification operation of determining whether the selected memory cell is programmed by applying a verification voltage to the selected word line may be executed. The programming verification operation may include a state verification operation corresponding to each of at least one target programming state. The state verification operation may be an operation of applying a verification voltage corresponding to the target programming state to the selected word line to determine whether the selected memory cell is programmed to the target programming state.

[0099] In an embodiment, the programming voltage may be determined according to the incremental step pulse programming (ISPP) method. That is, as the programming loop is repeated, the level of the programming voltage may gradually increase or decrease according to a predetermined voltage increase. The number of applications, voltage level, voltage application time, etc. of the programming voltage used in each programming loop may be determined in various forms according to the control of the memory controller.

[0100] A pass voltage may be applied to unselected word lines (remaining word lines other than the selected word line). In an embodiment, a pass voltage having the same level may be applied to the unselected word lines. In an embodiment, the pass voltage may have different levels according to the position of the word line.

[0101] A ground voltage may be applied as a programming enable voltage to a selected bit line connected to the memory cell to be programmed. A programming inhibit voltage may be applied to unselected bit lines (bit lines connected to memory cells other than the memory cell to be programmed).

[0102] In the programming verification step, the memory device may apply a verification voltage to the selected word line and may apply a verification pass voltage to the unselected word lines. The memory device may sense the voltage or current output through the bit lines respectively connected to the memory cells connected to the selected word line, and determine whether the verification step passes or fails based on the sensing result.

[0103] In the programming voltage application step, the selected memory cell can be programmed to any one of the first to the m-th (m is a natural number equal to or greater than 2) states.

[0104] In the verification step, a state verification operation for at least one target programming state among the first to the m-th states can be performed. For example, when a memory cell to be programmed to the k-th (k is a natural number equal to or greater than 1 and equal to or less than m) state among the selected memory cells is read as a cutoff cell by a verification voltage corresponding to the k-th state, the state verification operation for the k-th state can pass.

[0105] In Figure 5 , when the selected memory cell is a triple-level cell (TLC) storing three data bits, the selected memory cell can be programmed to an erased state and any one of the first to the seventh programming states. The number of data bits stored in the memory cell is not limited to this embodiment.

[0106] When performing the first programming loop Loop_1, after applying the first programming voltage Vpgm1, the first verification voltage PV1 to the seventh verification voltage PV7 are sequentially applied to verify the programming states of multiple memory cells. At this time, the memory cell with the target state being the first programming state can be verified by the first verification voltage PV1, the memory cell with the target state being the second programming state can be verified by the second verification voltage PV2, and the memory cell with the target state being the third programming state can be verified by the third verification voltage PV3. In the same way, the memory cell can be verified by one of the verification voltages PV1 to PV7 corresponding to the target programming state. The number of verification voltages of the memory cell is not limited to this embodiment.

[0107] The memory cells passing the verification through the verification voltages PV1 to PV7 can be determined to have the target state and then can be prohibited from being programmed in the second programming loop Loop_2. A programming prohibition voltage can be applied to the bit line connected to the memory cell prohibited from being programmed. A second programming voltage Vpgm2 with a step voltage Vstep_pgm higher than the first programming voltage Vpgm1 is applied to the word line selected in the second programming loop Loop_2.

[0108] Thereafter, a programming verification operation is performed in the same manner as the programming verification operation of the first programming loop Loop_1. Exemplarily, verification passing indicates that the memory cell is read as a cutoff cell by the corresponding verification voltage.

[0109] As described above, when the memory device programs the TLC, the memory device uses the first verification voltage PV1 to the seventh verification voltage PV7 to verify the memory cells whose respective programming states are set to the target state.

[0110] In another embodiment, since the possibility of a rapid increase in the threshold voltage of a cell in the erased state is low at the start of programming, a blind programming operation can be achieved in which the verification operation using a high-level verification voltage is omitted and the verification operation is performed using a low-level verification voltage. When performing the blind programming operation, since the number of verification operations can be reduced, the programming operation time can be shortened.

[0111] Specifically, the number of times of applying the programming voltage to perform the blind programming operation can be preset. For example, in each programming verification operation included in the first programming cycle Loop_1 and the second programming cycle Loop_2, a first verification voltage PV1 can be applied to verify the programming state of the memory cell. In each programming verification operation included in the third programming cycle Loop_3 and the fourth programming cycle Loop_4, the first verification voltage PV1 and the second verification voltage PV2 can be sequentially applied to verify the programming state of the memory cell. Thereafter, similar to the programming verification operations of the first programming cycle Loop_1 to the fourth programming cycle Loop_4, the programming verification operation can be performed using the verification voltage preset for each programming cycle.

[0112] In various embodiments, when the programming operation is not completed within a preset number of programming cycles, the programming operation may fail. When the programming operation is completed within a preset number of programming cycles, the programming operation may pass. It can be determined whether the programming operation is completed by whether all the programming verification operations of the selected memory cell pass. When all the programming verification operations pass, the next programming cycle may not be executed.

[0113] Figure 6 is a timing diagram showing a programming method according to an embodiment.

[0114] Referring to Figure 6 , shows a programming cycle in which some verification voltages are omitted and verification voltages are applied in the programming verification operations included in multiple programming cycles according to the blind programming method described in Figure 5 . According to an embodiment of the present disclosure, during each programming verification operation included in multiple programming cycles, the magnitude and type of the verification voltage applied to the selected word line can be determined based on the information stored in the voltage level storage unit 131 described in Figure 2 . According to another embodiment, during each programming operation included in multiple programming cycles, the magnitude of the verification voltage applied to the selected word line can be calculated by the programming operation controller 132 described in Figure 2 .

[0115] Specifically, the magnitude of the verification voltage applied to the selected word line during the verification operation can be a magnitude obtained by adding each default verification voltage and a value obtained by multiplying a reference offset value by a count value corresponding to each verification voltage. At this time, the magnitude of the default verification voltage can be the verification voltage when the verification voltage corresponding to the target programming state of the selected memory cell is first applied to the selected word line. The magnitudes of the default verification voltages corresponding to the target programming states of the respective selected memory cells can be predetermined in the voltage level storage unit 131 in advance.

[0116] In an embodiment, for each verification voltage applied to the selected word line, the count value can be different. For example, the count value can correspond to each verification voltage applied to the selected word line in the verification operations included in one programming cycle. Additionally, the count value can be the number of programming states higher than the target programming state corresponding to the corresponding verification voltage among the target programming states of the memory cells verified in the verification operation.

[0117] In an embodiment, the offset value can be the same while multiple programming cycles are being performed. In another embodiment, the offset value can be different according to the target programming state to be verified. Additionally, as the programming cycle progresses, the offset value can be continuously changed.

[0118] Specifically, as multiple programming cycles progress, the offset value can gradually increase. The offset value can be stored in the voltage level storage unit 131. Therefore, as the offset value and the count value change, in each of the multiple programming cycles, the magnitude of the verification voltage corresponding to the target programming state applied to the selected word line can be different.

[0119] For example, referring to Figure 6 , the first programming cycle Loop_1 to the sixth programming cycle Loop_6 can be executed for the programming operation of the selected memory cell. For ease of description, in the programming verification operations included in each of the first programming cycle Loop_1 to the sixth programming cycle Loop_6, the reference offset can be assumed to be 20 mV. At this time, for each target programming state corresponding to the verification voltage to be applied to the selected word line, the reference offset can be different, and for each programming cycle, the reference offset can be different. Additionally, 20 mV is only an example, and the reference offset can have different values.

[0120] When the first programming loop Loop_1 is executed, after the first programming voltage Vpgm for the first programming loop Loop_1 is applied to the selected word line, in order to verify the states of multiple memory cells, the first verification voltage PV1 can be applied. At this time, the memory cells with the target programming state being the first programming state can be verified through the first verification voltage PV1. The magnitude of the first verification voltage PV1 can be -1V. The first verification voltage PV1 applied to the selected word line in the first programming loop Loop_1 is the verification voltage that is first applied to verify the memory cells with the target programming state being the first programming state. Therefore, the default verification voltage for verifying the memory cells with the target programming state being the first programming state can be the first verification voltage PV1 of the first programming loop Loop_1. At this time, since there is no programming state higher than the first programming state corresponding to the first verification voltage PV1, in the verification operation included in the first programming loop Loop_1, the count value corresponding to the first verification voltage PV1 of the first programming loop Loop_1 is 0. After the first verification voltage PV1 is applied to the selected word line, the second programming voltage Vpgm can be applied.

[0121] When the second programming loop Loop_2 is executed, after the first programming voltage Vpgm for the second programming loop Loop_2 is applied to the selected word line, in order to verify the states of the first-programmed memory cells, the second verification voltage PV2 can be applied. The memory cells with the target programming state being the second programming state can be verified through the second verification voltage PV2. The magnitude of the second verification voltage PV2 can be -0.1V. Similar to the first programming loop Loop_1, the second verification voltage PV2 is the voltage that is first applied to the selected word line to verify the memory cells with the target programming state being the second programming state. Therefore, the default verification voltage for verifying the memory cells with the target programming state being the second programming state can be the second verification voltage PV2 of the second programming loop Loop_2. At this time, since there is no programming state higher than the second programming state corresponding to the second verification voltage PV2, in the verification operation included in the second programming loop Loop_2, the count value corresponding to the second verification voltage PV2 of the second programming loop Loop_2 is 0.

[0122] After the second verification voltage PV2 of the second programming loop Loop_2 is applied to the selected word line, the first verification voltage PV1 of the second programming loop Loop_2 for verifying that the target programming state is the first programming state can be applied. At this time, the magnitude of the first verification voltage PV1 can correspond to the value obtained by adding the first verification voltage PV1 (default verification voltage) of the first programming loop Loop_1 to the value obtained by multiplying the count value corresponding to the first verification voltage PV1 by an offset of 20 mV. At this time, since there is a second programming state higher than the first programming state, the count value corresponding to the first verification voltage PV1 of the second programming loop Loop_2 is 1. Therefore, the magnitude of the first verification voltage PV1 of the second programming loop Loop_2 is -0.98 V obtained by adding the default verification voltage -1 V to the value obtained by multiplying the count value 1 by the offset 20 mV. After the first verification voltage PV1 of the second programming loop Loop_2 is applied to the selected word line, the second programming voltage Vpgm of the second programming loop Loop_2 can be applied.

[0123] In an embodiment, the third programming loop Loop_3 to the sixth programming loop Loop_6 can be executed in the same manner as the previously executed first programming loop Loop_1 and second programming loop Loop_2. According to an embodiment, even if the same programming state is verified for each of the first programming loop Loop_1 to the sixth programming loop Loop_6, the magnitude of the verification voltage corresponding to the programming state to be verified can vary.

[0124] In another embodiment, during the verification operations included in each programming loop, as the magnitude of the verification voltage to be applied to the selected word line decreases, the verification voltage can be first applied to the selected word line. Additionally, according to an embodiment, during the verification operations included in one programming loop, some of the verification voltages applied to the selected word line can have a negative voltage level and others can have a positive voltage level.

[0125] Figure 7 is a timing diagram showing a programming method according to an embodiment.

[0126] Referring to Figure 7 , shows a programming loop that omits some verification voltages and applies verification voltages in the programming verification operations included in multiple programming loops according to the blind programming method described in Figure 5 . According to an embodiment of the present disclosure, during each programming verification operation included in multiple programming loops, the magnitude and type of the verification voltage applied to the selected word line can be determined based on the information stored in the voltage level storage unit 131 described in Figure 2 .

[0127] According to an embodiment of the present disclosure, when the first programming loop Loop_1 is executed, after applying the first programming voltage Vpgm_1, in order to verify the states of a plurality of memory cells, the first verification voltage PV1a is applied. In the second programming loop Loop_2, the second programming voltage Vpgm_2 which is a stepped-up voltage Vstep_pgm higher than the first programming voltage Vpgm_1 is applied to the selected word line. Thereafter, the first verification voltage PV1a corresponding to the first programming state may be applied.

[0128] In the third programming loop Loop_3, the third programming voltage Vpgm_3 which is a stepped-up voltage Vstep_pgm higher than the second programming voltage Vpgm_2 may be applied to the selected word line. Thereafter, in order to verify the programming states of a plurality of memory cells, the increased first verification voltage PV1b corresponding to the first programming state and the second verification voltage PV2a corresponding to the second programming state may be applied. At this time, the first verification voltage PV1b corresponding to the first programming state applied in the third programming loop Loop_3 may be a stepped-up voltage Vstep1_vfy higher than the first verification voltage PV1a applied in the first programming loop Loop_1 and the second programming loop Loop_2. The magnitude of the stepped-up voltage Vstep1_vfy may vary according to the voltage level information stored in the voltage level storage unit 131 described with reference to Figure 2 the voltage levels.

[0129] In the fourth programming loop Loop_4, the fourth programming voltage Vpgm_4 which is a stepped-up voltage Vstep_pgm higher than the third programming voltage Vpgm_3 may be applied to the selected word line. Thereafter, in order to verify the programming states of a plurality of memory cells, the increased first verification voltage PV1b corresponding to the first programming state and the second verification voltage PV2a corresponding to the second programming state may be applied.

[0130] In the fifth programming loop Loop5, a fifth programming voltage Vpgm_5 that is a step voltage Vstep_Pgm higher than the fourth programming voltage Vpgm_4 can be applied to the selected word line. Thereafter, in order to verify the programming states of multiple memory cells, a first verification voltage PV1c corresponding to a first programming state and a second verification voltage PV2b corresponding to a second programming state can be applied to the selected word line. Additionally, a third verification voltage PV3a corresponding to a third programming state can be applied to the selected word line. At this time, the magnitude of the first verification voltage PV1c applied in the fifth programming loop Loop_5 can be a step voltage Vstep1_vfy higher than the first verification voltage PV1b applied in the third programming loop Loop_3 and the fourth programming loop Loop_4. Further, the magnitude of the second verification voltage PV2b applied after the first verification voltage PV1c is applied to the selected word line can be a step voltage Vstep1_vfy higher than the second verification voltage PV2a applied in the third programming loop Loop_3 and the fourth programming loop Loop_4. The magnitude of the step voltage Vstep1_vfy can vary according to the voltage level information stored in the voltage level storage unit 131.

[0131] In an embodiment, multiple programming loops Loop_1 to Loop_n can be executed in the same manner as the above-described first programming loop Loop_1 to fifth programming loop Loop_5. At this time, as the multiple programming loops proceed, the number of verification voltages corresponding to the number of target programming states of the memory cells to be verified in the verification operations included in each programming loop can increase. Additionally, when the number of target programming states of the memory cells to be verified in each programming loop increases, the magnitudes of the corresponding verification voltages can increase. The number and magnitudes of the verification voltages included in each programming loop can be determined according to the voltage level information stored in the voltage level storage unit 131.

[0132] For convenience of description, after two of the multiple programming loops Loop_1 to Loop_n are repeated, a verification voltage corresponding to a new target programming state is applied, but this is not limited thereto.

[0133] Figure 8 is a timing diagram showing a programming method according to an embodiment.

[0134] Referring to Figure 8 , shows a programming loop in which some verification voltages are omitted and verification voltages are applied in the programming verification operations included in multiple programming loops according to the blind programming method described in Figure 5 . According to an embodiment of the present disclosure, the magnitude and type of the verification voltage applied to the selected word line can be determined based on the information stored in the voltage level storage unit 131 described in Figure 2 .

[0135] According to an embodiment of the present disclosure, the same first programming loop Loop_1 to second programming loop Loop_2 as those described with reference to Figure 7 can be executed.

[0136] In a third programming loop Loop_3, a third programming voltage Vpgm_3 that is a step voltage Vstep_pgm higher than a second programming voltage Vpgm_2 can be applied to a selected word line. Thereafter, in order to verify the programming states of a plurality of memory cells, an increased first verification voltage PV1b corresponding to a first programming state and a second verification voltage PV2a corresponding to a second programming state can be applied. At this time, the first verification voltage PV1b applied in the third programming loop Loop_3 can be a first step voltage Vstep2_vfy1 higher than the first verification voltage PV1a applied in the first programming loop Loop_1 and the second programming loop Loop_2. The magnitude of the first step voltage Vstep2_vfy1 can be different according to the voltage level information stored in a voltage level storage unit 131 described with reference to Figure 2 the description.

[0137] In a fourth programming loop Loop_4, a fourth programming voltage Vpgm_4 that is a step voltage Vstep_pgm higher than the third programming voltage Vpgm_3 can be applied to the selected word line. Thereafter, in order to verify the programming states of the plurality of memory cells, the first verification voltage PV1b and the second verification voltage PV2a can be applied.

[0138] In a fifth programming loop Loop5, a fifth programming voltage Vpgm_5 that is a step voltage Vstep_Pgm higher than the fourth programming voltage Vpgm_4 can be applied to the selected word line. Thereafter, in order to verify the programming states of the plurality of memory cells, a first verification voltage PV1c corresponding to a first programming state, a second verification voltage PV2b corresponding to a second programming state, and a third verification voltage PV3a corresponding to a third programming state can be applied. At this time, the magnitude of the first verification voltage PV1c corresponding to the first programming state applied in the fifth programming loop Loop_5 can be a second step voltage Vstep2_vfy2 higher than the first verification voltage PV1b applied in the third programming loop Loop_3 and the fourth programming loop Loop_4. At this time, the magnitude of the second step voltage Vstep2_vfy2 can be greater than the first step voltage Vstep2_vfy1. In addition, the magnitude of the second verification voltage PV2b applied after the first verification voltage PV1c is applied to the selected word line can be a step voltage Vstep2_vfy1 higher than the second verification voltage PV2a applied in the third programming loop Loop_3 and the fourth programming loop Loop_4.

[0139] The magnitudes of the step voltages Vstep2_vfy1 and Vstep2_vfy2 may vary according to the voltage level information stored in the voltage level storage unit 131. Additionally, as the multiple programming cycles Loop_1 to Loop_n proceed, the magnitude of the verification voltage corresponding to each target programming state may increase by the step voltage. At this time, for each programming cycle, the magnitude of the step voltage may change. Specifically, in the verification operations included in the programming cycle, whenever the number of target programming states of the memory cells to be verified increases, the magnitude of the verification voltage applied to the selected word line may increase by the step voltage. In the programming operation, as the number of times the verification voltage corresponding to the target programming state is applied to the selected word line increases, the magnitude of the step voltage may increase.

[0140] In an embodiment, the multiple programming cycles Loop_1 to Loop_n may be executed in the same manner as the first programming cycle Loop_1 to the fifth programming cycle Loop_5. During the programming verification operations included in each of the multiple programming cycles Loop_1 to Loop_n, for each target programming state of some of the multiple memory cells, the step voltage may be different. At this time, as the threshold voltage corresponding to the target programming state of the memory cell is higher, the step voltage may have a higher voltage level.

[0141] For ease of description, after two programming cycles among the multiple programming cycles Loop_1 to Loop_n are repeated, a verification voltage corresponding to a new target programming state is applied, but it is not limited thereto.

[0142] Figure 9 is a timing diagram showing a programming method according to an embodiment.

[0143] Referring to Figure 9 , shows a programming cycle in which some verification voltages are omitted and verification voltages are applied in the programming verification operations included in multiple programming cycles according to the blind programming method described in Figure 5 . During each programming verification operation included in the multiple programming cycles, the magnitude and type of the verification voltage applied to the selected word line may be determined based on the information stored in the voltage level storage unit 131 described in Figure 2 .

[0144] According to an embodiment of the present disclosure, during the verification operations included in the corresponding programming cycle among the multiple programming cycles, each verification voltage corresponding to each target programming state applied to the selected word line may be applied. At this time, some of the applied verification voltages may be the same as the verification voltages applied to the selected word line during the verification operations included in the previously executed programming cycle.

[0145] For example, referring to Figure 9, among multiple programming loops Loop_1 to Loop_n, the (L-1)th programming loop Loop_L-1 and the Lth programming loop Loop_L (where L is a natural number greater than 2 and less than n) are shown.

[0146] The (L-1)th programming voltage VpgmL-1 can be applied to the selected word line in the (L-1)th programming loop Loop_L-1. Thereafter, in order to verify the programming states of multiple memory cells, the first verification voltage PV1’ to the fifth verification voltage PV5’ corresponding to the first to fifth programming states can be applied.

[0147] The Lth programming voltage VpgmL can be applied to the selected word line in the Lth programming loop Loop_L that can be executed after the (L-1)th programming loop Loop_L-1. At this time, the Lth programming voltage VpgmL can be a higher step voltage Vstep_pgm than the (L-1)th programming voltage VpgmL-1. In the programming verification operation of the Lth programming loop Loop_L, the verification voltage corresponding to the target programming state not verified in the (L-1)th programming loop Loop_L-1 can be applied. At this time, among the verification operations included in the Lth programming loop, some verification voltages corresponding to multiple programming states can be the same as the verification voltages applied to the selected word line during the verification operation included in the (L-1)th programming loop.

[0148] Specifically, among the verification operations included in the Lth programming loop, the magnitude of the first verification voltage PV1’ corresponding to the first programming state can be the same as the first verification voltage PV1’ applied during the (L-1)th programming verification operation. Similarly, among the verification operations included in the Lth programming loop, the magnitude of the third verification voltage PV3’ corresponding to the third programming state can be the same as the third verification voltage PV3’ applied during the (L-1)th programming verification operation. In addition, in the Lth programming loop Loop_L, the second verification voltage PV2” corresponding to the second programming state can be applied to the selected word line. In addition, the fourth programming verification voltage PV4” to the sixth programming verification voltage PV6” corresponding to the fourth to sixth programming states can be applied. At this time, the second programming verification voltage PV2”, the fourth programming verification voltage PV4”, and the fifth programming verification voltage PV5” can be higher step voltages Vstep3_vfy than the corresponding verification voltages PV2’, PV4’, and PV5’ applied in the (L-1)th programming loop Loop_L-1, respectively.

[0149] In an embodiment, a plurality of programming loops Loop_1 to Loop_n may be executed in the same manner as the above-described (L-1)th programming loop Loop_L-1 and the Lth programming loop Loop_L. At this time, as the plurality of programming loops proceed, the number of verification voltages corresponding to the number of target programming states of the memory cells to be verified in the verification operations included in each programming loop may increase. In addition, when the target programming states of the memory cells to be verified in each programming loop increase, the magnitudes of the verification voltages corresponding thereto may partially increase. The number of verification voltages included in each programming loop, the magnitude of the verification voltage to be applied to the selected word line in each programming loop, and the magnitude of the step voltage Vstep3_vfy may be determined according to the voltage level information stored in the voltage level storage unit 131.

[0150] For convenience of description, even as the programming loop proceeds, the verification voltage corresponding to the first programming state and the verification voltage corresponding to the third programming state are applied at the same magnitude. However, the present disclosure is not limited thereto, and verification voltages corresponding to various programming states may be constantly applied to the selected word line.

[0151] Figure 10 is a timing diagram showing a programming method according to an embodiment.

[0152] Refer to Figure 10 , which shows a programming loop that omits some verification voltages and applies verification voltages in the programming verification operations included in a plurality of programming loops according to the blind programming method described in Figure 5 . During each programming verification operation included in the plurality of programming loops, the magnitude and type of the verification voltage applied to the selected word line may be determined based on the information stored in the voltage level storage unit 131 described in Figure 2 .

[0153] According to an embodiment of the present disclosure, when the first programming loop Loop_1 is executed, after applying the first programming voltage Vpgm_1, in order to verify the programming states of a plurality of memory cells, a first verification voltage PV1a is applied. The first verification voltage PV1a may be a negative voltage. At this time, the memory cells having the target state as the first programming state may be verified by the first verification voltage PV1a. In the second programming loop Loop_2, a second programming voltage Vpgm_2 that is a step voltage Vstep_pgm higher than the first programming voltage Vpgm_1 is applied to the selected word line. Thereafter, the first verification voltage PV1a corresponding to the first programming state is applied.

[0154] In the third programming cycle Loop_3, a third programming voltage Vpgm_3 that is a step voltage Vstep_pgm higher than the second programming voltage Vpgm_2 can be applied to the selected word line. Thereafter, in order to verify the programming states of multiple memory cells, an increased first verification voltage PV1b corresponding to the first programming state and a second verification voltage PV2a corresponding to the second programming state can be applied. At this time, both the first verification voltage PV1b and the second verification voltage PV2a can be negative voltages. Additionally, the first verification voltage PV1b applied in the third programming cycle Loop_3 can be a step voltage Vstep4_vfy higher than the first verification voltage PV1a applied in the first programming cycle Loop_1 and the second programming cycle Loop_2. The magnitude of the step voltage Vstep4_vfy can vary according to the voltage level information stored in the voltage level storage unit 131.

[0155] In the fourth programming cycle Loop_4, a fourth programming voltage Vpgm_4 that is a step voltage Vstep_pgm higher than the third programming voltage Vpgm_3 can be applied to the selected word line. Thereafter, in order to verify the programming states of multiple memory cells, an increased first verification voltage PV1b corresponding to the first programming state and a second verification voltage PV2a corresponding to the second programming state can be applied.

[0156] In the fifth programming cycle Loop5, a fifth programming voltage Vpgm_5 that is a step voltage Vstep_Pgm higher than the fourth programming voltage Vpgm_4 can be applied to the selected word line. Thereafter, in order to verify the programming states of multiple memory cells, first to third verification voltages PV1c, PV2b, and PV3a corresponding to the first and second programming states can be applied, respectively. At this time, the magnitude of the first verification voltage PV1c corresponding to the first programming state applied in the fifth programming cycle Loop_5 can be a step voltage Vstep4_vfy higher than the first verification voltage PV1b applied in the third programming cycle Loop_3 and the fourth programming cycle Loop_4.

[0157] Additionally, the magnitude of the second verification voltage PV2b applied after the first verification voltage PV1c is applied to the selected word line can be a step voltage Vstep4_vfy higher than the second verification voltage PV2a applied in the third programming cycle Loop_3 and the fourth programming cycle Loop_4. At this time, the second verification voltage PV2b can increase from a negative voltage to a positive voltage. The magnitude of the step voltage Vstep4_vfy can vary according to the voltage level information stored in the voltage level storage unit 131 described with reference to Figure 2 The voltage level information in the voltage level storage unit 131 varies.

[0158] In the sixth programming loop Loop_6, a sixth programming voltage Vpgm_6 that is a step voltage Vstep_pgm higher than the fifth programming voltage Vpgm_5 may be applied to the selected word line. Thereafter, in order to verify the programming states of multiple memory cells, an increased first verification voltage PV1c, a second verification voltage PV2b, and a third verification voltage PV3a corresponding to the third programming state may be applied.

[0159] In an embodiment, multiple programming loops Loop_1 to Loop_n may be executed in the same manner as the first programming loop Loop_1 to the sixth programming loop Loop_6 described above. At this time, as the multiple programming loops proceed, the number of verification voltages corresponding to the number of target programming states of the memory cells to be verified in the verification operations included in each programming loop may increase. In addition, when the target programming states of the memory cells to be verified in each programming loop increase, the magnitudes of the corresponding verification voltages may increase. The number and magnitudes of the verification voltages included in each programming loop may be determined according to the voltage level information stored in the voltage level storage unit 131.

[0160] In another embodiment, during the verification operations included in each of the multiple programming loops Loop_Loopn, as the voltage level of the verification voltage increases, the verification voltage applied to the selected word line may be first applied to the selected word line.

[0161] For ease of description, a verification voltage corresponding to a new target programming state is applied after two programming loops among the multiple programming loops Loop_1 to Loop_n are repeated, but this is not limited thereto.

[0162] In addition, as in the programming method described with reference to Figure 8 as the programming loop proceeds, the verification voltages corresponding to the respective programming states may change by different step voltages Vstep4_vfy compared to the verification voltages in the previously executed programming loops. For ease of description, in Figure 9 only the first verification voltage PV1a and the second verification voltage PV2a corresponding to the first programming state and the second programming state are negative voltages, but this is not limited thereto.

[0163] Figure 11 is a flowchart showing the programming voltage application operation and the verification operation included in the programming loop of the Figure 1 memory device according to an embodiment.

[0164] Referring to Figure 11, in step S1101, the memory device may perform a programming voltage application operation on the selected memory cells among the plurality of memory cells. The programming voltage application operation may be an operation of applying a programming voltage to the selected word line to which the selected memory cells are connected. Additionally, the memory device may apply a programming pass voltage to the unselected word lines.

[0165] In step S1103, the memory device may apply some verification voltages corresponding to the target programming states of the selected memory cells among the plurality of memory cells to the selected word line. At this time, the magnitude of the verification voltage applied to the selected word line may be determined according to the voltage level storage unit 131 described with reference to Figure 2

[0166] Figure 12 is a flowchart showing the programming voltage application operation and the verification operation using a changed verification voltage included in the programming cycle of the memory device according to an embodiment. Figure 2

[0167] With reference to Figure 12 , in step S1201, the memory device may perform a programming voltage application operation on the selected memory cells among the plurality of memory cells. The programming voltage application operation may be an operation of applying a programming voltage to the selected word line to which the selected memory cells are connected.

[0168] Operations S1203 to S1209 step - by - step show the verification operations included in the programming cycle. In step S1203, the control logic 130 included in the Figure 2 memory device may check the number of memory cells corresponding to the target programming state of the verification voltage applied to the selected word line during the verification operation in the programming cycle. In step S1205, the control logic 130 may control the voltage generator 122 included in the Figure 2 memory device to generate a changed verification voltage according to the number of target programming states checked in step S1203. In step S1205, the generated changed verification voltage is described in detail with reference to Figure 13

[0169] In step S1207, the control logic 130 may control the address decoder 121 described with reference to Figure 2 to apply the verification voltage generated in step S1205 to the selected word line.

[0170] In step S1209, with reference to Figure 2 ​​​The described sensing circuit 125 may generate a reference current based on a signal from the control logic 130. Additionally, the sensing circuit 125 may output a pass signal or a fail signal to the control logic 130 by comparing the sensed voltage VPB received from the read / write circuit 123 with a reference voltage generated by the reference current.

[0171] Figure 13 is a flowchart showing an operation of generating a changed verification voltage during a programming verification operation according to an embodiment.

[0172] Referring to Figure 13 in the programming verification operations included in each of the multiple programming cycles, according to a signal from the control logic 130, referring to Figure 2 the described voltage generator 122 may generate a changed verification voltage corresponding to each memory cell according to a predetermined reference for each programming cycle.

[0173] In step S1301, referring to Figure 2 the described control logic 130 may set an initial set value to PV1 and count = 0.

[0174] In step S1303, during the verification operation included in the programming cycle, when all verification voltages corresponding to the target programming states of the included memory cells are applied to the selected word line, step S1309 is performed. At this time, as the initial value 0, the count value does not change. Therefore, during the verification operation included in the previously executed programming cycle, the magnitude of the verification voltage is determined to be the same as the magnitude of the verification voltage applied to the selected word line. In step S1303, when all verification voltages corresponding to the target programming states of the memory cells included in the selected word line are not applied, the method proceeds to step S1305.

[0175] In step S1305, in the verification operation included in the previous programming cycle, it is determined whether a verification voltage corresponding to a memory cell having a different programming state that has not been applied to the selected word line is applied. When the verification voltage corresponding to the memory cell having a different programming state is not applied, the method proceeds to step S1309, and at this time, as the initial value 0, the count value does not change. Therefore, during the verification operation included in the previously executed programming cycle, the magnitude of the verification voltage is determined to be the same as the magnitude of the verification voltage applied to the selected word line.

[0176] In step S1305, when a verification voltage corresponding to a memory cell having a different target programming state is applied, the method proceeds to step S1307, the value of N is incremented to N + 1, and the count value is also incremented by 1.

[0177] After step S1307, step S1303 is performed again, and steps S1303 and S1305 are executed in the same manner. After step S1307, since the method is in the same programming loop, the method can proceed from step S1305 to step S1309.

[0178] In step S1309, since the count value increases, the magnitude of the verification voltage to be applied to the selected word line can be increased by count × offset compared to the verification voltage corresponding to the existing target programming state. At this time, the magnitude of the offset can be preset. In addition, the magnitude of the offset can be the same for all programming loops and can have different values for each programming loop. In addition, the offset can be set differently according to the target programming state corresponding to each verification voltage. The control logic 130 can control the peripheral circuit 120 to apply the verification voltage to the selected word line according to the magnitude of the verification voltage determined in step S1307. For convenience, limited examples are described, but the present disclosure is not limited thereto.

[0179] Steps S1301 to S1309 can be repeatedly executed for each programming loop.

[0180] Figure 14 It is a diagram showing the offset according to the count value during the programming verification operation.

[0181] Refer to Figure 14 , a table indicating the magnitude of the offset according to the count value can be stored in the voltage level storage unit 131 described in Figure 2 . The count value can correspond to each verification voltage applied to the selected word line in the verification operations included in the multiple programming loops Loop_1 to Loop_n described in Figure 5 . In addition, the count value can be the number of programming states higher than the target programming state corresponding to the corresponding verification voltage among the target programming states of the multiple memory cells verified in the verification operation.

[0182] In an embodiment, the magnitude of the reference offset can be different according to the count value. For example, when the count value is 1, the reference offset can be 10 mv. When the count value is 2, the reference offset can be 15 mv. As the count value increases, the reference offset can also increase. Therefore, as the programming loop progresses, the magnitude of the verification voltage corresponding to each target programming state can be further increased. In addition, the reference offset according to all count values can be constant. In this case, as the count value increases, the magnitude of the verification voltage corresponding to each target programming state can continuously increase as the programming loop progresses. For convenience of description, the magnitude value of the offset is described as an example, but the embodiments of the present disclosure are not limited thereto.

[0183] Figure 15 It is a diagram showing Figure 2 an embodiment of the memory cell array of

[0184] Refer to Figure 15 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, +Y direction, and +Z direction.

[0185] Figure 16 is a diagram showing Figure 1 an embodiment of the storage controller.

[0186] The storage controller 1000 is connected to a host Host and a memory device. The storage controller 1000 is configured to access the memory device in response to a request from the host Host. For example, the storage controller 1000 is configured to control write operations, read operations, erase operations, and background operations of the memory device. The storage controller 1000 is configured to provide an interface between the memory device and the host Host. The storage controller 1000 is configured to drive firmware for controlling the memory device.

[0187] Refer to Figure 16 , the storage controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller (buffer control circuit) 1050, a memory interface 1060, and a bus 1070.

[0188] The bus 1070 may be configured to provide a channel between components of the storage controller 1000.

[0189] The processor 1010 may control the overall operation of the storage controller 1000 and may perform logical operations. The processor 1010 may communicate with an external host through the host interface 1040 and communicate with the memory device through the memory interface 1060. In addition, the processor 1010 may communicate with the memory buffer 1020 through the buffer controller 1050. The processor 1010 may use the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory to control the operation of the storage device.

[0190] The processor 1010 may execute the function of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may use a mapping table to receive the LBA and convert the LBA into a PBA. According to the mapping unit, the address mapping method of the FTL includes various address mapping methods. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0191] Processor 1010 is configured to randomize data received from host Host. For example, processor 1010 may use a randomization seed to randomize data received from host Host. The randomized data is provided as data to be stored to the memory device and programmed into the memory cell array.

[0192] Processor 1010 may perform randomization and derandomization through driver software or firmware.

[0193] Memory buffer 1020 may be used as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store code and commands executed by processor 1010. Memory buffer 1020 may store data processed by processor 1010. Memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0194] ECC 1030 may perform error correction. ECC 1030 may perform error correction coding (ECC coding) based on data to be written to the memory device through memory interface 1060. The error correction coded data may be transmitted to the memory device through memory interface 1060. ECC 1030 may perform error correction decoding (ECC decoding) on data received from the memory device through memory interface 1060. For example, ECC 1030 may be included in memory interface 1060 as a component of memory interface 1060.

[0195] Host interface 1040 is configured to communicate with an external host under the control of processor 1010. Host interface 1040 may be configured to perform communication using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), High-Speed Peripheral Component Interconnect (High-Speed PCI), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0196] Buffer controller 1050 is configured to control memory buffer 1020 under the control of processor 1010.

[0197] Memory interface 1060 is configured to communicate with the memory device under the control of processor 1010. Memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0198] For example, the storage controller 1000 may not include the memory buffer 1020 and the buffer controller 1050.

[0199] For example, the processor 1010 may use code to control the operation of the storage controller 1000. The processor 1010 may load the code from a non-volatile memory device (e.g., read-only memory) provided inside the storage controller 1000. As another example, the processor 1010 may load the code from a memory device through the memory interface 1060.

[0200] For example, the bus 1070 of the storage controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to send data within the storage controller 1000, and the control bus may be configured to send control information such as commands and addresses within the storage controller 1000. The data bus and the control bus may be separated from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the ECC 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1202, and the memory interface 1060.

[0201] Figure 17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0202] Referring to Figure 17 , the memory card system 2000 includes a storage controller 2100, a memory device 2200, and a connector 2300.

[0203] The storage controller 2100 is connected to the memory device 2200. The storage controller 2100 is configured to access the memory device 2200. For example, the storage controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2200. The storage controller 2100 is configured to provide an interface between the memory device 2200 and the host. The storage controller 2100 is configured to drive firmware for controlling the memory device 2200. The storage controller 2100 may be implemented in the same manner as the storage controller 200 described with reference to Figure 1 .

[0204] For example, the storage controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an ECC.

[0205] The storage controller 2100 can communicate with an external device through the connector 2300. The storage controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the storage controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the above various communication standards.

[0206] For example, the memory device 2200 can be configured to include various types of non-volatile memory, such as Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0207] The storage controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card. For example, the storage controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card such as a PC Card (Personal Computer Memory Card International Association (PCMCIA)), CompactFlash (CF) card, SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), SD card (SD, miniSD, microSD, or SDHC), and Universal Flash Storage (UFS).

[0208] Figure 18 is a block diagram of a Solid State Drive (SSD) system applying a storage device according to an embodiment of the present disclosure.

[0209] Referring to Figure 18 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through the signal connector 3001 and receives power PWR through the power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0210] According to an embodiment of the present disclosure, the SSD controller 3210 can execute referring to Figure 1Functions of the described storage controller 200.

[0211] The SSD controller 3210 can control a plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG can be a signal based on the interface between the host 3100 and the SSD 3200. For example, the signal SIG can be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0212] The auxiliary power supply device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 can receive power PWR from the host 3100 and can be charged with the power. When the power supply from the host 3100 is unstable, the auxiliary power supply device 3230 can provide power to the SSD 3200. For example, the auxiliary power supply device 3230 can be provided in the SSD 3200 or can be provided outside the SSD 3200. For example, the auxiliary power supply device 3230 can be provided on the motherboard and can provide auxiliary power to the SSD 3200.

[0213] The buffer memory 3240 operates as the buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0214] Figure 19 is a block diagram of a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0215] Referring to Figure 19 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0216] The application processor 4100 can drive components, an operating system (OS), user programs, etc. included in the user system 4000. For example, the application processor 4100 can include a controller, an interface, a graphics engine, etc. that control components included in the user system 4000. The application processor 4100 can be provided as a system-on-chip (SoC).

[0217] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 can include volatile random access memories such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM or non-volatile random access memories such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package-on-package (POP) and provided as one semiconductor package.

[0218] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0219] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can send the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented using non-volatile semiconductor memories such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, the storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

[0220] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate in the same manner as the memory device 100 described with reference to Figure 1 The storage module 4400 can operate in the same manner as the storage device 50 described with reference to Figure 1

[0221] ​The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0222] Cross-reference to Related Applications

[0223] This application claims priority to Korean Patent Application No. 10-2020-0087830, filed with the Korean Intellectual Property Office on July 15, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A plurality of memory cells; Peripheral circuitry configured to perform a programming operation including a plurality of programming cycles, wherein each of the plurality of programming cycles includes an operation of sequentially applying at least one verification voltage among a programming voltage and a plurality of verification voltages to a selected word line commonly connected to the plurality of memory cells; And Control logic configured to increase the level of the selected verification voltage based on the number of verification voltages having a level higher than the level of the selected verification voltage among the verification voltages of the operations included in the selected programming cycle among the plurality of programming cycles.

2. The memory device according to claim 1, wherein The control logic is configured to control the peripheral circuitry: During the Nth programming cycle as the selected programming cycle, sequentially apply the programming voltage and the verification voltage to the selected word line, where N is a natural number equal to or greater than 1; and During the (N + 1)th programming cycle among the plurality of programming cycles, sequentially apply the programming voltage and the (N + 1)th cycle verification voltage to the selected word line, the (N + 1)th cycle verification voltage including the selected verification voltage whose level has increased by the level of a step voltage.

3. The memory device according to claim 2, wherein, The level of the step voltage is determined according to an offset value and the number of verification voltages having a level higher than the level of the selected verification voltage.

4. The memory device according to claim 2, wherein, The (N + 1)th cycle verification voltage includes at least one of the Nth cycle verification voltages.

5. The memory device according to claim 2, wherein, The level of the step voltage is determined according to the target programming state corresponding to each of the (N + 1)th cycle verification voltages.

6. The memory device according to claim 5, wherein, As the threshold voltage corresponding to the target programming state of the memory cell increases, the step voltage has a higher voltage level.

7. The memory device according to claim 5, wherein, As the threshold voltage corresponding to the target programming state corresponding to each of the (N + 1)th cycle verification voltages decreases, the step voltage has a higher voltage level.

8. The memory device according to claim 5, wherein, The Nth cycle verification voltage includes at least one verification voltage having a negative level and at least one verification voltage having a positive level.

9. The memory device according to claim 5, wherein, During the verification operation included in the (N + 1)th programming cycle, as the level of the (N + 1)th cycle verification voltage increases, the (N + 1)th cycle verification voltage is first applied to the selected word line.

10. A memory device, the memory device comprising: A memory cell array including a plurality of memory cells connected to a plurality of word lines; Peripheral circuitry configured to perform a programming operation including a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected word line among the plurality of word lines and a verification operation of applying at least one verification voltage among a plurality of verification voltages; And Control logic configured to: Increase the level of the selected verification voltage based on the number of verification voltages having a level higher than the level of the selected verification voltage among at least two verification voltages of the verification operation included in the selected programming cycle among the plurality of programming cycles, and Control the peripheral circuit to perform the programming operation using the selected verification voltage having an increased level.

11. The memory device according to claim 10, wherein, The control logic is configured to: During a verification operation included in the Nth programming cycle among the plurality of programming cycles, apply the at least two verification voltages to the selected word line, and During a verification operation included in the (N + 1)th programming cycle, apply a (N + 1)th cycle verification voltage of the selected verification voltage including a level increased by a step voltage to the selected word line.

12. The memory device according to claim 11, wherein, The level of the step voltage is determined based on an offset value and the number of verification voltages having a level higher than the level of the selected verification voltage.

13. The memory device according to claim 11, wherein, The control logic includes: A counter configured to count the number of times each of the plurality of verification voltages is applied to the selected word line; and A step voltage storage unit configured to store level information of the step voltage corresponding to the value of the counter, and Wherein, the control logic is configured to determine the step voltage according to the level information stored in the step voltage storage unit and the value of the counter during the verification operation included in the (N + 1)th programming cycle.

14. A method of operating a memory device, the memory device performing a programming operation of storing data in a plurality of memory cells, the programming operation including a plurality of programming cycles, each programming cycle including a programming voltage application operation and a verification operation, the method comprising the steps of: Apply a programming voltage to a word line commonly connected to the plurality of memory cells; And During the verification operation, apply a plurality of verification voltages each increased by a step voltage from a plurality of verification voltages applied during the verification operation of the previous programming cycle to the word line; Wherein, each step voltage among the step voltages is determined based on the number of verification voltages having a level higher than the level of the selected verification voltage corresponding to each step voltage among the plurality of verification voltages of the verification operation.

15. The method according to claim 14, wherein, The step of applying the plurality of verification voltages includes the steps of: generating the plurality of verification voltages each increasing the step voltage.

16. The method according to claim 14, wherein The verification voltages include at least one verification voltage having a negative level and at least one verification voltage having a positive level.

17. The method according to claim 14, wherein, Each step voltage among the step voltages is determined based on the number of the verification voltages having the higher level and an offset value.

18. A memory device, the memory device comprising: A plurality of memory cells; A peripheral circuit configured to perform a programming operation of storing data in the plurality of memory cells, wherein the programming operation includes a plurality of programming cycles, each programming cycle including an operation of applying a programming voltage to a selected word line commonly connected to the plurality of memory cells and a verification operation of applying at least one verification voltage among a plurality of verification voltages corresponding to target programming states of the plurality of memory cells; and A control logic configured to: Increase the level of the selected verification voltage based on the number of verification voltages having a level higher than the level of the selected verification voltage among at least two verification voltages included in a selected programming cycle among the plurality of programming cycles, and control the peripheral circuit to perform the programming operation using the selected verification voltage having the increased level, wherein the at least two verification voltages include at least one verification voltage having a negative level and at least one verification voltage having a positive level.

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