Field-effect transistor devices with gate spacer structure

Abstract

This disclosure relates to a field-effect transistor device having a gate spacer structure. A semiconductor device and a method of forming such a semiconductor device are provided. The method according to this disclosure includes: forming a semiconductor element on a substrate, the semiconductor element including a channel region and a source / drain region; forming a dummy gate stack on the channel region of the semiconductor element; depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; and after etching, removing the second spacer layer.

Description

Technical Field

[0001] This disclosure relates to field-effect transistor devices having a gate spacer structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. In the course of IC development, functional density (i.e., the number of interconnect devices per chip region) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, such scaling down also comes with increased complexity in the design and manufacture of the devices that contain these ICs, and similar advancements are needed in device manufacturing to achieve these progresses.

[0003] Gate replacement processes can be used to fabricate multi-gate transistors, such as FinFETs or multi-bridge channel (MBC) transistors. Taking FinFET fabrication as an example, a dummy gate is first formed over the channel region of the fin, and a gate spacer is formed along the sidewalls of the dummy gate. Using the gate spacer and the dummy gate as a mask, the source / drain regions of the fin are recessed before forming epitaxial source / drain features over the source / drain regions. The dummy gate is then removed and replaced with a functional gate. Because the dummy gate defines the functional gate, damage to the dummy gate can translate into defects or inhomogeneities in the functional gate. During the various dry or wet etching processes that produce the replacement gate, the gate spacer acts to protect the top and sidewall contours of the dummy gate. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a semiconductor element on a substrate, the semiconductor element including a channel region and a source / drain region; forming a dummy gate stack on the channel region of the semiconductor element; depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; and after the etching, removing the second spacer layer.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: providing a workpiece including a semiconductor element comprising a channel region and a source / drain region, and a dummy gate stack surrounding the channel region of the semiconductor element; depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer comprises at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; after the etching, removing the second spacer layer; and after removing the second spacer layer, forming a source / drain feature in the source / drain recess.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a dummy gate stack over a semiconductor element; depositing a first spacer layer over the sidewalls of the dummy gate stack; and depositing a second spacer layer over the first spacer layer, wherein depositing the second spacer layer comprises: depositing a silicon sublayer over the first spacer layer using atomic layer deposition (ALD), and depositing a nitrogen-containing sublayer over the silicon sublayer using ALD. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to various aspects of this disclosure.

[0009] Figures 2-15 It is based on various aspects of this disclosure at various manufacturing stages (e.g., with Figure 1 A partial schematic cross-sectional view of the workpiece under the manufacturing stages (as described in the methods).

[0010] Figure 16 and Figure 17 Based on all aspects of this disclosure Figure 7 An enlarged schematic cross-sectional view of a portion of a semiconductor device. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) are used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0013] Furthermore, when using terms such as "approximately," "about," etc., to describe numbers or ranges of numbers, the term is intended to include numbers within a reasonable range (taking into account the variations inherent during manufacturing as understood by those skilled in the art). For example, based on known manufacturing tolerances associated with manufacturing features (having the characteristics associated with the number), a number or range of numbers includes a reasonable range, such as within + / - 10% of the number. For example, a material layer with a thickness of "approximately 5 nm" may comprise a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0014] This disclosure relates to a structure of a multi-gate transistor or a process for forming a multi-gate transistor. Specifically, this disclosure relates to a multi-gate device including a gate spacer having a silicon sublayer and a nitrogen-containing sublayer.

[0015] As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed over more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels surrounded by gates on more than one side (e.g., the gates surround the top and sidewalls of a “fin” of semiconductor material extending from the substrate). MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structure surrounds the channel region, MBC transistors can also be called gate-around transistors (SGTs) or gate-all-around (GAA) transistors.

[0016] Gate replacement processes can be used to fabricate multi-gate devices. Taking FinFET fabrication as an example, a dummy gate is first formed over the channel region of the fin, and a gate spacer is formed along the sidewalls of the dummy gate. Using the gate spacer and the dummy gate as a mask, the source / drain regions of the fin are recessed before forming epitaxial source / drain features over the source / drain regions. The dummy gate is then removed and replaced with a functional gate. During the various dry or wet etching processes that produce the replacement gate, the gate spacer acts to protect the top and sidewall contours of the dummy gate. For example, if the gate spacer does not provide sufficient protection, etching of the source / drain regions may alter the contours of the dummy gate, resulting in height loss or an undesirable triangular top contour. When this occurs, the gate height between gate structures may be uneven, and yield may be affected. Additionally, thickness loss of the gate spacer can also lead to short circuits between the gate structure and the source / drain features.

[0017] This disclosure provides processes and structures for better protection of dummy gates. In some embodiments, after forming fins on a substrate and a dummy gate stack on the fins, a first gate spacer layer and a second gate spacer layer are sequentially deposited along the sidewalls of the dummy gate stack. The first gate spacer layer may be a low-k dielectric layer. The second gate spacer layer includes a silicon sublayer and a nitrogen-containing sublayer. The silicon sublayer may also be referred to as a silicon soak layer and can be formed by atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD). The nitrogen-containing sublayer may include silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride and can be formed by ALD or PEALD. In some embodiments, multiple silicon sublayers and nitrogen-containing sublayers are deposited alternately to form the second gate spacer layer. During an etching process, an etchant may react with the silicon sublayer to produce polymerization byproducts including silicon, carbon, oxygen, or fluorine. The polymerization byproducts may be redeposited on the first spacer layer and provide additional protection to the first spacer layer.

[0018] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor device according to various aspects of this disclosure. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly described in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps may be moved, substituted, or eliminated for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Method 100 will be described below in conjunction with... Figure 2-15 The workpiece 200 is described by a partial cross-sectional view shown. Since a semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor device 200 depending on the context. Furthermore, throughout this disclosure, unless otherwise described, the same reference numerals denote the same features. Note that although combined... Figure 2-15 Method 100 (which illustrates the formation of a FinFET) is described, but this disclosure is not limited thereto. Method 100 and many aspects of this disclosure can be applied to other types of multi-gate devices, such as MBC transistors.

[0019] refer to Figure 1 and Figure 2Method 100 includes block 102, in which a workpiece 200 including fins 210 is received. Workpiece 200 includes a substrate 202. In the depicted embodiment, substrate 202 is a bulk substrate comprising silicon (Si). Alternatively, in some embodiments, substrate 202 includes a bulk substrate (including, for example, silicon) and one or more material layers disposed on the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having various semiconductor layers (e.g., heterostructures) disposed on the bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form fins. The semiconductor layers may include any suitable semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of semiconductor device 200, the semiconductor layers may include the same or different materials, etch rates, component atomic percentages, component weight percentages, thicknesses, and / or configurations. Alternatively or additionally, the body substrate 202 and / or one or more material layers comprise another basic semiconductor, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), and / or cadmium telluride (CdTe); alloy semiconductors, such as silicon germanium (SiGe), silicon carbide phosphide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); other group III-V materials; other group II-V materials; or combinations thereof. Alternatively, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be fabricated using oxygen implantation separation (SIMOX), wafer bonding, and / or other suitable methods.

[0020] like Figure 2As shown, workpiece 200 may include a plurality of fins 210. In some embodiments, the plurality of fins 210 may be formed using one or more photolithography processes and one or more etching processes. In some embodiments, the plurality of fins 210 may be formed using a single patterning process or a multiple patterning process. Examples of multiple patterning processes include: dual patterning photolithography (DPL) processes (e.g., photolithography-etch-photolithography-etching (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric patterning (SIDP) process, other dual patterning processes, or combinations thereof); triple patterning processes (e.g., photolithography-etch-photolithography-etch-photolithography-etching (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof); other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process); or combinations thereof. To form multiple fins 210, a fin-top hard mask layer 208 is deposited on the substrate 202 and then patterned to form a patterned fin-top hard mask layer 208. The patterned fin-top hard mask layer 208 is then applied as an etch mask to etch the substrate 202 (or a stack of semiconductor layers thereon) to form the multiple fins 210. The fin-top hard mask layer 208 can be a single layer or multiple layers. Figure 2 A multilayer fin top hard mask layer 208 is shown, comprising a first fin top layer 204 and a second fin top layer 206. In some embodiments, the first fin top layer 204 may be formed of silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable materials, and the second fin top layer 206 may be formed of silicon oxide or other suitable dielectric materials. The first fin top layer 204 and the second fin top layer 206 may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods. Figure 2 In this configuration, each fin 210 extends longitudinally along the Y direction and rises from the substrate 202 along the Z direction. As a result of the fin formation process, the hard mask layer 208 on top of the fin can be circular.

[0021] refer to Figure 1 and Figure 3Method 100 includes block 104 in which isolation features 212 are formed. To isolate the plurality of fins 210 from each other, isolation features 212 are deposited on workpiece 200 (including on the plurality of fins 210 and the hard mask layer 208 on top of the fins). In some embodiments, isolation features 212 may be a shallow trench isolation (STI) layer formed of a dielectric material, such dielectric material being deposited using flowable chemical vapor deposition (FCVD), spin coating, CVD, or other suitable methods. Such dielectric materials may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In some embodiments, an annealing process or an ultraviolet (UV) curing process may be performed to cure the deposited dielectric material. The deposited dielectric material is planarized using, for example, chemical mechanical polishing (CMP). Then, as... Figure 3 As shown, the planarized dielectric material is etched back to form isolation feature 212, causing fin 210 to rise above isolation feature 212.

[0022] refer to Figure 1 , Figure 4 and Figure 5 Method 100 includes block 106, in which a dummy gate stack 214 is formed over the channel region 210C of the fin 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 214 serves as a placeholder for various processes, and the dummy gate stack 214 is removed and replaced by a functional gate structure (e.g., gate structure 240, which will be further described below). Other processes and configurations are possible. Figure 5 In some embodiments shown, a dummy gate stack 214 is formed on the fin 210, and the fin 210 can be divided into a channel region 210C located below the dummy gate stack 214 and a source / drain region 210SD not located below the dummy gate stack 214. The channel region 210C of the fin 210 is adjacent to the source / drain region 210SD. The channel region 210C is disposed between the two source / drain regions 210SD along the Y direction. Figure 4 and Figure 5As shown, the dummy gate stack 214 may include a dummy dielectric layer 216 and a dummy electrode layer 218. In some embodiments, the dummy dielectric layer 216 may include silicon oxide, and the dummy electrode layer 218 may include polysilicon (poly Si). The dummy dielectric layer 216 may be formed on the fin 210 using chemical vapor deposition (CVD), ALD, oxygen plasma oxidation, thermal oxidation, or other suitable processes. The dummy electrode layer 218 may be deposited on the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. To pattern the dummy dielectric layer 216 and the dummy electrode layer 218 into the dummy gate stack 214, a gate top hard mask layer 224 may be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. In the depicted embodiment, the gate top hard mask layer 224 may be multilayered and may include a silicon nitride layer 220 and a silicon oxide layer 222 situated above the silicon nitride layer 220. In other embodiments, the gate top hard mask layer 224 may include a silicon oxide layer and a silicon nitride layer situated above the silicon oxide layer. The gate top hard mask layer 224 is then patterned to serve as an etch mask to etch the dummy electrode layer 218 and the dummy dielectric layer 216 to form a dummy gate stack 214, as shown. Figure 5 As shown.

[0023] refer to Figure 1 and Figure 6 Method 100 includes block 108, in which a first gate spacer layer 226 is formed. After forming a dummy gate stack 214, the first gate spacer layer 226 is deposited over the dummy gate stack 214 and the source / drain regions 210SD of the fins 210. In some embodiments, the first gate spacer layer may be deposited using ALD, CVD, or other suitable methods. In some embodiments, to reduce parasitic capacitance between the subsequently formed gate structure and adjacent source / drain features, the first gate spacer layer 226 may include a low-k dielectric material. As used herein, a low-k dielectric material refers to a dielectric material with a dielectric constant equal to or lower than that of thermally heated silicon oxide. In some embodiments, according to some examples, the first gate spacer layer 226 may include silicon oxide, porous silicon oxide, silicon carbonitride, fluorinated silicon glass (FSG), carbon-doped silicon oxide, desiccant, aerogel, amorphous fluorinated carbon, parylene, BCB (bisbenzocyclobutene), polyimide, and / or other materials. Then, a dry etching process is used to pull back or etch back the deposited first gate spacer layer 226 to remove the first gate spacer layer 226 on the top-facing surface. After the etch back process, as Figure 6 As shown, the first gate spacer layer 226 is disposed along the sidewall of the fin 210.

[0024] refer to Figure 1 , Figure 7 and Figure 8 Method 100 includes block 110, in which a second gate spacer layer 228 is formed. First, refer to... Figure 7 In some embodiments, the second gate spacer layer 228 is multilayered and includes at least one silicon sublayer and at least one nitrogen-containing layer. Each of the at least one silicon sublayer can be formed by thermal atomic layer deposition (ALD) using a silicon-based precursor. Examples of such silicon-based precursors may include dichlorosilane (DCS), monochlorosilane (MCS), or hexachlorodisilane (HCD). When different silicon-based precursors are used, the process temperature for depositing the silicon sublayer can be different. In the example where DCS is used as the precursor, the deposition temperature of the ALD process can be between about 500°C and about 600°C. In the example where MCS is used as the precursor, the deposition temperature of the ALD process can be between about 350°C and about 450°C. In the example where hexachlorodisilane (HCD) is used as the precursor, the deposition temperature can be between about 540°C and about 640°C. It has been observed that when the deposition temperature of the silicon sublayer is below the aforementioned deposition temperature range, the activation energy for the surface reaction may not be reached, and deposition may not be effective. When the deposition temperature exceeds the aforementioned deposition temperature range, ALD deposition in block 110 may occur too rapidly and become more like CVD, resulting in undesirable trench filling and insufficient space to form at least one nitrogen-containing layer. In some embodiments, the deposition pressure of at least one silicon sublayer may be between about 1 Torr and about 10 Torr. Each of the at least one nitrogen-based sublayer may be formed by thermal atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD). In some embodiments, each of the at least one nitrogen-based sublayer may comprise silicon carbonitride, silicon boron nitride, silicon nitride, silicon oxynitride, or silicon carbonitride. In some alternative embodiments with larger device dimensions, CVD may be used to deposit the second gate spacer layer 228 without the risk of overfilling. The dielectric constant of the silicon sublayer (about 11) and the dielectric constant of the nitrogen-containing sublayer (about 7) are greater than the dielectric constant of the first gate spacer layer 226 (about 3.9 or less than 3.9).

[0025] In some implementations, the thickness of the nitrogen-based sublayer is greater than the thickness of the silicon sublayer. In some examples, the thickness of the silicon sublayer is 0.1 angstroms. To date Between. As will be further described below, the silicon sublayer in the second gate spacer layer 228 protects the sidewalls and contours of the dummy gate stack 214 by reacting with an oxygen-containing etchant / reactant in a subsequent etching process. This reaction can produce polymerization byproducts that can be redeposited on the sidewalls of the first gate spacer layer 226, thereby slowing down the etching of the first gate spacer layer 226. For example, fluorocarbons (e.g., fluoromethane (CH3F)) and oxygen (O2) used during the etching of block 112 can react with the silicon sublayer to produce a silicon-containing polymer comprising silicon (Si), carbon (C), oxygen (O), and fluorine (F). When the silicon sublayer is thicker than At this time, the silicon sublayer may not be satisfactorily removed during the subsequent etching process using phosphoric acid (H3PO4). When the silicon sublayer is thinner than... At that time, the silicon sublayer cannot provide sufficient protection for the first gate spacer layer 226.

[0026] In some embodiments, the second gate spacer layer 228 may include a plurality of alternating silicon sublayers and a plurality of nitrogen-based sublayers. For example, the second gate spacer layer 228 may include a first silicon sublayer on the first gate spacer layer 226, a first nitrogen-based sublayer on the first silicon sublayer, a second silicon sublayer on the first nitrogen-based sublayer, and a second nitrogen-based sublayer on the second silicon sublayer. The order may be reversed. For example, the second gate spacer layer 228 may include a first nitrogen-based sublayer on the first gate spacer layer 226, a first silicon sublayer on the first nitrogen-based sublayer, a second nitrogen-based sublayer on the first silicon sublayer, and a second silicon sublayer on the second nitrogen-based sublayer. Some of these example arrangements... Figure 15 As shown in the figure, it will be described further below. References Figure 8 Then, the deposited second gate spacer layer 228 is etched back to remove the second gate spacer layer 228 on the top-facing surface, leaving the second gate spacer layer 228 disposed along the sidewall of the first gate spacer layer 226.

[0027] exist Figure 16 and Figure 17 Various embodiments are shown in the figure. Figure 7 A magnified view of the dashed area in the image. First, refer to... Figure 16 This illustrates an embodiment where the second gate spacer layer 228 includes a first silicon sublayer 228-1 and a first nitrogen-containing sublayer 228-2. Figure 16 In the illustrated embodiment, the first silicon sublayer 228-1 may include silicon, and the first nitrogen-containing sublayer 228-2 may include silicon carbonitride, boron silicon nitride, silicon nitride, silicon oxynitride, or silicon carbonitride. Figure 16 In some alternative embodiments not explicitly shown, the deposition order of the first silicon sublayer 228-1 and the first nitrogen-containing sublayer 228-2 may be reversed.

[0028] Then refer to Figure 17 , Figure 17 An embodiment is shown where the second gate spacer layer 228 includes a first silicon sublayer 228-1, a first nitrogen-containing sublayer 228-2, a second silicon sublayer 228-3, and a second nitrogen-containing sublayer 228-4. Figure 17 In the illustrated embodiment, the first silicon sublayer 228-1 and the second silicon sublayer 228-3 may include silicon, and the first nitrogen-containing sublayer 228-2 and the second nitrogen-containing sublayer 228-4 may include silicon carbonitride, boron silicon nitride, silicon nitride, silicon oxynitride, or silicon carbonitride. Figure 17 In some alternative embodiments not explicitly shown, the deposition order of the first silicon sublayer 228-1, the first nitrogen-containing sublayer 228-2, the second silicon sublayer 228-3, and the second nitrogen-containing sublayer 228-4 may be reversed. In still other embodiments, additional silicon sublayers and additional nitrogen-containing layers may be deposited alternately, such that the second gate spacer layer 228 may include more than four sublayers.

[0029] refer to Figure 1 and Figure 9 Method 100 includes block 112, in which the source / drain region 210SD of fin 210 is recessed to form a source / drain recess 230. In some embodiments, the source / drain region 210SD is anisotropically etched by dry etching or a suitable etching process to form the source / drain recess 230. For example, the dry etching process can be implemented with oxygen (O2), oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. Figure 9 As shown, after the source / drain recess 230 is formed, the first gate spacer layer 226 and the second gate spacer layer 228 can remain disposed along the sidewalls of the dummy gate stack 214. In some embodiments not explicitly shown, a portion of the second gate spacer layer 228 can be consumed during operation of block 112, and silicon-containing polymerization byproducts generated by the reaction between at least one silicon sublayer and the etching gas of the dry etching process can be redeposited on the first gate spacer layer 226 to protect the first gate spacer layer 226. The redeposition of the silicon-containing polymerization byproducts during operation of block 112 prevents excessive consumption of the first gate spacer layer 226.

[0030] refer to Figure 1 and Figure 10Method 100 includes block 114, in which a second gate spacer layer 228 is removed. In some embodiments, selective wet etching or selective dry etching may be used to remove the second gate spacer layer 228. An example wet etching process may include using a hot phosphoric acid (H3PO4) solution. In this example, the hot phosphoric acid solution is selective for nitrogen-based sublayers and etches the substrate 202, (one or more) silicon sublayers, and the first gate spacer layer 226 at a much slower rate. Because the selective wet etching in block 114 etches the silicon sublayers at a slower rate, the thickness of the silicon sublayers (or each silicon sublayer when multiple silicon sublayers are present) can exceed [a certain value]. Alternatively, the second gate spacer layer 228 may not be completely removed.

[0031] refer to Figure 1 and Figure 11 Method 100 includes block 116, in which a source / drain feature 234 is formed in a source / drain recess 230. The source / drain feature 234 can be epitaxially and selectively formed from the surface of the source / drain recess 230. Suitable epitaxial processes for block 114 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process of block 114 can use a gas precursor that interacts with the composition of the substrate 202 and the fin 210. Figure 11 In some embodiments shown, the overgrowth of the source / drain feature 234 may extend over the sidewalls of the first gate spacer layer 226. Depending on the conductivity type of the FinFET on the semiconductor device 200, the source / drain feature 234 may have different compositions. When the FinFET on the semiconductor device 200 is n-type, the source / drain feature 234 may comprise silicon (Si) and may be doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the FinFET on the semiconductor device 200 is p-type, the source / drain feature 234 may comprise silicon germanium (SiGe) and be doped with a p-type dopant, such as boron (B), boron difluoride (BF2), or gallium (Ga). Although in Figure 11 While not explicitly shown, source / drain feature 234 may include two or more epitaxial layers. For example, each of source / drain features 234 may include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, which are doped with the same type of dopant but at different concentrations to reduce defect density and contact resistance. In one embodiment, when an n-type FinFET is required, source / drain feature 234 may include phosphorus-doped silicon (Si:P), and when a p-type FinFET is required, source / drain feature 234 may include boron-doped silicon germanium (SiGe:B).

[0032] refer to Figure 1 and Figure 12 Method 100 includes block 118, in which a contact etch stop layer (CESL) 236 and a first interlayer dielectric (ILD) layer 238 are deposited. Figure 12 As shown, a CESL 236 is formed prior to the formation of the first ILD layer 238. In some examples, the CESL 236 comprises silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 236 can be formed by an ALD, plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The first ILD layer 238 is then deposited on the CESL 236. In some embodiments, the first ILD layer 238 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials. The first ILD layer 238 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the first ILD layer 238, the workpiece 200 can be annealed to improve the integrity of the first ILD layer 238.

[0033] In some alternative embodiments, the composition and formation of CESL 236 may be similar to the composition and formation of the second gate spacer layer 228. In these alternative embodiments, CESL 236 is multilayer and includes at least one silicon sublayer and at least one nitrogen-containing layer. Each of the at least one silicon sublayer in CESL 236 can be formed by thermal atomic layer deposition (ALD) using a silicon-based precursor. Examples of such silicon-based precursors may include dichlorosilane (DCS), monochlorosilane (MCS), or hexachlorodisilane (HCD). When different silicon-based precursors are used, the process temperature for depositing the silicon sublayers may differ. In the example where DCS is used as the precursor, the deposition temperature of the ALD process can be between about 500°C and about 600°C. In the example where MCS is used as the precursor, the deposition temperature of the ALD process can be between about 350°C and about 450°C. In the example where hexachlorodisilane (HCD) is used as the precursor, the deposition temperature can be between about 540°C and about 640°C. It has been observed that when the deposition temperature of the silicon sublayer is below the aforementioned deposition temperature range, the activation energy for the surface reaction may not be reached, and deposition may not be effective. When the deposition temperature exceeds the aforementioned deposition temperature range, ALD deposition may occur too rapidly and become more like CVD, leaving insufficient space to form the first ILD layer 238. In some embodiments, the deposition pressure for at least one silicon sublayer is between about 1 Torr and about 10 Torr. Each of the at least one nitrogen-based sublayer can be formed by thermal atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD). In some embodiments, each of the at least one nitrogen-based sublayer may comprise silicon carbonitride, silicon boron nitride, silicon nitride, silicon oxynitride, or silicon carbonitride. In instances where CESL 236 is multilayered, the thickness of the nitrogen-based sublayer in CESL 236 is greater than the thickness of the silicon sublayer in CESL 236. When the device has a large size and the risk of CESL 236 limiting the deposition of the first ILD layer 238 is low, CVD can be used to deposit CESL 236.

[0034] In some embodiments, CESL 236 may include a plurality of silicon sublayers and a plurality of nitrogen-based sublayers formed alternately. For example, CESL 236 may include a first silicon sublayer on the source / drain feature 234, a first nitrogen-based sublayer on the first silicon sublayer, a second silicon sublayer on the first nitrogen-based sublayer, and a second nitrogen-based sublayer on the second silicon sublayer. The order may be reversed. For example, CESL 236 may include a first nitrogen-based sublayer on the source / drain feature 234, a first silicon sublayer on the first nitrogen-based sublayer, a second nitrogen-based sublayer on the first silicon sublayer, and a second silicon sublayer on the second nitrogen-based sublayer. After depositing CESL 236 and the first ILD layer 238, a process such as CMP is used to planarize the workpiece 200 to expose the dummy electrode layer 218 and provide a flat top surface.

[0035] refer to Figure 1 and Figure 13 Method 100 includes block 120, in which a dummy gate stack 214 is replaced with a gate structure 240. The operation in block 120 includes removing the dummy gate stack 214 and forming the gate structure 240 to surround the channel region 210C of the fin 210. Reference Figure 13 The dummy gate stack 214 exposed at the end of block 118 is removed from workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 216 and the dummy electrode layer 218 without substantially damaging the first gate spacer layer 226, the first ILD layer 238, and the CESL 236. Removal of the dummy gate stack 214 results in the formation of a gate trench over the channel region 210C. After removal of the dummy gate stack 214, a gate structure 240 is subsequently deposited on workpiece 200 to surround the channel region 210C of fin 210. The gate structure 240 may include a gate dielectric layer 242 on the channel region 210C and a gate electrode layer 244 on the gate dielectric layer 242. Although not explicitly stated in the original text... Figure 13As explicitly shown herein, the gate dielectric layer 242 includes an interface layer and a high-k dielectric layer. As used herein, the high-k dielectric material includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally heated silicon oxide) (~3.9). In some embodiments, the interface layer comprises silicon oxide and may be formed as a result of a pre-cleaning process. Exemplary pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel region 210C to form the interface layer. The high-k dielectric layer is then deposited over the interface layer using ALD, CVD, and / or other suitable methods. In one embodiment, the high-k dielectric layer may include hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming or depositing the gate dielectric layer 242, a gate electrode layer 244 is deposited on top of the gate dielectric layer.

[0036] The gate electrode layer 244 may be a multilayer structure comprising at least one work function layer and a metal filler layer. By way of example, the at least one work function layer may comprise titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filler layer may comprise aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer 244 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. A planarization process (e.g., CMP process) may be performed to remove excess material and provide a flat top surface.

[0037] refer to Figure 1 and Figure 14Method 100 includes block 122, in which a self-aligned cap (SAC) layer 246 is formed over a gate structure 240. After forming the gate structure 240 and planarizing the workpiece 200, the gate structure 240 is selectively recessed to form a self-aligned cap (SAC) recess. A dielectric material for the SAC layer 246 is then deposited over the workpiece 200 (including over the SAC recess) by CVD, PECVD, or a suitable deposition process. The dielectric material for the SAC layer 246 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. Subsequently, a planarization process (e.g., CMP process) may be performed to remove excess dielectric material over the first ILD layer 238, thereby forming the SAC layer 246 in the SAC recess.

[0038] refer to Figure 1 and Figure 15 Method 100 includes block 124, in which a second ILD layer 248 is deposited over a workpiece 200. In some embodiments, the second ILD layer 248 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials. The second ILD layer 248 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the second ILD layer 248, the workpiece 200 may be annealed to improve the integrity of the second ILD layer 248.

[0039] Still referencing Figure 1 and Figure 15Method 100 includes block 126, in which source / drain contacts 250 are formed to couple to source / drain features 234. In the example process, photolithography and etching processes are used to form contact openings through the second ILD layer 248, the first ILD layer 238, and CESL 236. The contact openings expose the source / drain features 234. To reduce contact resistance, a silicide layer 252 can be formed on the source / drain features 234 by depositing a metal precursor layer over the source / drain features 234 and performing an annealing process to induce silicide formation between the metal precursor layer and the source / drain features 234. Suitable metal precursor layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer 252 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After forming the silicide layer 252, a metal filler layer may be deposited into the contact opening. The metal filler layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). A planarization process may be followed to remove excess material, thereby forming the source / drain contact 250. Due to the planarization process, the top surfaces of the source / drain contact 250 and the second ILD layer 248 are coplanar.

[0040] At the end of the operation in box 126, FinFET 260 is formed, as follows. Figure 15 As shown. FinFET 260 includes a fin channel region 210C extending along the Y direction between two source / drain features 234. Gate structure 240 surrounds the channel region 210C. SAC layer 246 is disposed on gate structure 240. First gate spacer layer 226 extends continuously along the sidewall of SAC layer 246. CESL 236 and first ILD layer 238 are disposed on source / drain features 234. CESL 236 extends along first gate spacer layer 226. Second ILD layer 248 is disposed on SAC layer 246, first gate spacer layer 226, CESL 236 and first ILD layer 238. Source / drain contacts 250 extend through second ILD layer 248, first ILD layer 238 and CESL 236 to couple to source / drain features 234 by means of silicide layer 252.

[0041] The process disclosed herein offers advantages. An example process according to this disclosure includes: after forming fins on a substrate and forming a dummy gate stack on the fins, sequentially depositing a first gate spacer layer and a second gate spacer layer along the sidewalls of the dummy gate stack. The first gate spacer layer may be a low-k dielectric layer. The second gate spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer. Each of the at least one silicon sublayer may also be referred to as a silicon immersion layer and may be formed by atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD). Each of the at least one nitrogen-containing sublayer may include silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride and may be formed by ALD or PEALD. Etching at least one nitrogen sublayer with an oxygen-containing etchant can generate polymerization byproducts to provide additional protection to the first spacer layer. With this additional protection, etching of the source / drain regions does not alter the profile of the dummy gate, resulting in a uniform height and profile of the functional gate structure replacing the dummy gate. In addition, by protecting the low-k first spacer layer, the second gate spacer layer of this disclosure also prevents short circuits between the gate structure and the source / drain features.

[0042] This invention provides many different embodiments. In one embodiment, a method is provided. The method includes: forming a semiconductor element on a substrate, the semiconductor element including a channel region and a source / drain region; forming a dummy gate stack on the channel region of the semiconductor element; depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; and after the etching, removing the second spacer layer.

[0043] In some embodiments, the dielectric constant of the first spacer layer is less than the dielectric constant of the at least one silicon sublayer and the dielectric constant of the at least one nitrogen-containing sublayer. In some embodiments, depositing the second spacer layer includes depositing the at least one silicon sublayer using dichlorosilane (DCS) at a deposition temperature between about 500°C and about 600°C. In some instances, depositing the second spacer layer includes depositing the at least one silicon sublayer using monochlorosilane (MCS) at a deposition temperature between about 350°C and about 450°C. In some embodiments, depositing the second spacer layer includes depositing the at least one silicon sublayer using hexachlorodisilazane (HCD) at a deposition temperature between about 540°C and about 640°C. In some instances, etching the source / drain regions of the semiconductor device includes using fluorocarbon compounds and oxygen. In some embodiments, etching the source / drain regions of the semiconductor device produces polymerization byproducts comprising silicon, carbon, oxygen, and fluorine. In some embodiments, removing the second spacer layer includes using a hot phosphoric acid solution.

[0044] In another embodiment, a method is provided. The method includes: providing a workpiece including a semiconductor element (including a channel region and a source / drain region) and a dummy gate stack (surrounding the channel region of the semiconductor element); depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; after the etching, removing the second spacer layer; and after removing the second spacer layer, forming a source / drain feature in the source / drain recess.

[0045] In some embodiments, the thickness of each of the at least one silicon sublayer is approximately to approximately In some embodiments, depositing the second spacer layer includes depositing one of the at least one silicon sublayer directly on the first spacer layer. In some instances, depositing the second spacer layer includes depositing the at least one silicon sublayer using atomic layer deposition (ALD). In some embodiments, depositing the at least one silicon sublayer includes a deposition pressure between about 1 Torr and about 10 Torr. In some embodiments, the at least one nitrogen-containing sublayer includes silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride.

[0046] In another embodiment, a method is provided. The method includes: forming a dummy gate stack over a semiconductor element; depositing a first spacer layer over the sidewalls of the dummy gate stack; and depositing a second spacer layer over the first spacer layer, wherein depositing the second spacer layer includes depositing a silicon sublayer over the first spacer layer using atomic layer deposition (ALD), and depositing a nitrogen-containing sublayer over the silicon sublayer using ALD. In some embodiments, depositing the silicon sublayer includes using dichlorosilane (DCS), and the deposition temperature is between about 500°C and about 600°C. In some embodiments, depositing the silicon sublayer includes using monochlorosilane (MCS), and the deposition temperature is between about 350°C and about 450°C. In some instances, depositing the silicon sublayer includes using hexachlorodisilazane (HCD), and the deposition temperature is between about 540°C and about 640°C. In some embodiments, the nitrogen-containing sublayer includes silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride. In some instances, depositing the second spacer layer further includes: depositing another nitrogen-containing sublayer over the silicon sublayer, and depositing another silicon sublayer over the other nitrogen-containing sublayer. The nitrogen-containing sublayer is deposited on the other silicon sublayer.

[0047] The foregoing outlines features of several embodiments. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0048] Example 1 is a method for forming a semiconductor device, comprising: forming a semiconductor element on a substrate, the semiconductor element including a channel region and a source / drain region; forming a dummy gate stack on the channel region of the semiconductor element; depositing a first spacer layer on the sidewalls of the dummy gate stack; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; and after the etching, removing the second spacer layer.

[0049] Example 2 is the method described in Example 1, wherein the dielectric constant of the first spacer layer is less than the dielectric constant of the at least one silicon sublayer and the dielectric constant of the at least one nitrogen-containing sublayer.

[0050] Example 3 is the method of Example 1, wherein depositing the second spacer layer comprises: depositing the at least one silicon sublayer using dichlorosilane (DCS) at a deposition temperature between about 500°C and about 600°C.

[0051] Example 4 is the method of Example 1, wherein depositing the second spacer layer comprises: depositing the at least one silicon sublayer using monochlorosilane (MCS) at a deposition temperature between about 350°C and about 450°C.

[0052] Example 5 is the method of Example 1, wherein depositing the second spacer layer comprises: depositing the at least one silicon sublayer using hexachlorodisilazane (HCD) at a deposition temperature between about 540°C and about 640°C.

[0053] Example 6 is the method described in Example 1, wherein etching the source / drain regions of the semiconductor element includes using fluorocarbon compounds and oxygen.

[0054] Example 7 is the method of Example 6, wherein etching the source / drain regions of the semiconductor element produces polymerization byproducts comprising silicon, carbon, oxygen, and fluorine.

[0055] Example 8 is the method described in Example 1, wherein removing the second spacer layer includes using a hot phosphoric acid solution.

[0056] Example 9 is a method for forming a semiconductor device, comprising: providing a workpiece including a semiconductor element comprising a channel region and a source / drain region, and a dummy gate stack surrounding the channel region of the semiconductor element; depositing a first spacer layer over the sidewalls of the dummy gate stack; depositing a second spacer layer over the first spacer layer, wherein the second spacer layer comprises at least one silicon sublayer and at least one nitrogen-containing sublayer; after depositing the second spacer layer, etching the source / drain region of the semiconductor element to form a source / drain recess; after the etching, removing the second spacer layer; and after removing the second spacer layer, forming a source / drain feature in the source / drain recess.

[0057] Example 10 is the method described in Example 9, wherein the thickness of each of the at least one silicon sublayer is approximately to approximately between.

[0058] Example 11 is the method of Example 9, wherein depositing the second spacer layer comprises: directly depositing one of the at least one silicon sublayer on the first spacer layer.

[0059] Example 12 is the method of Example 9, wherein depositing the second spacer layer includes: depositing the at least one silicon sublayer using atomic layer deposition (ALD).

[0060] Example 13 is the method of Example 9, wherein depositing the at least one silicon sublayer comprises a deposition pressure between about 1 Torr and about 10 Torr.

[0061] Example 14 is the method described in Example 9, wherein the at least one nitrogen-containing sublayer comprises silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride.

[0062] Example 15 is a method for forming a semiconductor device, comprising: forming a dummy gate stack over a semiconductor element; depositing a first spacer layer over the sidewalls of the dummy gate stack; and depositing a second spacer layer over the first spacer layer, wherein depositing the second spacer layer comprises: depositing a silicon sublayer over the first spacer layer using atomic layer deposition (ALD), and depositing a nitrogen-containing sublayer over the silicon sublayer using ALD.

[0063] Example 16 is the method described in Example 15, wherein depositing the silicon sublayer includes using dichlorosilane (DCS) and the deposition temperature is between about 500°C and about 600°C.

[0064] Example 17 is the method described in Example 15, wherein depositing the silicon sublayer includes using monochlorosilane (MCS) and the deposition temperature is between about 350°C and about 450°C.

[0065] Example 18 is the method described in Example 15, wherein depositing the silicon sublayer includes using hexachlorodisilane (HCD) and the deposition temperature is between about 540°C and about 640°C.

[0066] Example 19 is the method described in Example 15, wherein the nitrogen-containing sublayer comprises silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride.

[0067] Example 20 is the method of Example 15, wherein depositing the second spacer layer further includes: depositing another nitrogen-containing sublayer on the silicon sublayer, and depositing another silicon sublayer on the other nitrogen-containing sublayer, wherein the nitrogen-containing sublayer is deposited on the other silicon sublayer.

Claims

1. A method for forming a semiconductor device, comprising: A semiconductor element is formed on a substrate, the semiconductor element including a channel region and a source / drain region; A dummy gate stack is formed over the channel region of the semiconductor element; A first spacer layer is deposited on the sidewalls of the dummy gate stack; A second spacer layer is deposited on top of the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; After depositing the second spacer layer, the source / drain regions of the semiconductor element are etched to form source / drain recesses; and After the etching, the second spacer layer is removed.

2. The method according to claim 1, wherein, The dielectric constant of the first spacer layer is less than the dielectric constant of the at least one silicon sublayer and the dielectric constant of the at least one nitrogen-containing sublayer.

3. The method according to claim 1, wherein, Depositing the second spacer layer includes: The at least one silicon sublayer is deposited using dichlorosilane (DCS) at a deposition temperature between about 500°C and about 600°C.

4. The method according to claim 1, wherein, Depositing the second spacer layer includes: The at least one silicon sublayer is deposited using monochlorosilane (MCS) at a deposition temperature between about 350°C and about 450°C.

5. The method according to claim 1, wherein, Depositing the second spacer layer includes: The at least one silicon sublayer is deposited using hexachlorodisilane (HCD) at a deposition temperature between about 540°C and about 640°C.

6. The method according to claim 1, wherein, Etching the source / drain regions of the semiconductor element involves using fluorocarbon compounds and oxygen.

7. The method according to claim 6, wherein, Etching the source / drain regions of the semiconductor element produces polymerization byproducts comprising silicon, carbon, oxygen, and fluorine.

8. The method according to claim 1, wherein, Removing the second spacer layer involves using a hot phosphoric acid solution.

9. A method for forming a semiconductor device, comprising: Provide workpieces that include the following: Semiconductor devices, including channel regions and source / drain regions, and A dummy gate stack surrounds the channel region of the semiconductor element; A first spacer layer is deposited on the sidewalls of the dummy gate stack; A second spacer layer is deposited on top of the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer; After depositing the second spacer layer, the source / drain regions of the semiconductor element are etched to form source / drain recesses; After the etching, the second spacer layer is removed; and After removing the second spacer layer, source / drain features are formed in the source / drain recess.

10. The method according to claim 9, wherein, The thickness of each of the at least one silicon sublayer is approximately to approximately between.

11. The method according to claim 9, wherein, Depositing the second spacer layer includes: One of the at least one silicon sublayers is deposited directly on the first spacer layer.

12. The method according to claim 9, wherein, Depositing the second spacer layer includes: At least one silicon sublayer is deposited using atomic layer deposition (ALD).

13. The method according to claim 9, wherein, Depositing the at least one silicon sublayer involves a deposition pressure between about 1 Torr and about 10 Torr.

14. The method according to claim 9, wherein, The at least one nitrogen-containing sublayer includes silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride.

15. A method for forming a semiconductor device, comprising: A dummy gate stack is formed on a semiconductor element, wherein the semiconductor element includes source / drain regions; A first spacer layer is deposited on the sidewalls of the dummy gate stack; Depositing a second spacer layer on top of the first spacer layer, wherein depositing the second spacer layer includes: A silicon sublayer is deposited on the first spacer layer using atomic layer deposition (ALD), and A nitrogen-containing sublayer was deposited on the silicon sublayer using ALD; After depositing the second spacer layer, the source / drain regions of the semiconductor element are etched to form source / drain recesses; and After the etching, the second spacer layer is removed.

16. The method according to claim 15, wherein, Depositing the silicon sublayer includes: Using dichlorosilane (DCS), and The deposition temperature is between approximately 500°C and approximately 600°C.

17. The method according to claim 15, wherein, Depositing the silicon sublayer includes: Using monochlorosilane (MCS), and The deposition temperature is between approximately 350°C and approximately 450°C.

18. The method according to claim 15, wherein, Depositing the silicon sublayer includes: Hexachlorodisilane (HCD) was used, and The deposition temperature is between approximately 540°C and approximately 640°C.

19. The method according to claim 15, wherein, The nitrogen-containing sublayer includes silicon carbonitride, silicon boron nitride, silicon nitride, silicon carbonitride, or silicon oxynitride.

20. The method of claim 15, wherein, Depositing the second spacer layer further includes: Another nitrogen-containing sublayer is deposited on top of the silicon sublayer, and Deposit another silicon sublayer on top of the other nitrogen-containing sublayer. The nitrogen-containing sublayer is deposited on the other silicon sublayer.

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