Integrated circuit structure and method of manufacturing the same

Abstract

This disclosure relates to integrated circuit structures and methods of manufacturing the same. One method includes depositing a dielectric cap on a gate structure. Source / drain contacts are formed adjacent to the gate structure over source / drain regions. The top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited on the dielectric cap, and an interlayer dielectric (ILD) layer is deposited on the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending through the ILD layer and the etch stop layer. Source / drain vias are filled into the via opening.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuit structures and their manufacturing methods. Background Technology

[0002] Technological advancements in IC materials and design have resulted in several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (the number of interconnect devices per chip area) has typically increased, while geometry (the smallest component (or line) that can be produced using manufacturing processes) has decreased. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: depositing a dielectric cap over a gate structure; forming source / drain contacts adjacent to the gate structure over a source / drain region; oxidizing a top of the dielectric cap; after oxidizing the top of the dielectric cap, depositing an etch stop layer over the dielectric cap and depositing an interlayer dielectric (ILD) layer over the etch stop layer; etching the ILD layer and the etch stop layer to form a via opening extending through the ILD layer and the etch stop layer; and filling source / drain vias in the via opening. According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: depositing source / drain contacts over a source / drain region; oxidizing the top of the source / drain contacts to form a metal oxide region in the source / drain contacts; after oxidizing the top of the source / drain contacts, forming an interlayer dielectric (ILD) layer to cover the metal oxide region of the source / drain contacts; forming via openings in the ILD layer to expose the source / drain contacts; and filling source / drain vias in the via openings.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a gate structure; a dielectric cap located on the gate structure and including an oxidized region and an unoxidized region located between the gate structure and the oxidized region; a source / drain contact adjacent to the gate structure; an interlayer dielectric (ILD) layer located on the dielectric cap and the source / drain contact; and a source / drain via in the ILD layer and electrically connected to the source / drain contact. Attached Figure Description

[0005] The various aspects of this disclosure are best understood through the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1-18D Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0007] Figures 19-23B Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown.

[0008] Figures 24-42D Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0009] Figures 43-47B Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatially relevant terms (e.g., "below," "under," "down," "above," "up," etc.) to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0012] As used herein, “approximately,” “about,” “closely,” or “basically” should generally mean within twenty percent, ten percent, or five percent of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “closely,” or “basically” can be inferred unless explicitly stated otherwise.

[0013] Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with spacing, for example, smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0014] After the front-end-of-line (FEOL) process for manufacturing transistors is completed, source / drain contacts are formed over the source / drain regions of the transistor. Then, source / drain vias are formed over the source / drain contacts to electrically connect them to subsequently formed interconnect metal lines. Forming source / drain vias typically involves depositing an interlayer dielectric (ILD) layer over the source / drain contacts, forming via openings extending through the ILD layer using anisotropic etching, and then depositing one or more metal layers in the via openings to serve as source / drain vias. To prevent over-etching of the source / drain contacts during the anisotropic etching process, an additional etch stop layer (also known as an intermediate contact etch stop layer (MCESL)) is formed over the source / drain contacts before forming the ILD layer. The MCESL has a different etch selectivity than the ILD layer, thus slowing down the etching process that forms the via openings and preventing over-etching of the source / drain contacts. To prevent over-etching of the dielectric material near the source / drain contacts during the MCESL etching process, an additional plasma treatment can be performed on the dielectric material before forming the MCESL. This plasma treatment creates an oxide region in the dielectric material, which has a different etching selectivity than the MCESL. Therefore, this oxide region can slow down or even stop the etching process that forms the via openings, thereby preventing over-etching of the dielectric material beneath the oxide region and reducing the risk of leakage current.

[0015] Figures 1-18DPerspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. It should be understood that additional embodiments of the method may be available. Figure 1-18D Additional operations are provided before, during, and after the processes shown, and some of these operations can be replaced or eliminated. The order of these operations / processes can be interchangeable.

[0016] Figure 1 A perspective view of the structure is shown. The structure includes a substrate 12. The substrate 12 may be a semiconductor substrate (also referred to as a wafer in some embodiments), which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. According to some embodiments of this disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon-germanium (SiGe) layer or germanium layer (without silicon) on the bulk silicon substrate. The substrate 12 may be doped with p-type or n-type impurities. Isolation regions 14, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 12. The portion of the substrate 12 located between adjacent isolation regions 14 is referred to as a semiconductor strip 102.

[0017] The isolation region 14 may include an inner oxide liner (not shown). The inner oxide liner may be formed from a thermal oxide formed by thermal oxidation of a surface layer of the substrate 12. The inner oxide liner may also be a deposited silicon oxide layer formed using methods such as atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation region 14 may also include a dielectric material situated on the inner oxide liner, and this dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0018] refer to Figure 2 The isolation region 14 is recessed such that the top portion of the semiconductor strip 102 protrudes above the top surface of the adjacent isolation region 14 to form a protruding fin 104. This etching can be performed using a dry etching process, in which NH3 and NF3 are used as etching gases. Plasma may be generated during this etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the isolation region 14 is performed using a wet etching process. Etching chemicals may include, for example, diluted HF.

[0019] In the exemplary embodiments described above, the fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0020] The material of the protruding fin 104 can also be replaced with a material different from that of the substrate 12. For example, if the protruding fin 104 is used in an n-type transistor, it can be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs). On the other hand, if the protruding fin 104 is used in a p-type transistor, it can be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb).

[0021] refer to Figure 3A and Figure 3B A dummy gate structure 106 is formed on the top surface and sidewalls of the protruding fin 104. Figure 3B It shows the contents Figure 3A A cross-sectional view obtained from the vertical plane of line BB in the diagram. The formation of the dummy gate structure 106 includes sequentially depositing a gate dielectric layer and a dummy gate electrode layer across multiple fins 104, followed by patterning the gate dielectric layer and the dummy gate electrode layer. As a result of this patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 located above the gate dielectric layer 108. The gate dielectric layer 108 can be any acceptable dielectric layer (e.g., silicon oxide, silicon nitride, etc., or combinations thereof) and can be formed using any acceptable process (e.g., thermal oxidation, spin coating, or CVD, etc.). The dummy gate electrode 110 can be any acceptable electrode layer, including, for example, polysilicon, metal, etc., or combinations thereof. The gate electrode layer can be deposited using any acceptable deposition process, such as CVD or plasma-enhanced CVD (PECVD), etc. Each dummy gate structure 106 spans one or more protruding fins 104. The dummy gate structure 106 may have a length direction perpendicular to the length direction of the corresponding protruding fin 104.

[0022] A mask pattern can be formed on the dummy gate electrode layer to assist in patterning. In some embodiments, the hard mask pattern includes a bottom mask 112 on top of the blanket polysilicon layer and a top mask 114 on top of the bottom mask 112. The hard mask pattern is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. In some embodiments, the bottom mask 112 comprises silicon oxide, and the top mask 114 comprises silicon nitride. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode 110, and the blanket gate dielectric layer is patterned into the gate dielectric layer 108.

[0023] Next, as Figure 4 As shown, a gate spacer 116 is formed on the sidewall of the dummy gate structure 106. In some embodiments of the gate spacer formation operation, a spacer material layer is deposited on the substrate 12. The spacer material layer may be a conformal layer that is subsequently etched back to form the gate spacer 116. In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed over the first spacer layer 118. The first spacer layer 118 and the second spacer layer 120 are each made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. By way of example and not limitation, the first spacer layer 118 and the second spacer layer 120 may be formed by sequentially depositing two different dielectric materials over the dummy gate structure 106 using a process such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer layers 118 and 120 to expose portions of fin 104 not covered by dummy gate structure 106 (e.g., in the source / drain regions of fin 104). The portion of spacer layers 118 and 120 directly above the dummy gate structure 106 can be removed by this anisotropic etching process. The portions of spacer layers 118 and 120 on the sidewalls of the dummy gate structure 106 can be retained to form a gate sidewall spacer, which is referred to for simplicity as gate spacer 116. In some embodiments, the first spacer layer 118 is formed of silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed of silicon nitride, which has higher etch resistance than silicon oxide for subsequent etching processes (e.g., etching the source / drain recesses in fin 104). In some embodiments, gate spacer 116 can be used to offset subsequently formed doped regions (e.g., source / drain regions). The gate spacer 116 can be further used to design or modify the source / drain region profile.

[0024] After the gate spacer 116 is formed, a source / drain structure 122 is formed on the source / drain region of the fin 104 that is not covered by the dummy gate structure 106 and the gate spacer 116. Figure 5 The resulting structure is shown. In some embodiments, the formation of the source / drain structure 122 includes recessing the source / drain regions of the fin 104 and then epitaxially growing semiconductor material in the recessed source / drain regions of the fin 104.

[0025] A suitable selective etching process can be used to recess the source / drain regions of the fin 104. This suitable selective etching process etches the semiconductor fin 104 but hardly etches the gate spacer 116 and the top mask 114 of the dummy gate structure 106. For example, recessing the semiconductor fin 104 can be performed by dry chemical etching using a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, or reactive ion etching (RIE), etc., and the etchant gas can be fluorine, chlorine, bromine, or combinations thereof, etc., which etches the semiconductor fin 104 at a faster etch rate than etching the gate spacer 116 and etching the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by wet chemical etching (e.g., ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), or combinations thereof), which etches the semiconductor fin 104 at a faster etch rate than etching the gate spacer 116 and etching the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by a combination of dry chemical etching and wet chemical etching.

[0026] Once a recess is formed in the source / drain region of fin 104, a source / drain epitaxial structure 122 is formed in the source / drain recess in fin 104 using one or more epitaxial processes that provide one or more epitaxial materials on semiconductor fin 104. During the epitaxial growth process, gate spacer 116 confines the one or more epitaxial materials in the source / drain region of fin 104. In some embodiments, the lattice constant of epitaxial structure 122 is different from the lattice constant of semiconductor fin 104, such that strain or stress can be applied through epitaxial structure 122 in the channel region of fin 104 and between epitaxial structures 122 to improve carrier mobility and enhance device performance of semiconductor device. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the components of semiconductor fin 104.

[0027] In some embodiments, the source / drain epitaxial structure 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 may be in-situ doped during the epitaxial process by introducing dopants, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations of the foregoing. If the source / drain epitaxial structure 122 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some exemplary embodiments, the source / drain epitaxial structure 122 in an n-type transistor includes SiP, while the source / drain epitaxial structure 122 in a p-type transistor includes GeSnB and / or SiGeSnB. In embodiments with different device types, a mask (e.g., photoresist) can be formed over the n-type device region while exposing the p-type device region, and a p-type epitaxial structure can be formed on the exposed fin 104 in the p-type device region. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type device region while exposing the n-type device region, and an n-type epitaxial structure can be formed on the exposed fin 104 in the n-type device region. The mask can then be removed.

[0028] Once the source / drain epitaxial structure 122 is formed, an annealing process can be performed to activate the p-type or n-type dopant in the source / drain epitaxial structure 122. This annealing process can be, for example, rapid thermal annealing (RTA), laser annealing, or millisecond thermal annealing (MSA).

[0029] Next, in Figure 6In this process, an interlayer dielectric (ILD) layer 126 is formed on substrate 12. In some embodiments, a contact etch stop layer (CESL) is also formed prior to the formation of the ILD layer 126. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 126. The CESL can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as oxides forming tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer 126 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 126 is formed, the wafer may undergo a high thermal budget process to anneal the ILD layer 126.

[0030] In some examples, after the formation of the ILD layer 126, a planarization process can be performed to remove excess material from the ILD layer 126. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 126 (and CESL, if present) above the dummy gate structure 106. In some embodiments, the CMP process also removes hard mask layers 112, 114 (e.g., Figure 5 (as shown) and exposes the dummy gate electrode 110.

[0031] Next, as Figure 7 As shown, the remaining dummy gate structure 106 is removed (see...). Figure 6 This forms a gate trench GT1 between the respective gate spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate structure 106 at a faster etch rate than etching other materials (e.g., gate spacers 116, CESL, and / or ILD layer 126).

[0032] After that, as Figure 8As shown, alternative gate structures 130 are formed in the gate trench GT1. Gate structures 130 can be the final gate of a FinFET. Each final gate structure can be a high-k / metal gate stack, however other compositions are possible. In some embodiments, each gate structure 130 forms a gate associated with three sides of the channel region provided by the fin 104. In other words, each gate structure 130 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a work function metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 formed over the work function metal layer 134 and filling the remainder of the gate trench GT1. The gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally heated silicon oxide (about 3.9)). The work function metal layer 134 and / or fill metal 136 used in the high-k / metal gate structure 130 may include metal, metal alloy, or metal silicide. The formation of the high-k / metal gate structure 130 may include a variety of deposition processes for forming various gate materials, one or more inner liner layers, and one or more CMP processes for removing excess gate material.

[0033] In some embodiments, the interface layer of the gate dielectric layer 132 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 132 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0034] The work function metal layer 134 may include a work function metal for providing a suitable work function for the high-k / metal gate structure 130. For an n-type FinFET, the work function metal layer 134 may include one or more n-type work function metals (N-metals). The n-type work function metals may, exemplarily, include, but are not limited to, the following: titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 may include one or more p-type work function metals (P-metals). p-type work function metals may include, but are not limited to, the following: titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0035] In some embodiments, the filler metal 136 may include, but is not limited to, the following: tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0036] Then refer to Figure 9 An etch-back process is performed to etch back the gate structure 130 and the gate spacer 116, thereby forming a recess R1 on the etched-back gate structure 130 and the etched-back gate spacer 116. In some embodiments, since the material replacing the gate structure 130 has a different etch selectivity than the gate spacer 116, a first selective etch-back process can be initially performed to etch back the gate structure 130 to reduce the replacement gate structure 130. Then, a second selective etch-back process is performed to reduce the gate spacer 116. As a result, the top surface of the replacement gate structure 130 can be at a different height than the top surface of the gate spacer 116. For example, in... Figure 9 In the illustrated embodiment, the top surface of the replacement gate structure 130 is lower than the top surface of the gate spacer 116. However, in some other embodiments, the top surface of the replacement gate structure 130 may be flush with or higher than the top surface of the gate spacer 116.

[0037] Subsequently, metal caps 138 are formed on top of the plurality of replacement gate structures 130 using a suitable process such as CVD or ALD. In some embodiments, the metal caps 138 are formed on the replacement gate structures 130 in a bottom-up manner. For example, the metal caps 138 are selectively grown on metal surfaces (e.g., work function metal layer 134 and filler metal 136), so that the sidewalls of the gate spacer 116 are substantially without metal caps 138. By way of example and not limitation, the metal caps 138 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. One or more fluorine-based tungsten precursors (e.g., but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6)) may be used to form FFW films or films including FFW by ALD or CVD. In some embodiments, portions of the metal caps 138 may overflow over the gate dielectric layer 132, such that the metal caps 138 may also cover the exposed surface of the gate dielectric layer 132. Since the metal cap 138 is formed in a bottom-up manner, the formation of the metal cap 138 can be simplified, for example, by reducing repeated back etching processes, which are used to remove unwanted metallic material resulting from conformal growth.

[0038] In some embodiments where the metal cap 138 is formed using a bottom-up approach, the growth of the metal cap 138 on the metal surface (i.e., the metal in the gate structure 130) has a different nucleation delay compared to the dielectric surface (i.e., the dielectric in the gate spacer 116). The nucleation delay on the metal surface is shorter than that on the dielectric surface. Therefore, the difference in nucleation delay allows for selective growth on the metal surface. This disclosure utilizes such selectivity in various embodiments to allow metal growth from the gate structure 130 while suppressing metal growth from the gate spacer 116. As a result, the deposition rate of the metal cap 138 on the gate structure 130 is faster than that on the gate spacer 116. In some embodiments, the top surface of the resulting metal cap 138 is lower than the top surface of the etched-back gate spacer 116. However, in some embodiments, the top surface of the metal cap 138 may be flush with or higher than the top surface of the etched-back gate spacer 116.

[0039] Next, as Figure 10As shown, a dielectric capping layer 140 is deposited on substrate 12 until the recess R1 is overfilled. The dielectric capping layer 140 comprises SiN, SiC, SiCN, SiON, SiCON, or a combination thereof, and is formed by a suitable deposition technique, such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), or a combination thereof. A CMP process is then performed to remove the capping layer located outside the recess R1, thereby leaving the portion of the dielectric capping layer 140 located in the recess R1 to serve as a dielectric cap 142. Figure 11 The resulting structure is shown.

[0040] refer to Figure 12 A source / drain contact 144 is formed, extending through the ILD layer 126 (and CESL, if present). By way of example and not limitation, the formation of the source / drain contact 144 includes: performing one or more etching processes to form contact openings extending through the ILD layer 126 to expose the source / drain epitaxial structure 122, depositing one or more metal materials to overfill the contact openings, and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 126 at a faster etch rate than etching the dielectric cap 142 and the gate spacer 116. As a result, this selective etching is performed using the dielectric cap 142 and the gate spacer 116 as an etch mask, such that the contact openings are formed to be self-aligned with the source / drain epitaxial structure 122 (and therefore the source / drain contact 144 is formed to be self-aligned with the source / drain epitaxial structure 122) without using additional photolithography processes. In this case, the dielectric cap 142 that allows the source / drain contacts 144 to be formed in a self-aligned manner can be referred to as a self-aligned contact (SAC) cap 142.

[0041] After the source / drain contact 144 is formed, the dielectric cap 142 is treated in an oxygen-containing environment such that the surface layer of the dielectric cap 142 is oxidized to form an oxidized region 1421 in the dielectric cap 142, leaving the remaining region 1422 of the dielectric cap 142 unoxidized. Figure 13 The resulting structure is shown. This processing operation may include O2 plasma treatment, wherein oxygen-containing gas is introduced into a processing chamber where plasma is generated by the oxygen-containing gas. As an example and not a limitation, [the following is an example / example]. Figure 12The semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to a plasma environment generated by oxygen (O2) gas, or an O2 gas mixed with one or more of the following: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z (Where x, y, and z are greater than zero and not greater than nine) gases, NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas. The plasma etching environment has a pressure of approximately 10 mTorr to approximately 100 mTorr, and the plasma is generated by RF power between approximately 50 watts and approximately 1000 watts.

[0042] As a result of O2 plasma treatment, oxidation occurs on the top surface of the dielectric cap 142, creating an oxidized region 1421. In some embodiments, for the 3nm technology node, the thickness T1 of the oxidized region 1421 is in the range of about 1 angstrom to about 50 angstroms. If the thickness T1 is less than about 1 angstrom, the oxidized region 1421 may be too thin to slow down or even stop subsequent etching processes. Furthermore, in some embodiments, since the oxidized region 1421 of the dielectric cap 142 has a thickness T1 of no more than about 50 angstroms, it can be naturally penetrated without concern about etching stopping (i.e., at...). Figure 19 In this case, there is no need to worry about the etching process being stopped by the oxidized region 1421. For other technology nodes, such as 20nm, 16nm, 10nm, 7nm, and / or 5nm, the thickness T1 can range from about 1nm to about 20nm. As an example and not a limitation, the thickness of the oxidized region 1421 can be controlled by the RF power and / or bias power used in O2 plasma treatment. In some embodiments, the unoxidized region 1422 is thicker than the oxidized region 1421.

[0043] In some embodiments where the dielectric cap 142 is made of SiN, O2 plasma treatment creates oxidized nitride regions (silicon oxynitride (SiO2)) in the dielectric cap 142. x N y ))1421 and an unoxidized nitride region 1422 located below the oxidized nitride region 1421. The oxidized nitride region 1421 can form a identifiable interface with the unoxidized nitride region 1422 because they have different material compositions (e.g., the oxidized nitride region 1421 has a higher percentage of oxygen atoms and / or a higher oxygen-nitrogen ratio than the unoxidized nitride region 1422).

[0044] In some embodiments, the oxidized region 1421 may have an oxygen concentration gradient due to plasma treatment. For example, the percentage of oxygen atoms in the oxidized region 1421 may decrease from the top surface of the dielectric cap 142 along the depth direction. In some embodiments where the dielectric cap 142 is silicon nitride, the oxygen-nitrogen atom ratio in the oxidized region 1421 may decrease from the top surface of the dielectric cap 142 along the depth direction.

[0045] In some embodiments, during O2 plasma treatment, the top portion of the source / drain contact 144 may be unintentionally oxidized to form a metal oxide region 1441 in the source / drain contact 144, leaving the remaining metal region 1442 of the source / drain contact 144 unoxidized. Figure 13 The resulting structure is shown. The metal oxide region 1441 can form a identifiable interface with the unoxidized metal region 1442 because they have different material compositions (e.g., the metal oxide region 1441 has a higher percentage of oxygen atoms and / or a higher oxygen-nitrogen ratio than the unoxidized metal region 1442).

[0046] In some embodiments, the thickness T2 of the metal oxide region 1441 ranges from about 1 angstrom to about 50 angstroms. Due to the material difference between the source / drain contact 144 and the dielectric cap 142, the oxidation of the metal oxide region 1441 and the oxidized region 1421 may have different degrees. For example, the thickness T1 of the oxidized region 1421 may be greater than, substantially equal to, or less than the thickness T2 of the metal oxide region 1441.

[0047] In some embodiments, the metal oxide region 1441 may have an oxygen concentration gradient due to plasma treatment. For example, the percentage of oxygen atoms in the metal oxide region 1441 may decrease from the top surface of the source / drain contact 144 along the depth direction. In some embodiments where the source / drain contact 144 is metal, the oxygen-to-metal atom ratio in the metal oxide region 1441 may decrease from the top surface of the source / drain contact 144 along the depth direction.

[0048] Once the oxidized region 1421 (and the metal oxide region 1441) have been formed, then in Figure 14 Then, an intermediate contact etch stop layer (MCESL) 146 is formed over the source / drain contacts 144 and the dielectric cap 142. The MCESL 146 can be formed by a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or has a junction with the subsequently formed ILD layer (e.g., ...). Figure 15 (As shown) and the oxidized region 1421, different etching selectivity of other suitable materials.

[0049] refer to Figure 15 Another ILD layer 148 is formed on top of the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as: an oxide forming tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials having different etch selectivity than the MCESL 146. In some embodiments, the ILD layer 148 is made of silicon oxide (SiO2). x The ILD layer 148 can be deposited using PECVD or other suitable deposition techniques.

[0050] refer to Figure 16A The ILD layer 148 is patterned using a first etching process (also known as a via etching process) ET1 to form a via opening O1 extending through the ILD layer 148. The etching duration of the via etching process ET1 is controlled to allow penetration through the ILD layer 148, while MCESL 146 serves as an etch stop layer for the etching process ET1. In some embodiments, a photolithography process is performed prior to the via etching process ET1 to define a desired top-view pattern of the via opening O1. For example, the photolithography process may include spin-coating a photoresist layer (such as...) over the ILD layer 148. Figure 15 As shown), a post-exposure baking process is performed, and a photoresist layer is developed to form a patterned mask with a top-view pattern of via openings O1. In some embodiments, patterning the photoresist to form the patterned mask can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0051] In some embodiments, the via etching process ET1 is an anisotropic etching process, such as plasma etching. Taking plasma etching as an example, vias with... Figure 15 The semiconductor substrate 12 of the illustrated structure is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gaseous mixture of a fluorine-containing gas (e.g., C4F8, C5F8, C4F6, CHF3, or similar substances), an inert gas (e.g., argon or helium), and optionally a weak oxidant (e.g., O2 or CO, or similar substances) for a duration sufficient to etch through the ILD layer 148 to form a via opening O1. The plasma generated in a gaseous mixture including C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148. The pressure of the plasma etching environment is between about 10 mTorr and about 100 mTorr, and the plasma is generated by RF power between about 50 watts and 1000 watts.

[0052] In some embodiments, the aforementioned etchant and etching conditions for the via etching process ET1 are selected in such a way that MCESL 146 (e.g., SiN) exhibits better performance than ILD layer 148 (e.g., SiO2). x A slower etching rate. This allows MCESL 146 to act as a detectable etch endpoint, which in turn prevents over-etching and therefore prevents etching of MCESL 146. In other words, the via etching process ET1 is tuned to etch silicon oxide at a faster etch rate than etching silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated from a hydrogen (H2) gas mixture. Therefore, according to some embodiments of this disclosure, the via etching process ET1 is performed using a hydrogen-free gas mixture to suppress the silicon nitride etch rate. In other words, the plasma in the via etching process ET1 is generated in a hydrogen-free (H2) gas mixture. This keeps the etch rate of silicon nitride low in the via etching process ET1, which in turn allows the silicon oxide (i.e., the ILD material) to be etched at a faster etch rate than etching silicon nitride (i.e., MCESL).

[0053] In such Figure 16A In some embodiments shown, the via opening O1 has a tapered sidewall profile due to the anisotropic etching nature. However, in some other embodiments, the etching conditions can be fine-tuned to allow the gate via opening O1 to have a vertical sidewall profile, such as... Figure 16B As shown.

[0054] refer to Figure 17A MCESL 146 is patterned using a second etching process (also known as a via etching process) ET2 to form via openings O2 extending through MCESL 146. The etching duration of the via etching process ET2 is controlled to allow penetration through MCESL 146, while the oxidized region 1421 serves as an etch stop layer for the etching process ET2.

[0055] In some embodiments, etching process ET2 is an anisotropic etching process using etchants and / or etching conditions different from those of via etching process ET1, such as plasma etching (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc.). The etchant and / or etching conditions of etching process ET2 are selected such that the oxidized region 1421 exhibits a slower etching rate than MCESL 146. Thus, the oxidized region 1421 can suppress or slow down over-etching in the dielectric cap layer 140 during etching process ET2. Taking plasma etching as an example, [the process] will have... Figure 16A or Figure 16BThe semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to fluorine-containing gases (e.g., CHF3, CF4, C2F2, C4F6, C6) by RF or microwave power. x H y F z The plasma etching environment is generated for a duration in a mixture of gases including (x, y, z greater than zero and not greater than nine), hydrogen-containing gases (e.g., H2), and inert gases (e.g., argon or helium), sufficient for etching through MCESL 146 but not through the oxidized region 1421. The pressure of the plasma etching environment is between approximately 10 mTorr and approximately 100 mTorr, and the plasma is generated by an RF power between approximately 50 watts and approximately 1000 watts.

[0056] The plasma generated by the hydrogen-containing gaseous mixture can etch silicon nitride at a faster etch rate than etching silicon oxynitride. Therefore, the etching process ET2 using the hydrogen-containing gaseous mixture etches the oxidized region 1421 at a slower etch rate than etching MCESL 146. In this way, the oxidized region 1421 can suppress or slow down over-etching during the etching process ET2. In some embodiments, the etching process ET2 uses a gaseous mixture of CHF3 gas and H2 gas, wherein the flow rate ratio of CHF3 gas to H2 gas is from about 1:1 to about 1:100. In some embodiments, the etching process ET2 uses a gaseous mixture of CF4 gas and H2 gas, wherein the flow rate ratio of CF4 gas to H2 gas is from about 1:1 to about 1:100. Excessively high H2 gas flow rates may cause the etch rate to be too fast when etching through MCESL 146, which in turn may result in non-negligible curved profiles in MCESL 146. Insufficient H2 gas flow rate may result in inadequate etch selectivity between MCESL 146 and the oxidized region 1421. In some embodiments, the metal oxide region 1441 may be removed during etching process ET2, such that the open O2 exposes the unoxidized region 1442 of the source / drain contact 144, as... Figure 17C and Figure 17D As shown. In addition, some oxidized areas 1421 of the dielectric cap 142 are consumed in the etching process ET2, thus exposing the unoxidized areas 1422 of the dielectric cap 142.

[0057] In some embodiments, due to process variations, there may be some misalignment (or overlap error) between the via opening O2 and the source / drain contact 144. Alternatively, in some embodiments, the size (or width) of the via opening O2 may be larger than the size (or width) of the source / drain contact 144. In any case, the via opening O2 exposes some portions of the oxidized region 1421. However, due to the etch selectivity between the MCESL 146 and the oxidized region 1421, the oxidized region 1421 can slow down or even stop the etching process that forms the via opening O2, which in turn prevents over-etching of the dielectric material (e.g., dielectric cap 142) and reduces the risk of leakage current.

[0058] exist Figure 17A and Figure 17C In some embodiments shown, the via opening O2 has a tapered sidewall profile due to the anisotropic etching nature of etching process ET2. However, in some other embodiments, the etching conditions of etching process ET2 and / or the preceding via etching process ET1 can be fine-tuned to allow the via opening O2 to have a vertical sidewall profile, such as... Figure 17B and Figure 17D As shown.

[0059] refer to Figure 18A Then, source / drain vias 150 are formed in via openings O1 and O2 to physically connect and electrically connect to source / drain contacts 144. By way of example and not limitation, the source / drain via 150 is formed by depositing one or more metallic materials to overfill via openings O1 and O2, followed by a CMP process to remove excess (one or more) metallic materials outside via openings O1 and O2. As a result of the CMP process, the source / drain via 150 has a top surface substantially coplanar with the ILD layer 148. The source / drain via 150 may include metallic materials such as copper, aluminum, tungsten, or combinations thereof, and may be formed using PVD, CVD, or ALD. In some embodiments, the source / drain via 150 may also include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148 and / or MCESL 146 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, or tantalum nitride, and may be formed using PVD, CVD, or ALD, etc.

[0060] The source / drain via 150 inherits the geometry of via openings O1 and O2. In other words, the sidewalls of the source / drain via 150 extend linearly through the entire thickness of the ILD layer 148 and the entire thickness of the MCESL 146. More specifically, the source / drain via 150 forms a first linear interface 1501 with the ILD layer 148 and a second linear interface 1502 with the MCESL 146. The second linear interface 1502 extends downward from the first linear interface 1501, and the linear interfaces 1501 and 1502 are aligned with each other.

[0061] exist Figure 18A and Figure 18C In some embodiments shown, the source / drain via 150 has a tapered sidewall profile due to the anisotropic etching nature of etching process ET2. However, in some other embodiments, the etching conditions of etching process ET2 can be fine-tuned to allow the via opening O1 to have a vertical sidewall profile (and therefore the source / drain via 150 to have a vertical sidewall profile), such as... Figure 18B and Figure 18D As shown. Furthermore, in Figure 18C and Figure 18D In the middle, the source / drain via 150 has a stepped bottom surface, wherein the upper step contacts the oxidized region 1421 and the lower step contacts the unoxidized region 1442 of the source / drain contact 144.

[0062] Figures 19-23B Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 100 according to some other embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 19-23B Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated. The order of these operations / processes can be interchanged. In the following embodiments, [the following text appears to be incomplete and requires further context]. Figures 1-18D The same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0063] In formation Figure 15 Following the structure shown, the ILD layer 148 is patterned to form at least one gate contact opening O3, which extends downward through the ILD layer 148, MCESL 146 and dielectric cap 142 to the metal cap 138. Figure 19 The resulting structure is shown. The ILD layer 148 can be patterned using appropriate photolithography and etching techniques.

[0064] Next, as Figure 20As shown, a patterned mask layer M1 is formed on substrate 12 to fill the gate contact opening O3. The patterned mask layer M1 has an opening O4 vertically above the source / drain contact 144. In some embodiments, the patterned mask layer M1 may be a photoresist mask formed by a suitable photolithography process. For example, the photolithography process may include, for example, a photoresist mask formed by a photolithography process such as... Figure 19 A photoresist layer is spin-coated onto the structure shown, followed by a post-exposure baking process and development of the photoresist layer to form a patterned mask layer M1. In some embodiments, patterning the resist to form a patterned mask element can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0065] refer to Figure 21 With the patterned mask layer M1 in place, via etching process ET3 is performed to form via openings O5 extending through ILD layer 148. The etching duration of via etching process ET3 is controlled to remove ILD 148, and via etching process ET3 is stopped at MCESL 146. The process details of via etching process ET3 have been discussed above regarding via etching process ET1, and therefore will not be repeated here for the sake of brevity.

[0066] refer to Figure 22 Etching process ET4 is performed to etch MCESL 146, thereby deepening the via opening O5 down to the portion of the metal oxide region 1441 of the source / drain contact 144 and the oxide region 1421 of the dielectric cap 142 located between the source / drain contact 144 and the patterned mask layer M1. As a result of etching process ET4, the metal oxide region 1441 of the source / drain contact 144 and the oxide region 1421 of the dielectric cap 142 are exposed at the bottom of the deepened via opening O5. The process details of etching process ET4 have been discussed previously regarding etching process ET2, and therefore will not be repeated here for the sake of brevity.

[0067] After the etching process ET4 is completed, the patterned mask layer M1 is removed from the gate contact opening O3 by ashing and / or wet stripping, and then the mating contact (or mating via) 152 is formed to fill the via opening O5 and the gate contact opening O4. Figure 23A and Figure 23B The resulting structure is shown. The material and manufacturing process details for the mating contact 152 are similar to those for the source / drain via 150, and therefore will not be repeated here for the sake of brevity.

[0068] The mating contact 152 inherits the geometry of the via openings O3 and O5. In other words, the sidewalls of the mating contact 152 extend linearly through the entire thickness of the ILD layer 148 and the entire thickness of the MCESL 146. More specifically, the mating contact 152 forms a first linear interface 1521 with the ILD layer 148 and a second linear interface 1522 with the MCESL 146. The second linear interface 1522 extends downward from the first linear interface 1521, and the linear interfaces 1521 and 1522 are aligned with each other.

[0069] In some embodiments, a portion of the metal oxide region 1441 of the source / drain contact 144 (and a portion of the oxidized region 1421 of the dielectric cap 142) is in Figure 22 The etching process ET4 in the process removes it. Thus, as... Figure 23B As shown, the mating contact 152 contacts the oxidized region 1421 and the unoxidized region 1442 of the source / drain contact 144.

[0070] Figures 24-42D Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type GAA FETs) and n-type transistors (e.g., n-type FAA FETs). In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional embodiments of the method may be available. Figures 24-42D Additional operations are provided before, during, and after the processes shown, and some of these operations can be replaced or eliminated. The order of these operations / processes can be interchangeable.

[0071] Figure 24 , Figure 25 , Figure 26 , Figure 27A , Figure 28A , Figure 29A and Figure 30A These are perspective views of some embodiments of an integrated circuit structure 200 during an intermediate stage of manufacturing. Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figures 31-33 , Figure 34A , Figure 35-42D These are some embodiments of the integrated circuit structure 200 during intermediate stages of manufacturing, along the first tangent (e.g., Figure 27A A cross-sectional view of the tangent XX in the channel, the first tangent being along the length of the channel and perpendicular to the top surface of the substrate. Figure 34BThis refers to some embodiments of the integrated circuit structure 200 during intermediate stages of manufacturing, along the second tangent (e.g., Figure 27A A cross-sectional view of the second tangent (YY) in the gate region, which is perpendicular to the length direction of the channel.

[0072] refer to Figure 24 An epitaxial stack 220 is formed on substrate 210. In some embodiments, substrate 210 may include silicon (Si). Alternatively, substrate 210 may include germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof), or other suitable semiconductor materials. In some embodiments, substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, substrate 210 may include a buried dielectric layer such as a buried oxide (BOX) layer, which is formed, for example, by a technique called oxygen implantation separation (SIMOX), wafer bonding, SEG, or other suitable methods.

[0073] The epitaxial stack 220 includes epitaxial layers 222 having a first composition, with epitaxial layers 224 having a second composition interposed in these epitaxial layers 222. The first and second compositions may be different. In some embodiments, the epitaxial layer 222 is SiGe, and the epitaxial layer 224 is silicon (Si). However, other embodiments are possible, including those providing first and second compositions with different oxidation rates and / or etch selectivity. In some embodiments, the epitaxial layer 222 comprises SiGe, and in the case where the epitaxial layer 224 comprises Si, the Si oxidation rate of the epitaxial layer 224 is less than the SiGe oxidation rate of the epitaxial layer 222.

[0074] Epitaxial layer 224, or portions thereof, can form one or more nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to both elongated material portions with circular and substantially circular cross-sections, and beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The use of epitaxial layer 224 to define one or more channels of a device is further discussed below.

[0075] Note that the three epitaxial layers 222 and 224 are as follows: Figure 24The alternating arrangement shown is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 220; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10.

[0076] As described in more detail below, epitaxial layer 224 can be used as one or more channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 222 in the channel region(s) can eventually be removed and used to define the vertical distance between adjacent channel regions(s) of the subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Therefore, epitaxial layer 222 can also be referred to as a sacrificial layer, and epitaxial layer 224 can also be referred to as a channel layer.

[0077] For example, the epitaxial growth of the layers of epitaxial stack 220 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer (e.g., epitaxial layer 224) comprises the same material as the substrate 210. In some embodiments, the epitaxially grown layers 222 and 224 comprise materials different from the substrate 210. As described above, in at least some examples, epitaxial layer 222 comprises an epitaxially grown silicon-germanium (SiGe) layer, and epitaxial layer 224 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 222 or 224 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials of epitaxial layers 222 and 224 can be selected based on providing different oxidation and / or etch selectivity characteristics. In some embodiments, epitaxial layers 222 and 224 are substantially doped (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 18 cm -3 (the concentration of non-intrinsic dopants), where, for example, no intentional doping is performed during the epitaxial growth process.

[0078] refer to Figure 25A plurality of semiconductor fins 230 extending from the substrate 210 are formed. In various embodiments, each fin 230 includes a substrate portion 212 formed from the substrate 210 and portions of each epitaxial layer in the epitaxial stack including epitaxial layers 222 and 224. The fins 230 can be fabricated using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 230 can then be patterned using the remaining spacers or mandrels by etching the initial epitaxial stack 220. This etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0079] exist Figure 24 and Figure 25 In the illustrated embodiment, a hard mask (HM) layer 910 is formed on the epitaxial stack 220 prior to patterning the fin 230. In some embodiments, the HM layer includes an oxide layer 912 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 914 (e.g., a pad nitride layer that may include Si3N4) formed on the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914, and may also act as an etch stop layer for etching the nitride layer 914. In some examples, the HM oxide layer 912 includes thermally grown oxides, oxides deposited by chemical vapor deposition (CVD), and / or oxides deposited by atomic layer deposition (ALD). In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0080] The fins 230 can then be fabricated using appropriate processes including photolithography and etching. The photolithography process may include: forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a patterned mask comprising the photoresist. In some embodiments, patterning the photoresist to form a patterned mask element can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography utilizing light in the EUV region (with wavelengths of, for example, about 1-200 nm). The patterned mask can then be used to protect certain areas of the substrate 210 and the layers formed thereon, while the etching process forms trenches 202 in the unprotected areas, which penetrate the HM layer 910, through the epitaxial stack 220, and into the substrate 210, leaving a plurality of extended fins 230. The trenches 202 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of the method of forming fins on a substrate can also be used, including, for example, defining a fin region (e.g., by means of a mask or isolation region) and epitaxially growing an epitaxial stack 220 in the form of fin 230.

[0081] Next, as Figure 26 As shown, an isolation region 240 is formed between the insertion fins 230. The material and process details of the isolation region 240 are similar to those of the previously discussed isolation region 14, and therefore will not be repeated for the sake of brevity.

[0082] refer to Figure 27A and Figure 27B A dummy gate structure 250 is formed on the substrate 210 and is at least partially disposed on the fin 230. The portion of the fin 230 located below the dummy gate structure 250 may be referred to as a channel region. The dummy gate structure 250 may also define a source / drain (S / D) region of the fin 230, for example, a region of the fin 230 adjacent to the channel region and located on the opposite side of the channel region.

[0083] The dummy gate formation operation first forms a dummy gate dielectric layer 252 over the fin 230. Subsequently, a dummy gate electrode layer 254 and a hard mask are formed over the dummy gate dielectric layer 252. The hard mask may include multiple layers 256 and 258 (e.g., oxide layer 256 and nitride layer 258). The hard mask is then patterned, and subsequently, the dummy gate electrode layer 254 is patterned using the patterned hard mask as an etch mask. In some embodiments, after the dummy gate electrode layer 254 is patterned, the dummy gate dielectric layer 252 is removed from the S / D region of the fin 230. The etching process may include wet etching, dry etching, and / or combinations thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 252 while substantially not etching the fin 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the previously discussed dummy gate dielectric layer 108 and dummy gate electrode layer 110, so they will not be repeated for the sake of brevity.

[0084] After the dummy gate structure 250 is formed, gate spacers 260 are formed on the sidewalls of the dummy gate structure 250. For example, a spacer material layer is deposited on the substrate 210. The spacer material layer may be a conformal layer, which is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structure 250. The spacer material layer 260 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed on the first spacer layer 262 (in Figure 27B (As shown in the diagram). For example, spacer material layer 260 can be formed by depositing a dielectric material on gate structure 250 using a suitable deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of fin 230 not covered by dummy gate structure 250 (e.g., in the source / drain regions of fin 230). The portion of the spacer material layer directly above the dummy gate structure 250 can be completely removed by this anisotropic etching process. The portions of the spacer material layer on the sidewalls of the dummy gate structure 250 can be retained, forming gate sidewall spacers, which are referred to as gate spacers 260 for simplicity. It should be noted that although gate spacers 260 are... Figure 27B The cross-sectional view shows a multi-layered structure, but for simplicity, they are... Figure 27A It is shown as a single-layer structure in the perspective view.

[0085] Next, as Figure 28A and Figure 28B As shown, a recess R2 is formed in the semiconductor fin 230 and between the corresponding dummy gate structures 250 by etching the lateral extension of the semiconductor fin 230 beyond the exposed portion of the gate spacer 260 (e.g., in the source / drain region of the fin 230) using, for example, an anisotropic etching process. This anisotropic etching process uses the dummy gate structures 250 and the gate spacer 260 as etching masks. After this anisotropic etching, the end faces of the epitaxial layer 222 and the channel layer 224 are aligned with the corresponding outermost walls of the gate spacer 260 due to the anisotropic etching. In some embodiments, this anisotropic etching can be performed by dry chemical etching utilizing a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, or an electron cyclotron resonance (ECR) source, and the reactant gas can be, for example, a fluorine-based gas (e.g., SF6, CH2F2, CH3F, or CHF3), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), or a combination of the foregoing.

[0086] Next, in Figure 29A and Figure 29B In this process, the epitaxial layer 222 is recessed laterally or horizontally using a suitable etching technique to form lateral recesses R3, each of which is vertically located between corresponding channel layers 224. This operation can be performed using a selective etching process. By way of example and not limitation, the epitaxial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective etching of the epitaxial layer 222. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture), which etches SiGe at a faster etch rate than etching Si. In some embodiments, selective etching includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 is not significantly etched by the process of the laterally recessed epitaxial layer 222. As a result, the channel layer 224 extends laterally beyond the opposite end face of the epitaxial layer 222.

[0087] exist Figure 30A and Figure 30B In the middle, an internal spacer material layer 270 is formed to fill the spacer material layer 270 formed by the reference above. Figure 29A and Figure 29B The recess R3 discussed is left by the lateral etching of the epitaxial layer 222. The internal spacer material layer 270 can be a low-k dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and can be formed by a suitable deposition method such as ALD. After the deposition of the internal spacer material layer 270, an anisotropic etching process can be performed to trim the deposited internal spacer material 270 so that only the portion of the deposited internal spacer material 270 filling the recess R3 left by the lateral etching of the epitaxial layer 222 is retained. After the trimming process, for simplicity, the remaining portion of the deposited internal spacer material is referred to as the internal spacer 270. The internal spacer 270 is used to isolate the metal gate from the source / drain regions formed in subsequent processes. Figure 30A and Figure 30B In the example, the sidewall of the inner spacer 270 is aligned with the sidewall of the channel layer 224.

[0088] exist Figure 31 In this process, a source / drain epitaxial structure 280 is formed on the source / drain region S / D of the semiconductor fin 230. The source / drain epitaxial structure 280 can be formed by performing an epitaxial growth process that provides epitaxial material on the fin 230. During this epitaxial growth process, a dummy gate structure 250, a gate spacer 260, and an internal spacer 270 confine the source / drain epitaxial structure 280 to the source / drain region S / D. The material and process details of the source / drain epitaxial structure 280 of the GAA FET are similar to those of the previously discussed FinFET source / drain epitaxial structure 122, and therefore will not be repeated for the sake of brevity.

[0089] exist Figure 32 In this configuration, an interlayer dielectric (ILD) layer 310 is formed on the substrate 210. In some embodiments, a contact etch stop layer (CESL) is also formed prior to the formation of the ILD layer 310. The material and process details regarding the CESL and ILD layer 310 are similar to those for CESL 124 and ILD layer 126, and therefore will not be repeated for brevity. In some examples, a planarization process may be performed after depositing the ILD layer 310 to remove excess material from the ILD layer 310. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes the portion of the ILD layer 310 (and the CESL layer, if present) above the dummy gate structure 250 and planarizes the top surface of the integrated circuit structure 200. In some embodiments, the CMP process also removes hard mask layers 256, 258 (e.g., Figure 31 (as shown) and exposes the dummy gate electrode layer 254.

[0090] Subsequently, the dummy gate structure 250 (e.g.) is first removed. Figure 32 As shown), then remove the epitaxial layer (i.e., the sacrificial layer) 222 (as shown). Figure 32 (As shown). Figure 33 The resulting structure is illustrated. In some embodiments, the dummy gate structure 250 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 250 at a faster etch rate than etching other materials (e.g., gate sidewall spacers 260 and / or ILD layer 310), thereby forming a gate trench GT2 between the respective gate sidewall spacers 260, and exposing the epitaxial layer 222 in the gate trench GT2. Subsequently, the epitaxial layer 222 in the gate trench GT2 is removed using another selective etching process that etches the epitaxial layer 222 at a faster etch rate than etching the channel layer 224, thereby forming an opening O6 between adjacent epitaxial layers (i.e., channel layers) 224. In this way, the epitaxial layer 224 becomes a nanosheet suspended above the substrate 210 and located between the source / drain epitaxial structures 280. This operation is also referred to as a channel release process. In this intermediate processing operation, the openings O6 between the epitaxial layers (i.e., nanosheets) 224 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the epitaxial layers 224 can be interchangeably referred to as nanowires, nanoplates, and nanorings depending on their geometry. For example, in some other embodiments, the channel layer 224 can be trimmed into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the epitaxial layer 222. In this case, the resulting epitaxial layer 224 can be referred to as a nanowire.

[0091] In some embodiments, epitaxial layer 222 is removed using a selective wet etching process. In some embodiments, epitaxial layer 222 is SiGe and epitaxial layer 224 is silicon, thereby allowing selective removal of epitaxial layer 222. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 may not be significantly etched by the channel release process. It can be noted that the channel release operation and the previous lateral recess sacrificial layer operation (such as...) Figure 29A and Figure 29BBoth operations (as shown) use a selective etching process to etch SiGe at a faster etch rate than Si, so in some embodiments, the two operations can use the same etchant chemistry. In this case, the etch time / duration of the channel release operation is longer than that of the previous lateral recess sacrificial layer operation in order to completely remove the sacrificial SiGe layer.

[0092] exist Figure 34A and Figure 34B In this configuration, replacement gate structures 320 are respectively formed in the gate trench GT2 to surround each epitaxial layer 224 suspended in the gate trench GT2. The gate structure 320 may be the final gate of a GAA FET. The final gate structure may be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each gate structure 320 forms a gate associated with a multi-channel provided by the plurality of epitaxial layers 224. For example, the high-k / metal gate structure 320 is formed in an opening O6 provided by releasing the epitaxial layers 224 (e.g., ...). Figure 34A (As shown). In various embodiments, the high-k / metal gate structure 320 includes: a gate dielectric layer 322 formed around an epitaxial layer 224, a work function metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 and filling the remaining portion of the gate trench GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally heated silicon oxide (about 3.9)). The work function metal layer 324 and / or the fill metal layer 326 used within the high-k / metal gate structure 320 may include a metal, a metal alloy, or a metal silicide. The formation of the high-k / metal gate structure 320 may include deposition for forming various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material. As shown in the figure taken along the longitudinal axis of the high-k / metal gate structure 320 Figure 34B As shown in the cross-sectional view, the high-k / metal gate structure 320 surrounds each epitaxial layer 224 and is therefore referred to as the gate of the GAA FET. The material and process details of the GAA FET gate structure 320 are similar to those of the FinFET gate structure 130, and therefore will not be repeated for the sake of brevity.

[0093] exist Figure 35In this process, an etch-back process is performed to replace the gate structure 320 and the gate spacer 260, thereby forming a recess on the etch-back gate structure 320 and the etch-back gate spacer 260. In some embodiments, because the material replacing the gate structure 320 has a different etch selectivity than the gate spacer 260, the top surface of the replacing gate structure 320 can be at a different height than the top surface of the gate spacer 260. For example, in... Figure 35 In the illustrated embodiment, the top surface of the replacement gate structure 320 is lower than the top surface of the gate spacer 260. However, in some other embodiments, the top surface of the replacement gate structure 320 may be flush with or higher than the top surface of the gate spacer 260.

[0094] Then, a metal cap 330 is formed on top of the replacement gate structure 320 using a suitable process such as CVD or ALD. By way of example and not limitation, the metal cap 330 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. Process details regarding the formation of the FFW have been previously discussed with respect to the metal cap 138, and will therefore be repeated for the sake of brevity.

[0095] exist Figure 36 In this configuration, a dielectric cap 340 is formed over the metal cap 330 and the gate spacer 260. Because the top surface of the metal cap 330 is lower than the top surface of the gate spacer 260, each dielectric cap 340 has a stepped bottom surface, with the lower step contacting the top surface of the metal cap 330 and the upper step contacting the top surface of the gate spacer 260. The material and process details of the dielectric caps are similar to those of the previously discussed dielectric cap 142, and therefore will not be repeated for the sake of brevity.

[0096] exist Figure 37In this process, source / drain contacts 350 extending through the ILD layer 310 are formed. By way of example and not limitation, the formation of the source / drain contacts 350 includes: performing one or more etching processes to form contact openings extending through the ILD layer 310 (and CESL, if present) to expose the source / drain epitaxial structure 280; depositing one or more metal materials to overfill the contact openings; and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 310 at a faster etch rate than etching the dielectric cap 340 and the gate spacer 260. As a result, this selective etching is performed using the dielectric cap 340 and the gate spacer 260 as etch masks, such that the contact openings, and therefore the source / drain contacts 350, are formed to be self-aligned with the source / drain epitaxial structure 280 without the use of additional photolithography processes. In this case, the dielectric cap 340 that allows the formation of self-aligned contacts 350 can be referred to as the SAC cap 340.

[0097] After the source / drain contact 350 is formed, the dielectric cap 340 is treated in an oxygen-containing environment so that the surface layer of the dielectric cap 340 is oxidized to form an oxidized region 341 in the dielectric cap 340, leaving the remaining region 342 of the dielectric cap 340 unoxidized. Figure 38 The resulting structure is shown. This processing operation may include O2 plasma treatment, wherein oxygen-containing gas is introduced into a processing chamber where plasma is generated by the oxygen-containing gas. As an example and not a limitation, [the following is an example / example]. Figure 36 The semiconductor substrate 210 with the structure shown is loaded into a plasma tool and exposed to a plasma environment generated by oxygen (O2) gas, or an O2 gas mixed with one or more of the following: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z (Where x, y, and z are greater than zero and not greater than nine) gases, NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas. The plasma etching environment has a pressure of approximately 10 mTorr to approximately 100 mTorr, and the plasma is generated by RF power between approximately 50 watts and approximately 1000 watts.

[0098] As a result of O2 plasma treatment, oxidation occurs on the top surface of the dielectric cap 340, creating an oxidized region 341. In some embodiments, for the 3nm technology node, the thickness T3 of the oxidized region 341 is in the range of about 1 angstrom to about 50 angstroms. If the thickness T3 is less than about 1 angstrom, the oxidized region 341 may be too thin to slow down or even stop subsequent etching processes. Furthermore, in some embodiments, since the oxidized region 341 of the dielectric cap 340 has a thickness T3 of no more than about 50 angstroms, it can be naturally penetrated without concern about etching stopping (i.e., in...). Figure 43 In this case, there is no need to worry about the etching process being stopped by the oxidized region 341. For other technology nodes, such as 20nm, 16nm, 10nm, 7nm and / or 5nm, the thickness T3 can range from about 1nm to about 20nm. As an example and not a limitation, the thickness of the oxidized region 341 can be controlled by the RF power and / or bias power of the O2 plasma treatment.

[0099] In some embodiments where the dielectric cap 340 is made of SiN, O2 plasma treatment creates oxidized nitride regions (silicon oxynitride (SiO2)) within the dielectric cap 340. x N y ))341 and an unoxidized nitride region 342 is formed below the oxidized nitride region 341. The oxidized nitride region 341 can form a distinguishable interface with the unoxidized nitride region 342 because they have different material compositions (e.g., the oxidized nitride region 341 has a higher percentage of oxygen atoms and / or a higher oxygen-nitrogen ratio than the unoxidized nitride region 342).

[0100] In some embodiments, the oxidized region 341 may have an oxygen concentration gradient due to plasma treatment. For example, the percentage of oxygen atoms in the oxidized region 341 may decrease from the top surface of the dielectric cap 340 along the depth direction. In some embodiments where the dielectric cap 340 is silicon nitride, the oxygen-nitrogen atom ratio in the oxidized region 341 may decrease from the top surface of the dielectric cap 340 along the depth direction.

[0101] In some embodiments, during O2 plasma treatment, the top portion of the source / drain contact 350 may be unintentionally oxidized to form a metal oxide region 351 in the source / drain contact 350, leaving the remaining metal region 352 of the source / drain contact 350 unoxidized. Figure 38The resulting structure is shown. The metal oxide region 351 can form a identifiable interface with the unoxidized metal region 352 because they have different material compositions (e.g., the metal oxide region 351 has a higher percentage of oxygen atoms and / or a higher oxygen-nitrogen ratio than the unoxidized metal region 352).

[0102] In some embodiments, the thickness T4 of the metal oxide region 351 ranges from about 1 angstrom to about 50 angstroms. Due to the material difference between the source / drain contact 350 and the dielectric cap 340, the oxidation of the metal oxide region 351 and the oxidized region 341 can have different degrees. For example, the thickness T3 of the oxidized region 341 can be greater than, substantially equal to, or less than the thickness T4 of the metal oxide region 351.

[0103] In some embodiments, the metal oxide region 351 may have an oxygen concentration gradient due to plasma treatment. For example, the percentage of oxygen atoms in the metal oxide region 351 may decrease from the top surface of the source / drain contact 350 along the depth direction. In some embodiments where the source / drain contact 350 is metal, the oxygen-to-metal atom ratio in the metal oxide region 351 may decrease from the top surface of the source / drain contact 350 along the depth direction.

[0104] Once the oxidized region 341 (and the metal oxide region 351) are formed, then in Figure 39 In this process, an intermediate contact etch stop layer (MCESL) 360 is deposited over the source / drain contacts 350 and the dielectric cap 340. Subsequently, another ILD layer 370 is deposited over the MCESL 360. In some embodiments, the MCESL 360 is silicon nitride, and the ILD layer 370 is silicon oxide (SiO2). x ).

[0105] refer to Figure 40A The ILD layer 370 is patterned using a first etching process (also known as a via etching process) ET5 to form a via opening O7 extending through the ILD layer 370. The etching duration of the via etching process ET5 is controlled to allow penetration through the ILD layer 370, while MCESL 360 serves as an etch stop layer for the etching process ET5. In some embodiments, a photolithography process is performed prior to the via etching process ET5 to define a desired top-view pattern of the via opening O7. For example, the photolithography process may include: spin-coating a photoresist layer (such as...) over the ILD layer 370. Figure 39As shown), a post-exposure baking process is performed, followed by development of the photoresist layer to form a patterned mask with a top-view pattern of via openings O7. In some embodiments, patterning the photoresist to form the patterned mask can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography. Process details regarding etching process ET5 were previously discussed... Figure 16A The discussion has been conducted, so for the sake of brevity, it will not be repeated.

[0106] In such Figure 40A In some embodiments shown, the via opening O7 has a tapered sidewall profile due to the anisotropic etching nature. However, in some other embodiments, the etching conditions can be fine-tuned to allow the via opening O7 to have a vertical sidewall profile, such as... Figure 40B As shown.

[0107] refer to Figure 41A MCESL360 is patterned using a second etching process (also known as via etching) ET6 to form via openings O8 extending through MCESL360. The etching duration of via etching process ET6 is controlled to allow penetration through MCESL360, while the oxidized region 341 serves as an etch stop layer for etching process ET6. Process details regarding etching process ET6 were previously discussed. Figure 17A This has been discussed, and therefore will not be repeated for the sake of brevity. In some embodiments, the metal oxide region 351 may be removed during etching process ET6, such that opening O8 exposes the unoxidized region 352 of the source / drain contact 350, as... Figure 41C and Figure 41D As shown.

[0108] In some embodiments, due to process variations, there may be some misalignment (or overlap error) between the via opening O8 and the source / drain contact 350. Alternatively, in some embodiments, the size (or width) of the via opening O8 may be larger than the size (or width) of the source / drain contact 350. Regardless, the via opening O8 exposes some portions of the oxidized region 341. However, due to the etch selectivity between the MCESL 360 and the oxidized region 341, the oxidized region 341 can slow down or even stop the etching process forming the via opening O8, which in turn prevents over-etching of the dielectric material (e.g., the dielectric cap 340) and reduces the risk of leakage current.

[0109] exist Figure 41A and Figure 41CIn some embodiments shown, the via opening O8 has a tapered sidewall profile due to the anisotropic etching nature of etching process ET6. However, in some other embodiments, the etching conditions of etching process ET6 and / or the preceding via etching process ET5 can be fine-tuned to allow the via opening O8 to have a vertical sidewall profile, such as... Figure 41B and Figure 41D As shown.

[0110] refer to Figure 42A Then, source / drain vias 380 are formed in via openings O7 and O8 to physically connect and electrically connect to source / drain contacts 350. The material and process details for source / drain via 380 are similar to those for source / drain via 150 discussed previously, and therefore will not be repeated for the sake of brevity. Figure 42A and Figure 42C In some embodiments shown, the source / drain via 380 has a tapered sidewall profile due to the anisotropic etching nature of etching process ET6. However, in some other embodiments, the etching conditions of etching process ET6 can be fine-tuned to allow via openings O7 and O8 to have vertical sidewall profiles (and thus the source / drain via 380 has a vertical sidewall profile), such as... Figure 42B and Figure 42D As shown.

[0111] Figures 43-47B Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 200a according to some other embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 43-47B Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated. The order of these operations / processes can be interchanged. In the following embodiments, [the following text appears to be incomplete and requires further context]. Figures 24-42D The same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0112] In formation Figure 39 Following the structure shown, the ILD layer 370 is patterned to form a gate contact opening O9, which extends downward through the ILD layer 370, ESL 360 and dielectric cap 340 to reach the metal cap 330. Figure 43 The resulting structure is shown. The ILD layer 370 can be patterned using appropriate photolithography and etching techniques.

[0113] Next, as Figure 44 As shown, a patterned mask layer M2 is formed on the substrate 210 to fill the gate contact opening O9. The patterned mask layer M2 has an opening O10 vertically above the source / drain contact 350.

[0114] refer to Figure 45 With the patterned mask layer M2 in place, via etching process ET7 is performed to form via openings O11 extending through ILD layer 370. The etching duration of via etching process ET7 is controlled to remove ILD 370 and stops at MCESL 360. Process details of via etching process ET7 have been discussed previously regarding via etching process ET1, and therefore will not be repeated here for the sake of brevity.

[0115] refer to Figure 46 Etching process ET8 is performed to etch the MCESL360, thereby deepening the via opening O11 down to a portion of the metal oxide region 351 of the source / drain contact 350 and the oxide region 341 of the dielectric cap 340 located between the source / drain contact 350 and the patterned mask layer M2. As a result of etching process ET8, the metal oxide region 351 of the source / drain contact 350 and the oxide region 341 of the dielectric cap 340 are exposed at the bottom of the deepened via opening O11. Process details of etching process ET8 have been discussed previously regarding etching process ET2, and therefore will not be repeated here for the sake of brevity.

[0116] refer to Figure 47A and Figure 47B The patterned mask layer M2 is removed from the gate contact opening O9 by ashing and / or wet stripping (see reference). Figure 46 Then, mating contacts 390 are formed to fill the via opening O9 and the gate contact opening O11. Figure 47A or Figure 47B The resulting structure is shown. Details regarding the material and manufacturing process of the mating contact 390 are similar to those of the source / drain via 150, and therefore will not be repeated here for the sake of brevity.

[0117] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage necessary for all embodiments. One advantage is that the risk of leakage current (e.g., leakage current from the source / drain via to the gate contact and / or gate structure) can be reduced due to the oxidized region of the dielectric cap. Another advantage is that the formation of the oxidized region of the dielectric cap can omit the patterning process. Yet another advantage is that the larger distance from the source / drain via to the gate contact can improve the resistive-capacitive (RC) delay. Furthermore, due to the doped region, the size of the source / drain via can be increased to reduce the resistance of the source / drain via and further increase the contact area between the source / drain via and the source / drain contact.

[0118] According to some embodiments, a method includes depositing a dielectric cap on a gate structure. Source / drain contacts are formed adjacent to the gate structure over a source / drain region. The top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited on the dielectric cap, and an interlayer dielectric (ILD) layer is deposited on the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending through the ILD layer and the etch stop layer. Source / drain vias are filled into the via opening.

[0119] According to some embodiments, a method includes depositing source / drain contacts over a source / drain region. The top of the source / drain contacts is oxidized to form a metal oxide region within the source / drain contacts. Following the oxidation of the top of the source / drain contacts, an interlayer dielectric (ILD) layer is formed to cover the metal oxide region of the source / drain contacts. Via openings are formed in the ILD layer to expose the source / drain contacts. Source / drain vias are filled into the via openings.

[0120] According to some embodiments, a device includes a gate structure, a dielectric cap, source / drain contacts, an interlayer dielectric (ILD) layer, and source / drain vias. The dielectric cap is located above the gate structure and includes an oxidized region and an unoxidized region located between the gate structure and the oxidized region. The source / drain contacts are adjacent to the gate structure. The ILD layer is located above the dielectric cap and the source / drain contacts. The source / drain vias are in the ILD layer and electrically connected to the source / drain contacts.

[0121] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0122] Example 1. A method of forming a semiconductor device, comprising:

[0123] A dielectric cap is deposited on the gate structure;

[0124] Source / drain contacts are formed adjacent to the gate structure above the source / drain region;

[0125] Oxidize the top of the dielectric cap;

[0126] After oxidizing the top of the dielectric cap, an etch stop layer is deposited on the dielectric cap, and an interlayer dielectric (ILD) layer is deposited on the etch stop layer.

[0127] Etching the ILD layer and the etch stop layer to form a via opening extending through the ILD layer and the etch stop layer; and

[0128] The source / drain vias are filled into the via openings.

[0129] Example 2. The method according to Example 1, wherein the top of the dielectric cap is oxidized using oxygen plasma.

[0130] Example 3. The method according to Example 2, wherein the oxygen plasma is generated by O2 gas.

[0131] Example 4. The method according to Example 2, wherein the oxygen plasma is generated by a gaseous mixture of O2 gas and one or more of the following: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z The gases are NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas, where x, y, and z are greater than zero.

[0132] Example 5. The method according to Example 1, wherein forming the via opening comprises:

[0133] Perform a first etching process to form the via opening, the via opening extending through the ILD layer and exposing the top surface of the etch stop layer; and

[0134] A second etching process is performed to deepen the via opening, such that the via opening extends through the etch stop layer.

[0135] Example 6. The method according to Example 5, wherein the second etching process uses an etchant different from the etchant used in the first etching process.

[0136] Example 7. According to the method of Example 5, wherein the first etching process is a plasma etching process using plasma generated from a hydrogen-free gaseous mixture.

[0137] Example 8. According to the method of Example 5, wherein the second etching process is a plasma etching process using plasma generated from a hydrogen-containing gaseous mixture.

[0138] Example 9. A method of forming a semiconductor device, comprising:

[0139] Deposit source / drain contacts on top of the source / drain regions;

[0140] The top of the source / drain contact is oxidized to form a metal oxide region in the source / drain contact;

[0141] After oxidizing the top of the source / drain contacts, an interlayer dielectric (ILD) layer is formed to cover the metal oxide region of the source / drain contacts;

[0142] Via openings are formed in the ILD layer to expose the source / drain contacts; and

[0143] The source / drain vias are filled into the via openings.

[0144] Example 10. The method according to Example 9 further includes: after forming the via opening in the ILD layer, removing a portion of the metal oxide region of the source / drain contact.

[0145] Example 11. The method according to Example 9, wherein the source / drain via is filled such that the source / drain via contacts the metal oxide region of the source / drain contact.

[0146] Example 12. The method according to Example 9, wherein the source / drain via is filled such that the source / drain via contacts an unoxidized region of the source / drain contact.

[0147] Example 13. The method according to Example 9 further includes: depositing an etch stop layer prior to forming the ILD layer, the etch stop layer covering the metal oxide region of the source / drain contact.

[0148] Example 14. The method according to Example 13, wherein the etch stop layer and the metal oxide region of the source / drain contact are made of different materials.

[0149] Example 15. The method according to Example 13, wherein the etch stop layer is deposited such that the etch stop layer contacts the metal oxide region of the source / drain contact.

[0150] Example 16. A semiconductor device comprising:

[0151] Gate structure;

[0152] A dielectric cap is located above the gate structure and includes an oxidized region and an unoxidized region located between the gate structure and the oxidized region;

[0153] Source / drain contacts are adjacent to the gate structure;

[0154] An interlayer dielectric (ILD) layer is located above the dielectric cap and the source / drain contacts; and

[0155] Source / drain vias are located in the ILD layer and are electrically connected to the source / drain contacts.

[0156] Example 17. The device according to Example 16, wherein the source / drain via contacts an oxidized region of the dielectric cap.

[0157] Example 18. The device according to Example 16, wherein the oxidized region of the dielectric cap has an oxygen concentration gradient.

[0158] Example 19. The device according to Example 16, wherein the percentage of oxygen atoms in the oxidized region of the dielectric cap decreases from the top surface of the dielectric cap along the depth direction.

[0159] Example 20. The device according to Example 16, wherein the thickness of the oxidized region is in the range of about 1 angstrom to about 50 angstroms.

Claims

1. A method for forming a semiconductor device, comprising: A dielectric cap is deposited on the gate structure; Source / drain contacts are formed adjacent to the gate structure above the source / drain region; Oxidize the top of the dielectric cap; After oxidizing the top of the dielectric cap, an etch stop layer is deposited on the dielectric cap, and an interlayer dielectric (ILD) layer is deposited on the etch stop layer. The interlayer dielectric layer and the etch stop layer are etched to form a via opening that extends through the interlayer dielectric layer and the etch stop layer; as well as The source / drain vias are filled into the via openings.

2. The method according to claim 1, wherein, The top of the dielectric cap is oxidized using oxygen plasma.

3. The method according to claim 2, wherein, The oxygen plasma is generated by O2 gas.

4. The method according to claim 2, wherein, The oxygen plasma is generated by a gaseous mixture of O2 gas and one or more of the following: Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z The gases are NF3 gas, carbonyl sulfide (COS) gas, and SO2 gas, where x, y, and z are greater than zero.

5. The method according to claim 1, wherein, Forming the via opening includes: Perform a first etching process to form the via opening, the via opening extending through the interlayer dielectric layer and exposing the top surface of the etch stop layer; and A second etching process is performed to deepen the via opening, such that the via opening extends through the etch stop layer.

6. The method according to claim 5, wherein, The second etching process uses an etchant that is different from the etchant used in the first etching process.

7. The method according to claim 5, wherein, The first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gaseous mixture.

8. The method according to claim 5, wherein, The second etching process is a plasma etching process that uses plasma generated from a hydrogen-containing gaseous mixture.

9. A method for forming a semiconductor device, comprising: A dielectric cap is deposited on the gate structure; Source / drain contacts are deposited adjacent to the gate structure above the source / drain region; The top of the source / drain contact and the top of the dielectric cap are oxidized to form a metal oxide region in the source / drain contact and an oxidized region in the dielectric cap; After oxidizing the top of the source / drain contacts, an interlayer dielectric (ILD) layer is formed to cover the metal oxide region of the source / drain contacts; Via openings are formed in the interlayer dielectric layer to expose the source / drain contacts; as well as The source / drain vias are filled into the via openings.

10. The method of claim 9, further comprising: After forming the via opening in the interlayer dielectric layer, a portion of the metal oxide region of the source / drain contact is removed.

11. The method according to claim 9, wherein, The source / drain vias are filled so that they contact the metal oxide region of the source / drain contacts.

12. The method according to claim 9, wherein, The source / drain vias are filled so that they contact the unoxidized areas of the source / drain contacts.

13. The method of claim 9, further comprising: An etch stop layer is deposited prior to the formation of the interlayer dielectric layer, which covers the metal oxide region of the source / drain contacts.

14. The method according to claim 13, wherein, The etch stop layer and the metal oxide region of the source / drain contact are made of different materials.

15. The method according to claim 13, wherein, The etch stop layer is deposited such that it contacts the metal oxide region of the source / drain contact.

16. A semiconductor device, comprising: Gate structure; A dielectric cap is located above the gate structure and includes an oxidized region and an unoxidized region located between the gate structure and the oxidized region; Source / drain contacts are adjacent to the gate structure; An interlayer dielectric (ILD) layer is located above the dielectric cap and the source / drain contacts; as well as Source / drain vias are located in the interlayer dielectric layer and are electrically connected to the source / drain contacts.

17. The device according to claim 16, wherein, The source / drain vias are in contact with the oxidized area of ​​the dielectric cap.

18. The device according to claim 16, wherein, The oxidized region of the dielectric cap has an oxygen concentration gradient.

19. The device according to claim 16, wherein, The percentage of oxygen atoms in the oxidized region of the dielectric cap decreases from the top surface of the dielectric cap along the depth direction.

20. The device according to claim 16, wherein, The thickness of the oxidized region ranges from 1 angstrom to 50 angstroms.

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