Semiconductor package with routable encapsulated conductive substrate and method

Abstract

A semiconductor package and method having a routable encapsulated conductive substrate. In one embodiment, the routable molded leadframe structure includes a first laminate containing the surface trimming layer, a via connected to the surface trimming layer, and a first resin layer covering the via to expose a top surface of the surface trimming layer. A second laminate includes a second conductive pattern connected to the via, a bump pad connected to the second conductive pattern, and a second resin layer covering one side of the first resin layer, the second conductive pattern, and the bump pad. A semiconductor die is electrically connected to the surface trimming layer, and an encapsulant covers the semiconductor die and the other side of the first resin layer. The surface trimming layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded leadframe structure.

Description

[0001] This application is a divisional application of application number 201610571284.9, filed on July 19, 2016, entitled "Semiconductor Packaging and Method with Routable Encapsulated Conductive Substrate". Technical Field

[0002] This invention relates to electronic components, and more particularly, to semiconductor packaging and methods having a routeable encapsulated conductive substrate. Background Technology

[0003] Generally, semiconductor packages are designed to protect integrated circuits or chips from physical damage and external stress. Furthermore, semiconductor packages provide thermal conductivity paths to effectively remove heat generated within the semiconductor chip and can further provide electrical connections to other components, such as printed circuit boards. Materials used in semiconductor packages typically include ceramics and / or plastics, and packaging technologies have evolved from ceramic flat packages and dual in-line packages to leaded gate arrays and leadless chip carrier packages, as well as other packaging options. Due to the continued demand for miniaturized and high-performance packaged semiconductor devices, conductive substrates with finer pitches are required; especially conductive substrates that support various external interconnect structures.

[0004] Accordingly, it is desirable to have structures and methods for forming packaged semiconductor devices comprising a routable encapsulated conductive substrate structure, such as a routable microlead frame structure, which supports the demand for miniaturized and high-performance electronic devices. It is also desirable to fabricate the routable encapsulated conductive substrate structure or portions thereof prior to the completion of assembly of the packaged semiconductor device to reduce manufacturing cycle time. Furthermore, it would be advantageous to enable the structures and methods to support multiple external interconnect structures. Additionally, it is desirable to make the structures and methods easily integrated into the manufacturing process and cost-effective. Summary of the Invention

[0005] This invention provides a semiconductor device with a routeable encapsulated conductive substrate and a manufacturing method thereof, which solves the problems of insufficient pitch and long manufacturing cycle of the conductive substrate in existing semiconductor devices.

[0006] This invention includes a packaged semiconductor device and a method of manufacturing the same, as well as other features, said packaged semiconductor device comprising a routable encapsulated conductive substrate (e.g., a routable molded lead frame) having a conductive surface trimming layer. More specifically, the embodiments described herein facilitate efficient routing of package-level conductive patterns and provide enhanced connectivity reliability between the surface trimming layer and the semiconductor die. In one embodiment of the routable encapsulated conductive substrate, the surface trimming layer may be formed at the initial stage of the manufacturing process. In another embodiment of the routable encapsulated conductive substrate, the surface trimming layer may be formed at both the initial and final stages of the manufacturing process.

[0007] In some embodiments, conductive balls are formed directly on bump pads that do not have a surface-trimmed layer, connected to or adjacent to the bump pads, during the initial stage of the manufacturing process when the surface trimming layer is formed, to provide a ball grid array package. Alternatively, when the surface trimming layer is formed at various stages of the manufacturing process of a routeable encapsulated conductive substrate, the surface trimming layer formed at the final stage can be used as an input / output terminal to provide a grid array package.

[0008] In some preferred embodiments, the materials of the first and second resin layers used to form the routable molded lead frame and the package used to form the encapsulated semiconductor die are the same or have similar coefficients of thermal expansion and other similar material properties, thereby effectively suppressing warping during the manufacturing process or operation of the device.

[0009] More specifically, in one embodiment, a semiconductor device includes a first laminate comprising: a first surface trimming layer; a first conductive pattern including a first portion connected to the first surface trimming layer and a second portion laterally spaced from the first surface trimming layer; a conductive via connected to the first conductive pattern; and a first resin layer covering the first conductive pattern, the conductive via, and a portion of the first surface trimming layer, wherein the first surface trimming layer is exposed in a first surface of the first resin layer and the conductive via is exposed in a second surface of the first resin layer. A second laminate is disposed adjacent to the first laminate and includes a second conductive pattern connected to the conductive via, a conductive pad connected to the second conductive pattern, and a second resin layer covering at least a portion of the first resin layer, the second conductive pattern, and the conductive pad, wherein the conductive pad is exposed in the first surface of the second resin layer. A semiconductor die is electrically connected to the first surface trimming layer, and an encapsulant covers at least a portion of the first laminate and the semiconductor die.

[0010] In another embodiment, an encapsulated semiconductor device includes a routeable encapsulated conductive substrate comprising a first conductive structure encapsulated within a first resin layer, a second conductive structure electrically coupled to the first conductive structure and encapsulated within a second resin layer, and a first surface trimming layer disposed on at least a portion of the first conductive structure. The first surface trimming layer is exposed in the first resin layer, and at least a portion of the second conductive structure is exposed in the second resin layer. A semiconductor die is electrically connected to the first surface trimming layer, and the encapsulant encapsulates both the semiconductor die and the first surface trimming layer.

[0011] In another embodiment, a method of manufacturing a semiconductor device includes providing a routeable encapsulated conductive substrate, the routeable encapsulated conductive substrate including a first conductive structure encapsulated within a first resin layer, a second conductive structure electrically coupled to the first conductive structure and encapsulated within a second resin layer, and a first surface trimming layer disposed on at least a portion of the first conductive structure, wherein the first surface trimming layer is exposed in the first resin layer and at least a portion of the second conductive structure is exposed in the second resin layer. The method includes electrically connecting a semiconductor die to the first surface trimming layer and forming an encapsulation covering the semiconductor die and the first surface trimming layer.

[0012] The beneficial effects of embodiments of the present invention are: the routable encapsulated conductive substrate facilitates efficient routing of package-level embedded conductive patterns, and the surface trimming layer provides enhanced connectivity reliability between the routable encapsulated conductive substrate and the semiconductor die. Furthermore, the routable encapsulated conductive substrate supports the demand for miniaturized and high-performance electronic devices, supports various interconnect schemes for the next stage of assembly, can be manufactured prior to further assembly steps to shorten manufacturing cycle time, can be easily integrated into the manufacturing process, and is cost-effective. Attached Figure Description

[0013] The above and other features of the present invention will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0014] For simplicity and clarity, the elements in the figures are not necessarily drawn to scale, and the same reference numerals represent the same elements in different figures. Furthermore, descriptions and details of well-known steps and elements are omitted for simplicity of description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Additionally, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form as well unless the context clearly indicates otherwise. It will be further understood that the terms "comprises / comprising" and / or "includes / including" as used in this specification define the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof. It will be understood that although the terms "first," "second," etc., may be used herein to describe various parts, elements, areas, layers, and / or sections, these parts, elements, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one component, element, region, layer, and / or segment from another component, element, region, layer, and / or segment. Thus, for example, the first component, first element, first region, first layer, and / or first segment discussed below may be referred to as the second component, second element, second region, second layer, and / or second segment without departing from the teachings of the invention. The reference to “one embodiment” or “embodiment” means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the appearance of the phrase “in one embodiment” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment, but in some cases may refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner, as will be apparent to those skilled in the art in one or more embodiments. Additionally, the term “at…” means that an action occurs at least within a portion of the duration of the initial action. The use of the words “approximately,” “about,” or “substantially” means that the value of an element is expected to be close to a state value or position. However, it is well known in the art that slight variations in value or position can prevent it from being exactly as stated. Unless otherwise specified, as used herein, the terms “on top of” or “on” include orientation, placement, or relationship in which the specified elements may be in direct or indirect physical contact. It should be further understood that the embodiments illustrated and described below may suitably be practiced in the absence of any elements precisely disclosed herein.

[0015] Figure 1A A cross-sectional view of a packaged semiconductor device illustrating an embodiment of the present invention;

[0016] Figure 1B To explain Figure 1A A magnified cross-sectional view of the region;

[0017] Figure 2A A cross-sectional view illustrating a packaged semiconductor device according to another embodiment of the present invention;

[0018] Figure 2B To explain Figure 2A A magnified cross-sectional view of the region;

[0019] Figure 2C For the purpose of this description based on alternative embodiments Figure 2A A magnified cross-sectional view of the region;

[0020] Figure 3 A cross-sectional view illustrating a packaged semiconductor device according to another embodiment of the present invention;

[0021] Figure 4 A cross-sectional view illustrating a packaged semiconductor device according to yet another embodiment of the present invention;

[0022] Figure 5A To illustrate a plan view of a carrier composed of (N×M) units;

[0023] Figure 5B To illustrate a plan view of a carrier composed of N units;

[0024] Figures 6A to 6J A cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to an embodiment of the present invention;

[0025] Figures 7A to 7C A cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to another embodiment of the present invention;

[0026] Figures 8A to 8I A cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to another embodiment of the present invention; and

[0027] Figures 9A to 9C A cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to yet another embodiment of the present invention. Detailed Implementation

[0028] This application claims priority to U.S. Patent Application No. 15 / 173,379, filed June 3, 2016, entitled “SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD”, and Korean Patent Application No. 10-2015-0126935, filed September 8, 2015, with the Korean Intellectual Property Office, and all benefits are derived from the aforementioned patent applications pursuant to 35 U.S.SC § 119, the entire contents of which are incorporated herein by reference.

[0029] Figure 1A This is a cross-sectional view of a semiconductor device 100 having a surface trimming layer or a packaged semiconductor device 100 according to the description of the first embodiment, and Figure 1B To explain Figure 1A An enlarged cross-sectional view of the region. For example... Figure 1A As described herein, the semiconductor device 100 includes a first laminate 110 or a first encapsulation layer, a second laminate 120 or a second encapsulation layer, a semiconductor die 130, conductive interconnect structures (e.g., wires), an encapsulation 150 or package, conductive bumps or bump pads 122, and conductive bumps 160. According to this embodiment, the first laminate 110 and the second laminate 120 may be referred to as a routable molded leadframe 101 or a routable encapsulated conductive substrate.

[0030] In one embodiment, the first laminate 110 includes a first surface trimming layer 111, a first bonding layer or a first wire-bondable trimming layer (wherein the first surface trimming layer 111 may be replaced by the first bonding layer or the first wire-bondable trimming layer), a first conductive pattern 112, a via 113, a conductive via, or a conductive post, and a first resin layer 114. In some embodiments, the first surface trimming layer 111 may be a metallic material, such as nickel / gold (Ni / Au), silver (Ag), copper (Cu), combinations thereof, and equivalents thereof, but aspects of this embodiment are not limited thereto. In one embodiment, the first conductive pattern 112 may be disposed on or adjacent to the first surface trimming layer 111, and / or may be disposed spaced apart from the first surface trimming layer 111. The first conductive pattern 112 may be made of a metal, such as copper (Cu) and equivalents thereof, but aspects of this embodiment are not limited thereto. In one embodiment, a via 113 is formed on, connected to, or adjacent to the first conductive pattern 112, and may have a smaller width and a larger thickness than the first conductive pattern 112. The via 113 may also be made of metal, such as copper (Cu) or equivalents, but this embodiment is not limited thereto. A first resin layer 114 may cover the first surface trimming layer 111, the first conductive pattern 112, and the via 113. However, the top surfaces of the first surface trimming layer 111 and the first conductive pattern 112 may not be covered by the first resin layer 114. Furthermore, the bottom surface of the via 113 may not be covered by the first resin layer 114. The first resin layer 114 may be made of a polymer material, such as one or more polyimides (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resins, epoxy molding compounds, and equivalents, but this embodiment is not limited thereto. In some embodiments, the via 113 is connected to only a first portion of the first conductive pattern 112, thereby causing a second portion of the first conductive pattern 112 to be at least partially embedded within the first resin layer 114, such as... Figure 1A This is a general explanation.

[0031] In one embodiment, the second laminate 120 includes a second conductive pattern 121, a bump pad 122 or a conductive pad, and a second resin layer 123. In one embodiment, the second conductive pattern 121 may be disposed on or adjacent to the via 113 and may be positioned adjacent to the bottom surface of the first resin layer 114. In some embodiments, the second conductive pattern 121 may be disposed on or adjacent to the bottom surface of the first resin layer 114. Additionally, the second conductive pattern 121 may be a metal, such as copper (Cu) or equivalents, but this embodiment is not limited thereto. In one embodiment, the bump pad 122 may be formed on, connected to, or adjacent to the second conductive pattern 121, and may have a smaller width and a larger thickness than the second conductive pattern 121. The bump pad 122 may also be a metal, such as copper (Cu) or equivalents, but this embodiment is not limited thereto. The second resin layer 123 may cover at least a portion of the first resin layer 114, the second conductive pattern 121, and the bump pad 122. However, the top surface of the second conductive pattern 121 may not be covered by the second resin layer 123. Furthermore, the bottom surface of the bump pad 122 may not be covered by the second resin layer 123 and may be exposed to the outside. The second resin layer 123 may be made of a polymer material, such as one or more polyimides (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resins, epoxy molding compounds, and equivalents thereof, but aspects of this embodiment are not limited thereto.

[0032] According to this embodiment, the stacked structure including the first laminate 110 and the second laminate 120 may be referred to as a routable encapsulated conductive substrate or a routable molded lead frame 101, which may be disposed as a single unit during the manufacturing process of the semiconductor device 100.

[0033] In one embodiment, the semiconductor die 130 is connected to a routable molded lead frame 101. In some embodiments, the semiconductor die 130 is attached to a first laminate 110 using, for example, an adhesive 135, and is further electrically connected to the first laminate 110. According to one embodiment, the semiconductor die 130 can be electrically connected to a first surface trimming layer 111 using wires. In one embodiment, the wires comprise gold wires, and the first surface trimming layer 111 comprises nickel / gold (Ni / Au) or silver (Ag). In this embodiment, the wires and the first surface trimming layer 111 can be easily interconnected. In some embodiments, the semiconductor die 130 may include circuitry including, for example, a digital signal processor (DSP), a network processor, a power management unit, an audio processor, RF circuitry, a wireless baseband system-on-a-chip (SoC) processor, a sensor, an application-specific integrated circuit (ASIC), and / or other active and / or passive electronic devices known to those skilled in the art.

[0034] In one embodiment, encapsulant 150 encapsulates, covers, or molds a routable molded lead frame 101, the routable molded lead frame 101 including, for example, a semiconductor die 130 and wires, and at least a portion of a first laminate 110. In some embodiments, encapsulant 150 may cover a first surface trimming layer 111 and a first conductive pattern 112. Encapsulant 150 may be a polymer composite material, such as an epoxy molding compound for encapsulating via a molding process, a liquid encapsulation component for encapsulating via a dispenser, or equivalents thereof, but aspects of this embodiment are not limited thereto. In a preferred embodiment, when the first resin layer 114, the second resin layer 123, and the encapsulant 150 are formed using the same material, they may have the same coefficient of thermal expansion, thereby minimizing warpage during the manufacturing process or operation of the semiconductor device 100.

[0035] In one embodiment, the conductive bump 160 may be connected to the bump pad 122. In another embodiment, the conductive bump 160 may be welded or attached to the bump pad 122, which is not covered by the second resin layer 123. The conductive bump 160 may be a guide post, a guide post with a solder cap, a conductive ball, a solder ball, or equivalents thereof, but aspects of this embodiment are not limited thereto. In the illustrated embodiment, the conductive bump 160 is shown as an example of a conductive ball.

[0036] According to this embodiment, the semiconductor device 100 is configured as a wire-joined, routable molded leadframe package, which is further configured as a ball grid array type package.

[0037] According to this embodiment, the side surfaces of the routable molded lead frame 101 and encapsulation 150, including, for example, a first laminate 110 and a second laminate 120, are configured to be coplanar with each other by separation during the fabrication of the semiconductor device 100. In one embodiment, the side surfaces of the following structures are substantially coplanar with each other: the first resin layer 114 of the first laminate 110, the second resin layer 123 of the second laminate 120, and the encapsulation 150. In a preferred embodiment, the first conductive pattern 112 of the first laminate 110 is not exposed to the outside through the side surface of the first resin layer 114, and the second conductive pattern 121 of the second laminate 120 is not exposed to the outside through the side surface of the second resin layer 123. Therefore, it is possible to prevent unnecessary electrical short circuits between the first conductive pattern 112 and the second conductive pattern 121 and external devices. In addition, because the first surface trimming layer 111 is formed on the first conductive pattern 112, wires can be easily connected to the first surface trimming layer 111.

[0038] like Figure 1B As described, in one embodiment, the top surface of the first surface trimming layer 111 is substantially coplanar with the top surface of the first resin layer 114. However, the top surface of the first conductive pattern 112, which is horizontally or laterally spaced from the first surface trimming layer 111, may be lower than or recessed relative to the top surface of the first resin layer 114. Furthermore, the bottom surface of each bump pad 122 is higher than or recessed relative to the bottom surface of the second resin layer 123. In other words, the top surface of each first conductive pattern 112 is recessed within a first opening 114a formed in the first resin layer 114. Similarly, the bottom surface of each bump pad 122 is recessed within a second opening 123a formed in the second resin layer 123.

[0039] According to this embodiment, such configuration features can be caused by the manufacturing process. For example, when a removal step (e.g., grinding and / or etching) is performed on the first resin layer 114, the first surface trimming layer 111 acts as a mask, and the top surface of each first conductive pattern 112 can be slightly over-etched more than the first resin layer 114 so that the top surface of the first conductive pattern 112 can be positioned inside or recessed within the first opening 114a. Additionally, when a removal step (e.g., grinding and / or etching) is performed on the second resin layer 123, the bottom surface of each second conductive pattern 121 is over-etched relative to the second resin layer 123 so that the bottom surface of the second conductive pattern 121 can be positioned inside or recessed within the second opening 123a.

[0040] Therefore, according to this embodiment, the first opening 114a formed in the first resin layer 114 improves the coupling force between the encapsulant 150 and the first resin layer 114, and the second opening 123a formed in the second resin layer 123 improves the coupling force between the conductive bump 160, the bump pad 122, and the second resin layer 123. In some embodiments, portions of the via 113 and the first conductive pattern 112 and / or the second conductive pattern 121 and the bump pad 122 are as shown in Figure 1B The cross-sectional view generally described in the figure forms a shape resembling a "T". In some embodiments, the first conductive pattern 112 and the through hole 113 are examples of a first conductive structure, and the second conductive pattern 121 and the bump pad 122 are examples of a second conductive structure. In other words, the first conductive structure may include the first conductive pattern 112 and the through hole 113, and the second conductive structure may include the second conductive pattern 121 and the bump pad 122.

[0041] Figure 2A A cross-sectional view of a semiconductor device 200 having a surface trimming layer or a packaged semiconductor device 200 according to another embodiment; Figure 2B To explain Figure 2A An enlarged cross-sectional view of the region; and Figure 2C This is an enlarged cross-sectional view of the area without a surface trimming layer, according to an alternative embodiment.

[0042] like Figure 2A As described, instead of using conductive bumps, the routable molded leadframe 101 may alternatively include a second surface trimming layer 224 or a second bonding layer formed on or connected to the bump pad 122 of the second laminate 120. In some embodiments, the second surface trimming layer 224 may include a metallic material, such as nickel / gold (Ni / Au), silver (Ag), tin (Sn), combinations thereof, and equivalents thereof, but aspects of the embodiments of the invention are not limited thereto. According to this embodiment, the semiconductor device 200 is configured as a wire-bonded routable molded leadframe package, which is further configured as a grid array type package. In another embodiment, conductive bumps may be connected to the second surface trimming layer 224.

[0043] like Figure 2BAs described, in one embodiment, the top surface of the first surface trimming layer 111 is substantially coplanar with the top surface of the first resin layer 114, and the bottom surface of the second surface trimming layer 224 is substantially coplanar with the bottom surface of the second resin layer 123. However, the top surface of each first conductive pattern, which is horizontally or laterally spaced from the first surface trimming layer 111, may be lower than or recessed relative to the top surface of the first resin layer 114. In other words, the top surfaces of all first conductive patterns 112 are recessed within the first opening 114a formed in the first resin layer 114.

[0044] According to this embodiment, such configuration features may be caused by the manufacturing process. For example, when a removal step (e.g., grinding and / or etching) is performed on the first resin layer 114 and / or the second resin layer 123, the first surface trimming layer 111 and / or the second resin layer 123 act as a mask, and the top surface of the first conductive pattern 112 may be slightly over-etched than the first resin layer 114, such that the top surface of the first conductive pattern 112 is positioned inside or recessed within the first opening 114a formed in the first resin layer 114.

[0045] like Figure 2C As explained, when no first surface trimming layer is formed on the first conductive pattern 112' and no second surface trimming layer is formed on the bump pad 122', the top surface of the first conductive pattern 112' may be positioned below or recessed relative to the top surface of the first resin layer 114', and the bottom surface of the bump pad 122' may be positioned above or recessed relative to the bottom surface of the second resin layer 123'. In one embodiment, when a removal step (e.g., grinding and / or etching) is performed on the first resin layer 114' and / or the second resin layer 123' in the absence of a mask layer, the top surface of the first conductive pattern 112' and / or the bottom surface of the bump pad 122' may be over-etched relative to the first resin layer 114' and / or the second resin layer 123'. Therefore, the first conductive pattern 112' is positioned inside the first opening 114a' of the first resin layer 114' or recessed within the first opening 114a' of the first resin layer 114', and the bottom surface of the bump pad 122' is positioned inside the second opening 123a' of the second resin layer 123' or recessed within the second opening 123a' of the second resin layer 123'.

[0046] Figure 3 This is a cross-sectional view of a semiconductor device 300 having a surface-trimmed layer or a packaged semiconductor device 300 according to another embodiment. Figure 3As described, the first surface trimming layer 311, the first bonding layer, or the first wire-bondable trimming layer comprises a metallic material, such as silver (Ag), and a via 113 made of copper (Cu) may be formed on the first surface trimming layer 311, connected to the first surface trimming layer 311, or adjacent to the first surface trimming layer 311. According to this embodiment, in the semiconductor device 300, wires can be easily bonded to the first surface trimming layer 311 made of silver (Ag). Additionally, according to this embodiment, the semiconductor device 300 is configured as a wire-bonded, routable molded leadframe package, which is further configured as a ball grid array type package. Furthermore, according to this embodiment, the first surface trimming layer 311 may also be configured as a first conductive pattern for the semiconductor device 300. In some embodiments, the via 113 is an example of a first conductive structure, and the second conductive pattern 121 and the bump pad 122 are examples of a second conductive structure.

[0047] Figure 4 This is a cross-sectional view of a semiconductor device 400 having a surface-trimmed layer or a packaged semiconductor device 400 according to another embodiment. Figure 4 As described, the first surface trimming layer 411, the first bonding layer, or the first wire-bondable trimming layer may comprise a metallic material, such as copper (Cu), and a via 113 made of copper (Cu) may be formed on the first surface trimming layer 411, connected to the first surface trimming layer 411, or adjacent to the first surface trimming layer 411. According to this embodiment, because the semiconductor die 130 is not directly connected to the first surface trimming layer 411 via wire bonding, it can be connected to the first surface trimming layer 411 via other types of conductive connection structures (e.g., microbumps 435). In one embodiment, the semiconductor die 130 is electrically connected to the first surface trimming layer 411 in a flip-chip configuration. Additionally, an encapsulant 150 is inserted between the semiconductor die 130 and the first laminate 110, thereby allowing the semiconductor die 130 and the first laminate 110 to be mechanically integrated with each other. Additionally, a second surface trimming layer 224 or a second bonding layer made of a metallic material (e.g., nickel / gold (Ni / Au), silver (Ag), or tin (Sn)) may be formed on the bump pad 122 instead of the conductive bump. According to this embodiment, the semiconductor device 400 is configured as a flip-chip routable molded leadframe package, which is further configured as a grid array type package. According to this embodiment, the first surface trimming layer 411 may also be configured as a first conductive pattern for the semiconductor device 400. In an alternative embodiment, conductive bumps may be formed on the second surface trimming layer 224. In some embodiments, the via 113 is an example of a first conductive structure, and the second conductive pattern 121 and the bump pad 122 are examples of a second conductive structure. It should be understood that... Figure 4The attachment configuration for semiconductor die 130 can be used in any of the embodiments described herein.

[0048] Figure 5A To illustrate the plan view of the carrier 171 composed of an N×M matrix or array of encapsulated units, and Figure 5B A plan view illustrating the carrier 172 composed of 1xM units. (See attached diagram.) Figure 5A As described above, the carrier 171 on which semiconductor devices 100 to 400 are fabricated (e.g.) is formed in a matrix of N×M units. In one embodiment, N and M are preferably integers greater than or equal to 2. As described above, since the carrier 171 is formed in a matrix type, semiconductor devices 100 to 400 according to embodiments of the present invention can be manufactured in large quantities. Figure 5B As described above, the carrier 172 can be formed as a strip of 1xM units. In one embodiment, M is preferably an integer greater than 1.

[0049] Figures 6A to 6J This is a cross-sectional view illustrating an embodiment of a semiconductor device 100 having a first surface trimming layer 111 or a method for manufacturing a packaged semiconductor device 100. (See also...) Figures 6A to 6J As described herein, the method for manufacturing a semiconductor device 100 includes the following steps: providing a carrier 170 and forming a first surface trimming layer 111; forming a first conductive pattern 112; forming a via 113; providing a first resin layer 114; firstly removing (e.g., grinding) a portion of the first resin layer 114; forming a second conductive pattern 121; forming a bump pad 122; providing a second resin layer 123; removing the carrier 170; connecting a semiconductor die 130; forming an encapsulation 150; and forming conductive bumps 160.

[0050] like Figure 6AAs described herein, in the steps of providing the carrier 170 and forming the first surface trimming layer 111, a carrier 170 having, for example, a substantially flat plate shape is prepared, and a plurality of first surface trimming layers 111 are formed on or adjacent to the main surface of the carrier 170. In one embodiment, the carrier 170 may be made of a conductive material (e.g., copper (Cu)), an insulating material (e.g., polyimide), and / or a ceramic material (e.g., alumina), or other materials known to those skilled in the art. In some embodiments where the carrier 170 is made of a conductive material, the first surface trimming layer 111 may be formed on the surface of the carrier 170, attached to, or adjacent to the surface of the carrier 170. In other embodiments where the carrier 170 is made of an insulating or ceramic material, a conductive seed layer (made of, for example, tungsten or tungsten-titanium) may be formed first, and the first surface trimming layer 111 may then be formed on the conductive seed layer, attached to, or adjacent to the conductive seed layer. Additionally, the first surface trimming layer 111 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. According to this embodiment, the first surface trimming layer 111 comprises a material that is readily bonded to or forms a bond with a conductive connection structure (e.g., a connecting line or bump). Furthermore, the first surface trimming layer 111 preferably comprises a material selectively etched relative to the first conductive pattern 112. In some embodiments, the first surface trimming layer 111 may be made of nickel / gold (Ni / Au) or silver (Ag), but aspects of this embodiment are not limited thereto. In one embodiment, the first surface trimming layer 111 has a thickness ranging from approximately 0.1 micrometers to 15 micrometers.

[0051] like Figure 6B As described herein, in the step of forming the first conductive pattern 112, the first conductive pattern 112 is formed on the surfaces of the first surface trimming layer 111 and the carrier 170, connected to or adjacent to the surfaces of the first surface trimming layer 111 and the carrier 170. More specifically, the first conductive pattern is configured as a routed first conductive pattern 112 and can be formed on the surfaces of the first surface trimming layer 111 and the carrier 170. The first conductive pattern 112 can be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. Additionally, the first conductive pattern 112 can be made of a conductive material, such as copper (Cu). In one embodiment, the first conductive pattern 112 has a thickness ranging from approximately 3 micrometers to 30 micrometers.

[0052] like Figure 6CAs described, in the step of forming the via 113, conductive via, or conductive post, the via 113, which is a relatively thick post, is formed on the first conductive pattern 112, connected to the first conductive pattern 112, or adjacent to the first conductive pattern 112. The via 113 can be formed by electroless plating and / or electroplating and can be made of copper (Cu). In one embodiment, the via 113 has a thickness in the range of approximately 20 micrometers to 100 micrometers.

[0053] like Figure 6D As described herein, in the step of forming the first resin layer 114, the first resin layer 114 is formed or coated onto the carrier 170, thereby allowing the first resin layer 114 to cover the carrier 170, the first surface trimming layer 111, the first conductive pattern 112, and the via 113. In some embodiments, the first resin layer 114 may be formed on the carrier 170 by, for example, spin coating, spraying, or deep coating followed by UV and / or thermosetting. The first resin layer 114 may be made of polymeric materials, such as one or more polyimides (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resins, epoxy molding compounds, and equivalents thereof, but aspects of this embodiment are not limited thereto. In one embodiment, the first resin layer 114, similar to the encapsulation 150, may be made of a common epoxy molding compound. In this embodiment, the first resin layer 114 may be formed by compression molding or transfer molding.

[0054] like Figure 6E As described, in the first removal step, the first resin layer 114 is partially removed using, for example, grinding and / or etching processes until the via 113 is exposed outside the first resin layer 114. In this way, the top surface of the via 113 becomes substantially coplanar with the top surface of the first resin layer 114.

[0055] According to this embodiment, the first surface trimming layer 111, the first conductive pattern 112, the via 113 and the first resin layer 114 can be collectively defined as the first laminate 110.

[0056] like Figure 6FAs described herein, in the step of forming the second conductive pattern 121, the second conductive pattern 121 is formed on, adjacent to, or connected to the via 113 exposed to the outside through the first resin layer 114. In one embodiment, the second conductive pattern 121 is routed on the second resin layer 123 and simultaneously electrically connected to the via 113. The second conductive pattern 121 can be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. Additionally, the second conductive pattern 121 can be made of a conductive material, such as copper (Cu). In one embodiment, the second conductive pattern 121 has a thickness ranging from approximately 3 micrometers to 15 micrometers.

[0057] like Figure 6G As described herein, in the step of forming the bump pad 122, the bump pad 122 is formed on the second conductive pattern 121, connected to the second conductive pattern 121, or adjacent to or connected to the second conductive pattern 121. The bump pad 122 can be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. Additionally, the bump pad 122 can be made of a conductive material, such as copper (Cu). In one embodiment, the bump pad 122 has a thickness ranging from approximately 20 micrometers to 100 micrometers.

[0058] like Figure 6H As described, in the step of forming the second resin layer 123, the second resin layer 123 is formed or coated onto the first laminate 110, thereby allowing the second resin layer 123 to cover the first resin layer 114, the second conductive pattern 121, and the bump pad 122. In some embodiments, the second resin layer 123 may be coated using the same method and the same material as the first resin layer 114. Additionally, after coating and curing the second resin layer 123, a second removal step may be performed. In the second removal step, the second resin layer 123 is partially removed using, for example, a grinding and / or etching process until the bump pad 122 is exposed outside the second resin layer 123. In this way, the top surface of the bump pad 122 becomes substantially coplanar with the top surface of the second resin layer 123. In one embodiment, if no mask layer is formed on the bump pad 122, then the surface of the bump pad 122 is as follows: Figure 1B The etching process described herein is then positioned inside the second opening of the second resin layer 123 or recessed inside the second opening of the second resin layer 123.

[0059] According to this embodiment, the second conductive pattern 121, the bump pad 122, and the second resin layer 123 can be collectively defined as the second laminate 120. Additionally, the first laminate 110 and the second laminate 120 can be collectively defined as a routable molded lead frame 101.

[0060] like Figure 6I As described, in the step of removing the carrier 170, the carrier 170 is removed from the first laminate 110. More specifically, the carrier 170 is removed from the first surface trimming layer 111, the first conductive pattern 112, and the first resin layer 114, thereby exposing the first surface trimming layer 111, the first conductive pattern 112, and the first resin layer 114 to the outside. In one embodiment, a grinding and / or etching process can be used to remove the carrier 170. In one embodiment, the surface of the first conductive pattern 112 without the first surface trimming layer 111 can be over-etched to position it as such. Figure 1B The first resin layer 114 described herein is recessed inside the first opening or within the first opening of the first resin layer 114.

[0061] like Figure 6J As described, in the steps of connecting the semiconductor die 130, forming the encapsulation 150, and forming the conductive bump 160, the semiconductor die 130 may be attached to the first laminate 110 using, for example, an adhesive 135. Furthermore, the semiconductor die 130 may be electrically connected to the first surface finishing layer 111 using a conductive connection structure (e.g., a wire). Next, the semiconductor die 130 and the wire are encapsulated using the encapsulation 150. The encapsulation 150 may be a polymer composite material, such as an epoxy molding compound for encapsulation via a molding process, a liquid encapsulation component for encapsulation via a dispenser, or equivalents thereof, but this embodiment is not limited thereto. In one embodiment, the conductive bump 160 is formed on or connected to a bump pad 122 exposed to the outside via the second laminate 120. The conductive bump 160 may be selected from the group consisting of: guide posts, guide posts with solder caps, conductive balls, solder balls, and equivalents thereof, but this embodiment is not limited thereto. Figure 6J In the illustrated embodiments, the conductive bump 160 is shown as a conductive ball as an example embodiment.

[0062] In addition, as described above, since the process of this embodiment can be performed in the form of an N×M matrix or 1xM stripes, a separation process (e.g., a sawing process) can then be performed to produce individual semiconductor devices 100.

[0063] According to this embodiment, a manufacturing method for manufacturing a semiconductor device 100 is provided, wherein a first surface trimming layer 111 is first formed and the remainder of the structure and components may be formed subsequently. Specifically, this embodiment provides a wire-jointed, routable molded leadframe ball grid array type package.

[0064] Figures 7A to 7C This is a cross-sectional view illustrating an embodiment of a manufacturing method for a semiconductor device 200 having a second surface trimming layer 224 or a packaged semiconductor device 200. In this embodiment, a combination of... Figures 6A to 6H The manufacturing steps are described, and their details will not be repeated here.

[0065] like Figure 7A As described herein, after the steps of forming (e.g., coating and curing) the second resin layer 123 and partially removing (e.g., grinding and / or etching) the second resin layer 123, a second surface trimming layer 224 may be further formed on, attached to, or adjacent to, the bump pad 122 exposed to the outside through the second resin layer 123. In one embodiment, the second surface trimming layer 224 may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. According to this embodiment, the second surface trimming layer 224 includes readily bondable to or forms a bond with a conductive structure (e.g., a printed circuit board) disposed on a next stage of assembly. In some embodiments, the second surface trimming layer 224 may be made of nickel / gold (Ni / Au), silver (Ag), tin (Sn), and equivalents thereof, but aspects of this embodiment are not limited thereto.

[0066] like Figure 7B As described, due to the removal of the carrier 170, a routable molded lead frame 101 is provided. The routable molded lead frame 101 has a first surface trimming layer 111 and a first conductive pattern 112 exposed to the outside via a first laminate 110, and a second surface trimming layer 224 exposed to the outside via a second laminate 120. According to this embodiment, the first surface trimming layer 111 is formed in the initial stage of the manufacturing process of the routable molded lead frame 101, and the second surface trimming layer 224 is formed in the final stage of the manufacturing process of the routable molded lead frame 101.

[0067] like Figure 7C As described herein, semiconductor die 130 is attached to routable molded lead frame 101 using, for example, an adhesive 135, and semiconductor die 130 is electrically connected to first surface trimming layer 111 by conductive connection structures (e.g., wires). Additionally, semiconductor die 130 and wires may be encapsulated or molded using encapsulant 150 as previously described.

[0068] According to this embodiment, the conductive bumps may not be included on the bump pad 122, and the previously formed second surface trimming layer 224 is exposed to the outside. Therefore, this embodiment provides a wire-jointed, routable molded leadframe grid array package. In an alternative embodiment, the conductive bumps may also be formed on the second surface trimming layer 224.

[0069] Figures 8A to 8I This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 300 having a surface-trimmed layer or a packaged semiconductor device 300 according to another embodiment. Figures 8A to 8I As described herein, the method for manufacturing a semiconductor device 300 may include the following steps: providing a carrier 170 and forming a first surface trimming layer 311; forming a via 113; providing a first resin layer 114; first removing (e.g., grinding); forming a second conductive pattern 121; forming a bump pad 122; providing a second resin layer 123; removing the carrier 170; connecting a semiconductor die 130; forming an encapsulation 150; and forming conductive bumps 160.

[0070] like Figure 8A As described above, in the steps of providing the carrier 170 and forming the first surface trimming layer 111, the carrier 170 is prepared as previously described, and the first surface trimming layer 311 is formed on the carrier 170. In one embodiment, the first surface trimming layer 311 may substantially serve as a first conductive pattern. According to this embodiment, the first surface trimming layer 311 comprises a material that is readily bonded to or forms a bond with a conductive connection structure (e.g., a connecting line or a bump). In some embodiments, the first surface trimming layer 311 may be made of silver (Ag). Additionally, the first surface trimming layer 311 may be formed by PVD, CVD, metal sputtering, metal evaporation, electrolytic or electroless plating, or other forming techniques known to those skilled in the art. In one embodiment, the first surface trimming layer 311 has a thickness ranging from approximately 3 micrometers to 15,000 micrometers.

[0071] like Figure 8B As described above, in the step of forming the via 113, the via 113, which is a relatively thick guide post, is formed on the first surface trimming layer 311, connected to the first surface trimming layer 311, or adjacent to the first surface trimming layer 311. The via 113 may be made of copper (Cu) and formed as previously described.

[0072] like Figure 8C As described herein, in the step of providing the first resin layer 114, the first resin layer 114 is formed or coated onto the carrier 170 as previously described, thereby allowing the first resin layer 114 to cover the carrier 170, the first surface trimming layer 311, and the via 113.

[0073] like Figure 8D As described herein, in the first removal step, the first resin layer 114 is partially removed using, for example, grinding and / or etching processes until the via 113 is exposed outside the first resin layer 114. According to this embodiment, the first surface trimming layer 311, the via 113, and the first resin layer 114 can be collectively defined as the first laminate 110.

[0074] like Figure 8E As described above, in the step of forming the second conductive pattern 121, the second conductive pattern 121 is formed on the via 113 exposed to the outside through the first resin layer 114, connected to the via 113, or adjacent to the via 113. According to this embodiment, the second conductive pattern 121 is routed on the second resin layer 123 and simultaneously electrically connected to the via 113. The second conductive pattern 121 can be formed as previously described and can be made of copper (Cu) or other materials known to those skilled in the art.

[0075] like Figure 8F As described above, in the step of forming the bump pad 122, the bump pad 122 is formed on or connected to the second conductive pattern 121. The bump pad 122 may be formed as previously described and may be made of copper (Cu) or other materials known to those skilled in the art.

[0076] like Figure 8G As described, in the step of providing the second resin layer 123, the second resin layer 123 is formed or coated onto the first laminate 110, thereby positioning the second resin layer 123 to cover the first resin layer 114, the second conductive pattern 121, and the bump pad 122. Furthermore, after coating and curing the second resin layer 123, a second removal step may be performed. In the second removal step, the second resin layer 123 is partially removed using, for example, grinding and / or etching processes until the bump pad 122 is exposed outside the second resin layer 123. In one embodiment, if no mask layer is formed on the bump pad 122, the surface of the bump pad 122 may be positioned inside or recessed within the second opening of the second resin layer 123 after the etching step.

[0077] According to this embodiment, the second conductive pattern 121, the bump pad 122, and the second resin layer 123 can be collectively defined as the second laminate 120.

[0078] like Figure 8HAs described, in the step of removing the carrier 170, the carrier 170 is removed from the first laminate 110. More specifically, the carrier 170 is removed from the first surface trimming layer 311 and the first resin layer 114, thereby exposing the first surface trimming layer 311 and the first resin layer 114 to the outside. In one embodiment, a grinding and / or etching process can be used to remove the carrier 170. According to this embodiment, the first surface trimming layer 311, which contains silver (Ag), acts as a mask, and the surface of the first surface trimming layer 311 becomes substantially coplanar with the surface of the first resin layer 114.

[0079] like Figure 8I As described above, in the steps of connecting the semiconductor die 130, forming the encapsulation 150, and forming the conductive bump 160, the semiconductor die 130 may be attached to the first laminate 110 using, for example, an adhesive 135. Furthermore, the semiconductor die 130 is electrically connected to the first surface trimming layer 311 using conductive connection structures (e.g., wires). Next, the semiconductor die 130 and the wires are encapsulated using the encapsulation 150 as previously described. In one embodiment, the conductive bump 160 is formed on or connected to a bump pad 122 exposed to the outside through the second laminate 120.

[0080] As described above, this embodiment provides a method of manufacturing a semiconductor device 300, wherein a first surface-trimming layer 311, including silver (Ag), is first formed and the remainder of the structure and components may be subsequently formed. Additionally, this embodiment provides a wire-bonded, routable molded leadframe ball grid array package.

[0081] Figures 9A to 9C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 400 having a surface-trimmed layer or a packaged semiconductor device 400 according to yet another embodiment. In this embodiment, a combination of... Figures 8A to 8G The manufacturing steps described herein will not be repeated here in detail. However, the manufacturing method of semiconductor device 400 differs from that of semiconductor device 300. Specifically, the first surface trimming layer 411 is made of a different material. In one embodiment, the first surface trimming layer 411 is made of copper (Cu) instead of silver (Ag).

[0082] like Figure 9A As described herein, after the steps of forming and curing the second resin layer 123 and grinding and / or etching the second resin layer 123, a second surface trimming layer 224 may be further formed on or attached to the bump pad 122 exposed to the outside of the second resin layer 123. In one embodiment, the second surface trimming layer 224 may be made as previously described and may include one or more of nickel / gold (Ni / Au), silver (Ag), tin (Sn), and equivalents thereof, but aspects of this embodiment are not limited thereto.

[0083] like Figure 9B As described above, after removing the carrier 170, a routable molded lead frame 101 is provided, comprising a lead frame 101 having the following structures: a first surface trimming layer 411 exposed to the outside via a first laminate 110 (which, as described above, also serves as a conductive pattern); and a second surface trimming layer 224 exposed to the outside via a second laminate 120. According to this embodiment, the first surface trimming layer 411 is formed in the initial stage of the manufacturing process of the routable molded lead frame 101, and the second surface trimming layer 224 is formed in the final stage of the manufacturing process of the routable molded lead frame 101.

[0084] like Figure 9C As described above, the semiconductor die 130 is positioned on a routable molded leadframe 101 and electrically connected to a first surface-trimmed layer 411 made of copper (Cu) by conductive bump structures (e.g., microbumps 435). More specifically, in the routable molded leadframe 101, the semiconductor die 130 is connected to the first surface-trimmed layer 411 of the first laminate 110 in a flip-chip configuration. In some embodiments, the semiconductor die 130 and the microbumps 435 are encapsulated using an encapsulant 150 as previously described.

[0085] In some embodiments, the conductive bumps are not formed separately on the bump pad 122, and the previously formed second surface trimming layer 224 is exposed to the outside. Therefore, this embodiment provides a flip-chip routable molded leadframe grid array package. In an alternative embodiment, the conductive bumps may also be formed on the second surface trimming layer 224.

[0086] Based on all the foregoing, those skilled in the art will determine that, according to one embodiment, a semiconductor device includes: a first laminate including a first surface trimming layer, a first conductive pattern connected to or spaced apart from the first surface trimming layer, a via formed on the first conductive pattern, and a first resin layer covering the first surface trimming layer, the first conductive pattern, and the via; a second laminate including a second conductive pattern formed in the via, a bump pad formed on the second conductive pattern, and a second resin layer covering the first resin layer, the second conductive pattern, and the bump pad; a semiconductor die connected to the first surface trimming layer of the first laminate; and an encapsulant covering the first laminate and the semiconductor die.

[0087] Based on all the foregoing, those skilled in the art will determine that, according to another embodiment, a method for manufacturing a semiconductor device includes: forming a first surface trimming layer on a carrier; forming a first conductive pattern on the carrier and the first surface trimming layer; forming a via on the first conductive pattern and coating a first resin layer on the carrier, the first surface trimming layer, the first conductive pattern, and the via; forming a second conductive pattern and a bump pad on the via and coating a second resin layer on the first resin layer, the second conductive pattern, and the bump pad; removing the carrier from the first surface trimming layer, the first conductive pattern, and the first resin layer; and attaching a semiconductor die to the first surface trimming layer and encapsulating the semiconductor die using an encapsulant.

[0088] Based on all the foregoing, those skilled in the art will determine that, according to another embodiment, the packaged semiconductor device may further include a second surface trimming layer connected to the second conductive structure and exposed to the exterior of the second resin layer, wherein the first surface trimming layer comprises one or more of nickel / gold (Ni / Au), silver (Ag), or copper (Cu); and the second surface trimming layer comprises one or more of nickel / gold (Ni / Au), silver (Ag), or tin (Sn). In another embodiment of the packaged semiconductor device, a semiconductor die may be electrically coupled to the first surface trimming layer in a flip-chip configuration via conductive bumps. In yet another embodiment of the packaged semiconductor device, the semiconductor die is attached to a routeable encapsulated conductive substrate and electrically coupled to the first surface trimming layer via interconnects.

[0089] Based on all the foregoing, those skilled in the art will recognize that, according to another embodiment, in a method of manufacturing a semiconductor device having a routeable encapsulated conductive substrate, providing the routeable encapsulated conductive substrate may include providing a first surface trimming layer comprising copper; and the electrically coupled semiconductor die may include being coupled to conductive bumps in a flip-chip configuration. In another embodiment, the electrically coupled semiconductor die may include being coupled to conductive bumps in a flip-chip configuration.

[0090] In view of all the foregoing, it is evident that a novel method for manufacturing semiconductor packages using routable encapsulated conductive substrates and structures has been disclosed. The routable encapsulated conductive substrate and other features include a first conductive structure encapsulated within a first resin layer, a second conductive structure encapsulated within a second resin layer, and a surface trimming layer disposed on at least a portion of the first conductive structure. The surface trimming layer is exposed in the first resin layer, the first conductive structure is electrically connected to the second conductive structure, and at least a portion of the second conductive structure is exposed outside the second resin layer. A semiconductor die is electrically coupled to the surface trimming layer, and the encapsulation covers both the semiconductor die and the first surface trimming layer. The routable encapsulated conductive substrate facilitates efficient routing of package-level embedded conductive patterns, and the surface trimming layer provides enhanced connectivity reliability between the routable encapsulated conductive substrate and the semiconductor die. Furthermore, the routable encapsulated conductive substrate supports the demand for miniaturized and high-performance electronic devices, supports various interconnect schemes for the next stage of assembly, can be manufactured prior to further assembly steps to shorten manufacturing cycle time, can be easily incorporated into the manufacturing process, and is cost-effective.

[0091] Although the invention has been shown and described with particular reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.

[0092] As reflected in the appended claims, aspects of the invention may lie in less than all of the features of a single disclosed embodiment. Therefore, the appended claims are expressly incorporated herein by reference, wherein each claim is itself an independent embodiment of the invention. Furthermore, while some embodiments described herein include some, but not all, of the other features included in other embodiments, it will be understood by those skilled in the art that combinations of features from different embodiments are intended to be within the scope of the invention and to form different embodiments.

Claims

1. A semiconductor device, characterized in that, It includes: The first lamination includes: The first conductive pattern includes a surface finishing material; A conductive via, which connects to the surface finishing material without an intermediate layer; and A first resin layer covers the first conductive pattern and the conductive via and includes a top side and a bottom side of the first resin layer, wherein the first conductive pattern is exposed from the top side of the first resin layer, wherein a portion of the first conductive pattern does not have the conductive via, and wherein a first surface is present, while the conductive via is exposed from the bottom side of the first resin layer. A second laminate, adjacent to the bottom side of the first resin layer, comprises: The second conductive pattern is connected to the conductive through-hole; Conductive pad, which is connected to the second conductive pattern; and The second resin layer at least partially covers the bottom side of the first resin layer, the second conductive pattern, and the conductive pad, wherein the second conductive pattern and the conductive pad are encapsulated within the second resin layer, and wherein the second resin layer includes a top side and a bottom side, and wherein the lower side of the conductive pad is exposed from the bottom side of the second resin layer. A semiconductor die coupled to the first conductive pattern; and An encapsulation that covers at least a portion of the first laminate and the semiconductor die.

2. The semiconductor device according to claim 1, characterized in that, The surface finishing material includes one or more of nickel / gold (Ni / Au) or silver (Ag).

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a surface trimming layer, the surface trimming layer being connected to the conductive pad at the bottom side of the second resin layer; and The surface finishing layer includes one or more of nickel / gold (Ni / Au), silver (Ag), or tin (Sn).

4. The semiconductor device according to claim 1, characterized in that, The semiconductor die is coupled to the first conductive pattern using conductive bumps.

5. The semiconductor device according to claim 1, characterized in that, The surface of the conductive pad is recessed within the opening in the second resin layer; and The semiconductor device also includes conductive bumps connected to the conductive pad.

6. The semiconductor device according to claim 1, characterized in that, The surface finishing material includes silver (Ag); and The first resin layer, the second resin layer, and the encapsulant comprise a molded compound material.

7. The semiconductor device according to claim 1, characterized in that, The first conductive pattern is coplanar with the outer surface of the first resin layer; and A portion of the second conductive pattern does not have the conductive pad.

8. The semiconductor device according to claim 1, characterized in that, It includes: Adhesive, in: The semiconductor die is attached to a portion of the first conductive pattern and the top side of the first resin layer by the adhesive.

9. A packaged semiconductor device, characterized in that, It includes: Routable encapsulated conductive substrate, comprising: The first conductive structure includes a surface trimming structure and a conductive via that is in contact with the surface trimming structure and has no intermediate layer. A first resin layer encapsulates the first conductive structure; The second conductive structure includes a conductive pattern connected to the conductive via and a conductive pad connected to the conductive pattern; and A second resin layer encapsulates the second conductive structure; Wherein: the conductive pattern and the conductive pad are encapsulated within the second resin layer; the first resin layer includes a top side; the second resin layer includes a bottom side opposite to the top side; the surface trimming structure is exposed from the top side; the conductive pad is exposed from the bottom side; and a portion of the surface trimming structure does not have the conductive via; and a semiconductor die coupled to the surface trimming structure.

10. The packaged semiconductor device according to claim 9, characterized in that, The surface trimming structure is configured as a first conductive pattern; The conductive via is coupled to only a portion of the first conductive pattern; and The conductive via is made of a different material than the first conductive pattern.

11. The packaged semiconductor device according to claim 9, characterized in that, The conductive pad is recessed inward from the bottom side of the second resin layer; and The packaged semiconductor device also includes conductive bumps coupled to the conductive pad.

12. The packaged semiconductor device according to claim 9, characterized in that, Further includes: A surface trimming layer is applied over the conductive pad exposed at the bottom side of the second resin layer.

13. The packaged semiconductor device according to claim 9, characterized in that, The semiconductor die is coupled to the surface trimming structure using conductive bumps.

14. The packaged semiconductor device according to claim 9, characterized in that, Further includes: Encapsulation material that encapsulates the semiconductor die.

15. The packaged semiconductor device according to claim 9, characterized in that, The surface trimming structure and the conductive via are made of different materials.

16. A method for forming a packaged semiconductor device, characterized in that, It includes: A routeable encapsulated conductive substrate is provided, comprising: The first conductive structure includes a surface trimming structure and a conductive via that is in contact with the surface trimming structure and has no intermediate layer. A first resin layer encapsulates the first conductive structure; The second conductive structure includes a conductive pattern connected to the conductive via and a conductive pad connected to the conductive pattern; and A second resin layer encapsulates the second conductive structure; Wherein: the conductive pattern and the conductive pad are encapsulated within the second resin layer; the first resin layer includes a top side; the second resin layer includes a bottom side; the surface trimming structure is exposed from the top side of the first resin layer; the conductive pad is exposed from the bottom side of the second resin layer; and a portion of the surface trimming structure does not have the conductive via; and a semiconductor die is coupled to the surface trimming structure.

17. The method according to claim 16, characterized in that, Further includes: A surface finishing layer is provided on the conductive pad exposed from the bottom side of the second resin layer.

18. The method according to claim 16, characterized in that, include: Provide an encapsulation for encapsulating the semiconductor die.

19. The method according to claim 16, characterized in that, Coupling the semiconductor die includes attaching the semiconductor die with conductive bumps.

20. The method according to claim 16, characterized in that, Further includes: The conductive bump is attached to the conductive pad exposed from the bottom side of the second resin layer.

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