Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate having a cell array region, a first interface region, and a second interface region, the cell array region being provided with an active region; a bit line on the cell array region and the second interface region; a dielectric pattern on a top surface of the bit line and extending along the top surface of the bit line and further extending onto the first interface region; a device isolation pattern on the substrate and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active region, the second portion being provided with a first recess, and each first recess being arranged between two adjacent dielectric patterns; and a first sacrificial semiconductor pattern arranged on the first interface region and in the first recess. The first sacrificial semiconductor pattern includes polysilicon.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0089026, filed on July 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device comprising a sacrificial semiconductor pattern. Background Technology

[0004] Semiconductor devices are beneficial in the electronics industry due to their small size, multifunctionality, and / or low manufacturing cost. With the development of the electronics industry, the integration level of semiconductor devices is becoming increasingly higher. To achieve high integration, the linewidth of the patterns in semiconductor devices needs to be reduced. However, new and / or expensive exposure techniques are required to form finer patterns, making it difficult to highly integrate semiconductor devices. Therefore, various studies on new integration technologies have been conducted recently. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor memory device with enhanced reliability.

[0006] Those skilled in the art will clearly understand the inventive concept from the following description.

[0007] According to an embodiment of the present invention, a semiconductor memory device includes: a substrate having a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, the cell array region having a plurality of active regions extending in a first direction; a plurality of bit lines located on the cell array region and the second interface region, the plurality of bit lines extending in a second direction intersecting the first direction; a plurality of dielectric patterns located on the top surface of the plurality of bit lines, the plurality of dielectric patterns extending along the top surface of the plurality of bit lines in the second direction and further extending into the first interface region; a device isolation pattern located on the substrate, the device isolation pattern including a first portion on the cell array region and a second portion on the first interface region, the first portion of the device isolation pattern defining the plurality of active regions, the second portion of the device isolation pattern having a plurality of first recesses, and each of the plurality of first recesses being disposed between two adjacent dielectric patterns of the plurality of dielectric patterns disposed on the first interface region when the semiconductor memory device is viewed in a plan view; and a plurality of first sacrificial semiconductor patterns disposed on the first interface region and disposed in the plurality of first recesses of the device isolation pattern. The plurality of first sacrificial semiconductor patterns include polycrystalline silicon.

[0008] According to an embodiment of the present invention, a semiconductor memory device includes: a substrate having a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, the cell array region having a plurality of active regions extending in a first direction; a plurality of bit lines located on the cell array region and the second interface region, the plurality of bit lines extending in a second direction different from the first direction; a plurality of word lines located on the substrate, the plurality of word lines extending in a third direction perpendicular to the second direction, the first direction, the second direction, and the third direction being in the same plane; a plurality of insulating barriers spaced apart from each other on the plurality of word lines in the third direction, the plurality of insulating barriers and the plurality of bit lines being arranged alternately and repeatedly in the third direction; and a plurality of first sacrificial semiconductor patterns disposed on the first interface region, the plurality of first sacrificial semiconductor patterns and the plurality of insulating barriers being arranged alternately and repeatedly in the second direction, and the plurality of first sacrificial semiconductor patterns comprising polysilicon.

[0009] According to an embodiment of the present invention, a semiconductor memory device includes: a substrate having a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, the cell array region having a plurality of active regions extending in a first direction; a plurality of bit lines located on the cell array region and the second interface region, the plurality of bit lines extending in a second direction intersecting the first direction; a plurality of word lines disposed on the plurality of active regions, the plurality of word lines extending in a third direction perpendicular to the second direction, the first direction, the second direction, and the third direction being in the same plane; a plurality of dielectric patterns located on the top surface of the plurality of bit lines, the plurality of dielectric patterns extending along the top surface of the plurality of bit lines and also extending to the first interface region; and a plurality of spacer structures located on the plurality of active regions. On opposite sidewalls of the dielectric pattern, each of the plurality of spacer structures includes a first spacer, a second spacer, and an air gap between the first and second spacers; a device isolation pattern located on a substrate, the device isolation pattern including a first portion on a cell array region and a second portion on a first interface region, the first portion of the device isolation pattern defining the plurality of active regions, and the second portion of the device isolation pattern having a plurality of recesses; a plurality of first sacrificial semiconductor patterns in the plurality of recesses of the device isolation pattern on the first interface region, the plurality of first sacrificial semiconductor patterns including polysilicon; a diffusion destruction pattern covering the plurality of dielectric patterns and the plurality of spacer structures; a plurality of landing pads located on the diffusion destruction pattern; and a plurality of bottom electrodes located on the plurality of landing pads. Attached Figure Description

[0010] Figure 1A A plan view of a semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0011] Figure 1B Show along Figure 1A The sectional view taken from lines I-I' and II-II'.

[0012] Figure 1C Show along Figure 1A The sectional view taken from lines III-III' and IV-IV'.

[0013] Figures 2A to 10A A plan view showing a method of manufacturing a semiconductor memory device according to some example embodiments of the concept of the present invention is shown.

[0014] Figures 2B to 10B Show along Figures 2A to 10A The sectional view taken from lines I-I' and II-II'.

[0015] Figures 2C to 10C Show along Figures 2A to 10A The sectional view taken from lines III-III' and IV-IV'. Detailed Implementation

[0016] In this specification, the same reference numerals may refer to the same elements. Semiconductor memory devices according to some exemplary embodiments of the present invention will now be described.

[0017] Figure 1A A plan view of a semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 1B Show along Figure 1A The sectional view taken from lines I-I' and II-II'. Figure 1C Show along Figure 1A The sectional view taken from lines III-III' and IV-IV'.

[0018] Reference Figures 1A to 1C A substrate 100 may be provided. The substrate 100 may have a cell array region CAR and an interface region INT adjacent to the cell array region CAR. The interface region INT may be located between the cell array region CAR and a peripheral circuit region (not shown). When the semiconductor device is viewed in a plan view (or top view), the interface region INT may surround the cell array region CAR. The cell array region CAR may have an active segment ACT (i.e., an active region). The interface region INT does not have an active segment ACT. The interface region INT may include a first interface region INT1 and a second interface region INT2. The second interface region INT2 may be located between the first interface region INT1 and the cell array region CAR.

[0019] Device isolation pattern 102 may be formed on the cell array region CAR of substrate 100. Device isolation pattern 102 may include or be formed of a dielectric material. For example, device isolation pattern 102 may include or be formed of silicon oxide. On cell array region CAR, device isolation pattern 102 may define active segments ACT of substrate 100. When viewed in plan view of a semiconductor device, device isolation pattern 102 may isolate the active segments ACT from each other. When viewed in plan view of a semiconductor device, each of the active segments ACT may have a stripe extending in a first direction D1. The active segment ACT may be a portion of substrate 100 surrounded by device isolation pattern 102.

[0020] Device isolation pattern 102 may be arranged on interface region INT1. On first interface region INT1, device isolation pattern 102 may have a plurality of second recesses GRV2. Second recesses GRV2 may extend along a second direction D2 parallel to dielectric pattern 137. Second recesses GRV2 may be arranged in a third direction D3, spaced apart from each other. Second recesses GRV2 may be arranged across dielectric pattern 137, spaced apart from each other. Second recesses GRV2 and dielectric pattern 137 may be arranged alternately in the third direction D3. The width of second recesses GRV2 may decrease as it approaches the top surface of substrate 100. The top surface of device isolation pattern 102 may be higher on first interface region INT1 than on second interface region INT2. Designations such as "first," "second," "third," etc., may be simply used as labels for specific elements, steps, etc., to distinguish them from each other. In the specification, terms not described using "first," "second," "third," etc., may still be referred to as "first" or "second" in the claims. In addition, terms referenced with a specific number (e.g., “first” in a particular claim) may be described elsewhere with a different number (e.g., “second” in the specification or another claim).

[0021] Substrate 100 may include or be formed of a semiconductor material. For example, substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Device isolation pattern 102 may include or be formed of one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride). One of the active segments ACT may be arranged adjacent to the center of other neighboring active segments ACT.

[0022] Word lines WL can be disposed on the cell array region CAR and the interface region INT of the substrate 100. Word lines WL can extend in a third direction D3 intersecting the first direction D1. On the cell array region CAR, word lines WL can extend across an active segment ACT. For example, a pair of word lines WL can be disposed on an active segment ACT. Word lines WL can be disposed in a first recess GRV1 defined by the device isolation pattern 102 and the active segment ACT. In an embodiment, each of the first recesses GRV1 can be a trench extending in the third direction D3. Word lines WL can comprise or be formed of a conductive material. For example, word lines WL can comprise polysilicon, doped polysilicon, metal, or metal silicide, or can be formed of polysilicon, doped polysilicon, metal, or metal silicide. A dielectric layer 107 can be disposed between the inner wall of the first recess GRV1 and each word line WL. The dielectric layer 107 may include one or more of thermal oxides, silicon nitride, silicon oxynitride, and high-k dielectrics, or may be formed of one or more of thermal oxides, silicon nitride, silicon oxynitride, and high-k dielectrics. The word line WL may have an uneven bottom surface (e.g., a corrugated bottom surface). See below for further details. Figure 2A , Figure 2B and Figure 2C Describe the formation of the uneven bottom surface of the character line WL.

[0023] A first impurity region 112a and a pair of second impurity regions 112b can be disposed on the cell array region CAR. The first impurity region 112a can be arranged in each active segment ACT between a pair of word lines WL. The pair of second impurity regions 112b can be arranged at opposite ends of each active segment ACT. For example, the first impurity region 112a and the second impurity region 112b can be doped with N-type impurities. The first impurity region 112a can correspond to a common drain region, and the second impurity region 112b can correspond to a source region. The transistor can be composed of each word line WL and its adjacent first impurity region 112a and second impurity region 112b. Since the word line WL is arranged in the first recess GRV1, the length of the channel below the word line WL can be increased. Therefore, the short-channel effect can be reduced or minimized.

[0024] The top surface of the word line WL may be at a lower horizontal height than the top surface of the active segment ACT. A word line capping pattern 110 may be disposed on the corresponding word line WL. The word line capping pattern 110 may have a linear shape extending along the length direction of the word line WL (e.g., third direction D3). The word line capping pattern 110 may cover the entire top surface of the word line WL. The top surface of the word line capping pattern 110 may be at the same horizontal height as the top surface of the substrate 100. In an embodiment, the top surface of the word line capping pattern 110 may be at the same horizontal height as the top surfaces of the first impurity region 112a and the second impurity region 112b disposed on the substrate 100. The word line capping pattern 110 may comprise or be formed of a dielectric material. For example, the word line capping pattern 110 may comprise or be formed of silicon oxide or silicon nitride.

[0025] An interlayer dielectric pattern 5 may be arranged on the substrate 100. The interlayer dielectric pattern 5 may be formed of a single layer or multiple layers, including at least one selected from silicon oxide, silicon nitride, and silicon oxynitride layers. When viewed in plan view of the semiconductor device, the interlayer dielectric pattern 5 may be formed as islands spaced apart from each other. The interlayer dielectric pattern 5 may cover the ends of two adjacent active segments ACT. The substrate 100, the device isolation pattern 102, and the word line capping pattern 110 may be partially recessed to provide a third recess 7. When viewed in plan view of the semiconductor device, the third recess 7 may have a mesh-like shape.

[0026] A second contact DC can be disposed on the cell array region CAR. The second contact DC can be disposed in a portion of the active segment ACT of the substrate 100 between a pair of word lines WL. The second contact DC can be disposed in a third recess 7. The second contact DC can pass through the interlayer dielectric pattern 5 and can be electrically connected to a first impurity region 112a disposed in a portion of the active segment ACT of the substrate 100. The bottom surface of the second contact DC can be at a higher horizontal height than the top surface of the word line WL. Therefore, the second contact DC can electrically connect the first impurity region 112a to the bit line BL, which will be discussed below, without contacting the word line WL. The second contact DC can comprise or be formed of a conductive material. For example, the second contact DC can comprise or be formed of a polycrystalline material doped with impurities. It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or "located" "on" another element, it can be directly connected to or coupled to another element or located on another element, or there may be intermediate elements present. Conversely, when a component is referred to as being "directly connected to" or "directly coupled to" another component, or "in contact with" or "in contact with another component," there is no intermediate component in terms of contact.

[0027] Bit lines BL can be arranged on the cell array region CAR and the second interface region INT2 of substrate 100. Bit lines BL are not arranged on the first interface region INT1. For example, the second interface region INT2 may correspond to the region of substrate 100 between the distal end of the cell array region CAR and the distal end of the bit line BL extending from the cell array region CAR. In an embodiment, the second interface region INT2 may correspond to the region of substrate 100 where the bit line BL is arranged without the active segment ACT. Bit lines BL may be arranged on the interlayer dielectric pattern 5. Bit lines BL may extend across the word line capping pattern 110 and the word line WL. For example, as... Figure 1A As shown, bit line BL can extend in a second direction D2 that intersects the first direction D1 and the third direction D3. Bit line BL can extend to a plurality of second contacts DC arranged in the second direction D2. Bit line BL can be electrically connected to the second contacts DC. The first direction D1, the second direction D2, and the third direction D3 can be in the same plane parallel to the bottom surface of the substrate 100.

[0028] Bit lines BL may each include a first conductive pattern 130, a second conductive pattern 131, and a third conductive pattern 132 stacked in sequence. The first conductive pattern 130 may include or be formed of doped or undoped polysilicon. The second conductive pattern 131 may include or be formed of a metal silicide layer. The third conductive pattern 132 may include or be formed of a metal or a conductive metal nitride. For example, the metal may include one or more of tungsten, titanium, tantalum, aluminum, copper, nickel, and cobalt, and the conductive metal nitride may include one or more of titanium nitride, tantalum nitride, and tungsten nitride.

[0029] A dielectric pattern 137 may be disposed on a corresponding bit line BL. The dielectric pattern 137 may extend along the bit line BL in a second direction D2 and may cover the top surface of the bit line BL. The dielectric pattern 137 may extend from the cell array region CAR to the second interface region INT2 and the first interface region INT1. The dielectric pattern 137 may comprise or be formed of a dielectric material. For example, the dielectric pattern 137 may comprise one or more of nitrides and oxides of nitrides, or may be formed of one or more of nitrides and oxynitrides. For example, the nitride may comprise silicon nitride, and the oxide of nitride may comprise silicon oxynitride.

[0030] When viewed in a plan view, the semiconductor device may include a first component 137L overlapping the word line WL and a second component 137H not overlapping the word line WL. The first component 137L and the second component 137H may be connected to each other, and therefore may have indistinguishable boundaries between them. Figure 1BAs shown, the first component 137L and the second component 137H of the dielectric pattern 137 may have different heights from each other. For example, as Figure 1B As shown, the height H3 of the second component 137H of the dielectric pattern 137 can be greater than the height H4 of the first component 137L of the dielectric pattern 137. On the second interface region INT2, the recess R of the dielectric pattern 137 can expose the top surface of the bit line BL. When viewing the semiconductor device in a plan view, the recess R can overlap with the bit line BL. The recesses R can be spaced apart from each other in the third direction D3. On the first interface region INT1, the dielectric pattern 137 can be arranged on the device isolation pattern 102. For example, the dielectric pattern 137 can be arranged on the top surface of the device isolation pattern 102 between the second recesses GRV2. The height of the dielectric pattern 137 on the first interface region INT1 can be less than its height on the second interface region INT2.

[0031] Cell embedded dielectric patterns 141 can be arranged on the cell array region CAR. For example, the cell embedded dielectric pattern 141 can be arranged in the third recess 7. The cell embedded dielectric pattern 141 can fill the space between the second contact DC and the inner wall of the third recess 7. The cell embedded dielectric pattern 141 can be formed of a single layer or multiple layers, including at least one selected from silicon oxide, silicon nitride, and silicon oxynitride layers. Although not shown, a cell dielectric liner can be interposed between the cell embedded dielectric pattern 141 and the inner wall of the third recess 7 and between the cell embedded dielectric pattern 141 and the second contact DC. The cell dielectric liner can include a dielectric material with etch selectivity relative to the cell embedded dielectric pattern 141. For example, the cell embedded dielectric pattern 141 can include or be formed of a silicon nitride layer, and the cell dielectric liner can include or be formed of a silicon oxide layer.

[0032] The first contact BC may be disposed on the cell array region CAR of the substrate 100. The first contact BC may not be disposed on the first interface region INT1 or the second interface region INT2 of the substrate 100. For example, the first contact BC may be disposed between a pair of adjacent bit lines BL. The first contact BC may be arranged to be spaced apart from each other in the second direction D2 and the third direction D3. A plurality of first contacts BC may be arranged in the second direction D2 and the third direction D3. The lower portion of the first contact BC may be buried in the active segment ACT of the substrate 100. The first contact BC may be electrically connected to the second impurity region 112b disposed at the end of the active segment ACT. The first contact BC may comprise impurity-doped polysilicon or undoped polysilicon, or may be formed from impurity-doped polysilicon or undoped polysilicon.

[0033] An insulating barrier 40 may be disposed on a substrate 100. The insulating barrier 40 may be disposed on the cell array region CAR, the first interface region INT1, and the second interface region INT2 of the substrate 100. The insulating barrier 40 may be disposed between the first contacts BC. When the semiconductor device is viewed in a plan view, the insulating barrier 40 may overlap with the word line WL. On the cell array region CAR, the insulating barrier 40 and the first contacts BC may be arranged alternately along a second direction D2. For example, on the cell array region CAR, the first contacts BC and the insulating barrier 40 may be arranged alternately and repeatedly along the sidewalls of the bit line BL in the second direction D2. The insulating barrier 40 may comprise or be formed of a dielectric material. For example, the dielectric material may comprise or be formed of silicon nitride, silicon oxide, or silicon oxynitride. The height (horizontal height) of the top of the insulating barrier 40 may be greater than the height of the top of the first contact BC.

[0034] Reference Figure 1B and Figure 1C The spacer structure SP can be correspondingly arranged on the sidewall of the bit line BL. The spacer structure SP can extend along the bit line BL in the second direction D2. The spacer structure SP can extend toward the first interface region INT1 beyond the far end of the bit line BL. Therefore, the spacer structure SP can be arranged on both the interface region INT and the cell array region CAR of the substrate 100.

[0035] The spacer structure SP may each include a first spacer 21, an air gap AG, and a second spacer 25. The first spacer 21 and the second spacer 25 may be located between the first contact BC and the bit line BL. On the cell array region CAR and the second interface region INT2 of the substrate 100, the first spacer 21 may cover the sidewalls of the dielectric pattern 137 and the sidewalls of the bit line BL. The second spacer 25 may be adjacent to the first contact BC. The first spacer 21 may be spaced apart from the second spacer 25. The air gap AG may be arranged between the first spacer 21 and the second spacer 25. The first spacer 21, the air gap AG, and the second spacer 25 may extend along the side surface (i.e., sidewall) of the bit line BL, thereby being located between the bit line BL and the insulating fence 40. The height (horizontal height) of the top of the air gap AG may be higher than the top of the top surface of the bit line BL.

[0036] On the cell array region CAR, the bottom surface of the second spacer 25 may be lower than the bottom surface of the first spacer 21. The height (horizontal height) of the top of the second spacer 25 may be lower than the height of the top of the first spacer 21. Therefore, the first spacer 21 may have an exposed upper sidewall. This increases the formation margin of the landing pad LP, which will be described below, and aids in the connection between the landing pad LP and the first contact BC. The first spacer 21 may extend to cover the sidewall of the second contact DC and the sidewall and bottom surface of the third recess 7. For example, the first spacer 21 may be positioned between the second contact DC and the cell buried dielectric pattern 141, between the word line capping pattern 110 and the cell buried dielectric pattern 141, between the substrate 100 and the cell buried dielectric pattern 141, and between the device isolation pattern 102 and the cell buried dielectric pattern 141.

[0037] On the first interface region INT1, the first spacer 21 may cover the sidewalls of the dielectric pattern 137 and the sidewalls of the second recess GRV2. The second spacer 25 may be configured to span the air gap AG and be spaced apart from the first spacer 21. On the second interface region INT2, the bottom surfaces of the first spacer 21 and the second spacer 25 may be at the same horizontal height. The top surface of the second spacer 25 may cover the sidewalls of the dielectric pattern 137 and the sidewalls of the bit line BL. Between the separation patterns 144, the height of the first spacer 21 may be greater than the height of the second spacer 25. The first spacer 21 and the second spacer 25 may comprise the same material or may be formed of the same material. For example, the first spacer 21 and the second spacer 25 may comprise a silicon nitride layer or may be formed of a silicon nitride layer.

[0038] A memory node ohmic layer 9 may be disposed on the first contact BC. The memory node ohmic layer 9 may include or may be formed of a metal silicide. A diffusion destruction pattern 11 may be disposed on the substrate 100. On the cell array region CAR, the diffusion destruction pattern 11 may conformally cover the memory node ohmic layer 9 and the first spacer 21 and the second spacer 25. On the first interface region INT1, the diffusion destruction pattern 11 may conformally cover the spacer structure SP, the top surface of the dielectric pattern 137, and the top surface 32a of the first sacrificial semiconductor pattern 32, which will be discussed below. On the second interface region INT2, the diffusion destruction pattern 11 may conformally cover the spacer structure SP, the inner wall of the recess R, the top surface of the bit line BL exposed in the recess R, and the top surface of the second sacrificial semiconductor pattern 34, which will be discussed below. The diffusion destruction pattern 11 may include or may be formed of a metal nitride, such as a titanium nitride layer or a tantalum nitride layer.

[0039] Landing pads LP can be disposed on the cell array region CAR and interface region INT of substrate 100. Landing pads LP can be disposed on diffusion-damping pattern 11. The top surfaces of landing pads LP can be at the same horizontal level. Landing pads LP can comprise, for example, a metallic material of tungsten or can be formed of a metallic material. Landing pads LP can be spaced apart from each other across separation pattern 144. On cell array region CAR, the upper portion of landing pads LP can cover the corresponding top surface of dielectric pattern 137. The width of the top surface of landing pads LP can be greater than the width of the top surface of the first contact BC. The center of landing pads LP can not be vertically aligned with the center of the first contact BC. Landing pads LP can partially cover insulating fence 40. A portion of bit line BL can be vertically aligned with landing pads LP.

[0040] On the first interface region INT1, a landing pad LP can be arranged on the diffusion destruction pattern 11. The landing pad LP can extend into and fill the second recess GRV2. The upper part of the landing pad LP can cover the upper part of the dielectric pattern 137. On the second interface region INT2, the landing pad LP can be arranged on the diffusion destruction pattern 11. One LPa of the landing pad LP can extend into and fill the recess R. In this case, the landing pad LPa can be electrically connected to the exposed bit line BL.

[0041] Separator pattern 144 may be arranged between landing pads LP. Separator pattern 144 may electrically insulate the landing pads LP from each other. Separator pattern 144 may include or be formed of a dielectric material. For example, separator pattern 144 may include or be formed of one or more of silicon oxide and silicon nitride. The top surface of separator pattern 144 may be coplanar with the top surface of landing pad LP. Separator pattern 144 may define the planar shape of landing pad LP.

[0042] On the cell array region CAR, data storage elements (e.g., capacitors) may be arranged on landing pads LP. Each of the data storage elements may include a bottom electrode BE, a dielectric layer, and a top electrode. When the semiconductor device is viewed in a plan view, the bottom electrode BE may overlap with the landing pad LP. The bottom electrode BE and the first contact BC may be electrically connected to each other via the landing pad LP.

[0043] The first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34 may be disposed on the interface region INT of the substrate 100. For example, the first sacrificial semiconductor pattern 32 may be disposed on the first interface region INT1, and the second sacrificial semiconductor pattern 34 may be disposed on the second interface region INT2. The first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34 may comprise or be formed of polysilicon. For example, the first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34 may comprise or be formed of undoped polysilicon. However, the inventive concept is not limited thereto, and the first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34 may comprise or be formed of various materials having etch selectivity relative to silicon oxide.

[0044] On the first interface region INT1, a first sacrificial semiconductor pattern 32 may be disposed in the second recess GRV2. As the width of the second recess GRV2 decreases with approach to the top surface of the substrate 100, the width W1 of the first sacrificial semiconductor pattern 32 may also decrease with approach to the top surface of the substrate 100. Therefore, when the semiconductor device is viewed in cross-sectional view, the first sacrificial semiconductor pattern 32 may have a generally triangular shape. Each of the first sacrificial semiconductor patterns 32 may have a range of approximately to approximately The height H1. A value of about 0.3 to about 0.8 can be given as the ratio of the height H1 of the first sacrificial semiconductor pattern 32 to the height of the second recess GRV2. When viewed in a plan view of the semiconductor device, the first sacrificial semiconductor pattern 32 may be spaced apart from each other across the dielectric pattern 137 in a third direction D3. The first sacrificial semiconductor pattern 32 and the dielectric pattern 137 may be arranged alternately and repeatedly along the third direction D3. The first sacrificial semiconductor pattern 32 may be spaced apart from each other across the insulating barrier 40 in a second direction D2. The first sacrificial semiconductor pattern 32 and the insulating barrier 40 may be arranged alternately and repeatedly along the second direction D2. Terms such as “about” or “approximately” can reflect an amount, size, orientation, or layout that varies only in a relatively small way and / or in a way that does not significantly alter the operation, function, or structure of a particular element. For example, a range of “about 0.1 to about 1” can cover a range of deviations such as 0%-5% for about 0.1 and 0%-5% for about 1, especially where such deviations maintain the same effect as the listed ranges. When referring to orientation, layout, location, shape, size, quantity, or other measurement, terms such as “identical,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean completely identical orientation, layout, location, shape, size, quantity, or other measurement, but are intended to include substantially identical orientation, layout, location, shape, size, quantity, or other measurement within permissible variations, for example, that may result from manufacturing processes. Unless the context or other description indicates otherwise, the term “substantially” may be used herein to emphasize this meaning. For example, terms described as “substantially identical,” “substantially equal,” or “substantially planar” may mean completely identical, equal, or planar, or may mean identical, equal, or planar within permissible variations, for example, that may result from manufacturing processes.

[0045] On the second interface region INT2, a second sacrificial semiconductor pattern 34 may be arranged on the interlayer dielectric pattern 5. For example, the second sacrificial semiconductor pattern 34 may be correspondingly arranged between spacer structures SP. The upper width W2 of the second sacrificial semiconductor pattern 34 may be substantially the same as the lower width W2. The width W2 of the second sacrificial semiconductor pattern 34 may be greater than the width W1 of the first sacrificial semiconductor pattern 32. The top surface 34a of the second sacrificial semiconductor pattern 34 may be at the same horizontal height as the top surface 32a of the first sacrificial semiconductor pattern 32. The bottom surface of the second sacrificial semiconductor pattern 34 may be at a higher horizontal height than the lowermost part of the first sacrificial semiconductor pattern 32. When viewing the semiconductor device in a plan view, the second sacrificial semiconductor pattern 34 may be arranged to be spaced apart from each other across the bit line BL in the third direction D3. The second sacrificial semiconductor pattern 34 and the bit line BL may be arranged alternately and repeatedly along the third direction D3. The second sacrificial semiconductor pattern 34 may be arranged to be spaced apart from each other across the insulating barrier 40 in the second direction D2. The second sacrificial semiconductor pattern 34 and the insulating fence 40 may be arranged alternately and repeatedly along the second direction D2. The sidewalls of the second sacrificial semiconductor pattern 34 may be vertically aligned with the sidewalls of the spacer structure SP.

[0046] [Manufacturing Method]

[0047] Figures 2A to 10A A plan view showing a method of manufacturing a semiconductor memory device according to some example embodiments of the concept of the present invention is shown. Figures 2B to 10B Show along Figures 2A to 10A The sectional view taken from lines I-I' and II-II'. Figures 2C to 10C Show along Figures 2A to 10A The sectional view taken from lines III-III' and IV-IV'.

[0048] Reference Figures 2A to 2CA substrate 100 may be provided with a cell array region CAR, a first interface region INT1, and a second interface region INT2. An active segment ACT may be provided on the substrate 100 and may be defined by a device isolation pattern 102 on the cell array region CAR of the substrate 100. The device isolation pattern 102 may cover both the first interface region INT1 and the second interface region INT2 of the substrate 100. The active segment ACT may not be formed on either the first interface region INT1 or the second interface region INT2. For example, a trench may be formed on the cell array region CAR of the substrate 100. The device isolation pattern 102 may fill the trench. The device isolation pattern 102 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or may be formed from one or more of them. When viewed in a plan view of the semiconductor device, the active segments ACT may be arranged parallel to each other in a first direction D1. The active segments ACT and the device isolation pattern 102 on the cell array region CAR may be patterned to form a first recess GRV1 in which a word line WL will be formed. In an embodiment, each of the first recesses GRV1 may be a trench extending in the third direction D3. When forming the first recesses GRV1, the etching conditions of the substrate 100 and the device isolation pattern 102 may be adjusted to allow the device isolation pattern 102 to be etched (or recessed) further than the substrate 100. Therefore, the first recesses GRV1 may have an uneven bottom surface. In an embodiment, each first recess GRV1 may have a bottom surface defined by the top surface of the recessed active segment ACT and the top surface of the recessed device isolation pattern 102. The top surface of the device isolation pattern 102 in the first recesses GRV1 may be recessed further than the top surface of the active segment ACT in the recess, thereby forming an uneven (e.g., corrugated) bottom surface of each first recess GRV1.

[0049] Word lines WL can be formed on the cell array region CAR, the first interface region INT1, and the second interface region INT2 of the substrate 100. The word lines WL can extend across the active segment ACT. A pair of word lines WL can extend across each of the active segments ACT. For example... Figure 2B As shown, a pair of word lines WL can divide each of the active segments ACT into a first source / drain region SDR1 and a pair of second source / drain regions SDR2. The first source / drain region SDR1 can be defined between the pair of word lines WL, and the pair of second source / drain regions SDR2 can be defined at opposite ends of each of the active segments ACT.

[0050] Before forming the word line WL, a dielectric layer 107 may be formed on the inner wall and bottom surface of the first recess GRV1. The dielectric layer 107 may be formed by one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition. The dielectric layer 107 may be formed of one or more dielectric materials such as silicon oxide, silicon nitride, and metal oxide. A gate conductive layer may be formed to fill the first recess GRV1, and then the gate conductive layer may be etched to form the word line WL. The gate conductive layer may be formed of one or more of, for example, doped polysilicon, metal nitride, and metal. The word line WL may be recessed to have a top surface lower than the top surface of the active segment ACT. The word line WL may be formed to extend in a third direction D3 intersecting the first direction D1. A dielectric layer such as silicon nitride may be formed on the substrate 100 to fill the first recess GRV1, and then the dielectric layer may be etched to form a word line capping pattern 110 on the corresponding word line WL. The word line capping pattern 110 may extend in the third direction D3. The stacked structure of the letter line WL and the letter line cover pattern 110 can fill the first recess GRV1.

[0051] Reference Figures 3A to 3C The word line capping pattern 110 and the device isolation pattern 102 can be used as masks to incorporate impurities into the active segment ACT. Therefore, a first impurity region 112a and a second impurity region 112b can be formed in the active segment ACT. These can be respectively... Figure 2B A first impurity region 112a and a second impurity region 112b are formed in the first source / drain region SDR1 and the second source / drain region SDR2.

[0052] A dielectric layer can be formed on the entire surface of the cell array region CAR, the first interface region INT1, and the second interface region INT2 of the substrate 100. The dielectric layer can be patterned to form an interlayer dielectric pattern 5 that exposes portions of the word line capping pattern 110, portions of the active segment ACT, and portions of the device isolation pattern 102. A third recess 7 can be formed on the cell array region CAR of the substrate 100. The third recess 7 is not formed on the interface region INT of the substrate 100. Forming the third recess 7 may include etching the device isolation pattern 102, the substrate 100, and the word line capping pattern 110 using the interlayer dielectric pattern 5 as an etching mask. The interlayer dielectric pattern 5 may be a single layer or multiple layers including one or more of silicon oxide, silicon nitride, and silicon oxynitride layers. The interlayer dielectric pattern 5 may be formed having multiple islands spaced apart from each other. The interlayer dielectric pattern 5 may be formed to simultaneously cover the ends of two adjacent active segments ACT. The third recess 7 may be formed with a mesh pattern in a planar view. When viewing the semiconductor device in a plan view, the third recess 7 can be the area other than the interlayer dielectric pattern 5. The third recess 7 can expose the first impurity region 112a.

[0053] A polysilicon layer can be formed on the entire surface of the substrate 100 to fill the third recess 7. A planar etching process can then be performed on the polysilicon layer. This planar etching process removes the polysilicon layer on the interlayer dielectric pattern 5 to expose the top surface of the interlayer dielectric pattern 5. Therefore, a first polysilicon pattern 129 can be formed to fill the third recess 7.

[0054] Reference Figures 4A to 4C A first conductive layer 130a, a second conductive layer 131a, and a third conductive layer 132a may be formed sequentially on the interlayer dielectric pattern 5 and the first polysilicon pattern 129. The first conductive layer 130a, the second conductive layer 131a, and the third conductive layer 132a may be formed on the entire surface of the cell array region CAR, the first interface region INT1, and the second interface region INT2 of the substrate 100. The first conductive layer 130a may comprise or be formed from doped polysilicon. The second conductive layer 131a may comprise or be formed from a metal silicide such as cobalt silicide. The second conductive layer 131a may be formed by the following steps: depositing a metal layer on the first conductive layer 130a and the first polysilicon pattern 129; and subsequently performing an annealing process. The annealing process may be performed such that the first conductive layer 130a and the first polysilicon pattern 129 may react with the metal layer to form a metal silicide layer. Unreacted metal layers can be removed to form a second conductive layer 131a.

[0055] On the first interface region INT1, the interlayer dielectric pattern 5, the first conductive layer 130a, the second conductive layer 131a, and the third conductive layer 132a can be removed to expose the top surface of the device isolation pattern 102. A dielectric layer can be formed on the exposed top surface of the device isolation pattern 102. The dielectric layer may include the same material as the device isolation pattern 102. Therefore, the dielectric layer and the device isolation pattern 102 are exposed to allow the device isolation pattern 102 to have a raised top surface. Then, an initial dielectric pattern layer 137a can be formed on the entire surface of the cell array region CAR, the first interface region INT1, and the second interface region INT2 of the substrate 100. A planarization process can be performed on the top surface of the initial dielectric pattern layer 137a, and thus the top surface of the initial dielectric pattern layer 137a on the cell array region CAR can be at the same horizontal height as the top surface of the initial dielectric pattern layer 137a on the interface region INT.

[0056] A first mask pattern 139 may be formed on the initial dielectric pattern layer 137a to define the planar shape of the bit line BL, which will be discussed below. The first mask pattern 139 may be formed of a material such as an amorphous carbon layer (ACL), a silicon oxide layer, or a photoresist pattern that has etch selectivity relative to the initial dielectric pattern layer 137a. The first mask pattern 139 may extend in a second direction D2 intersecting the first direction D1 and the third direction D3.

[0057] Reference Figures 5A to 5C On the cell array region CAR and the second interface region INT2, the first mask pattern 139 can be used as an etching mask to sequentially etch the initial dielectric pattern layer 137a, the third conductive layer 132a, the second conductive layer 131a, the first conductive layer 130a, and the first polysilicon pattern 129. Thus, the dielectric pattern 137, the second contact DC, and the bit line BL can be formed. Each bit line BL may include the first conductive pattern 130, the second conductive pattern 131, and the third conductive pattern 132. The interlayer dielectric pattern 5 may have a partially exposed top surface, and the third recess 7 may have partially exposed inner walls and a bottom surface. On the first interface region INT1, the first mask pattern 139 can be used as an etching mask to etch the initial dielectric pattern layer 137a and the device isolation pattern 102. Thus, the device isolation pattern 102 may have a second recess GRV2, and the dielectric pattern 137 can be formed on the device isolation pattern 102. The width of the second recess GRV2 can decrease as it approaches the top surface of the substrate 100. Then, the first mask pattern 139 can be removed.

[0058] Reference Figures 6A to 6CA first spacer layer can be conformally formed on the entire surface of the cell array region CAR and the interface region INT of the substrate 100. On the cell array region CAR, the first spacer layer conformally covers the bottom surface and inner wall of the third recess 7. On the second interface region INT2, the first spacer layer covers the side surface of the bit line BL, the top surface of the interlayer dielectric pattern 5, and the side and top surfaces of the dielectric pattern 137. On the first interface region INT1, the first spacer layer covers the inner wall of the second recess GRV2 and the top and side surfaces of the dielectric pattern 137. For example, the first spacer layer can be a silicon nitride layer. A dielectric layer, such as a silicon nitride layer, can be formed on the cell array region CAR of the substrate 100 to fill the third recess 7, and then the dielectric layer can be anisotropically etched to form a cell buried dielectric pattern 141 in the third recess 7. In this step, the first spacer layer can also be etched to form a first spacer 21 on the cell array region CAR and the interface region INT. Therefore, the top surface of the interlayer dielectric pattern 5 can be exposed. A sacrificial spacer layer can be conformally formed over the entire surface of the substrate 100, and then anisotropically etched to form a sacrificial spacer 23 covering the sidewalls of the first spacer 21. The sacrificial spacer 23 can be formed of a material such as a silicon oxide layer that has etch selectivity relative to the first spacer 21. A second spacer 25 can be formed to cover the sidewalls of the sacrificial spacer 23. The second spacer 25 can be formed of, for example, a silicon nitride layer. The top surface of the interlayer dielectric pattern 5 can be exposed after the formation of the second spacer 25.

[0059] Reference Figures 7A to 7C A sacrificial layer may be formed over the entire surface of substrate 100, and then the sacrificial layer may be patterned to form a sacrificial semiconductor pattern 30 defining a portion of the first contact BC, which will be discussed below. In this step, a first opening 31 may be formed between the sacrificial semiconductor patterns 30. The sacrificial layer may comprise a material having etch selectivity relative to the sacrificial spacer 23. For example, the sacrificial layer may comprise or be formed of polysilicon. More specifically, the sacrificial layer may comprise undoped polysilicon. The sacrificial semiconductor patterns 30 may be formed to be spaced apart from each other between bit lines BL. The sacrificial semiconductor patterns 30 may vertically overlap with the second impurity region 112b. A first opening 31 defining the location of the insulating barrier 40, which will be discussed below, may be provided between the sacrificial semiconductor patterns 30. The first opening 31 may vertically overlap with the word line WL. The first opening 31 may expose the top surfaces of the cell buried dielectric pattern 141 and the interlayer dielectric pattern 5. Although partial etching is performed on the upper parts of the first spacer 21, sacrificial spacer 23 and second spacer 25 exposed to the first opening 31 during the patterning process of the sacrificial layer, damage to the first spacer 21, sacrificial spacer 23 and second spacer 25 can be avoided by controlling the etching conditions and taking into account the load effect.

[0060] The sacrificial spacer 23 can be removed in subsequent processing, and therefore, the region where the sacrificial spacer 23 is present can be changed into an air gap AG to reduce capacitance dispersion of the bit line BL. Therefore, when the sacrificial spacer 23 and the sacrificial layer are simultaneously etched and damaged, the air gap AG may not be effectively formed. For example, when the sacrificial spacer 23 is damaged during the patterning of the sacrificial layer to form the sacrificial semiconductor pattern 30, the reference... Figure 10A , Figure 10B and Figure 10C In the described steps of forming the air gap AG, the air gap AG cannot be effectively formed from the damaged sacrificial spacer 23. According to some exemplary embodiments of the invention, the sacrificial layer may comprise, or be formed from, a material such as undoped polysilicon that has etch selectivity relative to the sacrificial spacer 23. Therefore, compared to the case where the sacrificial layer and sacrificial spacer 23 comprise the same material, in the step of patterning the sacrificial layer to form the sacrificial semiconductor pattern 30, damage to the sacrificial spacer 23, which will later be replaced by the air gap AG, can be prevented, resulting in a semiconductor memory device with improved performance and enhanced reliability.

[0061] Reference Figures 8A to 8C A dielectric layer, such as a silicon nitride layer, can be formed across the entire surface of the substrate 100 to fill the first opening 31. The dielectric layer may undergo a planarization etching process to form an insulating barrier 40 filling the first opening 31. The cell array region CAR may undergo an etching process to remove the sacrificial semiconductor pattern 30. In this step, an etch protection layer may be formed on the interface region INT such that the sacrificial semiconductor pattern 30 is not removed from the interface region INT. The sacrificial semiconductor pattern 30 on the cell array region CAR may be removed to form a second opening 33 exposing the interlayer dielectric pattern 5 overlapping with the second impurity region 112b.

[0062] Reference Figures 9A to 9C On the cell array region CAR, the interlayer dielectric pattern 5 is exposed through the second opening 33, which can partially remove the device isolation pattern 102 and the substrate 100 (e.g., the second impurity region 112b) to expose the second impurity region 112b. In an embodiment, the second impurity region 112b may be over-etched. A polysilicon layer may be formed on the cell array region CAR of the substrate 100 to fill the second opening 33, and then the polysilicon layer may be etched to form the first contact BC. Figure 9BAs shown, the height (horizontal height) of the top surface of the first contact BC can be lower than the height (horizontal height) of the top ends of the first spacer 21, sacrificial spacer 23, and second spacer 25. Therefore, the upper portions of the first spacer 21, sacrificial spacer 23, and second spacer 25 can be exposed. During the formation of the first contact BC, the upper portions of the sacrificial spacer 23 and second spacer 25 can be removed. The first spacer 21 can therefore have exposed upper sidewalls. This process provides a large process margin for forming the landing pads, which will be discussed below. When the upper portions of the sacrificial spacer 23 and second spacer 25 are removed, the upper portion of the first spacer 21 can be partially removed to reduce the width of the first spacer 21. A cleaning process can be performed to clean the top surface of the first contact BC. The top surface of the first contact BC can undergo a metallization process to form the memory node ohmic layer 9. The memory node ohmic layer 9 can be formed from a metallization layer such as a cobalt silicide layer.

[0063] On the interface region INT, the upper portion of the sacrificial semiconductor pattern 30 can be etched to form the first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34. For example, the sacrificial semiconductor pattern 30 can be etched during the etching process that forms the first contact BC on the cell array region CAR. Thus, the first contact BC can have a top surface at the same horizontal level as the top surfaces of the first sacrificial semiconductor pattern 32 and the second sacrificial semiconductor pattern 34. When etching the sacrificial semiconductor pattern 30, the upper portions of the first spacer 21 and the second spacer 25, the upper portion of the sacrificial spacer 23, and the upper portion of the dielectric pattern 137 can also be partially removed. On the second interface region INT2, the dielectric pattern 137 can be partially etched to form a recess R. The recess R can expose the top surface of the bit line BL and the inner wall of the first spacer 21. A diffusion-degrading layer 11a can be formed conformally across the entire surface of the substrate 100. The diffusion-degrading layer 11a can be formed, for example, a titanium nitride layer or a tantalum nitride layer.

[0064] Reference Figures 10A to 10C A landing pad layer can be formed across the entire surface of substrate 100 to fill the spaces between dielectric patterns 137. The landing pad layer may include tungsten. A second mask pattern 140 may be formed on the landing pad layer. The second mask pattern 140 may be formed from, for example, an amorphous carbon layer (ACL). The second mask pattern 140 may define the location of the landing pads, which will be discussed below. On the cell array region CAR, the second mask pattern 140 may be formed to vertically overlap with the first contact BC. On the cell array region CAR, the second mask pattern 140 may be formed to have islands spaced apart from each other. On the interface region INT, the second mask pattern 140 may be formed to have a line extending in one direction (e.g., a second direction D2).

[0065] An etching process can be performed, allowing the second mask pattern 140 to be used as an etching mask to partially remove the landing pad layer, diffusion-damping layer 11a, and dielectric pattern 137, thereby forming the landing pad LP and diffusion-damping pattern 11a, and simultaneously forming the fourth recess 142. In this step, the first spacer 21 and the second spacer 25 on one side of the dielectric pattern 137 can be removed to expose the tip of the sacrificial spacer 23. When the etching process is performed to form the landing pad LP and the fourth recess 142, the etchant supply can be controlled to suppress the etching of the sidewalls of the landing pad LP, thereby preventing a reduction in the width of the landing pad LP. Therefore, the process margin of the landing pad LP can be increased.

[0066] The sacrificial spacer 23 exposed to the fourth recess 142 can be selectively removed. Etch to etch the sacrificial spacer 23 can be introduced through the fourth recess 142, thereby removing the sacrificial spacer 23. The etchant removes the sacrificial spacer 23 and can flow downwards along it, thus the entire area containing the sacrificial spacer 23 can be transformed into an air gap AG. The air gap AG can be uniformly formed on the sidewalls of the bit lines BL, resulting in a reduction in the coupling capacitance between adjacent bit lines BL.

[0067] Return to reference Figures 1A to 1C The second mask pattern 140 can be removed, and a separation pattern 144 can be formed between the landing pads LP. The separation pattern 144 can fill the fourth recess 142. The separation pattern 144 can close the entrance to the air gap AG. The separation pattern 144 may include a dielectric material, such as silicon oxide or silicon nitride. On the cell array region CAR, data storage elements (e.g., capacitors) can be formed on the landing pads LP. Each of the data storage elements may include a bottom electrode BE, a dielectric layer, and a top electrode. The data storage elements are not formed on the interface region INT. The above process can fabricate semiconductor memory devices according to some exemplary embodiments of the present invention.

[0068] For the semiconductor memory device conceived according to the present invention, polysilicon with etch selectivity relative to adjacent spacer structures can be used to form an insulating barrier. Therefore, damage to adjacent spacer structures can be prevented during the step of forming the insulating barrier, and thus a semiconductor memory device with improved electrical reliability can be provided.

[0069] The detailed description of the inventive concept should not be construed as limiting it to the embodiments described herein, and the inventive concept is intended to cover various combinations, modifications, and variations of the invention without departing from its spirit and scope. The appended claims should be construed as including other embodiments.

Claims

1. A semiconductor memory device, comprising: The substrate has a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, wherein the cell array region is provided with a plurality of active regions extending in a first direction. Multiple bit lines are located on the cell array region and the second interface region, and the multiple bit lines extend in a second direction that intersects the first direction; Multiple dielectric patterns are located on the top surface of the multiple bit lines, the multiple dielectric patterns extend along the top surface of the multiple bit lines in the second direction, and also extend to the first interface region; Device isolation patterns, which are located on the substrate, The device isolation pattern includes a first portion on the cell array region and a second portion on the first interface region. The first portion of the device isolation pattern defines the plurality of active regions. The second portion of the device isolation pattern is provided with a plurality of first recesses, and Wherein, when the semiconductor memory device is viewed in a plan view, each of the plurality of first recesses is disposed between two adjacent dielectric patterns of the plurality of dielectric patterns arranged on the first interface region; and Multiple first sacrificial semiconductor patterns are arranged on the first interface region and in the multiple first recesses of the device isolation pattern. The plurality of first sacrificial semiconductor patterns include polycrystalline silicon.

2. The semiconductor memory device according to claim 1, further comprising: Multiple first contacts are located on the multiple active regions. The plurality of first contacts and the plurality of bit lines are arranged alternately and repeatedly in a third direction perpendicular to the second direction. Wherein, the first direction, the second direction, and the third direction are on the same plane. Wherein, the plurality of first contacts comprise polycrystalline silicon doped with impurities, and The polysilicon of the plurality of first sacrificial semiconductor patterns is undoped polysilicon.

3. The semiconductor memory device according to claim 2, further comprising: Multiple insulating barriers are located between the multiple first sacrificial semiconductor patterns. The plurality of first sacrificial semiconductor patterns and the plurality of insulating fences are arranged alternately and repeatedly along the second direction.

4. The semiconductor memory device according to claim 1, further comprising: Multiple spacer structures are located on opposite sidewalls of the multiple bit lines; as well as Multiple second sacrificial semiconductor patterns are arranged on the second interface region. Each of the plurality of second sacrificial semiconductor patterns is arranged between two adjacent spacer structures in the plurality of spacer structures, and The plurality of second sacrificial semiconductor patterns include undoped polycrystalline silicon.

5. The semiconductor memory device according to claim 4, further comprising: Multiple letter lines extend upwards in a third direction perpendicular to the second direction. Wherein, the first direction, the second direction, and the third direction are on the same plane, and The plurality of bit lines and the plurality of second sacrificial semiconductor patterns are arranged alternately and repeatedly in the third direction.

6. The semiconductor memory device according to claim 4, in, The top surfaces of the plurality of first sacrificial semiconductor patterns are at the same horizontal height as the top surfaces of the plurality of second sacrificial semiconductor patterns.

7. The semiconductor memory device according to claim 1, in, The first height of the plurality of first sacrificial semiconductor patterns is at to Within the range.

8. The semiconductor memory device according to claim 1, in, The first width of the plurality of first sacrificial semiconductor patterns decreases as they approach the top surface of the substrate.

9. The semiconductor memory device according to claim 8, further comprising: Multiple spacer structures are located on opposite sidewalls of the multiple bit lines; as well as Multiple second sacrificial semiconductor patterns are arranged in the second interface region. Each of the plurality of second sacrificial semiconductor patterns is located between two adjacent spacer structures in the plurality of spacer structures. Wherein, the second width of the plurality of second sacrificial semiconductor patterns in a third direction perpendicular to the second direction is greater than the first width of the plurality of first sacrificial semiconductor patterns in the third direction, and The first direction, the second direction, and the third direction are all on the same plane.

10. The semiconductor memory device of claim 1, further comprising: Multiple landing pads covering the multiple dielectric patterns, In the second interface region, the plurality of dielectric patterns include a plurality of recesses that partially expose the top surfaces of the plurality of bit lines, and The plurality of landing pads extend into the plurality of recesses and are disposed on the exposed top surface of the plurality of bit lines.

11. The semiconductor memory device of claim 1, further comprising: Multiple spacer structures are located on opposite sidewalls of the multiple dielectric patterns, the multiple spacer structures extending from the cell array region to the first interface region. Each of the plurality of spacer structures includes a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

12. The semiconductor memory device according to claim 1, further comprising: Multiple word lines are arranged on the multiple active areas and extend upward in a third direction perpendicular to the second direction. Wherein, the first direction, the second direction, and the third direction are on the same plane. When the semiconductor memory device is viewed in a plan view, the plurality of dielectric patterns include a plurality of first components that overlap with the plurality of word lines and a plurality of second components that do not overlap with the plurality of word lines. The height of the plurality of second components of the plurality of dielectric patterns is greater than the height of the plurality of first components of the plurality of dielectric patterns.

13. A semiconductor memory device, comprising: The substrate has a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, wherein the cell array region is provided with a plurality of active regions extending in a first direction. Multiple bit lines are located on the cell array region and the second interface region, and the multiple bit lines extend in a second direction different from the first direction; Multiple word lines are located on the substrate and extend upward in a third direction perpendicular to the second direction, wherein the first direction, the second direction, and the third direction are on the same plane; Multiple insulating fences, spaced apart from each other on the multiple word lines and in the third direction. Wherein, the plurality of insulating fences and the plurality of bit lines are arranged alternately and repeatedly in the third direction; and Multiple first sacrificial semiconductor patterns are arranged on the first interface region. The plurality of first sacrificial semiconductor patterns and the plurality of insulating barriers are arranged alternately and repeatedly in the second direction, and The plurality of first sacrificial semiconductor patterns include polycrystalline silicon.

14. The semiconductor memory device of claim 13, further comprising: Multiple spacer structures are located on opposite sidewalls of the multiple bit lines in the cell array region, and the multiple spacer structures extend to the first interface region and the second interface region; as well as Device isolation patterns, which are located on the substrate, The device isolation pattern includes a first portion on the cell array region and a second portion on the first interface region. The first portion of the device isolation pattern defines the plurality of active regions. The second portion of the device isolation pattern has multiple recesses, and The plurality of first sacrificial semiconductor patterns fill the plurality of recesses such that each of the plurality of first sacrificial semiconductor patterns is arranged between two adjacent spacer structures arranged in the third direction of the plurality of spacer structures.

15. The semiconductor memory device of claim 13, further comprising: Multiple dielectric patterns are located on the top surface of the multiple bit lines, extending along the top surface of the multiple bit lines and also extending to the first interface region. When the semiconductor memory device is viewed in a plan view, the plurality of first sacrificial semiconductor patterns and the plurality of dielectric patterns are arranged alternately and repeatedly in the third direction.

16. The semiconductor memory device of claim 13, further comprising: Multiple first contacts are located on the multiple active regions. The plurality of first contacts and the plurality of bit lines are arranged alternately and repeatedly in the third direction. Wherein, the plurality of first contacts comprise polycrystalline silicon doped with impurities, and The polysilicon of the plurality of first sacrificial semiconductor patterns is undoped polysilicon.

17. The semiconductor memory device of claim 13, further comprising: Multiple spacer structures are located on opposite sidewalls of the multiple bit lines; as well as Multiple second sacrificial semiconductor patterns are arranged on the second interface region. Each of the plurality of second sacrificial semiconductor patterns is arranged between two adjacent spacer structures in the plurality of spacer structures, and Wherein, the second width of the plurality of second sacrificial semiconductor patterns in the third direction is greater than the first width of the plurality of first sacrificial semiconductor patterns in the third direction.

18. The semiconductor memory device according to claim 17, in, Each of the plurality of second sacrificial semiconductor patterns has an opposing sidewall in contact with the inner sidewall of two adjacent spacer structures in the plurality of spacer structures.

19. A semiconductor memory device, comprising: The substrate has a cell array region, a first interface region, and a second interface region between the cell array region and the first interface region, wherein the cell array region is provided with a plurality of active regions extending in a first direction. Multiple bit lines are located on the cell array region and the second interface region, and the multiple bit lines extend in a second direction that intersects the first direction; Multiple word lines are arranged on the multiple active areas, and the multiple word lines extend upward in a third direction perpendicular to the second direction, wherein the first direction, the second direction and the third direction are on the same plane; Multiple dielectric patterns are located on the top surface of the multiple bit lines, the multiple dielectric patterns extend along the top surface of the multiple bit lines, and also extend to the first interface region; Multiple spacer structures are located on opposite sidewalls of the multiple dielectric patterns, each of the multiple spacer structures including a first spacer, a second spacer and an air gap between the first spacer and the second spacer; Device isolation patterns, which are located on the substrate, The device isolation pattern includes a first portion on the cell array region and a second portion on the first interface region. Wherein, the first portion of the device isolation pattern defines the plurality of active regions, and The second portion of the device isolation pattern is provided with multiple recesses; A plurality of first sacrificial semiconductor patterns, which are located in the plurality of recesses of the device isolation pattern on the first interface region, the plurality of first sacrificial semiconductor patterns comprising polysilicon; A diffusion-damage pattern that covers the plurality of dielectric patterns and the plurality of spacer structures; Multiple landing pads located on the diffusion destruction pattern; and Multiple bottom electrodes are located on the multiple landing pads.

20. The semiconductor memory device of claim 19, further comprising: Multiple first contacts are located on the multiple active regions. Wherein, the plurality of first contacts and the plurality of bit lines are arranged alternately and repeatedly in the third direction; and Multiple insulating fences are located on the multiple word lines. The plurality of insulating fences and the plurality of first contacts are arranged alternately and repeatedly in the second direction.

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