Integrated circuitry, methods of forming the same, and methods for forming memory arrays

Abstract

This application relates to integrated circuitry and methods of forming the same and methods for forming memory arrays. A method for forming integrated circuitry includes forming a stack comprising vertically alternating first and second layers. The first layers comprise doped silicon dioxide and the second layers comprise undoped silicon dioxide. Horizontally elongated trenches are formed into the stack. The doped silicon dioxide in the first layers is etched selectively with respect to the undoped silicon dioxide in the second layers through the trenches. Conduction material is formed in void spaces left by the etching in the first layers. Structures independent of the method are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to integrated circuit systems, methods for forming integrated circuit systems, and methods for forming memory arrays including strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two distinct optional states. In binary systems, states are considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] Field-effect transistors (FETs) are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell device includes at least one selection device series-coupled with a series combination of memory cells (wherein the series combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each vertically stacked memory cell individually including a vertically stacked transistor that can be reversibly programmed. Control components or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells individually including transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described, for example, in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in so-called “step structures” at the ends or edges of the array of vertically stacked memory cells. A step structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) that define contact areas for individual word lines, with vertically extending conductive vias contacting these contact areas to provide electrical access to the word lines. Summary of the Invention

[0008] In one aspect, this application provides a method for forming an integrated circuit system, comprising: forming a stack comprising a vertically alternating first layer and a second layer, the first layer comprising doped silicon dioxide and the second layer comprising undoped silicon dioxide; forming a horizontally elongated trench into the stack; selectively etching the doped silicon dioxide in the first layer through the trench relative to the undoped silicon dioxide in the second layer; and forming a conductive material in the void space left by the etching in the first layer.

[0009] In another aspect, this application further provides a method for forming a memory array including strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers, the first layer comprising doped silicon dioxide and the second layer comprising undoped silicon dioxide, the stack comprising laterally spaced memory block regions having horizontally elongated trenches between the laterally spaced memory block regions, a trench material string extending through the first and second layers in the memory block regions; selectively etching the doped silicon dioxide in the first layer through the trenches relative to the undoped silicon dioxide in the second layer; forming conductive material of conductive lines in the void spaces left by the etching in the first layer; and forming an intervening material in the trenches, laterally located between laterally adjacent memory block regions and longitudinally along the memory block regions.

[0010] In another aspect, this application further provides an integrated circuit system comprising: a first vertical stack including alternating insulating and conductive layers, the conductive layers individually including horizontally elongated conductive lines; and a second vertical stack adjacent to the first vertical stack, the second vertical stack including alternating first and second insulating layers, the first insulating layer being individually at least primarily doped silicon dioxide, and the second insulating layer being individually at least primarily undoped silicon dioxide.

[0011] In another aspect, this application further provides an integrated circuit system including a memory array comprising strings of memory cells, comprising: laterally spaced memory blocks, each including a first vertical stack, the first vertical stack including alternating insulating and conductive layers, the memory cell strings including strings of channel material extending through the insulating and conductive layers, the conductive layers each including horizontally elongated conductive lines; and a second vertical stack adjacent to the first vertical stack, the second vertical stack including alternating first and second insulating layers, the first insulating layer being at least primarily doped silicon dioxide, and the second insulating layer being at least primarily undoped silicon dioxide. Attached Figure Description

[0012] Figure 1 This is a schematic cross-sectional view of a portion of a substrate in processing according to an embodiment of the present invention, and is through... Figure 2 It was cut from line 1-1 in the middle.

[0013] Figure 2 Is it through Figure 1 The diagram shows a cross-sectional view taken from line 2-2 in the figure.

[0014] Figure 3 and 4 yes Figure 1 and2 A magnified view of the portion.

[0015] Figure 5 yes Figure 1 A view of another part of the substrate not shown in the image.

[0016] Figures 6 to 15 In the process according to some embodiments of the present invention Figures 1 to 5 The structure or its parts are illustrated in sequence as cross-sections, unfolded, enlarged and / or partial views. Detailed Implementation

[0017] Embodiments of the present invention cover methods for forming integrated circuit systems, such as memory circuit systems, logic circuit systems, or other existing or future-developed integrated circuit systems. In one example, such an integrated circuit system includes a memory array, such as an array of NAND or other memory cells that may have at least some peripheral control circuitry (e.g., under-array CMOS) beneath the array. Embodiments of the present invention also cover existing or future-developed integrated circuit systems independent of the manufacturing method, such as memory circuit systems including memory arrays (e.g., NAND architecture). Reference Figures 1 to 15 A first example method embodiment is described, which can be considered as a process for forming a "back gate" or "replacement gate" in a memory circuit system, and from... Figures 1 to 5 start.

[0018] Figure 1 and 2 The illustration shows a configuration 10 having an array or array region 12 in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having any one or more of the following materials: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulating (i.e., electrically insulating herein). Various materials have been vertically formed over the substrate 11. The materials may be... Figures 1 to 5 The material depicted may be adjacent to, vertically inside, or vertically outside. For example, other portions or fully fabricated components of the integrated circuit system may be provided somewhere above, around, or inside the substrate 11. Controls and / or other peripheral circuitry for operating components within an array (e.g., array 12) of vertically extending strings of memory cells may also be fabricated, and these controls and / or other peripheral circuitry may or may not be fully or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated relatively independently of each other, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0019] A conductor layer 16, comprising conductor material 17, has been formed above the substrate 11. The conductor layer 16 may include portions of a control circuitry (e.g., an array-below peripheral circuitry and / or a common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within the array 12. A stack 18, comprising vertically alternating insulating layers 20 and conductive layers 22, has been formed above the conductor layer 16. Examples of the thickness of each of layers 20 and 22 are 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown; the stack 18 is more likely to comprise tens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be portions of the peripheral and / or control circuitry, may be situated between the conductor layer 16 and the stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the bottommost conductive layer 22 and / or above the topmost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the bottommost conductive layer 22, and one or more select gate layers may be above the topmost conductive layer 22. Alternatively or additionally, at least one of the depicted topmost and bottommost conductive layers 22 may be a select gate layer. In any case, conductive layer 22 (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include insulating material, or may be insulating when processed in conjunction with the example method embodiments of the "back gate" or "alternate gate" initially described herein. Example conductive layer 22 includes a first material 26 (e.g., doped silicon dioxide) that may be completely or partially sacrificed. Example insulating layer 20 includes a second material 24 (e.g., undoped silicon dioxide) whose composition differs from that of the first material 26 and which may be completely or partially sacrificed.

[0020] In this document, apart from silicon and oxygen, "doped silicon dioxide" has a minimum of 1 × 10⁻⁶. 12 atoms / cm 3 The total number of dopant atoms (whether in elemental, compound, and / or other forms). In this document, “undoped silicon dioxide” has less than 1 × 10⁻⁶ atoms, excluding silicon and oxygen. 12 atoms / cm 3 The total number of dopant atoms (whether in elemental, compound, or other forms).

[0021] In one embodiment, the doped silicon dioxide of the first material 26 comprises a total dopant atoms other than silicon and oxygen, comprising no more than 30 atomic percent of total dopant atoms in addition to silicon and oxygen; in another embodiment, it comprises at least 1 × 10⁻⁶ dopant atoms other than silicon and oxygen. 18 atoms / cm 3The total dopant atoms, in one embodiment comprising at least 1 atomic percentage of total dopant atoms other than silicon and oxygen, and in another embodiment comprising at least 5 atomic percentage of total dopant atoms other than silicon and oxygen. In one embodiment, the doped silicon dioxide of the first material 26 comprises at least one of borosilicate glass (BPSG), borosilicate glass (BSG), and phosphosilicate glass (PSB). In one embodiment, the undoped silicon dioxide of the second material 24 comprises 0 atoms / cm² other than silicon and oxygen. 3 Up to no greater than the minimum 1×10 10 atoms / cm 3 The total number of dopant atoms, and in one embodiment, it includes 0 atoms / cm² in addition to silicon and oxygen. 3 Up to no greater than the minimum 1×10 5 atoms / cm 3 Total dopant atoms.

[0022] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 to the conductor layer 16. The channel opening 25 may gradually narrow radially inward as it moves deeper within the stack 18 (not shown). In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or it may terminate at the top (not shown). Alternatively, as an example, the channel opening 25 may terminate at the top or inside of the lowermost insulating layer 20. The reason for extending the channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect to the material within the channel opening 25. An etch-stopping material (not shown) may be inside or on top of the conductor material 17 of the conductor layer 16 to facilitate the termination of etching of the channel opening 25 relative to the conductor layer 16 when desired. Such an etch-stopping material may be sacrificial or non-sacrificial.

[0023] Horizontally elongated trenches 40 have been formed in stack 18 (e.g., by anisotropic etching) to form laterally spaced memory block regions 58. For the sake of simplicity and by way of example, channel openings 25 are shown as groups or columns arranged in staggered rows of four and five channel openings 25 per row, arranged within the laterally spaced memory block regions 58, which will comprise laterally spaced memory blocks 58 in the final circuit system construction. In this document, "block" generally includes "sub-block". Trench 40 will typically be wider than channel openings 25 (e.g., 10 to 20 times wider, but such wider extents are not shown for simplicity). Memory block regions 58 and the resulting memory blocks 58 (not yet shown) can be considered as longitudinally elongated and oriented, for example, along direction 55. Any alternative existing or future-developed arrangements and constructions can be used.

[0024] Transistor channel material may be formed vertically along the insulating and conductive layers in individual channel openings, thus comprising individual channel material strings directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally located between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) is formed vertically along the individual charge-blocking region. The insulating charge-transfer material (e.g., a bandgap-engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally located between the channel material and the storage material.

[0025] Figures 1 to 4 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transport material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor materials over stack 18 and within individual openings 25 and subsequently planarizing such transistor materials back at least to the top surface of stack 18.

[0026] Channel material 36 has also been vertically formed along the insulating layer 20 and the conductive layer 22 in the channel opening 25, thus including individual operational channel material strings 53 in the channel opening 25. In one embodiment, the channel material strings 53 are arranged along their respective memory cell materials (e.g., 30, 32, and 34), and a second layer of material (e.g., 24) is horizontally located between adjacent channel material strings 53. Due to proportions, materials 30, 32, 34, and 36 are... Figure 1 and 2The material 37 is shown and designated only in the examples. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Each of materials 30, 32, 34, and 36 has an example thickness of 25 to 100 angstroms. Stamping etching can be performed to remove materials 30, 32, and 34 from the substrate (not shown) of the channel opening 25 to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. Such stamping etching can occur individually with respect to each of materials 30, 32, and 34 (as shown), or only with respect to some (not shown). Alternatively, and only by way of example, stamping etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 only through individual conductive interconnects (not shown). The channel opening 25 is shown to include a radially central solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void spaces (not shown) and / or contain no solid material (not shown).

[0027] In some embodiments, construction 10 may be considered to include a first region (e.g., as defined by...). Figure 1 and 2 (as shown) and the second zone 70 next to the first zone (e.g., as shown) Figure 5 (As shown in the diagram). The second region 70 may be laterally contacted (not shown) the first region, or may be laterally spaced from the first region (e.g., laterally adjacent to the first region but not touching it, or laterally away from the first region). The second region 70 may be located within one or more memory block regions (not shown). In some embodiments, the configuration 10 may be considered to include a first vertical stack (e.g., Figure 2 The second vertical stack (e.g., stack 18 in the second region 70) and the second vertical stack (e.g., stack 18 in the second region 70), wherein the second stack comprises vertically alternating first and second insulating layers (e.g., in... Figure 5 The layers are 22 and 20, respectively, and regardless of whether layers 22 and 20 are conductive, insulating, or semi-conductive during processing or in the finished product construction.

[0028] refer to Figures 6 to 9In one embodiment, the doped silicon dioxide 26 in the first layer 22 (e.g., in the first region, and not shown here) has been selectively etched relative to the undoped silicon dioxide 24 in the second layer 20 (e.g., in the first region), thereby leaving void spaces 75 in the first layer 22. Such etching can be performed using any existing or future-developed chemicals and conditions. In one embodiment, etching is performed using an etching chemical that is at least predominantly in the gas phase (here, "predominantly" means greater than 50 vol%), and in another embodiment, etching is performed using an etching chemical that is at least predominantly in the liquid phase. An example of an ideal gas phase chemical is a combination of hydrogen fluoride and water (e.g., at 5°C to 35°C, 200 mTorr to 200 Torr, 100 sccm to 500 sccm HF, 50 sccm to 200 sccm H2O), and an example of an ideal liquid phase chemical is a combination of ammonium hydroxide and water (e.g., at room pressure and at room temperature or high temperature), each of which enables etching selectivity of doped silicon dioxide relative to undoped silicon dioxide in the thousands of volumes. In one embodiment, and as shown, for example, if trench 40 is not formed in the second region 70 or undoped silicon dioxide 24 is not additionally etched laterally in the second region 70, then etching has already occurred in the first region (e.g., Figure 1 and 2 It occurred in Zone 70 and has not yet occurred in Zone 2.

[0029] refer to Figures 10 to 15 The conductive material 48 has been formed in the first layer 22 through Figures 6 to 9 The example shown has voids 75 left by etching. Figures 10 to 14 (Not specified in the text). The conductive material 48 has then been removed from the trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56. A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate locations of the transistors and / or memory cells 56 are in Figure 13 Parentheses are used to indicate this, and some are in Figures 10 to 12 In Figures 1 and 14, the transistors and / or memory cells 56 are indicated by dashed outlines, where they are substantially annular or ring-shaped in the depicted examples. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in the individual conductive layer, and not shown). The conductive material 48 can be considered as having ends 50 corresponding to control gate regions 52 of the individual transistors and / or memory cells 56. Figure 13In the depicted embodiment, the control gate region 52 includes individual portions of the individual conductive lines 29. Materials 30, 32, and 34 can be considered as a memory structure 65 located laterally between the control gate region 52 and the channel material 36.

[0030] A charge-blocking region (e.g., charge-blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge-blocking member in the memory cell may function to prevent charge carriers from flowing from the storage material (e.g., a floating gate material, a charge trapping material, etc.) to the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge-blocking member can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown in the example, the charge-blocking region includes an insulating material 30. By other examples, the charge-blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein this storage material is insulating (e.g., in the absence of any different compositional material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the junction between the storage material and the conductive material of the control gate may be sufficient to act as a charge-blocking region even in the absence of any separately composed insulating material 30. Furthermore, the junction between the conductive material 48 and the material 30 (if present) and the insulating material 30 can together serve as a charge blocking region, and can alternatively or additionally serve as a lateral outer region of the insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0031] Intervention material 57 has been formed in trench 40, and thus is located laterally between laterally adjacent memory blocks 58, and longitudinally along the memory blocks. Intervention material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This can comprise one or more of insulating, semiconductive, and conductive materials, and in any case, can help prevent short circuits of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervention material 57 may include through-hole arrays (not shown).

[0032] In one embodiment, and as shown, the formation of conductive material 48 in void space 75 occurs in the first region rather than in the second region 70, such that at least some of the doped silicon dioxide 26 in the first layer 22 and at least some of the undoped silicon dioxide 24 in the second layer 20 remain in the second region 70 in the finished construction of the integrated circuit system.

[0033] Any other properties or aspects shown and / or described herein with reference to other embodiments may be used in the embodiments shown and described above.

[0034] In some embodiments, a method for forming an integrated circuit system (e.g., 10, and regardless of whether it includes memory) includes forming a stack (e.g., 18) comprising vertically alternating first layers (e.g., 22) and second layers (e.g., 20), wherein the first layer comprises doped silicon dioxide and the second layer comprises undoped silicon dioxide. Horizontally elongated trenches (e.g., 40) have been formed into the stack. The doped silicon dioxide in the first layer has been selectively etched through the trenches relative to the undoped silicon dioxide in the second layer. A conductive material (e.g., 48) is formed in the void spaces (e.g., 75) left by the etching in the first layer. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of the manufacturing method. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate any of the properties described with respect to the device embodiments.

[0036] In one embodiment, the integrated circuit system (e.g., 10, and regardless of whether it includes memory) includes a first vertical stack (e.g., Figure 2 18), the first vertical stack comprises alternating insulating layers (e.g., 20, regardless of whether they include doped silicon dioxide, undoped silicon dioxide, and / or other insulating compositions) and conductive layers (e.g., 22). The conductive layers individually comprise horizontally elongated conductive lines (e.g., 29). The second vertical stack (e.g., Figure 15 18) is adjacent to the first vertical stack. The second vertical stack includes alternating first insulating layers (e.g., 20) and second insulating layers (e.g., ...). Figure 15 (22) The first insulating layer is individually at least primarily doped silicon dioxide, and the second insulating layer is individually at least primarily undoped silicon dioxide. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0037] In one embodiment, the integrated circuit system (e.g., 10) includes a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56). The integrated circuit system includes laterally spaced memory blocks (e.g., 58), each memory block individually comprising a first vertical stack (e.g., ...). Figure 218), the first vertical stack includes alternating insulating layers (e.g., 20, regardless of whether they include doped silicon dioxide, undoped silicon dioxide, and / or other insulating compositions) and conductive layers (e.g., 22). Strings (e.g., 49) of memory cells (e.g., 12) including channels (e.g., 53) extend through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines (e.g., 29). The second vertical stack (e.g., Figure 15 18) is adjacent to the first vertical stack. The second vertical stack includes alternating first insulating layers (e.g., 20) and second insulating layers (e.g., ...). Figure 15 (22) The first insulating layer is individually at least primarily doped silicon dioxide. The second insulating layer is individually at least primarily undoped silicon dioxide. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0038] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of such components, or within a single stack or group, which is above or part of an underlying substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed as part of the finished construction at any location, and in some embodiments may be under the array (e.g., under-array CMOS). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the figures or described above. Furthermore, the arrays of components may be the same or different relative to each other in different stacks / groups, and the different stacks / groups may have the same or different thicknesses relative to each other. Intervention structures (e.g., additional circuitry and / or dielectric layers) may be disposed between vertically adjacent stacks / groups. And, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0039] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0040] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a generally relative direction (i.e., within 10 degrees) along the surface of the main substrate, where the substrate is processed during manufacturing, and which is generally orthogonal to vertical. “Just horizontal” is a generally relative direction (i.e., not at an angle) along the surface of the main substrate. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction inclined at least 45° from just horizontal. Furthermore, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., relative to the orientation of the channel length of a field-effect transistor, along which current flows between the source and drain regions during operation. For bipolar junction transistors, "vertically extended," "vertically extended," "horizontally extended," "horizontally extended," etc., are orientations relative to the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extended component, feature, and / or region extends vertically or within a vertical 10°.

[0041] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) between the two stated areas / materials / components relative to each other. Moreover, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above the other stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under the other stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0042] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material covering them. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of one or more of such compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0043] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” only requires that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, “different compositions” only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when a stated material, region, or structure is in at least some physical contact with each other, one material, region, or structure “directly contacts” another material, region, or structure. In contrast, the words "above," "on," "near," "along," and "against" without the preceding "positive" encompass "directly against" and constructions in which the intervention of materials, areas, or structures results in the stated materials, areas, or structures not being in physical contact with each other.

[0044] In this context, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0045] Any use of “row” and “column” in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for components that have been or may be formed along said “row” and “column”. “Row” and “column” are used synonymously with respect to any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0046] The composition of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds, or a combination thereof.

[0047] In this document, any use of "selective" in relation to etching, removal, deposition, and / or forming is an action of one stated material relative to another stated material at a volume ratio of at least 2:1. Additionally, any use of selective deposition, selective growth, or selective forming is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1, up to a minimum of 75 angstroms.

[0048] Unless otherwise indicated, the use of “or” in this document covers either one or both.

[0049] in conclusion

[0050] In some embodiments, a method for forming an integrated circuit system includes forming a stack comprising a vertically alternating first layer and a second layer. The first layer comprises doped silicon dioxide, and the second layer comprises undoped silicon dioxide. Horizontally elongated trenches are formed into the stack. The doped silicon dioxide in the first layer is selectively etched through the trenches relative to the undoped silicon dioxide in the second layer. Conductive material is formed in the voids left by the etching in the first layer.

[0051] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming a stack comprising vertically alternating first and second layers. The first layer comprises doped silicon dioxide, and the second layer comprises undoped silicon dioxide. The stack includes laterally spaced memory block regions with horizontally elongated trenches between them. Strings of trench material extend through the first and second layers in the memory block regions. The doped silicon dioxide in the first layer is selectively etched through the trenches relative to the undoped silicon dioxide in the second layer. Conductive material for conductive lines is formed in the void spaces left by the etching in the first layer. Intervening material is formed in the trenches, laterally located between laterally adjacent memory block regions and longitudinally along the memory block regions.

[0052] In some embodiments, an integrated circuit system includes a first vertical stack comprising alternating insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines. A second vertical stack is placed adjacent to the first vertical stack. The second vertical stack includes alternating first and second insulating layers. The first insulating layer is individually at least primarily doped silicon dioxide. The second insulating layer is individually at least primarily undoped silicon dioxide.

[0053] In some embodiments, an integrated circuit system including a memory array comprising strings of memory cells includes laterally spaced memory blocks, each of which individually includes a first vertical stack comprising alternating insulating and conductive layers. The memory cell strings include strings of channel material extending through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines. A second vertical stack is placed adjacent to the first vertical stack. The second vertical stack includes alternating first and second insulating layers. The first insulating layer is individually at least primarily doped silicon dioxide. The second insulating layer is individually at least primarily undoped silicon dioxide.

[0054] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming an integrated circuit system, comprising: A stack comprising a vertically alternating first layer and a second layer is formed, wherein the first layer comprises doped silicon dioxide and the second layer comprises undoped silicon dioxide; Horizontally elongated grooves are formed into the stack; Selectively etch the doped silicon dioxide in the first layer through the trench relative to the undoped silicon dioxide in the second layer; and Conductive material is formed in the void space left by the etching in the first layer, wherein the stack includes a first region and a second region adjacent to the first region, the etching and the formation of conductive material in the void space occur in the first region but not in the second region, such that the doped silicon dioxide in the first layer and the undoped silicon dioxide in the second layer remain in the second region in the finished structure of the integrated circuit system.

2. The method of claim 1, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 1 × 10⁻⁶ ppm. 18 atoms / cm 3 Total dopant atoms.

3. The method of claim 1, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 1 atomic percentage of total dopant atoms.

4. The method of claim 1, wherein, in addition to silicon and oxygen, the doped silicon dioxide further comprises at least 5 atomic percent of total dopant atoms.

5. The method of claim 1, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 1 × 10⁻⁶ ppm. 18 atoms / cm 3 The total dopant atoms are no more than 30 atomic percent.

6. The method according to claim 1, wherein the doped silicon dioxide comprises at least one of BPSG, BSG, and PSG.

7. The method of claim 1, wherein the undoped silicon dioxide comprises 0 atoms / cm², in addition to silicon and oxygen. 3 Up to no greater than the minimum 1×10 10 atoms / cm 3 Total dopant atoms.

8. The method of claim 1, wherein the undoped silicon dioxide comprises 0 atoms / cm², in addition to silicon and oxygen. 3 Up to no greater than the minimum 1×10 5 atoms / cm 3 The total number of dopant atoms.

9. The method of claim 1, wherein the etching is performed using etching chemicals that are at least primarily in the gas phase.

10. The method of claim 1, wherein the etching is performed using etching chemicals that are at least primarily in the liquid phase.

11. A method for forming a memory array comprising strings of memory cells, comprising: A stack comprising vertically alternating first and second layers is formed, the first layer comprising doped silicon dioxide and the second layer comprising undoped silicon dioxide, the stack comprising laterally spaced memory block regions having horizontally elongated trenches between the laterally spaced memory block regions, and a channel material string extending through the first and second layers in the memory block regions; The doped silicon dioxide in the first layer is selectively etched through the trench relative to the undoped silicon dioxide in the second layer; Conductive material forming conductive lines in the void spaces left by the etching in the first layer; as well as The intervention material is formed in the trench, located laterally between the laterally adjacent memory block regions and longitudinally along the memory block regions.

12. The method of claim 11, wherein the stack comprises a first region and a second region adjacent to the first region, the channel material string is formed in the first region, and the etching and the formation of conductive material in the void space occur in the first region but not in the second region, such that the doped silicon dioxide in the first layer and the undoped silicon dioxide in the second layer remain in the second region in the finished construction of the memory array.

13. The method of claim 11, wherein the channel material string comprises a portion of the memory cell string in the stack of the finished integrated circuit system construction, and individual memory cells in the memory cells are in individual first layers of the first layer and include: The channel material string is the channel material; Gate region, which is a portion of one of the conductive lines; as well as A memory structure, laterally located between the gate region and the channel material, the memory structure comprising: A charge blocking region that is laterally adjacent to the gate region; An insulating charge-transmitting material, which is laterally adjacent to the channel material; and Storage material, which is located laterally between the charge-blocking region and the insulating charge-transfer material.

14. The method of claim 13, wherein the memory array comprises NAND.

15. An integrated circuit system comprising: The first vertical stack comprises alternating insulating and conductive layers, each of the conductive layers individually comprising horizontally elongated conductive lines; as well as A second vertical stack is located next to the first vertical stack. The second vertical stack includes alternating first and second insulating layers, wherein the first insulating layer is individually at least primarily doped silicon dioxide and the second insulating layer is individually at least primarily undoped silicon dioxide.

16. The integrated circuit system of claim 15, wherein the doped silicon dioxide includes at least 1 x 1018 atoms / cm3of total dopant atoms in addition to silicon and oxygen. 18 3 atoms / cm3of total dopant atoms in addition to silicon and oxygen.​ 17. The integrated circuit system of claim 15, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 1 atomic percentage of total dopant atoms.

18. The integrated circuit system of claim 15, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 5 atomic percent of total dopant atoms.

19. The integrated circuit system of claim 15, wherein the doped silicon dioxide includes at least 1 x 1018 atoms / cm3 of a dopant other than silicon and oxygen to no more than 30 atomic percent of total dopant atoms. 18 3 atoms / cm3.​ 20. The integrated circuit system of claim 15, wherein the doped silicon dioxide comprises at least one of BPSG, BSG, and PSG.

21. The integrated circuit system of claim 15, wherein the undoped silicon dioxide comprises 0 atoms / cm 3 up to no more than a minimum of 1 x 10 10 atoms / cm 3 of total dopant atoms, in addition to silicon and oxygen.

22. An integrated circuit system comprising a memory array including strings of memory cells, comprising: The memory blocks are spaced horizontally apart, each including a first vertical stack, the first vertical stack including alternating insulating and conductive layers, the memory cell string including a string of channel material extending through the insulating and conductive layers, the conductive layer including horizontally elongated conductive lines; as well as A second vertical stack is located next to the first vertical stack. The second vertical stack includes alternating first and second insulating layers, wherein the first insulating layer is individually at least primarily doped silicon dioxide and the second insulating layer is individually at least primarily undoped silicon dioxide.

23. The integrated circuit system of claim 22, wherein, in addition to silicon and oxygen, the doped silicon dioxide comprises at least 1 × 10⁻⁶ ppm. 18 atoms / cm 3 The total dopant atoms are no more than 30 atomic percent.

24. The integrated circuit system of claim 22, wherein the doped silicon dioxide comprises at least one of BPSG, BSG, and PSG, and the undoped silicon dioxide comprises 0 atoms / cm². 3 Up to no greater than the minimum 1×10 10 atoms / cm 3 Total boron and / or phosphorus atoms.

25. The integrated circuit system of claim 22, wherein the channel material string includes a portion of the memory cell string in the stack, and individual memory cells are located in individual conductive layers of the conductive layer and include: The channel material string is the channel material; Gate region, which is a portion of one of the conductive lines; as well as A memory structure, laterally located between the gate region and the channel material, the memory structure comprising: A charge blocking region that is laterally adjacent to the gate region; An insulating charge-transmitting material, which is laterally adjacent to the channel material; and a storage material located laterally between the charge-blocking region and the insulating charge-transport material.

26. The integrated circuitry of claim 25, wherein the memory array comprises NAND.

Images