Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The manufacturing method comprises the following steps: providing a substrate; forming scan lines, gate electrodes and data lines on the substrate; forming a second insulating layer on a gate insulating layer; covering a negative photoresist layer on the second insulating layer; exposing and developing the negative photoresist layer from the bottom of the substrate, and finally removing the second insulating layer corresponding to the positions of the scan lines, the gate electrodes and the data lines, while keeping the second insulating layer in other areas; forming a metal oxide semiconductor layer on the second insulating layer; and performing a patterning process on the metal oxide semiconductor layer, so that the metal oxide semiconductor layer forms source electrodes, drain electrodes and data line bridge portions. The array substrate and the manufacturing method thereof save cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display device, in particular to an array substrate, a manufacturing method thereof and a display panel. BACKGROUND

[0002] At present, metal oxide TFT is widely concerned due to its higher electron mobility, higher light transmittance, lower leakage current, lower deposition temperature, lower manufacturing cost and other advantages compared with low-temperature polysilicon TFT and amorphous silicon TFT. However, in the structure of metal oxide TFT, in order to prevent the etching damage of the metal oxide back channel, an etch stop layer (ESL) structure is usually used to prevent the etching damage of the back channel, but a photomask is needed to be added, and before the S / D (source / drain) electrode of the TFT is manufactured, a conductor treatment is usually performed to ensure the good ohmic contact between the S / D and the semiconductor layer. In this way, the alignment deviation accumulated by the two-step photolithography process limits the precision of the active channel size, which is not conducive to the miniaturization of the TFT device size, and at the same time, the etch stop layer introduced in the etch stop layer (ESL) structure increases a thin film growth and photolithography process, increases the process complexity and cost, and indirectly reduces the market competitiveness of metal oxide.

[0003] In addition, as shown in Figure 1 and Figure 2 , the current array architecture of metal oxide semiconductor in cell touch control is as follows: in the case of the OC layer 42, the process is 9 masks and above. The specific process includes the following steps in sequence: forming a pattern including the gate 31 and the peripheral wire 37 by a one-time patterning process (1Mask); forming a pattern including the gate insulating layer 32 by a one-time patterning process (2Mask); forming a pattern including the metal oxide semiconductor layer 33 by a one-time patterning process (3Mask); forming a pattern including the etch stop layer 34 covering the metal oxide semiconductor layer 33 by a one-time patterning process (4Mask); forming a pattern including the drain 35, the source 36, the data line (not shown in the figure) and the bridge layer 38 for connecting the common electrode 41 and the peripheral wire 37 by a one-time patterning process (5Mask); forming a first insulating layer pattern; forming a pattern including the OC flat layer 42 by a one-time patterning process (6Mask); forming a pattern including the common electrode 41 by a one-time patterning process (7Mask); forming a second insulating layer pattern by a one-time patterning process (8Mask), and forming a through via hole 104 above the drain 35; forming a pattern of the pixel electrode 39 by a one-time patterning process (9Mask), and the pixel electrode 39 is connected with the drain 35 through the via hole 104. SUMMARY

[0004] Therefore, the present application provides an array substrate and a manufacturing method thereof, which saves the cost.

[0005] A manufacturing method of an array substrate, the manufacturing method comprising:

[0006] providing a substrate;

[0007] forming a first metal layer and a first insulating layer on the substrate in sequence;

[0008] covering the first insulating layer with a first positive photoresist layer;

[0009] exposing the first positive photoresist layer from the top of the substrate using a first half-tone mask plate, wherein the first half-tone mask plate comprises a first opaque area, a first semi-transparent area and a first fully transparent area, the first opaque area corresponds to the wire part of the scan line, the gate and the data line, the first semi-transparent area corresponds to the connecting part of the data line, and the first fully transparent area corresponds to other areas;

[0010] developing the first positive photoresist layer, retaining the first positive photoresist layer at positions corresponding to the scan line, the gate and the wire part, retaining the first positive photoresist layer at positions corresponding to the connecting part, and the thickness of the first positive photoresist layer corresponding to the connecting part is less than the thickness of the first positive photoresist layer corresponding to the scan line, the gate and the wire part, and the first positive photoresist layer is removed at other areas;

[0011] performing a patterning process on the first insulating layer and the first metal layer, so that the first metal layer forms the scan line, the gate and the data line, and the first insulating layer forms the gate insulating layer covering the scan line, the gate and the data line, wherein the data line comprises the wire part and the connecting part, the wire part is located between two adjacent scan lines, the connecting part is located at both ends of the wire part and connected to the wire part, and the gate is connected to the scan line;

[0012] performing a grayed thinning process on the first positive photoresist layer to remove the first positive photoresist layer corresponding to the connecting part, but still retaining the first positive photoresist layer corresponding to the scan line, the gate and the wire part;

[0013] performing a patterning process on the first insulating layer again to remove the gate insulating layer covering the connecting part, so that the connecting part is exposed;

[0014] stripping the first positive photoresist layer;

[0015] forming a second insulating layer on the gate insulating layer;

[0016] covering the second insulating layer with a negative photoresist layer;

[0017] exposing the negative photoresist layer from the bottom of the substrate;

[0018] developing the negative photoresist layer, removing the negative photoresist layer at positions corresponding to the scan line, the gate and the data line, and retaining the negative photoresist layer at other areas;

[0019] The second insulating layer is patterned to remove the second insulating layer corresponding to the scan lines, the gate and the data lines to expose the gate insulating layer and the connecting part;

[0020] The negative photoresist layer is peeled off;

[0021] A metal oxide semiconductor layer is formed on the second insulating layer, the gate insulating layer and the data lines;

[0022] The second positive photoresist layer is formed on the metal oxide semiconductor layer;

[0023] The second positive photoresist layer is exposed by using a second half-tone mask plate, wherein the second half-tone mask plate comprises a second opaque area, a second semi-transparent area and a second full-transparent area, the second opaque area corresponds to the active layer, the second semi-transparent area corresponds to the source, the drain and the data line bridge part, and the second full-transparent area corresponds to other areas;

[0024] The second positive photoresist layer is developed, the second positive photoresist layer is reserved at positions corresponding to the active layer, the second positive photoresist layer is reserved at positions corresponding to the source, the drain and the data line bridge part, the thickness of the second positive photoresist layer corresponding to the source, the drain and the data line bridge part is less than the thickness of the second positive photoresist layer corresponding to the active layer, and the second positive photoresist layer is removed at other areas;

[0025] The metal oxide semiconductor layer is patterned to form the active layer, the source, the drain and the data line bridge part, wherein the data line is connected to the source through the data line bridge part, the data line bridge part spans the scan line, and the two ends of the data line bridge part are respectively in contact with the connecting parts at the end parts of the two adjacent data lines to electrically connect the two adjacent data lines through the data line bridge part;

[0026] The second positive photoresist layer is thinned by ashing to remove the second positive photoresist layer corresponding to the source, the drain and the data line bridge part, but the second positive photoresist layer corresponding to the active layer is still reserved;

[0027] The source, the drain and the data line bridge part are conductorized to change the source, the drain and the data line bridge part from semiconductor to conductor, and the active layer is reserved as semiconductor;

[0028] The second positive photoresist layer is peeled off.

[0029] In the embodiment of the present application, the manufacturing method further comprises: when the metal oxide semiconductor layer is patterned, the metal oxide semiconductor layer also forms a pixel electrode,

[0030] performing gray thinning on the second positive photoresist layer to remove the second positive photoresist layer corresponding to the source electrode, the drain electrode and the data line bridge portion, and simultaneously removing the second positive photoresist layer corresponding to the pixel electrode;

[0031] performing conductorization processing on the source electrode, the drain electrode and the data line bridge portion to change the source electrode, the drain electrode and the data line bridge portion from semiconductor to conductor, and simultaneously performing conductorization processing on the pixel electrode to change the pixel electrode from semiconductor to conductor.

[0032] In an embodiment of the present application, the manufacturing method further comprises: exposing the first positive photoresist layer from the top of the substrate by using a first half-tone mask plate, wherein the first opaque area corresponds to the conductive portion of the scan line, the gate electrode and the data line, and the first opaque area also corresponds to the peripheral trace,

[0033] retaining the first positive photoresist layer at the position corresponding to the peripheral trace when developing the first positive photoresist layer;

[0034] performing patterning processing on the first insulating layer and the first metal layer to form the peripheral trace when the first metal layer forms the scan line, the gate electrode and the data line;

[0035] forming a third insulating layer covering the source electrode, the drain electrode, the active layer, the pixel electrode and the data line bridge portion, forming a first through hole at the position corresponding to the peripheral trace when performing patterning processing on the third insulating layer, and forming a first transparent conductive layer covering the third insulating layer;

[0036] performing patterning processing on the first transparent conductive layer to form a common electrode, and the common electrode is filled into the first through hole to contact the peripheral trace.

[0037] In an embodiment of the present application, the manufacturing method further comprises:

[0038] performing patterning processing on the first insulating layer and the first metal layer to form the peripheral trace when the first metal layer forms the scan line, the gate electrode and the data line;

[0039] forming a third insulating layer covering the source electrode, the drain electrode, the active layer and the data line bridge portion, forming a planar layer covering the third insulating layer, forming a second transparent conductive layer covering the planar layer, and performing patterning processing on the second transparent conductive layer to form a common electrode, and the common electrode is conductively connected with the peripheral trace;

[0040] forming a fourth insulating layer on the common electrode;

[0041] forming a third transparent conductive layer on the fourth insulating layer;

[0042] performing a patterning process on the third transparent conductive layer, so that the third transparent conductive layer forms a pixel electrode, and the pixel electrode is in conductive connection with the drain electrode.

[0043] In the embodiments of the present application, the conductorization process includes a hydrogenation process or an ion doping process.

[0044] The present application also provides an array substrate, which comprises:

[0045] a substrate;

[0046] scan lines, gate electrodes and data lines formed on the substrate, the data lines comprising wire portions and connecting portions, the wire portions being located between two adjacent scan lines, the connecting portions being located at two ends of the wire portions and connected with the wire portions, and the gate electrodes being connected with the scan lines;

[0047] a gate insulating layer corresponding to the scan lines, the gate electrodes and the wire portions;

[0048] a second insulating layer formed on the gate insulating layer, the second insulating layer covering areas other than the scan lines, the gate electrodes and the data lines, and the connecting portions not being covered by the second insulating layer;

[0049] a source electrode, a drain electrode, an active layer and a data line bridging portion formed on the second insulating layer, wherein the source electrode, the drain electrode and the data line bridging portion are converted from semiconductors to conductors by a conductorization process, the active layer remains a semiconductor, the data line is connected with the source electrode through the data line bridging portion, the data line bridging portion spans the scan lines, and two ends of the data line bridging portion are in contact with the connecting portions of two adjacent data line ends respectively, so that the two adjacent data lines are electrically connected through the data line bridging portion.

[0050] In the embodiments of the present application, the array substrate further comprises a pixel electrode formed on the second insulating layer, the pixel electrode being converted from a semiconductor to a conductor by a conductorization process, and the pixel electrode is arranged in the same layer as the drain electrode and is in electrical connection with the drain electrode.

[0051] In the embodiments of the present application, the array substrate further comprises:

[0052] a third insulating layer formed on the source electrode, the drain electrode, the active layer, the data line bridging portion and the pixel electrode;

[0053] Peripheral traces formed on the substrate;

[0054] The third insulating layer forms a first through-hole at the position corresponding to the peripheral trace;

[0055] A common electrode is formed on the third insulating layer, and the common electrode is filled into the first through hole and makes conductive contact with the peripheral trace.

[0056] In embodiments of the present invention, the array substrate further includes:

[0057] Peripheral traces formed on the substrate;

[0058] A third insulating layer is formed on the source, the drain, the active layer, and the data line bridging portion;

[0059] A planarization layer is formed on the third insulating layer; a common electrode is formed on the planarization layer, the common electrode being electrically connected to the peripheral trace;

[0060] A fourth insulating layer is formed on the common electrode;

[0061] A pixel electrode is formed on the fourth insulating layer, and the pixel electrode is conductively connected to the drain electrode.

[0062] The present invention also provides a display panel comprising the array substrate described above.

[0063] The array substrate of the present invention first forms a full-surface first metal layer and a first insulating layer on a substrate, and then covers the first insulating layer with a first positive photoresist layer. Next, the first positive photoresist layer is exposed and developed from the top of the substrate using a first halftone mask. Then, through patterning, scan lines, gate lines, and data lines are formed on the first metal layer, and a gate insulating layer is formed covering the scan lines, gate lines, and data lines. Immediately afterward, a full-surface second insulating layer is formed on the gate insulating layer, and a negative photoresist layer is covered on the second insulating layer. The negative photoresist layer is then exposed and developed from the bottom of the substrate. At this point, by using the patterned first metal layer to replace the function of the photomask, an additional photomask is not needed to expose the negative photoresist layer, and the patterning of the second insulating layer can still be completed. Ultimately, the second insulating layer corresponding to the scan lines, gate lines, and data lines is removed to expose the gate insulating layer and the connection portion. This eliminates the need for a separate photomask for fabricating the second insulating layer.

[0064] The data line comprises a wire part and a connecting part. The wire part is located between two adjacent scanning lines. The connecting part is located at the two ends of the wire part and connected with the wire part. When the first insulating layer is patterned, the gate insulating layer covering the connecting part is removed to expose the connecting part. When the second insulating layer is patterned, the gate insulating layer covering the connecting part is also removed to expose the connecting part. Finally, a whole surface metal oxide semiconductor layer is formed on the second insulating layer, the gate insulating layer and the data line. The metal oxide semiconductor layer is patterned to form an active layer, a source, a drain, a pixel electrode and a data line bridging part. The two ends of the data line bridging part are respectively in contact with the exposed connecting parts of the two adjacent data line ends to achieve the purpose of electrically connecting the two adjacent data lines through the touch bridging part. At this time, the connecting part of the data line has been exposed when the first insulating layer and the second insulating layer are patterned, so that an additional mask for forming a bridging hole for electrically connecting the two adjacent data lines is not needed. One mask for forming the bridging hole is saved.

[0065] Meanwhile, the active layer, the source, the drain, the pixel electrode and the data line bridging part are integrally formed by the metal oxide semiconductor layer. Therefore, the active layer, the source, the drain, the pixel electrode and the data line bridging part do not need to be respectively formed by a separate mask, and at least one mask is saved. BRIEF DESCRIPTION OF DRAWINGS

[0066] Figure 1 It is a schematic diagram of a partial cross-sectional structure of an array substrate in the prior art;

[0067] Figure 2 It is a schematic diagram of a partial cross-sectional structure of an array substrate in the prior art;

[0068] Figures 3 to 8 It is a schematic diagram of a cross-sectional manufacturing process of a manufacturing method of an array substrate of the present application;

[0069] Figure 9 It is a schematic diagram of a cross-sectional manufacturing process of a manufacturing method of an array substrate of the present application; Figure 8 It is a schematic diagram of a planar structure of an array substrate;

[0070] Figures 10 to 13 It is a schematic diagram of a cross-sectional manufacturing process of a manufacturing method of an array substrate of the present application;

[0071] Figures 13 to 17 It is a schematic diagram of a cross-sectional manufacturing process of a manufacturing method of an array substrate of the first embodiment of the present application;

[0072] Figure 18 It is a schematic diagram of a planar structure of an array substrate; Figure 17

[0073] ​Figures 19 to 20 A cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the first embodiment of the present invention;

[0074] Figure 21 yes Figure 20 A schematic diagram of the planar structure of the array substrate shown;

[0075] Figures 22 to 23 A cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the first embodiment of the present invention;

[0076] Figure 24 yes Figure 23 A schematic diagram of the planar structure of the array substrate shown;

[0077] Figure 25 This is a schematic cross-sectional view of the array substrate according to the second embodiment of the present invention; Detailed Implementation

[0078] To facilitate understanding by those skilled in the art, the following embodiments illustrate the specific implementation process of the technical solution provided in this application.

[0079] First Embodiment

[0080] Figures 3 to 8 This is a cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method of the present invention; Figure 9 yes Figure 8 A schematic diagram of the planar structure of the array substrate shown; Figures 10 to 13 This is a cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method of the present invention; Figures 13 to 17 This is a cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the first embodiment of the present invention; Figure 18 yes Figure 17 A schematic diagram of the planar structure of the array substrate shown; Figures 19 to 20 A cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the first embodiment of the present invention; Figure 21 yes Figure 20 A schematic diagram of the planar structure of the array substrate shown;

[0081] Figures 22 to 23 A cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the first embodiment of the present invention; Figure 24 yes Figure 23 The schematic diagram of the planar structure of the array substrate shown is as follows; Figures 1 to 24 As shown, the present invention provides a method for fabricating an array substrate, the method comprising:

[0082] like Figure 3 and Figure 9 As shown, a substrate 11 is provided; the substrate 11 may be made of materials such as glass, quartz, acrylic or polycarbonate.

[0083] A first metal layer 12 and a first insulating layer 13 are formed on the substrate 11 in sequence; the first metal layer 12 can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo); the first insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, for example.

[0084] A first positive photoresist layer 14 is coated on the first insulating layer 13; the part of the first positive photoresist layer 14 exposed to light will dissolve in the photoresist developer, while the part not exposed to light will not dissolve in the photoresist developer and thus remain on the first insulating layer 13.

[0085] The first positive photoresist layer 14 is exposed to light from the top of the substrate 11 using a first half-tone mask 15, wherein the first half-tone mask 15 includes a first opaque area 151, a first semi-transparent area 152 and a first fully transparent area 153; the first opaque area 151 corresponds to the wire part 1231 of the scan line 121, the gate 122 and the data line 123; the first semi-transparent area 152 corresponds to the connection part 1232 of the data line 123; and the first fully transparent area 153 corresponds to other areas.

[0086] As shown in Figure 4 and Figure 9 , the first positive photoresist layer 14 is developed, the first positive photoresist layer 14 is retained at positions corresponding to the scan line 121, the gate 122 and the wire part 1231, the first positive photoresist layer 14 is retained at positions corresponding to the connection part 1232, the thickness of the first positive photoresist layer 14 corresponding to the connection part 1232 is less than the thickness of the first positive photoresist layer 14 corresponding to the scan line 121, the gate 122 and the wire part 1231, and the first positive photoresist layer 14 is removed from other areas.

[0087] As shown in Figure 5 and Figure 9 , the first insulating layer 13 and the first metal layer 12 are subjected to a patterning process, so that the first metal layer 12 forms the scan line 121, the gate 122 and the data line 123, and the first insulating layer 13 forms the gate insulating layer 131 covering the scan line 121, the gate 122 and the data line 123; the data line 123 includes the wire part 1231 and the connection part 1232; the wire part 1231 is located between two adjacent scan lines 121; the connection part 1232 is located at both ends of the wire part 1231 and connected to the wire part 1231; and the gate 122 is connected to the scan line 121. In this embodiment, the patterning process of the first insulating layer 13 and the first metal layer 12 is as follows: first, dry etching is performed on the first insulating layer 13 to form the gate insulating layer 131, and then wet etching is performed on the first metal layer 12 to form the scan line 121, the gate 122 and the data line 123.

[0088] As shown in Figure 6 and Figure 9 The first positive photoresist layer 14 is thinned by ashing to remove the first positive photoresist corresponding to the connection portion 1232, but still retains the first positive photoresist layer 14 corresponding to the scan line 121, the gate 122 and the wire portion 1231.

[0089] As shown in Figure 7 and Figure 9 The first insulating layer 13 is again patterned to remove the gate insulating layer 131 covering the connection portion 1232, so that the connection portion 1232 is exposed. In this embodiment, the first insulating layer 13 is again patterned by dry etching to expose the connection portion 1232, and the gate insulating layer 131 on the scan line 121, the gate 122 and the wire portion 1231 is continuously retained to avoid the scan line 121, the gate 122 and the wire portion 1231 from being corroded in the subsequent process.

[0090] As shown in Figure 8 and Figure 9 After the first insulating layer 13 is patterned, the first positive photoresist layer 14 is stripped to expose the gate insulating layer 131.

[0091] As shown in Figure 10 and Figure 18 A second insulating layer 16 is formed on the gate insulating layer 131; a negative photoresist layer 17 is covered on the second insulating layer 16; and the negative photoresist layer 17 is exposed from the bottom of the substrate 11.

[0092] As shown in Figure 11 and Figure 18 The negative photoresist layer 17 is developed to remove the negative photoresist layer 17 corresponding to the scan line 121, the gate 122 and the data line 123, while the negative photoresist layer 17 in other areas is retained. In this embodiment, since the photoresist layer covered on the second insulating layer 16 is the negative photoresist layer 17, the part of the negative photoresist layer 17 not exposed to light will dissolve in the photoresist developer, while the part exposed to light will not dissolve in the photoresist developer and thus remain on the first insulating layer 13. Therefore, when the negative photoresist layer 17 is exposed from the bottom of the substrate 11, the negative photoresist layer 17 on the scan line 121, the gate 122 and the data line 123 will not be exposed to light because the scan line 121, the gate 122 and the data line 123 block the light from the bottom of the substrate 11. Finally, the negative photoresist layer 17 corresponding to the scan line 121, the gate 122 and the data line 123 can be removed, while the other negative photoresist layer 17 exposed to light is retained.

[0093] As shown in Figure 12 and Figure 18As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232.

[0094] As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232. Figure 13 Figure 18 As shown, after the second insulating layer 16 is patterned, the negative photoresist layer 17 is stripped; at this time, the patterned second insulating layer 16 not only can play an insulating role, but also can protect the cross sections of the scan line 121, the gate 122 and the data line 123 from being corroded in the subsequent process.

[0095] As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232. Figure 14 Figure 18 As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232.

[0096] As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232. Figure 15 18 As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232.

[0097] As shown, the second insulating layer 16 is patterned, and the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232. Figure 16 Figure 18 ​​​​As shown in FIG. 1 1, the metal oxide semiconductor layer 18 is subjected to a patterning process, so that the metal oxide semiconductor layer 18 forms an active layer 183, a source electrode 181, a drain electrode 182, a pixel electrode 185, and a data line bridge portion 184. The data line 123 is connected to the source electrode 181 through the data line bridge portion 184. The data line bridge portion 184 crosses the scan line 121, and the two ends of the data line bridge portion 184 are in contact with the connection portions 1232 of the end portions of two adjacent data lines 123, so that the two adjacent data lines 123 are electrically connected through the data line bridge portion 184. In the embodiment, since the pixel electrode 185 and the drain electrode 182 are integrally formed by the metal oxide semiconductor layer 18, the pixel electrode 185 and the drain electrode 182 are directly connected, and no insulating layer and bridge layer are needed to electrically connect the pixel electrode 185 and the drain electrode 182, so that the direct connection between the pixel electrode 185 and the drain electrode 182 is better. Meanwhile, the source electrode 181, the drain electrode 182, and the active layer 183 can also be directly connected, so that the direct connection between the source electrode 181, the drain electrode 182, and the active layer 183 is better.

[0098] As shown in FIG. 12, Figure 17 and Figure 18 the second positive photoresist layer 19 is subjected to a gray ash thinning process, so that the second positive photoresist layer 19 corresponding to the source electrode 181, the drain electrode 182, the pixel electrode 185, and the data line bridge portion 184 is removed, but the second positive photoresist layer 19 corresponding to the active layer 183 is still retained.

[0099] As shown in FIG. 13, Figure 19 and Figure 21 the source electrode 181, the drain electrode 182, the pixel electrode 185, and the data line bridge portion 184 are subjected to a conductorization process, so that the source electrode 181, the drain electrode 182, the pixel electrode 185, and the data line bridge portion 184 are converted from semiconductors to conductors, while the active layer 183 remains a semiconductor. In the embodiment, the conductorization process of the source electrode 181, the drain electrode 182, the pixel electrode 185, and the data line bridge portion 184 includes a hydrogenation process or an ion doping process. Since the second positive photoresist layer 19 corresponding to the active layer 183 is not removed, the active layer 183 is protected by the second positive photoresist layer 19 during the hydrogenation process or the ion doping process, and remains a conductor. The source electrode 181, the drain electrode 182, the pixel electrode 185, and the data line bridge portion 184 are not protected by the second positive photoresist layer 19, and are further converted from semiconductors to conductors.

[0100] As shown in FIG. 14, Figure 20 and Figure 21As shown, after the source 181, the drain 182, the pixel electrode 185 and the data line bridge portion 184 are subjected to hydrogenation treatment or ion doping treatment, the second positive photoresist layer 19 is stripped to expose the active layer 183.

[0101] The array substrate of the present application is first formed by sequentially forming a whole first metal layer 12 and a first insulating layer 13 on the substrate 11, and covering the first positive photoresist layer 14 on the first insulating layer 13; then the first positive photoresist layer 14 is exposed and developed from the top of the substrate 11 by using the first half-tone mask 15; and the first metal layer 12 is patterned to form the scan line 121, the gate 122 and the data line 123, and the first insulating layer 13 is patterned to form the gate insulating layer 131 covering the scan line 121, the gate 122 and the data line 123. Next, a whole second insulating layer 16 is formed on the gate insulating layer 131, and a negative photoresist layer 17 is covered on the second insulating layer 16; and the negative photoresist layer 17 is exposed and developed from the bottom of the substrate 11. At this time, by using the first metal layer 12 after the patterning process to replace the function of the mask, it is not necessary to additionally increase a mask to expose the negative photoresist layer 17, and the second insulating layer 16 can also be patterned, and finally the second insulating layer 16 corresponding to the scan line 121, the gate 122 and the data line 123 is removed to expose the gate insulating layer 131 and the connecting portion 1232. One mask for making the second insulating layer 16 is saved.

[0102] The data line 123 includes a wire part 1231 and a connecting part 1232. The wire part 1231 is located between two adjacent scan lines 121. The connecting part 1232 is located at the two ends of the wire part 1231 and connected to the wire part 1231. When the first insulating layer 13 is patterned, the gate insulating layer 131 covering the connecting part 1232 is removed to expose the connecting part 1232. When the second insulating layer 16 is patterned, the gate insulating layer 131 covering the connecting part 1232 is also removed to expose the connecting part 1232. Finally, the metal oxide semiconductor layer 18 is formed on the second insulating layer 16, the gate insulating layer 131 and the data line 123. The metal oxide semiconductor layer 18 is patterned to form the active layer 183, the source 181, the drain 182, the pixel electrode 185 and the data line bridge part 184. The two ends of the data line bridge part 184 are respectively connected to the connecting parts 1232 exposed at the ends of the two adjacent data lines 123 to achieve the electrical connection of the two adjacent data lines 123 through the data line bridge part. At this time, the connecting part 1232 of the data line 123 has been exposed when the first insulating layer 13 and the second insulating layer 16 are patterned, so an additional mask is not needed to form a bridge hole for the electrical connection of the two adjacent data lines 123. One mask for forming the bridge hole is saved.

[0103] Meanwhile, the active layer 183, the source 181, the drain 182, the pixel electrode 185 and the data line bridge part 184 are integrally formed by the metal oxide semiconductor layer 18. Therefore, the active layer 183, the source 181, the drain 182, the pixel electrode 185 and the data line bridge part 184 do not need to be formed by separate masks, and at least one mask is saved.

[0104] Further, the first positive photoresist layer 14 is exposed by the first half-tone mask 15 from the top of the substrate 11. When the first opaque area 151 corresponds to the scan line 121, the gate 122 and the wire part 1231, the first opaque area 151 also corresponds to the peripheral wire. In this embodiment, the peripheral wire is located in the non-display area, and the peripheral wire is, for example, a common line, a touch lead and the like.

[0105] When the first positive photoresist layer 14 is developed, the first positive photoresist layer 14 is retained at the position corresponding to the peripheral wire. When the first insulating layer 13 and the first metal layer 12 are patterned, the first metal layer 12 forms the scan line 121, the gate 122 and the data line 123, and also forms the peripheral wire (not shown).

[0106] As shown in FIG. 1, the display panel 100 includes a substrate 11, a scan line 121, a gate 122, a data line 123, a first insulating layer 13, a first metal layer 12, a second insulating layer 16, a gate insulating layer 131, a metal oxide semiconductor layer 18 and a pixel electrode 185. Figure 22 and 24As shown, a full-surface third insulating layer 22 is formed on the source electrode 181, drain electrode 182, active layer 183, pixel electrode 185, and data line bridging portion 184. The third insulating layer 22 is patterned to form first vias at positions corresponding to peripheral traces. A full-surface first transparent conductive layer is formed on the third insulating layer 22. The third insulating layer 22 is, for example, made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The first transparent conductive layer is, for example, made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the first transparent conductive layer is indium tin oxide (ITO).

[0107] like Figure 23 and Figure 24 As shown, the first transparent conductive layer is patterned to form a common electrode 23, which is filled into the first via and contacts the peripheral traces. In this embodiment, the peripheral traces are, for example, common lines, and these common lines can be reused as touch leads. Correspondingly, the common electrode 23 can also be reused as a touch electrode. When the common electrode 23 is reused as a touch electrode, the common line also switches to a touch lead. During the touch phase, the common line (touch lead) provides touch driving signals to the common electrode 23 (touch electrode) and receives touch feedback signals. During the display phase, the common line provides common signals to the common electrode 23, providing the signals required by the common electrode 23 during display. By reusing the common electrode 23 as a touch electrode and the common line as a touch lead, the thickness of the array substrate can be reduced, thus reducing the thickness of the touch display panel when the array substrate is applied to a touch display panel.

[0108] The present invention also provides an array substrate, the array substrate comprising:

[0109] The substrate 11 may be made of materials such as glass, quartz, acrylic or polycarbonate.

[0110] Scan lines 121, gates 122, and data lines 123 are formed on a substrate 11. Each data line 123 includes a conductor portion 1231 and a connecting portion 1232. The conductor portion 1231 is located between two adjacent scan lines 121, and the connecting portion 1232 is located at both ends of the conductor portion 1231 and connected to it. The gate 122 is connected to the scan lines 121. In this embodiment, the scan lines 121, gates 122, and data lines 123 are all obtained by patterning a first metal layer 12. The first metal layer 12 can be made of copper and molybdenum-niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo).

[0111] A gate insulating layer 131 is formed on the scan line 121, the gate 122 and the conductor portion 1231. In the present embodiment, the gate insulating layer 131 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of both, for example.

[0112] A second insulating layer 16 is formed on the gate insulating layer 131, covering the areas other than the scan line 121, the gate 122 and the data line 123, and the connection portion 1232 is not covered by the second insulating layer 16. In the present embodiment, the scan line 121, the gate 122 and the data line 123 are formed by patterning the first metal layer 12, and therefore, the scan line 121, the gate 122 and the data line 123 have multiple sections. The second insulating layer 16 is arranged immediately adjacent to the sections of the scan line 121, the gate 122 and the data line 123, and can not only serve as an insulating layer, but also protect the sections of the scan line 121, the gate 122 and the data line 123 from being corroded in the subsequent processes.

[0113] A source 181, a drain 182, an active layer 183, a pixel electrode 185 and a data line bridge portion 184 are formed on the second insulating layer 16. The source 181, the drain 182, the pixel electrode 185 and the data line bridge portion 184 are converted from a semiconductor to a conductor by a conductorization process, and the active layer 183 remains a semiconductor. The data line 123 is connected to the source 181 through the data line bridge portion 184, the data line bridge portion 184 spans the scan line 121, and the two ends of the data line bridge portion 184 are in contact with the connection portions 1232 of the two adjacent data lines 123, so that the two adjacent data lines 123 are electrically connected through the data line bridge portion 184. In the present embodiment, the source 181, the drain 182, the active layer 183, the pixel electrode 185 and the data line bridge portion 184 are integrally formed by a metal oxide semiconductor layer 18, and the metal oxide semiconductor layer 18 after hydrogenation treatment or ion doping treatment forms the source 181, the drain 182, the pixel electrode 185 and the data line bridge portion 184, and the metal oxide semiconductor layer 18 without hydrogenation treatment or ion doping treatment forms the active layer 183. The drain 182 is in direct contact with the pixel electrode 185.

[0114] Further, the array substrate further comprises:

[0115] A third insulating layer 22 is formed on the source 181, the drain 182, the active layer 183, the data line bridge portion 184 and the pixel electrode 185. The third insulating layer 22 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of both, for example.

[0116] The peripheral traces formed on the substrate 11. In the present embodiment, the peripheral traces are located in the non-display area, and the peripheral traces are, for example, common lines, touch lead lines, and the like.

[0117] The third insulating layer 22 forms a first via hole (not shown in the figure) at the position corresponding to the peripheral traces.

[0118] The common electrode 23 formed on the third insulating layer 22, and the common electrode 23 fills the first via hole and is in conductive contact with the peripheral traces. In the present embodiment, the common electrode 23 is obtained by patterning a first transparent conductive layer, wherein the first transparent conductive layer is made of, for example, a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the present embodiment, the first transparent conductive layer is indium tin oxide (ITO).

[0119] Further, the peripheral traces are, for example, common lines, and the common lines can be reused as touch lead lines, and accordingly, the common electrode 23 can also be reused as a touch electrode. When the common electrode 23 is reused as a touch electrode, the common lines are also switched to touch lead lines. In the touch phase, the common lines (touch lead lines) provide a touch driving signal to the common electrode 23 (touch electrode) and receive a touch feedback signal; in the display phase, the common lines provide a common signal to the common electrode 23, which provides the signal required by the common electrode 23 during display. By reusing the common electrode 23 as a touch electrode and the common lines as touch lead lines, the thickness of the array substrate can be reduced, and when the array substrate is applied to a touch display panel, the thickness of the touch display panel is reduced.

[0120] Further, the present application also provides a display device comprising the array substrate described above.

[0121] Further, the display panel comprises a color film substrate (not shown in the figure) arranged opposite to the array substrate and a liquid crystal layer (not shown in the figure) arranged between the array substrate and the color film substrate. The array substrate and the color film substrate are pasted together by a frame sealant, so as to limit the liquid crystal layer in the area surrounded by the frame sealant.

[0122] Further, the color film substrate further comprises a substrate and a color filter layer arranged on the substrate, and the color filter layer comprises a red photoresist unit, a green photoresist unit and a blue photoresist unit. The red photoresist unit, the green photoresist unit and the blue photoresist unit are arranged periodically, and the red photoresist unit is arranged in a column, the green photoresist unit is arranged in a column, and the blue photoresist unit is arranged in a column. At the same time, the red photoresist unit, the green photoresist unit and the blue photoresist unit are respectively one-to-one opposite to each sub-pixel on the array substrate, and along the thickness direction of the display panel, the projections of the two one-to-one opposite ones on the substrate overlap.

[0123] Further, in order to avoid the light emitted from the adjacent two sub-pixels from mutual crosstalk, the color film substrate can further include a black matrix pattern (BM). For example, the black matrix pattern includes a plurality of parallel first light shielding strips and a plurality of parallel second light shielding strips, and the plurality of first light shielding strips and the plurality of second light shielding strips enclose a plurality of grids. Each grid encloses an area where a sub-pixel is located.

[0124] For other structures of the display panel, refer to the prior art, which will not be described here.

[0125] Second embodiment

[0126] Figures 3 to 8 A cross-sectional manufacturing process schematic diagram of the manufacturing method of the array substrate of the present application is shown in FIG. 2. Figure 9 Figure 8 A planar structure schematic diagram of the array substrate is shown in FIG. 3. Figures 10 to 13 A cross-sectional manufacturing process schematic diagram of the manufacturing method of the array substrate of the present application is shown in FIG. 2. Figure 25 A cross-sectional structure schematic diagram of the array substrate of the second embodiment of the present application is shown in FIG. 4. Figures 3 to 13 Figure 25 As shown in FIGS. 1 and 2, the array substrate and the manufacturing method thereof provided by the second embodiment of the present application are basically the same as the array substrate and the manufacturing method thereof in the first embodiment, and the difference lies in that, in the present embodiment, the manufacturing method and the structure after forming the third insulating layer covering the source, the drain, the active layer and the data line bridge portion are different.

[0127] Further, the manufacturing method of the array substrate further includes:

[0128] When the first metal layer 12 is patterned to form the scan line 121, the gate 122 and the data line 123, the peripheral wire is also formed. The peripheral wire includes the touch lead or the common line.

[0129] The third insulating layer 22 covering the source 181, the drain 182, the active layer 183 and the data line bridge portion 184 is formed, the planar layer 24 covering the third insulating layer is formed, the second transparent conductive layer covering the planar layer 24 is formed, and the second transparent conductive layer is patterned to form the common electrode 23. The common electrode 23 is conductively connected with the peripheral wire.

[0130] ​​A fourth insulating layer 25 is formed on the common electrode 23; a third transparent conductive layer is formed on the fourth insulating layer 25; the third transparent conductive layer is patterned to form a pixel electrode 185, which is electrically connected with the drain electrode 182. When the fourth insulating layer 25 is patterned, a second through hole is formed at the position corresponding to the drain electrode 182, the drain electrode 182 is exposed through the second through hole, and the pixel electrode 185 is filled into the second through hole to be electrically connected with the drain electrode 182.

[0131] The application further provides an array substrate, which further comprises:

[0132] A peripheral trace formed on the substrate 11;

[0133] A third insulating layer 22 formed on the source electrode 181, the drain electrode 182, the active layer 183 and the data line bridge 184;

[0134] A planar layer 24 formed on the third insulating layer 22; and a common electrode 23 formed on the planar layer 24, which is electrically connected with the peripheral trace.

[0135] A fourth insulating layer 25 formed on the common electrode 23;

[0136] A pixel electrode 185 formed on the fourth insulating layer 25, which is electrically connected with the drain electrode 182. The fourth insulating layer 25 has a second through hole penetrating to the drain electrode 182, the drain electrode 182 is exposed through the second through hole, and the pixel electrode 185 is filled into the second through hole to be electrically connected with the drain electrode 182. In this context, the orientation words such as up, down, left, right, front and back are defined according to the position of the structure in the drawing and the position of the structure relative to each other, only for the purpose of expressing the technical solution clearly and conveniently. It should be understood that the use of orientation words should not limit the scope of the application claimed. It should also be understood that the terms "first" and "second" used herein are only used for distinguishing names, and do not limit the number and order.

[0137] The above is only the preferred embodiment of the application, and does not limit the application in any form. Although the application has been disclosed as above with the preferred embodiment, it is not intended to limit the application. Any skilled person in the art can make some changes or modifications to the disclosed technical content without departing from the technical solution of the application, and the equivalent embodiments with equivalent changes are equivalent. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application are still within the protection scope of the technical solution of the application.

Claims

1. An array substrate, characterized in that, The array substrate includes: Base (11); Scan lines (121), gates (122), and data lines (123) are formed on the substrate (11). The data lines (123) include conductor portions (1231) and connecting portions (1232). The conductor portions (1231) are located between two adjacent scan lines (121). The connecting portions (1232) are located at both ends of the conductor portions (1231) and connected to the conductor portions (1231). The gates (122) are connected to the scan lines (121). A gate insulating layer (131) is correspondingly covered on the scan line (121), the gate (122) and the conductor portion (1231). A second insulating layer (16) is formed on the gate insulating layer (131), the second insulating layer (16) covers the area except for the scan line (121), the gate (122) and the data line (123), and the connection portion (1232) is not covered by the second insulating layer (16). A source (181), a drain (182), an active layer (183), and a data line bridging portion (184) are formed on the second insulating layer (16). The source (181), the drain (182), and the data line bridging portion (184) are converted from semiconductors to conductors through a conductor-forming process, while the active layer (183) remains a semiconductor. The data line (123) is connected to the source (181) through the data line bridging portion (184). The data line bridging portion (184) spans the scan line (121), and both ends of the data line bridging portion (184) are respectively in contact with the connection portion (1232) at the ends of two adjacent data lines (123), so that the two adjacent data lines (123) are electrically connected through the data line bridging portion (184).

2. The array substrate according to claim 1, characterized in that, The array substrate further includes a pixel electrode (185) formed on the second insulating layer (16), wherein the pixel electrode (185) is converted from a semiconductor to a conductor through a conductor-conducting process, and the pixel electrode (185) is disposed on the same layer as the drain (182) and electrically connected to the drain (182).

3. The array substrate according to claim 2, characterized in that, The array substrate further includes: A third insulating layer (22) is formed on the source electrode (181), the drain electrode (182), the active layer (183), the data line bridging portion (184), and the pixel electrode (185). Peripheral traces formed on the substrate (11); The third insulating layer (22) forms a first through hole at the position corresponding to the peripheral trace; A common electrode (23) is formed on the third insulating layer (22), and the common electrode (23) is filled into the first through hole and makes conductive contact with the peripheral trace.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes: Peripheral traces formed on the substrate (11); A third insulating layer (22) is formed on the source (181), the drain (182), the active layer (183) and the data line bridging portion (184). A planarization layer (24) is formed on the third insulating layer (22); a common electrode (23) is formed on the planarization layer (24), the common electrode (23) being electrically connected to the peripheral wiring; A fourth insulating layer (25) is formed on the common electrode (23); A pixel electrode (185) is formed on the fourth insulating layer (25), and the pixel electrode (185) is electrically connected to the drain electrode (182).

5. A method for fabricating an array substrate, characterized in that, The manufacturing method includes: Provide a base (11); A first metal layer (12) and a first insulating layer (13) are sequentially formed on the substrate (11). A first positive photoresist layer (14) is covered on the first insulating layer (13). The first positive photoresist layer (14) is exposed from the top of the substrate (11) using a first halftone mask (15). The first halftone mask (15) includes a first opaque area (151), a first semi-transparent area (152), and a first fully transparent area (153). The first opaque area (151) corresponds to the conductor portion (1231) of the scan line (121), the gate (122), and the data line (123). The first semi-transparent area (152) corresponds to the connection portion (1232) of the data line (123). The first fully transparent area (153) corresponds to other areas. The first positive photoresist layer (14) is developed, and the first positive photoresist layer (14) is retained at the positions corresponding to the scan line (121), the gate (122) and the conductor portion (1231), and the first positive photoresist layer (14) is retained at the position corresponding to the connection portion (1232). The thickness of the first positive photoresist layer (14) corresponding to the connection portion (1232) is less than the thickness of the first positive photoresist layer (14) corresponding to the scan line (121), the gate (122) and the conductor portion (1231), while the first positive photoresist layer (14) is removed in other areas. The first insulating layer (13) and the first metal layer (12) are patterned so that the first metal layer (12) forms the scan line (121), the gate (122) and the data line (123), and the first insulating layer (13) forms a gate insulating layer (131) covering the scan line (121), the gate (122) and the data line (123). The data line (123) includes the conductor portion (1231) and the connecting portion (1232). The conductor portion (1231) is located between two adjacent scan lines (121). The connecting portion (1232) is located at both ends of the conductor portion (1231) and connected to the conductor portion (1231). The gate (122) is connected to the scan line (121). The first positive photoresist layer (14) is thinned by ashing to remove the first positive photoresist layer (14) corresponding to the connection portion (1232), but the first positive photoresist layer (14) corresponding to the scan line (121), the gate (122) and the conductor portion (1231) is still retained. The first insulating layer (13) is patterned again to remove the gate insulating layer (131) covering the connection portion (1232), so that the connection portion (1232) is exposed. Peel off the first positive photoresist layer (14); A second insulating layer (16) is formed on the entire surface of the gate insulating layer (131). A negative photoresist layer (17) is covered on the second insulating layer (16). The negative photoresist layer (17) is exposed from the bottom of the substrate (11); The negative photoresist layer (17) is developed, and the negative photoresist layer (17) is removed at the positions corresponding to the scan line (121), the gate (122) and the data line (123), while the negative photoresist layer (17) is retained in other areas. The second insulating layer (16) is patterned to remove the second insulating layer (16) corresponding to the scan line (121), the gate (122) and the data line (123) to expose the gate insulating layer (131) and the connection portion (1232). The negative photoresist layer (17) is stripped off. A full-surface metal oxide semiconductor layer (18) is formed on the second insulating layer (16), the gate insulating layer (131) and the data line (123). A second positive photoresist layer (19) is covered on the metal oxide semiconductor layer (18). The second positive photoresist layer (19) is exposed using a second halftone mask (21). The second halftone mask (21) includes a second opaque area (211), a second semi-transparent area (212), and a second fully transparent area (213). The second opaque area (211) corresponds to the active layer (183), the second semi-transparent area (212) corresponds to the source (181), the drain (182), and the data line bridging part (184), and the second fully transparent area (213) corresponds to other areas. The second positive photoresist layer (19) is developed, and the second positive photoresist layer (19) is retained at the position corresponding to the active layer (183), and the second positive photoresist layer (19) is retained at the positions corresponding to the source (181), the drain (182) and the data line bridge (184). The thickness of the second positive photoresist layer (19) corresponding to the source (181), the drain (182) and the data line bridge (184) is less than the thickness of the second positive photoresist layer (19) corresponding to the active layer (183), while the second positive photoresist layer (19) is removed in other areas. The metal oxide semiconductor layer (18) is patterned to form the active layer (183), the source (181), the drain (182), and the data line bridging portion (184). The data line (123) is connected to the source (181) through the data line bridging portion (184). The data line bridging portion (184) spans the scan line (121), and both ends of the data line bridging portion (184) are respectively in contact with the connection portion (1232) at the ends of two adjacent data lines (123), so that the two adjacent data lines (123) are electrically connected through the data line bridging portion (184). The second positive photoresist layer (19) is thinned by ashing to remove the second positive photoresist layer (19) corresponding to the source (181), the drain (182) and the data line bridge (184), but the second positive photoresist layer (19) corresponding to the active layer (183) is still retained. The source (181), drain (182) and data line bridging portion (184) are made into conductors, so that the source (181), drain (182) and data line bridging portion (184) are changed from semiconductors to conductors, while the active layer (183) remains a semiconductor. The second positive photoresist layer (19) is peeled off.

6. The method for fabricating an array substrate according to claim 5, characterized in that, The manufacturing method further includes: When the metal oxide semiconductor layer (18) is patterned, the metal oxide semiconductor layer (18) is also used to form pixel electrodes (185). When the second positive photoresist layer (19) is thinned by ashing and the second positive photoresist layer (19) corresponding to the source electrode (181), the drain electrode (182) and the data line bridge (184) is removed, the second positive photoresist layer (19) corresponding to the pixel electrode (185) is also removed at the same time. When the source electrode (181), the drain electrode (182), and the data line bridging portion (184) are made into conductors, and the pixel electrode (185) is made into a conductor, the pixel electrode (185) is also made into a conductor.

7. The method for fabricating an array substrate according to claim 6, characterized in that, The manufacturing method further includes: The first positive photoresist layer (14) is exposed from the top of the substrate (11) using a first halftone mask (15). When the first opaque area (151) corresponds to the conductor portion (1231) of the scan line (121), the gate (122), and the data line (123), the first opaque area (151) also corresponds to the peripheral trace. When developing the first positive photoresist layer (14), the first positive photoresist layer (14) is retained at the position corresponding to the peripheral trace. The first insulating layer (13) and the first metal layer (12) are patterned so that when the first metal layer (12) forms the scan line (121), the gate (122) and the data line (123), the peripheral trace is also formed. A full-surface third insulating layer (22) is formed on the source electrode (181), the drain electrode (182), the active layer (183), the pixel electrode (185), and the data line bridging portion (184). When the third insulating layer (22) is patterned, a first via is formed at the position corresponding to the peripheral trace. A full-surface first transparent conductive layer is formed on the third insulating layer (22). The first transparent conductive layer is patterned to form a common electrode (23), which is filled into the first through hole and contacts the peripheral trace.

8. The method for fabricating an array substrate according to claim 5, characterized in that, The manufacturing method further includes: The first insulating layer (13) and the first metal layer (12) are patterned so that when the first metal layer (12) forms the scan line (121), the gate (122) and the data line (123), peripheral traces are also formed. A full-surface third insulating layer (22) is formed on the source (181), the drain (182), the active layer (183), and the data line bridging portion (184). A full-surface planarization layer (24) is formed on the third insulating layer (22). A full-surface second transparent conductive layer is formed on the planarization layer (24). The second transparent conductive layer is patterned to form a common electrode (23). The common electrode (23) is conductively connected to the peripheral trace. A fourth insulating layer (25) is formed on the entire surface of the common electrode (23); A third transparent conductive layer is formed on the entire surface of the fourth insulating layer (25); The third transparent conductive layer is patterned to form a pixel electrode (185), and the pixel electrode (185) is electrically connected to the drain electrode (182).

9. The method for fabricating an array substrate according to claim 5, characterized in that, The conductor treatment includes hydrogenation or ion doping.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 4.

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