A dual-mode fundamental frequency synthesizer circuit

Abstract

The application provides a dual-mode fundamental frequency frequency synthesis circuit, which comprises a fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator, a dual-mode heterodyne frequency divider, a dynamic current mode quarter frequency divider, a 96 division frequency divider chain, a frequency discriminator and a programmable charge pump. The application provides a dual-mode fundamental frequency local oscillator signal by using the bidirectional asymmetric propagation standing wave, so as to reduce the volume of passive magnetic elements while ensuring the operation of dual-frequency isolation. In order to improve the locking accuracy of the frequency divider circuit to the dual-mode input frequency, the dual-mode heterodyne frequency divider is designed as follows: in the 94GHz working state, the input clock signal and the feedback clock signal are directly down-converted, and in the 140GHz working state, the double frequency of the input clock signal and the feedback clock signal is mixed. Therefore, when the frequency divider reaches a steady state, the output end will generate a fixed 47GHz frequency output signal in any working state, thereby further saving the circuit area and greatly simplifying the design of the subsequent high-frequency frequency divider.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of millimeter wave transceiver circuit, in particular to a dual-mode base frequency synthesizer circuit. BACKGROUND

[0002] The microwave communication frequency band is increasingly crowded, and the development of millimeter wave frequency band transceiver system has become the focus of the industry.

[0003] The frequency synthesizer module including multiple modes is generally provided in the millimeter wave frequency band transceiver system, which can realize frequency switching and non-interference operation. The frequency synthesizer is a key component in the radio frequency communication transceiver system, which is used to generate constant and high-precision frequency, and plays a decisive role in the receiving sensitivity, frequency accuracy and tuning range of the transceiver. The existing frequency synthesizer mainly includes phase-locked frequency synthesis and digital frequency synthesis. In the microwave or lower frequency band, the digital synthesis method has the advantages of high precision and easy to realize high integration compared with the other two methods. However, when the application frequency reaches the millimeter wave frequency band, the digital integrated circuit is difficult to meet the requirements of clock and switching speed, so the phase-locked frequency synthesis is widely studied in the millimeter wave wireless communication system.

[0004] The phase-locked frequency synthesizer circuit generally includes a local oscillator, a loop filter, a frequency discriminator and a phase discriminator, and a voltage-controlled oscillator at the output end, wherein the local oscillator and the voltage-controlled oscillator need to use high-quality magnetic elements for design, which limits the realization of small-area on-chip integration of the oscillator component. For the design of the multi-mode frequency synthesizer which needs more magnetic elements, how to limit the on-chip area of the magnetic elements is a more difficult problem.

[0005] In addition, the attenuation of the signal by the planar transmission line and the parasitic effect is also a major problem in the design of millimeter wave circuit. How to optimize the input locking range of the frequency divider and how to improve its output precision are also problems to be solved in the prior art. SUMMARY

[0006] The present application provides a dual-mode base frequency synthesizer circuit to solve the problems in the prior art. The present application realizes frequency tuning by generating a standing wave corresponding to the frequency in the metal transmission line through the cross-coupling of NMOS and PMOS, which can reduce the volume of passive magnetic elements while ensuring the dual-frequency isolation operation. The present application specifically adopts the following technical solutions.

[0007] First, to achieve the above object, a dual-mode fundamental local oscillator circuit is proposed, which includes a fundamental dual-mode bi-directional asymmetrically propagated standing-wave oscillator (Fundamental Dual-mode Bi-directional Asymmetrically Propagated Standing-Wave Oscillator, abbreviated as BAP-SWO), which includes a switching control signal receiving port, and further includes two groups of cross-coupled pairs respectively responding to different switching control signals, each cross-coupled pair respectively generates a frequency signal matched to the switching control signal corresponding to it, and the frequency signal is asymmetrically propagated to the alternating current ground node at both ends of the transmission line at the same time, forming a bi-directional standing wave in the transmission line, and providing a local oscillator signal output; a dual-mode heterodyne frequency divider is connected to the fundamental dual-mode bi-directional asymmetrically propagated standing-wave oscillator, receives the local oscillator signal generated by the fundamental dual-mode bi-directional asymmetrically propagated standing-wave oscillator, mixes the local oscillator signal with the internal local oscillator signal generated by the oscillator in the loop to obtain a mixed signal, and generates a corresponding direct current feedback signal through a frequency discriminator according to the mixed signal, and drives the oscillator in the loop to generate a quadrature feedback signal according to the direct current feedback signal, and uses the quadrature feedback signal as the internal local oscillator signal, so that the dual-mode heterodyne frequency divider finally outputs a corresponding frequency division signal; a dynamic current mode four-frequency divider is connected to the dual-mode heterodyne frequency divider, which is used to further reduce the clock frequency of the frequency division signal; a 96 frequency divider chain receives the clock frequency output by the dynamic current mode four-frequency divider, and a first stage of extended true single-phase clock 2 divider (E-TSPC) realizes the frequency division of 10GHz working frequency in the case of low power consumption, and the next stage of the extended true single-phase clock 2 divider is a 48 frequency divider using a true single-phase clock frequency division structure, and finally generates a 125MHz frequency division output; a frequency discriminator and phase discriminator receives two input signals, which are respectively the 125MHz frequency division output generated by the 96 frequency divider chain and the 125MHz high-precision reference clock signal generated and input by an external crystal oscillator, and outputs a double-channel pulse signal for driving the subsequent programmable charge pump to perform charging and discharging, and the width difference of the double-channel pulse signal is proportional to the frequency and phase difference of the two input signals; a programmable charge pump is integrated with a second-order loop filter on the charge pump sheet, and the charge pump converts the double-channel pulse signal output by the frequency discriminator and phase discriminator into a net charging or discharging current, and the second-order loop filter filters out the ripple of the net charging or discharging current while converting the net charging or discharging current into a control voltage to drive the fundamental dual-mode bi-directional asymmetrically propagated standing-wave oscillator loop to lock, and outputs the desired frequency.

[0008] Optionally, the dual-mode baseband frequency synthesizer circuit of any of the above, wherein the programmable charge pump triggers the charge pump to generate a net charging current into the second-order loop filter when the high-precision reference clock signal input to the phase-frequency detector leads in phase or is faster in frequency than the 125MHz frequency-divided output from the divide-by-96 divider chain, causing the output voltage of the second-order loop filter to rise and the frequency of the voltage-controlled oscillator to rise as well, to drive the 125MHz frequency-divided output from the divide-by-96 divider chain to chase the phase of the high-precision reference clock signal; and the programmable charge pump triggers the charge pump to generate a net discharging current into the second-order loop filter when the high-precision reference clock signal input to the phase-frequency detector lags in phase or is slower in frequency than the 125MHz frequency-divided output from the divide-by-96 divider chain, causing the output voltage of the second-order loop filter to fall and the frequency of the voltage-controlled oscillator to fall as well, to drive the 125MHz frequency-divided output from the divide-by-96 divider chain to chase the phase of the high-precision reference clock signal; and eventually when the loop locks, the high-precision reference clock signal and the frequency-divided output clock achieve frequency and phase lock, and the voltage-controlled oscillator outputs the desired frequency stably.

[0009] Optionally, the dual-mode baseband frequency synthesizer circuit of any of the above, wherein the dynamic current-mode quadrature divider receives a frequency-divided signal input via an AC-coupled differential drive of a PMOS current source and an NMOS current sink, and the PMOS current source and the NMOS current sink alternately charge and discharge the parasitic capacitance of their respective output nodes.

[0010] Optionally, the dual-mode baseband frequency synthesizer circuit of any of the above, wherein the baseband dual-mode dual-direction asymmetric traveling wave oscillator outputs a dual-mode reference frequency at the same port; and the dual-mode heterodyne frequency divider outputs only a single 48GHz frequency-divided signal.

[0011] Optionally, the dual-mode fundamental frequency synthesizing circuit according to any one of the preceding claims, wherein the fundamental dual-mode dual-direction asymmetrically propagating standing wave oscillator comprises a first set of cross-coupled pairs and a second set of cross-coupled pairs connected across a loop transmission line, the loop transmission line converges outside the two sets of cross-coupled pairs to form a first AC ground node and a second AC ground node, wherein the first set of cross-coupled pairs is 1 / 4 wavelength of the 96GHz microwave signal away from the first AC ground node, the second set of cross-coupled pairs is 1 / 4 wavelength of the 144GHz microwave signal away from the second AC ground node, and the two sets of cross-coupled pairs are switched on by the EN_96G switching control signal and the EN_144G switching control signal of the switching control signal receiving port, respectively, to realize dual-frequency operation: when the EN_96G switching control signal is effective, the PMOS and NMOS tail currents in the first set of cross-coupled pairs are turned on, the first set of cross-coupled pairs starts to form a wave trough of the standing wave at the AC ground nodes at both ends of the transmission line, forms a wave peak of the standing wave at the position of the first set of cross-coupled pairs, and forms a bidirectional standing wave in the transmission line to provide a 96GHz local oscillator signal output; when the EN_144G switching control signal is effective, the PMOS and NMOS tail currents in the second set of cross-coupled pairs are turned on, the second set of cross-coupled pairs starts to form a wave trough of the standing wave at the AC ground nodes at both ends of the transmission line, forms a wave peak of the standing wave at the position of the second set of cross-coupled pairs, and forms a bidirectional standing wave in the transmission line to provide a 144GHz local oscillator signal output.

[0012] Optionally, the dual-mode fundamental frequency synthesizing circuit according to any one of the preceding claims, wherein the dual-mode heterodyne frequency divider (DHFD) comprises: a dual-mode double-balanced mixer (DDM) arranged at a first stage, a frequency discriminator (FD) based on a mixer structure arranged at a second stage, a differential-to-single-ended amplifier for generating a frequency error signal, a second-order loop filter, a current-multiplexed in-phase injection-locked quadrature VCO (IPIC-QVCO) for generating a frequency division signal and simultaneously for driving the dual-mode double-balanced mixer and the frequency discriminator, and a buffer stage for driving a subsequent dynamic current-mode divider; the dual-mode double-balanced mixer at the first stage receives a 96GHz or 140GHz local oscillator signal from the fundamental dual-mode dual-direction asymmetrically propagating standing wave oscillator, mixes it with a quadrature signal from the current-multiplexed in-phase injection-locked quadrature VCO to generate an output signal close to 48GHz, and then mixes the output signal again with the signal from the current-multiplexed in-phase injection-locked quadrature VCO in the frequency discriminator to compare the frequencies, generate a direct-current error signal proportional to the frequency difference through the differential-to-single-ended amplifier and the loop filter, and further drive the frequency discriminator to achieve frequency locking.

[0013] Optionally, the dual-mode fundamental frequency synthesizing circuit as claimed in any of the above, wherein the dual-mode heterodyne frequency divider realizes 2 frequency division when the fundamental frequency dual-mode bidirectional non-symmetrical propagation standing wave oscillator provides 96GHz local oscillator signal output, thereby outputting 48GHz frequency division signal; and realizes 3 frequency division when the fundamental frequency dual-mode bidirectional non-symmetrical propagation standing wave oscillator provides 144GHz local oscillator signal output, thereby outputting 48GHz frequency division signal.

[0014] Optionally, the dual-mode fundamental frequency synthesizing circuit as claimed in any of the above, wherein the first stage dual-mode double-balanced mixer (DDM) of the dual-mode heterodyne frequency divider, when working in the fundamental frequency mode, the bottom differential common-source tubes Mt1 and Mt2 receive 96GHz local oscillator signal from the fundamental frequency dual-mode bidirectional non-symmetrical propagation standing wave oscillator, and the middle switch tube array receives 48GHz quadrature feedback signal from the current multiplexing in-phase injection-locked quadrature VCO, only the NMOS tube connected to EN1 in the switch tube array is in working state, and the remaining NMOS tubes connected to EN2 are turned off, at this time, EN1 provides direct current bias, so that the two groups of switch tubes, namely I+ and Q+, I- and Q-, periodically switch the 96GHz current generated by the lower common-source stage at a frequency of 48GHz, thereby realizing fundamental frequency mixing; when the first stage dual-mode double-balanced mixer works in the sub-harmonic mode, the bottom differential common-source tubes receive 144GHz local oscillator signal from the fundamental frequency dual-mode bidirectional non-symmetrical propagation standing wave oscillator, and the middle switch tube array still receives 48GHz quadrature feedback signal from the current multiplexing in-phase injection-locked quadrature VCO, at this time, only the NMOS tube connected to EN2 in the switch tube array is in working state, and the remaining NMOS tubes connected to EN1 are turned off, at this time, EN2 provides direct current bias, so that the two groups of switch tubes, namely I+ and I-, Q+ and Q-, are in class C working zone, the switch tubes periodically switch the 144GHz current generated by the lower common-source stage at an equivalent frequency of 96GHz, thereby realizing sub-harmonic mixing.

[0015] Optionally, the dual-mode fundamental frequency synthesizing circuit as claimed in any of the above, wherein the frequency discriminator of the second stage of the dual-mode heterodyne frequency divider uses a double-balanced mixer structure, the radio frequency end of which inputs 48GHz frequency division signal output provided by the dual-mode double-balanced mixer of the previous stage, and the local oscillator end of which inputs quadrature signal from the current multiplexing in-phase injection-locked quadrature VCO; the double-balanced mixer structure automatically filters out the up-conversion component and retains the down-conversion component; and the down-conversion component is proportional to the frequency difference of the input signal, and is used to drive the subsequent circuit.

[0016] Advantages

[0017] The application provides a 94 / 140GHz double-mode base frequency frequency synthesizing circuit, which belongs to the field of millimeter wave frequency synthesizing technology.

[0018] The double-mode double-direction asymmetric propagation standing wave oscillator circuit and the double-mode heterodyne divide-by-2 divide-by-3 frequency divider are used to generate a standing wave with a limited length to realize base frequency output and compensate errors by cooperating with a tuning module.

[0019] Compared with the traditional injection locking millimeter wave frequency divider, the double-mode heterodyne divide-by-2 divide-by-3 frequency divider has a larger input locking range, and the output signal clock in different working states is locked in the 47GHz frequency band, which can greatly simplify the design of the subsequent high-frequency frequency divider.

[0020] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application, and are used to explain the present application, and do not constitute a limitation on the present application. In the drawings:

[0022] Figure 1 is a design scheme block diagram of the 94 / 140GHz double-mode base frequency frequency synthesizing circuit provided by the present application;

[0023] Figure 2 is a schematic diagram of the base frequency double-mode double-direction asymmetric propagation standing wave oscillator circuit used in the present application;

[0024] Figure 3 is a schematic diagram of the double-mode heterodyne frequency divider circuit used in the present application;

[0025] Figure 4 for Figure 3 The schematic diagram of the dual-mode dual-balanced mixer circuit used in the dual-mode heterodyne frequency divider. Detailed Implementation

[0026] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0028] In this invention, "and / or" means either the existence of each individually or the existence of both simultaneously.

[0029] In this invention, "inner" and "outer" refer to the direction of the transmission line that forms the bidirectional standing wave pointing towards the internal cross-coupled circuit, relative to the dual-mode fundamental frequency local oscillator circuit itself; and the opposite direction is "outer". This does not mean a specific limitation on the device mechanism of this invention.

[0030] In this invention, the term "connection" can mean either a direct connection between components or an indirect connection between components through other components.

[0031] Figure 1 A dual-mode fundamental frequency synthesis circuit according to the present invention includes:

[0032] (1) such as Figure 2The fundamental dual-mode bidirectional asymmetrically propagated standing-wave oscillator (BAP-SWO) shown includes a switching control signal receiving port to achieve dual-frequency operation via switching control signals EN_94G and EN_140G. It also includes two sets of cross-coupled pairs, each responding to a different switching control signal. Each cross-coupled pair generates a frequency signal matched to its corresponding switching control signal. When the EN_94G signal is active, the corresponding PMOS and NMOS tail currents and the cross-coupled pairs are activated. Similarly, when EN_140G is active, the corresponding PMOS and NMOS tail currents and the cross-coupled pairs are also activated. The activated cross-coupled pairs generate signals with corresponding frequencies that propagate asymmetrically to the AC ground nodes at both ends of the transmission line, forming a bidirectional standing wave within the transmission line and providing the local oscillator signal output. In practical operation, at low frequencies, the standing wave propagates asymmetrically to both sides of the transmission line, propagating 1 / 4 wavelength to the right and 3 / 4 wavelength to the left. This bidirectional wave is totally reflected at the AC ground node, forming a trough, while forming a peak at the cross-coupling pair, thus forming a 94 GHz standing wave. Similarly, at high frequencies, the left and right waves propagate 1 / 4 and 5 / 4 wavelengths respectively, thus forming a 140 GHz standing wave. A 4-bit binary weighted capacitor array and an AC-coupled variable capacitor are used to achieve frequency tuning. The transmission line is implemented using a microstrip line structure, where the top metal layer serves as the signal line and the bottom metal layer serves as the ground line.

[0033] (2) such as Figure 3 The dual-mode heterodyne divider shown is connected to the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator BAP-SWO. It receives the local oscillator signal generated by the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator BAP-SWO, mixes the local oscillator signal with the internal local oscillator signal generated by the oscillator in its own loop, obtains a mixed signal, and generates a corresponding DC feedback signal based on the mixed signal through a frequency discriminator. The DC feedback signal drives the oscillator in its own loop to generate a quadrature feedback signal, which is used as the internal local oscillator signal, so that the dual-mode heterodyne divider finally outputs the corresponding divided frequency signal.

[0034] (3) A dynamic current-mode divider, which is connected to the dual-mode heterodyne frequency divider, is used to further reduce the clock frequency of the divided signal. The input of the dynamic current-mode divider is AC-coupled differentially to drive the PMOS current source and NMOS current sink alternately to charge and discharge the parasitic capacitance of the output node. The principle is similar to the commonly used D flip-flop-based 4 divider, but thanks to its smaller parasitic capacitance and dynamic characteristics, the divider can achieve high-speed frequency division with smaller power consumption;

[0035] (4) A divide-96 frequency divider chain, which receives the clock frequency output by the dynamic current-mode divider, is implemented by a first-stage extended true single-phase clock 2 divider (E-TSPC) to achieve frequency division of about 10 GHz at low power consumption, and the next stage of the extended true single-phase clock 2 divider is a 48 divider using a true single-phase clock frequency division structure, finally generating a 125 MHz divided output; the extended true single-phase clock 2 divider (E-TSPC) in the frequency divider chain can use a conventional design;

[0036] (5) A frequency discriminator and phase detector, which can be implemented by a conventional tri-state frequency discriminator and phase detector, receives two input signals, the 125 MHz divided output generated by the divide-96 frequency divider chain, and the 125 MHz high-precision reference clock signal input externally (usually generated by a commercial crystal oscillator), and outputs a double-path pulse signal for driving the subsequent programmable charge pump to perform charging and discharging, the width difference of the double-path pulse signal is proportional to the frequency and phase difference of the two input signals;

[0037] (6) A programmable charge pump, which is integrated with a second-order loop filter on the charge pump chip, converts the double-path pulse signal output by the frequency discriminator and phase detector into a net charging or discharging current, and the second-order loop filter filters out the ripple of the net charging or discharging current while converting it into a control voltage to drive the fundamental frequency dual-mode bidirectional asymmetric traveling wave oscillator loop to be locked, outputting the desired frequency.

[0038] Thus, the dual-mode fundamental frequency synthesizing circuit realized by the above circuit structure can generate a standing wave of a limited length by a fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator, a dual-mode heterodyne 2 / 3 divider, a dynamic current mode four divider (CML), a 96 divider chain, a frequency discriminator, and a programmable current pump (CP) integrated with an on-chip second-order loop filter (LPF), and realize the fundamental frequency output by the standing wave, compensate for errors by a tuning module, and realize dual-mode operation only by using a single on-chip inductor. The fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator provided in the application can output a dual-mode signal at a single port without using a multiplexer, thereby reducing signal attenuation. The dual-mode heterodyne 2 / 3 divider provided in the application has a larger input locking range compared with a conventional injection-locked millimeter wave divider. The output signal clock under different working conditions is set to a 47 GHz frequency band, which can further simplify the design of subsequent high-frequency dividers.

[0039] The circuit design ideas of the above-mentioned innovative fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator and dual-mode heterodyne 2 / 3 divider are described in detail below.

[0040] 1. The fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator circuit of the application: dual-frequency operation is completed by switching 94 GHz and 140 GHz frequency signals, and a digital current source determines the working state of the two signals. When the low-frequency and high-frequency working modes are turned on, respectively, NMOS and PMOS cross-coupled pairs are used to generate standing waves of corresponding frequencies in the metal transmission line. A 4-bit binary weight capacitor array and an AC-coupled varactor are used to realize frequency tuning.

[0041] The fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator circuit includes a first group of cross-coupled pairs and a second group of cross-coupled pairs connected in parallel across the ring transmission line. The ring transmission line is folded at both ends of the two groups of cross-coupled pairs to form a first AC ground node A and a second AC ground node B, and the first group of cross-coupled pairs is arranged at a position 1 / 4 wavelength away from the 96 GHz microwave signal of the first AC ground node A, and the second group of cross-coupled pairs is arranged at a position 1 / 4 wavelength away from the 144 GHz microwave signal of the second AC ground node B. The two groups of cross-coupled pairs are switched on by the EN_96G switching control signal and the EN_144G switching control signal of the switching control signal receiving port in response to the switching control signal, respectively, to realize dual-frequency operation.

[0042] When the EN_96G switching control signal is effective, the first group of cross-coupled pairs is switched on, and the second group of cross-coupled pairs is switched off. Figure 2The PMOS and NMOS tail currents in the first cross-coupled pair on the right side are turned on, which forms a standing wave with a trough at the AC ground nodes at both ends of the transmission line and a peak at the position of the first cross-coupled pair, and a bidirectional standing wave is formed in the transmission line, providing a 96 GHz local oscillator signal output;

[0043] When the EN_144G switching control signal is effective, the PMOS and NMOS tail currents in the second cross-coupled pair on the left side are turned on, which forms a standing wave with a trough at the AC ground nodes at both ends of the transmission line and a peak at the position of the second cross-coupled pair, and a bidirectional standing wave is formed in the transmission line, providing a 144 GHz local oscillator signal output. Figure 2

[0044] Therefore, whether the PMOS tail currents at both ends are turned on or not, the nodes A and B are high-impedance nodes for the differential signal, and thus a trough of the standing wave is formed at the nodes A and B. The maximum energy is formed at the position of the cross-coupled pair, and thus a peak of the standing wave is formed. The length of the transmission line and the position (node C) of the cross-coupled pair connected to the transmission line are properly selected, so that the transmission distance from the node C to the node A is 1 / 4 of the wavelength of the 96 GHz microwave signal, and the transmission distance from the node C to the node B is 3 / 4 of the wavelength of the 96 GHz microwave signal. When the bidirectional standing wave is generated, the circuit naturally oscillates at 96 GHz. Similarly, when the EN_144G is effective, the PMOS and NMOS tail currents on the left side are turned on, and the corresponding cross-coupled pair is started. The position (node D) of the 144 GHz cross-coupled pair connected to the transmission line is properly selected, so that the transmission distance from the node D to the node B is 1 / 4 of the wavelength of the 144 GHz microwave signal, and the transmission distance from the node D to the node A is 5 / 4 of the wavelength of the 144 GHz microwave signal. When the bidirectional standing wave is generated, the circuit naturally oscillates at 144 GHz. A 4-bit binary weight capacitor array has been used to realize frequency tuning. The transmission line can be realized by a microstrip line structure, in which the top layer metal is used as a signal line and the bottom layer metal is used as a ground line. In addition, for the design of a millimeter wave oscillator, a key difficulty is that a very small capacitance is required for realizing a fine frequency step, which is very difficult to realize. Thanks to the proposed circuit structure, the effective capacitance can be greatly reduced through the inductance of the transmission line, so that only a common capacitor is required to realize a very fine capacitance value. In addition, the output buffer is placed near the high-frequency cross-coupled pair, so that the output power will not be greatly attenuated. Figure 2

[0045] ​​And, since the above-mentioned base frequency dual-mode bidirectional asymmetric propagation standing wave oscillator outputs dual-mode reference frequency at the same port. In this way, frequency multiplexer for frequency selection can be omitted, thereby reducing power loss. Meanwhile, in order to receive the single-port dual-mode output of the oscillator.

[0046] 2, The dual-mode heterodyne frequency divider of the present application: through the dual-mode double-balanced mixer (LOPS-Mixer) of the selectable input local oscillator signal in the first stage, the frequency discriminator composed of the ordinary mixer and the wideband amplifier in the second stage, and the oscillator (QVCO) for generating the quadrature feedback signal, the input clock signal and the feedback clock signal are directly down-converted in the 94GHz working state, and the double frequency of the input clock signal and the feedback clock signal is down-converted in the 140GHz working state. In this way, when the frequency divider reaches a steady state, a fixed 47GHz frequency output signal will be generated at the output end.

[0047] The dual-mode heterodyne frequency divider can be realized by the following circuit components: a) a dual-mode double-balanced mixer (DDM) arranged in the first stage; b) a frequency discriminator (FD) based on a mixer structure arranged in the second stage; c) a differential-to-single-ended amplifier for generating a frequency error signal; d) a second-order loop filter for generating a frequency division signal; e) a current multiplexing in-phase injection locking quadrature VCO (IPIC-QVCO) for driving the dual-mode double-balanced mixer and the frequency discriminator; and f) a buffer stage for driving a subsequent dynamic current mode frequency divider. The working principle is as follows:

[0048] The dual-mode double-balanced mixer in the first stage receives the 96 or 140GHz local oscillator signal from the base frequency dual-mode bidirectional asymmetric propagation standing wave oscillator BAP-SWO, mixes it with the quadrature signal from the current multiplexing in-phase injection locking quadrature VCO (IPIC-QVCO) to generate an output signal close to 48GHz, and then compares the output signal with the signal from the current multiplexing in-phase injection locking quadrature VCO in the frequency discriminator. Through the differential-to-single-ended amplifier and the loop filter, a direct current error signal proportional to the frequency difference is generated, which further drives the frequency discriminator IPIC-QVCO. Similar to a class I phase-locked loop, finally, frequency locking is achieved, i.e. the IPIC-QVCO finally outputs a 48GHz frequency division signal. When the input signal of the entire loop is 96GHz, the output signal is 48GHz, thereby realizing 2 frequency division; and when the input signal of the entire loop is 144GHz, the output signal is also 48GHz, thereby realizing 3 frequency division.

[0049] The double-mode heterodyne frequency divider frequency provides 96GHz local oscillator signal output when the base frequency double-mode bidirectional asymmetric propagation standing wave oscillator provides 48GHz frequency division signal; the double-mode heterodyne frequency divider frequency provides 144GHz local oscillator signal output when the base frequency double-mode bidirectional asymmetric propagation standing wave oscillator provides 48GHz frequency division signal. This output single 48GHz frequency division signal design can greatly simplify the subsequent frequency divider chain design, while greatly widening the locking range, thereby solving the potential problem of the frequency synthesis circuit.

[0050] In a more specific implementation, the above-mentioned double-mode heterodyne frequency divider, the first stage of the double-mode double-balanced mixer (DDM) can be realized by Figure 4 Circuit. When it works in the base frequency mode, the bottom differential common source tube (Mt1 and Mt2) receives the 96GHz local oscillator signal from the base frequency double-mode bidirectional asymmetric propagation standing wave oscillator BAP-SWO, and the middle switch tube array receives the 48GHz quadrature feedback signal from the current multiplexing in-phase injection locking quadrature VCO (IPIC-QVCO). Only the NMOS tube connected to EN1 in the switch tube array is in working condition, and the remaining NMOS tubes connected to EN2 are turned off. At this time, EN1 as a direct current bias makes two groups of switch tubes (I+ and Q+, I- and Q-) periodically switch (switch tube waveform can be seen Figure 4 (b)) the 96GHz current generated by the lower common source stage at a frequency of 48GHz, thereby realizing the base frequency mixing;

[0051] When the first stage of the DDMDBM works in sub-harmonic mode, the bottom differential common-source receives the 144GHz LO signal from the fundamental BAP-SWO, while the middle switch array still receives the 48GHz quadrature feedback signal from the current-multiplexed in-phase injection-locked quadrature VCO (IPIC-QVCO). At this time, only the NMOS connected to EN2 in the switch array is in working state, while the rest of the NMOS connected to EN1 is turned off. At this time, EN2 provides a lower DC bias, so that the two groups of switch tubes (i.e. I+ and I-, Q+ and Q-) are in class-C working zone. The switch tubes periodically switch the 144GHz current generated by the lower common-source stage at a frequency equivalent to 96GHz, thereby realizing sub-harmonic mixing. Since the mixer is a double-balanced structure, its output inherently contains only the 48GHz signal component generated by the down-mixing, and filters out the high-frequency component generated by the up-mixing. The cross-coupled pair with adjustable tail current in parallel at the output can generate adjustable negative resistance, thereby improving the output voltage amplitude. Another advantage of the circuit is that a transmission line can be inserted between the Mt1 / Mt2 tube and the switch array to achieve the effect of inductive peaking, thereby improving the conversion efficiency of the mixing. On the layout, since the BAP-SWO and the DDM both have transmission lines or inductors, they will occupy a relatively large area, so the distance between the two modules must be far. If Mt1 / Mt2 is placed far from the BAP-SWO, a relatively long transmission line will inevitably be introduced at the gate of Mt1 / Mt2. This transmission line will become a load of the BAP-SWO, affecting its output voltage amplitude and tuning range, and other important performance. If the Mt1 / Mt2 tube is placed close to the BAP-SWO output, and the transmission line is used to connect between Mt1 / Mt2 and the switch array, not only does it solve the aforementioned BAP-SWO load effect, but it also takes advantage of the inductive peaking effect to improve the mixing efficiency of the DDM.

[0052] Specifically, in the 94GHz operating state, the LOPS-Mixer directly performs down-conversion operation on the input clock signal fL and the feedback clock signal fqvc, and generates a clock signal with a frequency of fL-fqvco. In the 140GHz operating state, the LOPS-Mixer operates in a subharmonic state, i.e., performs down-conversion operation on the input clock signal fL and the double frequency of the feedback clock signal fqvc, and generates a clock signal with a frequency of fL-2*fqvco. The generated clock signal then drives the next-stage down-converter and wideband amplifier, and further generates a direct-current feedback signal Vtune to control the quadrature oscillator. When the entire frequency divider loop reaches a steady state, the 94GHz clock signal generates a 47GHz signal at the final output end to achieve 2 frequency division, and the 140GHz clock signal also generates a 47GHz signal at the final output end to achieve 3 frequency division. Specifically, in the sub-circuit implementation, the second stage is a simple double-balanced mixer with a resistance load. The wideband amplifier is similar to the equalizer structure, and a capacitor Cz is connected to the source end of the input tube, so as to expand the bandwidth and increase the phase margin of the entire frequency divider loop by introducing a left half-plane zero point, thereby improving the loop stability. The QVCO utilizes current multiplexing technology to reduce power consumption, and also utilizes in-phase injection coupling technology (IPIC) to reduce phase noise. The next stage of the QVCO is an IQ clock buffer with gain improvement, which serves as an isolation function to reduce the influence of the heavy load of the subsequent circuit on the QVCO.

[0053] In other implementations, the description of the remaining sub-modules of the dual-mode heterodyne frequency divider DHFD is as follows:

[0054] The frequency discriminator of the second stage in the dual-mode heterodyne frequency divider DHFD uses a double-balanced mixer structure, the radio frequency end input of which comes from the 48GHz frequency division signal output provided by the dual-mode double-balanced mixer DDM of the previous stage, and the local oscillator end input comes from the quadrature signal of the current multiplexing in-phase injection locking quadrature VCO; the double-balanced mixer structure automatically filters out the up-conversion component and retains the down-conversion component; and the down-conversion component is proportional to the frequency difference of the input signal, and is used to drive the subsequent circuit.

[0055] The differential-to-single-ended wideband amplifier for generating frequency error signal in the dual-mode heterodyne frequency divider DHFD converts the differential input frequency error signal into a single-ended signal, and then drives the loop filter in the rear stage. The source stage of the differential input tube of the amplifier is connected with a capacitor Cz, which can introduce a left half plane zero point, so as to expand the bandwidth and stabilize the loop of the DHFD. (3) The second-order loop filter, which is similar to the loop filter in the frequency synthesizer loop, is used to filter out the ripple on the error signal, and generates a control signal Vtune to control the output frequency of the IPIC-QVCO. (4) The IPIC-QVCO is provided with a buffer stage of current multiplexing structure. As long as a large decoupling capacitor is connected at the center tap of the inductor of the IPIC-QVCO, the node can be approximately alternating current, so that the buffer stage can be directly stacked on the IPIC-QVCO to realize current multiplexing and save power consumption. The core oscillator part of the IPIC-QVCO adopts a classical IPIC coupling network to generate a quadrature output signal. The coupling network can make the injected current signal almost in phase with the intrinsic signal of the cross-coupled pair, thereby greatly reducing the phase noise of the IPIC-QVCO. (5) The buffer stage for driving the subsequent dynamic current mode 4 divider. The buffer stage works at 48GHz and adopts a common inductive peaking common source amplifier structure.

[0056] In a specific implementation, the programmable charge pump in the dual-mode fundamental frequency synthesizing circuit can be set as follows: when the phase of the high-precision reference clock signal input into the phase-frequency detector leads (or the frequency is faster than) the phase of the 125MHz frequency division output generated by the 96 divider chain, the charge pump is triggered to generate a net charging current to inject into the second-order loop filter, so that the output voltage of the second-order loop filter continuously increases, and the frequency of the voltage-controlled oscillator also continuously increases, so as to drive the phase of the 125MHz frequency division output generated by the 96 divider chain to catch up with the phase of the high-precision reference clock signal; similarly, when the phase of the high-precision reference clock signal input into the phase-frequency detector lags (or the frequency is slower than) the phase of the 125MHz frequency division output generated by the 96 divider chain, the charge pump is triggered to generate a net discharging current to inject into the second-order loop filter, so that the output voltage of the second-order loop filter continuously decreases, and the frequency of the voltage-controlled oscillator also continuously decreases, so as to drive the phase of the 125MHz frequency division output generated by the 96 divider chain to catch up with the phase of the high-precision reference clock signal; finally, when the loop is locked, the high-precision reference clock signal and the frequency division output clock are locked in frequency and phase, and the voltage-controlled oscillator stably outputs the expected frequency.

[0057] In a specific implementation, the dynamic current mode frequency divider in the dual-mode fundamental frequency synthesizing circuit can be designed to input the received frequency division signal to the AC coupled differential ground PMOS current source and NMOS current sink, and the parasitic capacitance of the respective output nodes is alternately charged and discharged by the PMOS current source and the NMOS current sink. Thus, the dynamic current mode frequency divider can achieve the alternating charging and discharging of the parasitic capacitance of the output nodes by a principle similar to the commonly used D flip-flop based 4 frequency divider. Benefiting from the smaller parasitic capacitance and dynamic characteristics, the frequency divider can achieve high-speed frequency division with smaller power consumption.

[0058] Thus, the application realizes frequency tuning by the NMOS and PMOS cross-coupling to the standing wave of the corresponding frequency generated in the metal transmission line, and can reduce the volume of the passive magnetic element while ensuring the dual-frequency isolation operation.

[0059] The above is only an embodiment of the application, which is described in detail, but it cannot be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which are all within the protection scope of the application.

Claims

1. A dual-mode fundamental frequency synthesis circuit, characterized in that, include: A fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator includes a switching control signal receiving port and two sets of cross-coupled pairs that respond to different switching control signals respectively. Each cross-coupled pair generates a frequency signal that matches its corresponding switching control signal. The frequency signals propagate asymmetrically to the AC ground nodes at both ends of the transmission line, forming a bidirectional standing wave in the transmission line and providing a local oscillator signal output. A dual-mode heterodyne frequency divider is connected to the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator. It receives the local oscillator signal generated by the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator, mixes the local oscillator signal with the internal local oscillator signal generated by the oscillator in its own loop to obtain a mixed signal, and generates a corresponding DC feedback signal based on the mixed signal through a frequency discriminator. The DC feedback signal drives the oscillator in its own loop to generate a quadrature feedback signal, and uses the quadrature feedback signal as the internal local oscillator signal, so that the dual-mode heterodyne frequency divider finally outputs the corresponding frequency division signal. A dynamic current-mode frequency divider, which is connected to the dual-mode heterodyne frequency divider, is used to further reduce the clock frequency of the divided signal. In addition to the 96 divider chain, the clock frequency output from the dynamic current mode divider-4 is divided by the first-stage extended true single-phase clock divider to achieve a 10GHz operating frequency with low power consumption. The next stage of the 2-divider is a 48-divider using a true single-phase clock divider structure, which ultimately produces a 125MHz divided output. The frequency and phase detector receives two input signals: a 125MHz frequency division output generated by the 96 divider chain and an external 125MHz high-precision reference clock signal. The frequency and phase detector outputs a dual-path pulse signal to drive the subsequent programmable charge pump to perform charging and discharging. The width difference between the two pulse signals is proportional to the frequency and phase difference of the two input signals. The programmable charge pump integrates a second-order loop filter on the charge pump chip. The charge pump converts the dual-path pulse signal output by the frequency and phase detector into net charging or discharging current. The second-order loop filter filters out the ripple of the net charging or discharging current and converts the net charging or discharging current into a control voltage to drive the loop lock of the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator and output the desired frequency.

2. The dual-mode fundamental frequency synthesis circuit as described in claim 1, characterized in that, When the phase of the high-precision reference clock signal input to the frequency and phase detector leads the 125MHz division output generated by the 96 divider chain, the programmable charge pump triggers the charge pump to generate a net charging current injected into the second-order loop filter. This causes the output voltage of the second-order loop filter to continuously increase, and the frequency of the voltage-controlled oscillator to continuously increase, thereby driving the phase of the 125MHz division output generated by the 96 divider chain to be adjusted to be close to the phase of the high-precision reference clock signal. Conversely, when the phase of the high-precision reference clock signal input to the frequency and phase detector lags behind the 125MHz division output generated by the 96 divider chain, the charge pump triggers the charge pump to generate a net discharging current injected into the second-order loop filter. This causes the output voltage of the second-order loop filter to continuously decrease, and the frequency of the voltage-controlled oscillator to continuously decrease, thereby driving the phase of the 125MHz division output generated by the 96 divider chain to be adjusted to be close to the phase of the high-precision reference clock signal. Finally, when the loop is locked, the high-precision reference clock signal and the frequency-divided output clock achieve frequency and phase locking, and the voltage-controlled oscillator stably outputs the desired frequency.

3. The dual-mode fundamental frequency synthesis circuit as described in claim 1, characterized in that, The dynamic current-mode divider receives a frequency division signal input that differentially drives a PMOS current source and an NMOS current drain via AC coupling. The PMOS current source and NMOS current drain alternately charge and discharge the parasitic capacitance of their respective output nodes.

4. The dual-mode fundamental frequency synthesis circuit as described in claim 1, characterized in that, The fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator outputs a dual-mode reference frequency at the same port; The dual-mode heterodyne frequency divider outputs a single-frequency divided signal.

5. The dual-mode fundamental frequency synthesis circuit as described in claim 4, characterized in that, The fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator includes a first set of cross-coupled pairs and a second set of cross-coupled pairs connected across a ring transmission line. The ring transmission line converges outside the two sets of cross-coupled pairs to form a first AC ground node and a second AC ground node. The first set of cross-coupled pairs is 1 / 4 wavelength away from the first AC ground node (96 GHz microwave signal), and the second set of cross-coupled pairs is 1 / 4 wavelength away from the second AC ground node (144 GHz microwave signal). The two sets of cross-coupled pairs switch on / off states in response to the EN_96G and EN_144G switching control signals at the switching control signal receiving port, respectively, to achieve dual-frequency operation: when the EN_96G switching control signal is valid, the PMOS and NMOS tail currents in the first set of cross-coupled pairs are turned on. After the first set of cross-coupled pairs is activated, a trough of the standing wave is formed at the AC ground node at both ends of the transmission line, and a peak of the standing wave is formed at the position of the first set of cross-coupled pairs, forming a bidirectional standing wave within the transmission line to provide a 96 GHz local oscillator signal output. When the EN_144G switching control signal is valid, the tail currents of the PMOS and NMOS in the second cross-coupled pair are turned on. After the second cross-coupled pair is started, a trough of the standing wave is formed at the AC ground node at both ends of the transmission line, and a peak of the standing wave is formed at the position of the second cross-coupled pair. A bidirectional standing wave is formed in the transmission line, providing a 144GHz local oscillator signal output.

6. The dual-mode fundamental frequency synthesis circuit as described in claim 5, characterized in that, The dual-mode heterodyne frequency divider includes: The first stage consists of a dual-mode dual-balanced mixer, the second stage consists of a frequency discriminator based on the mixer structure, a differential-to-single-ended amplifier for generating frequency error signals, a second-order loop filter, a current-multiplexed in-phase injection locked quadrature VCO for generating frequency division signals and simultaneously driving the dual-mode dual-balanced mixer and the frequency discriminator, and a buffer stage for driving the subsequent dynamic current-mode divider. The first-stage dual-mode dual-balanced mixer receives a 96GHz local oscillator signal from a baseband dual-mode bidirectional asymmetric propagating standing wave oscillator and mixes it with an orthogonal signal from a current-multiplexed in-phase injection locked quadrature VCO to generate an output signal close to 48GHz. This output signal is then compared with the signal from the current-multiplexed in-phase injection locked quadrature VCO in a frequency discriminator. Through a differential-to-single-ended amplifier and a loop filter, a DC error signal proportional to the frequency difference is generated, which further drives the frequency discriminator to achieve frequency locking.

7. The dual-mode fundamental frequency synthesis circuit as described in claim 6, characterized in that, The dual-mode heterodyne frequency divider divides the frequency by 2 when the baseband dual-mode bidirectional asymmetric propagation standing wave oscillator provides a 96GHz local oscillator signal output, thereby outputting a 48GHz frequency-divided signal; the dual-mode heterodyne frequency divider divides the frequency by 3 when the baseband dual-mode bidirectional asymmetric propagation standing wave oscillator provides a 144GHz local oscillator signal output, thereby outputting a 48GHz frequency-divided signal.

8. The dual-mode fundamental frequency synthesis circuit as described in claim 6, characterized in that, In the dual-mode heterodyne frequency divider, when the first-stage dual-mode dual-balanced mixer operates in baseband mode, the bottom differential common-source transistor receives the 96GHz local oscillator signal from the baseband dual-mode bidirectional asymmetric propagation standing wave oscillator, while the middle switch array receives the 48GHz quadrature feedback signal from the current-multiplexed in-phase injection locked quadrature VCO. Only the NMOS transistor connected to EN1 in the switch array is in the working state, while the other NMOS transistors connected to EN2 are turned off. At this time, EN1 acts as a DC bias, causing the two sets of switches to periodically switch the 96GHz current generated by the lower common-source stage at a frequency of 48GHz, thereby realizing baseband mixing. When the first-stage dual-mode dual-balanced mixer operates in subharmonic mode, the bottom differential common-source transistor receives the 144GHz local oscillator signal from the fundamental frequency dual-mode bidirectional asymmetric propagation standing wave oscillator, while the middle switch array still receives the 48GHz quadrature feedback signal from the current-multiplexed in-phase injection locked quadrature VCO. At this time, only the NMOS transistor connected to EN2 in the switch array will be in the working state, while the other NMOS transistors connected to EN1 will be turned off. At this time, EN2 provides DC bias, so that the two sets of switches are in the Class C operating region. The switches periodically switch the 144GHz current generated by the lower common-source stage at a frequency equivalent to 96GHz, thereby realizing subharmonic mixing.

9. The dual-mode fundamental frequency synthesis circuit as described in claim 6, characterized in that, In the dual-mode heterodyne frequency divider, the second-stage frequency discriminator uses a dual-balanced mixer structure. Its RF input comes from the 48GHz frequency division signal output provided by the dual-mode dual-balanced mixer in the previous stage, while its local oscillator input comes from the quadrature signal of the current-multiplexed in-phase injection locked quadrature VCO. The dual-balanced mixer structure automatically filters out the up-conversion component and retains the down-conversion component. Furthermore, the down-conversion component is proportional to the frequency difference of the input signal and is used to drive the subsequent circuit.

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