Delay locked loop and phase locking method thereof

Abstract

A delay locked loop and a phase locking method thereof are provided. The delay locked loop includes a first frequency divider, a delay string, a frequency multiplier, a second frequency divider, a phase detection and control circuit, and a setting signal generator. The first frequency divider generates a frequency-divided reference frequency signal. The second frequency divider divides the output frequency signal to generate complementary first and second feedback frequency signals, and selects the first feedback frequency signal or the second feedback frequency signal according to the setting signal to generate a selected feedback frequency signal. The phase detection and control circuit compares the phases of the selected feedback frequency signal and the frequency-divided reference frequency signal to generate a delay control signal. The setting signal generator samples the first feedback frequency signal with respect to the frequency-divided reference frequency signal to generate a setting signal.

Description

Technical Field

[0001] The present invention relates to a delay locked loop and a phase locking method thereof, and more particularly to a delay locked loop and a phase locking method thereof applied to a memory chip. Background Art

[0002] With the evolution of the times, the operating frequency of future dynamic random access memories will continue to increase. Therefore, a large number of circuits may adopt a frequency reduction method for control to improve the performance and yield of the chip. For the delay locked loop (DLL) in the dynamic random access memory, adopting frequency reduction control also helps to improve its performance. However, due to the limitation of the locking mechanism of the delay locked loop, the delay line therein needs to provide extra delay, so the current consumption and the locking time increase accordingly, reducing the operating efficiency of the dynamic random access memory. Summary of the Invention

[0003] The present invention is directed to a delay locked loop and a phase locking method thereof, which can reduce the number of delay components required by the delay line and reduce power consumption.

[0004] According to an embodiment of the present invention, the delay locked loop includes a first frequency divider, a delay line, a frequency multiplier, a second frequency divider, a phase detection and control circuit, and a setting signal generator. The first frequency divider divides the reference frequency signal to generate a divided reference frequency signal. The delay line receives the divided reference frequency signal and a delay control signal, and delays the divided reference frequency signal according to the delay control signal to generate a first output frequency signal. The frequency multiplier multiplies the first output frequency signal to generate a second output frequency signal. The second frequency divider divides the second output frequency signal to generate a complementary first feedback frequency signal and a second feedback frequency signal, and the second frequency divider selects one of the first feedback frequency signal and the second feedback frequency signal according to a setting signal to generate a selected feedback frequency signal. The phase detection and control circuit compares the phases of the selected feedback frequency signal and the divided reference frequency signal to generate a delay control signal. The setting signal generator samples the divided reference frequency signal with the first feedback frequency signal to generate a sampling result, and generates a setting signal according to the sampling result.

[0005] According to an embodiment of the present invention, a phase locking method includes: dividing a reference frequency signal to generate a divided reference frequency signal; delaying the divided reference frequency signal according to a delay control signal to generate a first output frequency signal; multiplying the first output frequency signal to generate a second output frequency signal; dividing the second output frequency signal to generate a complementary first feedback frequency signal and a second feedback frequency signal, and a second divider selects one of the first feedback frequency signal and the second feedback frequency signal according to a setting signal to generate a selected feedback frequency signal; comparing the phase of the selected feedback frequency signal and the divided reference frequency signal to generate a delay control signal; and sampling the divided reference frequency signal with the first feedback frequency signal to generate a sampling result, and generating a setting signal according to the sampling result.

[0006] Based on the above, the present invention samples the divided reference frequency signal with the selected feedback frequency signal of the phase-locked loop, and selects, according to the sampling result, the one with a phase closer to the divided reference frequency signal from the complementary first feedback frequency signal and the second feedback frequency signal to perform a phase locking operation with the divided reference frequency signal. In this way, the amount of delay provided by the delay string in the delay-locked loop can be reduced, effectively reducing the required power consumption. Moreover, the phase locking speed can be increased, improving the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0008] Figure 1 Showing a schematic diagram of a delay-locked loop according to an embodiment of the present invention;

[0009] Figure 2 Showing a schematic diagram of an implementation manner of a setting signal generator according to an embodiment of the present invention;

[0010] Figure 3A And Figure 3B Showing an operation waveform diagram of the setting signal generator;

[0011] Figure 4 Showing a schematic diagram of a locking operation of a delay-locked loop according to an embodiment of the present invention;

[0012] Figures 5A to 5C Showing waveform diagrams of locking operations of delay-locked loops according to different implementation manners of the present invention respectively;

[0013] Figure 6 Showing a schematic diagram of a delay-locked loop according to another embodiment of the present invention;

[0014] Figure 7A flowchart of a phase locking method according to an embodiment of the present invention is shown.

[0015] Explanation of the reference numerals in the attached drawings

[0016] 100, 600: Delay locked loop;

[0017] 110, 140, 610, 640: Frequency divider;

[0018] 120, 620: Delay string;

[0019] 130, 630: Frequency multiplier;

[0020] 150, 650: Phase detection and control circuit;

[0021] 151, 651: Phase detector;

[0022] 152, 652: Control circuit;

[0023] 160, 200, 660: Setting signal generator;

[0024] 670: Frequency signal receiver;

[0025] 680: Load simulation circuit;

[0026] AN1: AND gate;

[0027] CLK: Frequency terminal;

[0028] CLK_dllA, CLK_dll: Output frequency signal;

[0029] CLK_fb: Output frequency signal;

[0030] CLK_fb_div: First feedback frequency signal;

[0031] CLK_fb_div_n: Second feedback frequency signal;

[0032] CLK_ref: Reference frequency signal;

[0033] CLK_ref_div: Divided reference frequency signal;

[0034] D: Data terminal;

[0035] CLK_ref_div1: Reference signal;

[0036] DLC: Delay control signal;

[0037] DLL_reset: Delay locked loop reset signal;

[0038] FF1: Flip-flop

[0039] Q: Output terminal;

[0040] RESET: Reset signal;

[0041] RST_n: Reset terminal;

[0042] S410 - S470: Locking action steps;

[0043] S710 - S760: Phase - locking steps;

[0044] SET: Setting signal;

[0045] SEL_CLK_fb: Selected feedback frequency signal;

[0046] T1 - T3: Time points;

[0047] UP, DN: Detection results;

[0048] VCLK: Input frequency signal. Detailed implementation manners

[0049] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0050] Please refer to Figure 1 , Figure 1 which shows a schematic diagram of a delay - locked loop according to an embodiment of the present invention. The delay - locked loop 100 includes frequency dividers 110, 140, a delay string 120, a frequency multiplier 130, a phase detection and control circuit 150, and a setting signal generator 160. The frequency divider 110 receives a reference frequency signal CLK_ref and divides the reference frequency signal CLK_ref to generate a divided reference frequency signal CLK_ref_div. The delay string 120 is coupled to the frequency divider 110 and receives the divided reference frequency signal CLK_ref_div. The delay string 120 provides a delay value according to a delay control signal DLC to delay the divided reference frequency signal CLK_ref_div to generate an output frequency signal CLK_dllA. The frequency multiplier 130 is coupled to the delay string 120, receives and multiplies the first output frequency signal CLK_dllA, and generates another output frequency signal CLK_dll. The frequency of the output frequency signal CLK_dll can be any real - number multiple of the first output frequency signal CLK_dllA.

[0051] In addition, in this embodiment, the frequency divider 140 can receive an output frequency signal CLK_fb that is the same as the second output frequency signal CLK_dll, and perform frequency division on the output frequency signal CLK_fb to generate a selected feedback frequency signal SEL_CLK_fb. In detail, the frequency divider 140 performs frequency division on the output frequency signal CLK_fb to generate a first feedback frequency signal CLK_fb_div and a second feedback frequency signal CLK_fb_div_n that is complementary in phase to the first feedback frequency signal CLK_fb_div. Among them, the frequency divider 140 can perform frequency division on the output frequency signal CLK_fb to generate the first feedback frequency signal CLK_fb_div, and generate the second feedback frequency signal CLK_fb_div_n by inverting the first feedback frequency signal CLK_fb_div. Moreover, the frequency divider 140 can select one of the first feedback frequency signal CLK_fb_div and the second feedback frequency signal CLK_fb_div_n according to the setting signal SET to generate the selected feedback frequency signal SEL_CLK_fb.

[0052] The setting signal generator 160 receives the first feedback frequency signal CLK_fb_div, the frequency division reference frequency signal CLK_ref_div, and the delay locked loop reset signal DLL_reset. The setting signal generator 160 samples the first feedback frequency signal CLK_fb_div with respect to the frequency division reference frequency signal CLK_ref_div to generate a sampling result, and generates a setting signal SET according to the generated sampling result. The setting signal SET is transmitted to the frequency divider 140.

[0053] On the other hand, the phase detection and control circuit 150 is coupled to the frequency dividers 110 and 140. The phase detection and control circuit 150 includes a phase detector 151 and a control circuit 152. The phase detector 151 receives the selected feedback frequency signal SEL_CLK_fb and the frequency division reference frequency signal CLK_ref_div. The phase detector 151 performs a detection operation on the phase difference between the selected feedback frequency signal SEL_CLK_fb and the frequency division reference frequency signal CLK_ref_div to generate detection results UP, DN. The control circuit 152 is coupled to the phase detector 151, and generates a delay control signal DLC according to the detection results UP, DN that indicate whether the phase of the selected feedback frequency signal SEL_CLK_fb is ahead of or behind the phase of the frequency division reference frequency signal CLK_ref_div.

[0054] In this embodiment, when the selected feedback frequency signal SEL_CLK_fb is the first feedback frequency signal CLK_fb_div, the phase detector 151 performs a phase alignment operation on the divided reference frequency signal CLK_ref_div and the first feedback frequency signal CLK_fb_div. When the selected feedback frequency signal SEL_CLK_fb is the second feedback frequency signal CLK_fb_div_n, the phase detector 151 performs a phase alignment operation on the divided reference frequency signal CLK_ref_div and the second feedback frequency signal CLK_fb_div_n.

[0055] Specifically, the signal generator 160 determines whether the rising edge (or falling edge) of the divided reference frequency signal CLK_ref_div is closer to the rising edge (or falling edge) of the first feedback frequency signal CLK_fb_div or the rising edge (or falling edge) of the second feedback frequency signal CLK_fb_div_n by sampling the divided reference frequency signal CLK_ref_div with the first feedback frequency signal CLK_fb_div, and generates a setting signal SET accordingly. Through the setting signal SET, the divider 140 can select and output the selected feedback frequency signal SEL_CLK_fb whose rising edge (or falling edge) is closer to the rising edge (or falling edge) of the divided reference frequency signal CLK_ref_div, and the phase detector 151 performs a phase difference detection operation with the divided reference frequency signal CLK_ref_div. In this way, the delay string 120 does not need to provide an excessive delay value, which can reduce current consumption and improve the locking speed.

[0056] Please refer to Figure 2 , Figure 2 FIG. shows a schematic diagram of an embodiment of the signal generator according to the embodiment of the present invention. The signal generator 200 includes a flip-flop FF1 and an AND gate AN1. The AND gate AN1 receives the divided reference frequency signal CLK_ref_div and the delay locked loop reset signal DLL_reset. When the delay locked loop reset signal DLL_reset is at a high logic level, the AND gate AN1 generates a reference signal CLK_ref_div1 equal to the divided reference frequency signal CLK_ref_div to the data terminal D of the flip-flop FF1. In contrast, when the delay locked loop reset signal DLL_reset is at a low logic level, the divided reference frequency signal CLK_ref_div is masked and not provided to the data terminal D of the flip-flop FF1. In addition, the clock terminal CLK of the flip-flop FF1 receives the first feedback frequency signal CLK_fb_div, and samples the reference signal CLK_ref_div1 according to the rising edge of the first feedback frequency signal CLK_fb_div.

[0057] The setting signal generator 200 generates a setting signal SET based on the sampling result obtained from the output terminal Q of the flip-flop FF1. When the rising edge of the first feedback frequency signal CLK_fb_div samples the high logic level of the divided reference frequency signal CLK_ref_div, the setting signal generator 200 can generate a setting signal SET with a high logic level. In contrast, when the rising edge of the first feedback frequency signal CLK_fb_div samples the low logic level of the divided reference frequency signal CLK_ref_div, the setting signal generator 200 can generate a setting signal SET with a low logic level.

[0058] Incidentally, the flip-flop FF1 is a D-type flip-flop. The flip-flop FF1 also has a reset terminal RST_n to receive a reset signal RESET. The flip-flop FF1 can reset the setting signal SET to a low logic level according to the reset signal RESET with a low logic level.

[0059] Please refer here Figure 2 、 Figure 3A and Figure 3B , where Figure 3A and Figure 3B show the operation waveform diagram of the setting signal generator. In Figure 3A , when the delay locked loop reset signal DLL_reset is at a high logic level, the reference signal CLK_ref_div1 has a positive pulse same as the divided reference frequency signal CLK_ref_div. And by sampling the reference signal CLK_ref_div1 at the rising edge of the divided reference frequency signal CLK_ref_div, a setting signal SET with a high logic level can be generated.

[0060] In Figure 3B , similarly when the delay locked loop reset signal DLL_reset is at a high logic level, the reference signal CLK_ref_div1 has a positive pulse same as the divided reference frequency signal CLK_ref_div. And by sampling the reference signal CLK_ref_div1 at the rising edge of the divided reference frequency signal CLK_ref_div, a setting signal SET with a low logic level can be generated.

[0061] Please refer to Figure 4 , Figure 4A schematic diagram showing the locking operation of a delay-locked loop according to an embodiment of the present invention. In step S410, power-on is performed; in step S420, a reset operation is performed on the delay-locked loop. Then, the first feedback frequency signal is sampled according to the divided reference frequency signal, and in step S430, it is determined whether the high logic level of the first feedback frequency signal is latched by the rising edge of the divided reference frequency signal. When the determination result is yes, step S440 is executed; on the contrary, when the determination result is no, step S45 is executed.

[0062] In step S440, the second feedback frequency signal can be set to perform an alignment operation of the transition edge with the divided reference frequency signal, and in step S460, the locking operation of the delay-locked loop (DLL) is started. Step S450 then sets the first feedback frequency signal to perform an alignment operation of the transition edge with the divided reference frequency signal, and then starts the DLL locking operation in step S460. Finally, the DLL locking operation is completed in step S470.

[0063] Please refer to the following Figures 5A to 5C , Figures 5A to 5C which respectively show waveform diagrams of the locking operations of delay-locked loops according to different embodiments of the present invention. In Figure 5A , there is a phase difference between the reference frequency signal CLK_ref and the output frequency signal CLK_fb. Dividing the output frequency signal CLK_fb can generate the first feedback frequency signal CLK_fb_div and the second feedback frequency signal CLK_fb_div_n. Dividing the reference frequency signal CLK_ref can obtain the divided reference frequency signal CLK_ref_div. At time point T1, sampling the divided reference frequency signal CLK_ref_div through the rising edge of the first feedback frequency signal CLK_fb_div can latch the divided reference frequency signal CLK_ref_div with a high logic level. Therefore, the second feedback frequency signal CLK_fb_div_n can be selected to perform a locking operation of phase alignment with the divided reference frequency signal CLK_ref_div.

[0064] In Figure 5BIn this case, at time point T2, the rising edge of the first feedback frequency signal CLK_fb_div exactly corresponds to the transition point of the divided reference frequency signal CLK_ref_div. Therefore, by sampling the divided reference frequency signal CLK_ref_div at the rising edge of the first feedback frequency signal CLK_fb_div, it is possible to latch the divided reference frequency signal CLK_ref_div that is at a high logic level or the divided reference frequency signal CLK_ref_div that is at a low logic level. Therefore, the first feedback frequency signal CLK_fb_div or the second feedback frequency signal CLK_fb_div_n can be selected to perform a locking operation for phase alignment with the divided reference frequency signal CLK_ref_div.

[0065] In Figure 5C In this case, at time point T3, by sampling the divided reference frequency signal CLK_ref_div at the rising edge of the first feedback frequency signal CLK_fb_div, it is possible to latch the divided reference frequency signal CLK_ref_div that is at a low logic level. Therefore, the first feedback frequency signal CLK_fb_div can be selected to perform a locking operation for phase alignment with the divided reference frequency signal CLK_ref_div.

[0066] Please refer to Figure 6 , Figure 6 FIG. shows a schematic diagram of a delay locked loop according to another embodiment of the present invention. The delay locked loop 600 includes dividers 610, 640, a delay string 620, a multiplier 630, a phase detection and control circuit 650, a setting signal generator 660, a frequency signal receiver 670, and a load simulation circuit 680. The phase detection and control circuit 650 includes a phase detector 651 and a control circuit 652. Different from Figure 1 the embodiment, the delay locked loop 600 of this embodiment receives an input frequency signal VCLK through the frequency signal receiver 670 and outputs a reference frequency signal CLK_ref. In addition, the output terminal of the delay locked loop 600 of this embodiment is coupled to the load simulation circuit 680, and the output frequency signal CLK_dll passes through the load simulation circuit 680 to generate an output frequency signal CLK_fb. Here, the load simulation circuit 680 is used to simulate the load connected to the delay locked loop 600 in actual use, and the output frequency signal CLK_fb can reflect the phase state of the frequency signal in actual use, improving the accuracy of the delay locked loop 600.

[0067] Incidentally, in this embodiment, the division factors provided by the dividers 610, 640 can be the same, and the multiplication factor provided by the multiplier 630 can be the same as the division factors provided by the dividers 610, 640.

[0068] More notably, in the embodiments of the present invention, by applying the frequency dividers 610 and 640, it is possible to eliminate the phenomenon that the rising edge and the falling edge of the reference frequency signal CLK_ref cannot be simultaneously aligned with the output frequency signal CLK_fb respectively when the duty cycle of the reference frequency signal CLK_ref is not 50-50.

[0069] Regarding the hardware architecture, the frequency dividers 610 and 640, the delay string 620, the frequency multiplier 630, the phase detection and control circuit 650, the frequency signal receiver 670, and the load simulation circuit 680 in the embodiments of the present invention can all be implemented using any circuit architecture well-known to those skilled in the field of delay-locked loops, without fixed limitations.

[0070] Next, please refer to Figure 7 , Figure 7 FIG. shows a flowchart of a phase locking method according to an embodiment of the present invention. Among them, in step S710, the reference frequency signal is divided in frequency to generate a divided reference frequency signal; in step S720, the divided reference frequency signal is delayed according to a delay control signal to generate a first output frequency signal; in step S730, the first output frequency signal is multiplied in frequency to generate a second output frequency signal; in step S740, the second output frequency signal is divided in frequency to generate a complementary first feedback frequency signal and a second feedback frequency signal, and one of the first feedback frequency signal and the second feedback frequency signal is selected according to a setting signal to generate a selected feedback frequency signal; in step S750, the phase of the selected feedback frequency signal and the divided reference frequency signal is compared to generate a delay control signal; and in step S760, the first feedback frequency signal samples the divided reference frequency signal to generate a sampling result, and a setting signal is generated according to the sampling result.

[0071] Regarding the implementation details of the above steps, detailed descriptions have been given in the foregoing multiple embodiments and implementation manners, and thus will not be elaborated herein.

[0072] In summary, the present invention samples the divided reference frequency signal with the first feedback frequency signal to generate a sampling result, and selects one of the complementary first feedback frequency signal and the second feedback frequency signal according to the sampling result to perform a phase locking operation with the divided reference frequency signal. It can effectively reduce the delay value provided by the delay string, reduce current consumption and accelerate the locking speed.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A delay locked loop, characterized in that, comprising: a first frequency divider for dividing the reference frequency signal to generate a divided reference frequency signal; a delay string for receiving the divided reference frequency signal and a delay control signal, and delaying the divided reference frequency signal according to the delay control signal to generate a first output frequency signal; a multiplier for multiplying the first output frequency signal to generate a second output frequency signal; a second frequency divider for dividing the second output frequency signal to generate a complementary first feedback frequency signal and a second feedback frequency signal, and the second frequency divider selects one of the first feedback frequency signal and the second feedback frequency signal according to a setting signal to generate a selected feedback frequency signal; a phase detection and control circuit for comparing the phases of the selected feedback frequency signal and the divided reference frequency signal to generate the delay control signal; and a setting signal generator for sampling the divided reference frequency signal according to the transition edge of the first feedback frequency signal to generate a sampling result, and generating the setting signal according to the sampling result.

2. The delay locked loop according to claim 1, characterized in that, when the transition edge is a rising edge and the sampling result is a high logic level, the setting signal generator generates the setting signal of a first logic level, and the second frequency divider selects the second feedback frequency signal according to the setting signal to generate the selected feedback frequency signal.

3. The delay locked loop according to claim 2, characterized in that, when the transition edge is a rising edge and the sampling result is a low logic level, the setting signal generator generates the setting signal of a second logic level, and the second frequency divider selects the first feedback frequency signal according to the setting signal to generate the selected feedback frequency signal.

4. The delay locked loop according to claim 1, characterized in that, the setting signal generator is a flip-flop, the frequency terminal of the flip-flop receives the first feedback frequency signal, the data terminal of the flip-flop receives the divided reference frequency signal, and the output terminal of the flip-flop generates the sampling result.

5. The delay locked loop according to claim 1, characterized in that, further comprising: a load simulation circuit coupled between the output terminal of the delay locked loop and the second frequency divider.

6. The delay locked loop according to claim 1, characterized in that, the setting signal generator further receives a delay locked loop reset signal, and determines whether to perform a sampling operation according to the delay locked loop reset signal.

7. The delay locked loop according to claim 1, characterized in that, the first frequency divider and the second frequency divider provide the same division number, and the division number is the same as the multiplication number provided by the multiplier.

8. The delay locked loop according to claim 1, characterized in that, further comprising: a frequency signal receiver for receiving an input frequency signal and generating the reference frequency signal according to the input frequency signal.

9. A phase locking method, characterized in that, comprising: Dividing a reference frequency signal to generate a divided reference frequency signal; Delaying the divided reference frequency signal according to a delay control signal to generate a first output frequency signal; Multiplying the first output frequency signal to generate a second output frequency signal; Dividing the second output frequency signal to generate a complementary first feedback frequency signal and a second feedback frequency signal, and selecting one of the first feedback frequency signal and the second feedback frequency signal according to a setting signal to generate a selected feedback frequency signal; Comparing the phases of the selected feedback frequency signal and the divided reference frequency signal to generate the delay control signal; and Sampling the divided reference frequency signal according to the transition edge of the first feedback frequency signal to generate a sampling result, and generating the setting signal according to the sampling result.

10. The phase locking method according to claim 9, wherein, when the transition edge is a rising edge and the sampling result is a high logic level, selecting the second feedback frequency signal according to the setting signal to generate the selected feedback frequency signal.

11. The phase locking method according to claim 10, wherein, when the transition edge is a rising edge and the sampling result is a low logic level, selecting the first feedback frequency signal according to the setting signal to generate the selected feedback frequency signal.

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