Three-dimensional NAND memory device and method for forming the same

Abstract

In a method for manufacturing a semiconductor device, a stack of alternating insulating and sacrificial layers is formed over a substrate. A staircase having a plurality of steps is formed in the stack, wherein each of the plurality of steps has a tread and a riser, and further comprising a corresponding pair of insulating and sacrificial layers for the corresponding steps, the sacrificial layers being located above the insulating layers. A dielectric layer is formed along the treads and risers of the plurality of steps. The dielectric layer is doped with one or a combination of carbon, phosphorus, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form a wordline layer disposed between the insulating layers. A plurality of wordline contacts are formed extending from the wordline layer of the plurality of steps and also extending through the dielectric layer.

Description

Background Art

[0001] Flash memory devices have recently experienced rapid development. Flash memory devices are able to maintain stored data for a long period of time without applying voltage. In addition, the read rate of flash memory devices is relatively high, and it is easy to erase stored data and rewrite data into the flash memory device. Therefore, flash memory devices are widely used in microcomputers, automated control systems, etc. In order to increase the bit density of flash memory devices and reduce their bit cost, three-dimensional (3D) NAND (NAND) flash memory devices have been developed. 3D-NAND memory devices may include an array area and a stepped area coupled to the array area. The stepped area may have multiple steps. Multiple word line contacts may also extend from the steps of the stepped area and couple to the memory cells in the array area. Summary of the Invention

[0002] The present disclosure describes embodiments generally related to structures and methods for fabricating stepped regions of 3D-NAND memory devices.

[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. In the method, a stack of alternating insulating layers and sacrificial layers can be formed above a substrate. A staircase having a plurality of steps can be formed in the stack, wherein each of the plurality of steps can have a horizontal plate and a vertical plate, and further comprising a corresponding pair of insulating layers and sacrificial layers for the corresponding steps, the sacrificial layers being above the insulating layers. A dielectric layer can be formed along the horizontal plates and vertical plates of the plurality of steps. The dielectric layer can be doped with one of carbon, phosphorus, boron, arsenic and oxygen, or a combination thereof. The sacrificial layer can also be replaced with a conductive material to form a word line layer arranged between the insulating layers. A plurality of word line contacts can be formed to extend from the word line layer of the plurality of steps and also extend through the dielectric layer.

[0004] In an example, to replace the sacrificial layer, the sacrificial layer may be removed to form a space between the insulating layers, and the space may be filled with the conductive material to form the word line layer between the insulating layers.

[0005] In another example, to replace the sacrificial layer, the sacrificial layer and the portion of the dielectric layer in contact with the sacrificial layer may be removed to form a space between the insulating layers. Subsequently, the space may be filled with the conductive material to form the word line layer between the insulating layers.

[0006] In some embodiments, in each of the multiple steps, the word line layer may extend further into the dielectric layer in a direction parallel to the substrate compared to the insulating layer, and a portion of the word line layer covered by the insulating layer of an overlying step in the multiple steps may have a smaller thickness than a portion of the word line layer at the horizontal plate.

[0007] In an example of the method, a SiN layer may be formed to form the dielectric layer. The SiN layer may be doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof.

[0008] In another example of the method, in order to form the dielectric layer, a SiN layer may be formed.

[0009] The SiN layer may be doped with carbon by a process gas including tetramethylsilane and NH 3 .

[0010] In yet another example of the method, in order to form the dielectric layer, a SiN layer may be formed.

[0011] The SiN layer may be doped with oxygen by a process gas including SiH 4 and N 2 O.

[0012] In the method, each of the plurality of word line contacts may extend from a corresponding word line layer at a lateral plate of the plurality of steps and further extend through the dielectric layer in a direction perpendicular to the substrate.

[0013] In the method, in order to replace the sacrificial layer, the sacrificial layer may be removed by an etching process, wherein the dielectric layer may have a lower etching rate than the sacrificial layer in the etching process.

[0014] To form a stack of alternating insulating layers and sacrificial layers, insulating layers comprising SiO and sacrificial layers comprising SiN may be alternately deposited on the substrate such that the sacrificial layers are disposed between the insulating layers.

[0015] According to another aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stack of alternating insulating layers and wordline layers on a substrate and a staircase having a plurality of steps formed in the stack. Each of the plurality of steps has a horizontal plate and a vertical plate, and further includes a corresponding pair of insulating layers and wordline layers for the corresponding steps, the wordline layers being located above the insulating layers. In the semiconductor device, a dielectric layer may be formed along the horizontal plates and vertical plates of the plurality of steps, wherein the dielectric layer may be doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof. The semiconductor device may also include a plurality of wordline contacts extending from the wordline layers of the plurality of steps and also extending through the dielectric layer.

[0016] In some embodiments, in each of the multiple steps, the word line layer may extend further into the dielectric layer in a direction parallel to the substrate compared to the insulating layer, and a portion of the word line layer covered by the insulating layer of an overlying step in the multiple steps may have a smaller thickness than a portion of the word line layer at the horizontal plate.

[0017] In an example, the dielectric layer may include a SiN layer doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof.

[0018] In another example, the dielectric layer may include a SiN layer doped with carbon by a process gas including tetramethylsilane and NH 3 .

[0019] In yet another example, the dielectric layer may include a SiN layer doped with oxygen by a process gas including SiH 4 and N 2 O.

[0020] In some embodiments, each of the plurality of word line contacts may extend from a corresponding word line layer at a horizontal plate of the plurality of steps and further extend through the dielectric layer in a direction perpendicular to the substrate.

[0021] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. In the method, a stack consisting of alternating oxide layers and first nitride layers can be formed on a substrate. The stack can be etched to form a staircase having multiple steps in the stack, wherein each of the multiple steps can have a horizontal plate and a vertical plate, and further includes corresponding pairs of the oxide layer and the nitride layer for the corresponding steps, the nitride layer being located above the oxide layer. A second nitride layer can be formed along the horizontal plates and vertical plates of the multiple steps. The second nitride layer can be doped with one or a combination of carbon, phosphorus, boron, arsenic and oxygen. The first nitride layer can be removed by an etching process to form spaces between the oxide layers. These spaces can be filled with a conductive material to form the wordline layer arranged between the oxide layers. A plurality of wordline contacts can be formed to extend from the wordline layer of the multiple steps and also extend through the second nitride layer.

[0022] To remove the first nitride layer, portions of the first nitride layer and the second nitride layer that are in contact with the first nitride layer may be removed to form a space between the oxide layers.

[0023] In some embodiments, in each of the multiple steps, the word line layer may extend further into the second nitride layer in a direction parallel to the substrate compared to the oxide layer, and a portion of the word line layer covered by the insulating layer of an overlying step in the multiple steps may have a smaller thickness than a portion of the word line layer at the cross plate.

[0024] To form the second nitride layer, in one example, a SiN layer doped with carbon may be formed using a process gas including tetramethylsilane and NH 3 . In another example, a SiN layer doped with oxygen may be formed using a process gas including SiH 4 and N 2 O. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By reading the detailed description below in conjunction with the accompanying drawings, various aspects of the present disclosure can be understood. It should be noted that, in accordance with the conventions of the industry, various features are not drawn to scale. In fact, the sizes of various features may be increased or reduced for clarity of discussion.

[0026] Figure 1 is a cross-sectional view of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure.

[0027] Figure 2A 、 2B 2C are cross-sectional views of forming a stepped region in a related 3D-NAND memory device according to an exemplary embodiment of the present disclosure.

[0028] Figure 3A 、 3B 3C and 3D are cross-sectional views of various intermediate steps in fabricating a stepped region of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure.

[0029] Figure 4 is a cross-sectional view of a first exemplary stepped region of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure.

[0030] Figure 5 is a cross-sectional view of a second exemplary stepped region of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure.

[0031] Figure 6 is a flow chart of a process for fabricating a stepped region of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The disclosure below provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature as described below may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, spatially relative terms, such as "below," "beneath," "beneath," "above," and the like, may be used herein for ease of description to describe one element or feature in its relationship to other elements or features as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0034] In order to form a 3D-NAND memory device, a stack consisting of alternating oxide layers and sacrificial layers (e.g., SiN layers) can be formed on a substrate. A staircase comprising multiple steps can be formed in the stack. Next, the sacrificial layer can be removed (e.g., by wet etching) and replaced with a conductive material to form a word line layer arranged between the oxide layers. Multiple word line contacts can also be formed on the word line layer at the steps of the staircase. With the development of 3D-NAND memory devices, the height of the stack continues to increase, and the challenges faced by the contact window (landing window) on the word line layer where the word line contacts are located at the steps also increase. For example, if the contact window is small, the word line contact may extend through (or penetrate) the word line layer at the step. In order to increase the contact window, in a related example, two SiN layers can be selectively deposited on the step by atomic layer deposition (ALD). The selectively deposited SiN layer and the sacrificial layer can also be replaced by a conductive material at the same time to form a word line layer. Therefore, the word line layer may have a greater thickness at the step in the staircase, and the word line contact may be prevented from penetrating the word line layer at the step.

[0035] However, in the examples described above, the selective formation of these SiN layers requires high standards. For example, precise control is required to control the film difference between the SiN layers on the upper and lower steps in the staircase, the step profile angle, and the wet etching concentration and etching time, which in turn brings more challenges and difficulties to the subsequent manufacturing processes.

[0036] In the present disclosure, in order to increase the contact window of the word line contact, a processing gas precursor containing one or a combination of elements such as carbon, phosphorus, arsenic and oxygen can be applied to dope the SiN layer in a selective SiN deposition process. The doped SiN layer can have a much lower etching rate than the sacrificial layer. For example, carbon-doped SiN can have a much lower etching rate in phosphoric acid (H3PO4) than a sacrificial layer composed of SiN. Therefore, during the subsequent removal of the sacrificial layer (e.g., SiN layer), the selectively deposited SiN layer can remain on the steps of the step. The selectively deposited SiN layer can act as an etch stop layer to prevent the word line contact from penetrating the word line layer at the step. Accordingly, the control of the manufacturing process for forming the step region in the 3D-NAND memory device can become much easier.

[0037] Figure 1 is an exemplary embodiment of a 3D-NAND memory device (or device) 100. Figure 1 As shown in FIG, device 100 may include an array region 200A and stepped regions 200B-200C disposed in dielectric layer 24. Array region 200A may be disposed between stepped regions 200B-200C and formed in a stack of alternating wordline layers 12a-12p and insulating layers 14a-14q above substrate 10. Wordline layers 12a-12p may include one or more bottom select gate (BSG) layers, gate layers (or wordline layers), and one or more top select gate (TSG) layers sequentially disposed above substrate 10. For example, wordline layer 12a may be a BSG layer in device 100, and wordline layer 12p may be a TSG layer in device 100.

[0038] In some embodiments, device 100 may include one or more bottom dielectric trenches (e.g., 26 and 28) formed in one or more BSGs (e.g., in wordline layer 12a). Bottom dielectric trenches 26 and 28 may extend along the X-direction of substrate 10 to divide each BSG into multiple sub-BSGs (e.g., 12a-1, 12a-2, and 12a-3). Furthermore, one or more top dielectric trenches (e.g., 30 and 32) may be formed in one or more TSGs (e.g., in wordline layer 12p). Top dielectric trenches 30 and 32 may also extend along the X-direction of substrate 10 and divide each TSG into multiple sub-TSGs (e.g., 12p-1, 12p-2, and 12p-3). The sub-BSGs and sub-TSGs may divide device 100 into multiple sub-blocks. Each sub-block may have a corresponding sub-BSG and a corresponding sub-TSG. Therefore, the memory cell strings in the corresponding sub-blocks can be individually operated by controlling the corresponding sub-BSGs and sub-TSGs.

[0039] The array area 200A may include a plurality of channel structures 18. Each of the channel structures 18 may include a corresponding top channel contact 19. Each of the channel structures 18 may extend through the stack and may be coupled to the word line layers 12a-12p to form a corresponding vertical NAND memory cell string. A vertical NAND memory cell string may include one or more bottom selection transistors (BSTs), a plurality of memory cells (MCs), and one or more top selection transistors (TSTs) sequentially arranged in series along the height direction (e.g., Z direction) of the substrate above the substrate 10. One or more BSTs may be formed by a channel structure and one or more BSG layers, MCs may be formed by a channel structure and a word line layer, and one or more TSTs may be formed by a channel structure and one or more TSG layers.

[0040] In device 100, each of the memory cells can store one or more logic bits depending on the device design. For example, the memory cells can be single-level cells (SLC), multi-level cells (MLC), or triple-level cells (TLC). Accordingly, each of the memory cells can store one logic bit, two logic bits, or three logic bits.

[0041] Still refer to Figure 1 In the stepped regions 200B and 200C, word line layers 12a-12p may be formed in a stepped configuration, and a plurality of word line contacts 22 may be formed along the height direction and coupled to the word line layers 12a-12p. Thus, a gate voltage can be applied to the gate of the memory cell via the word line contacts 22 coupled to the word line layers 12a-12p.

[0042] In addition, each of the channel structures can be coupled to a corresponding bit line (or bit line structure). In some embodiments, the bit line can be connected to the top channel contact 19 of the channel structure 18 and configured to apply a bias voltage when operating the channel structure (e.g., programming, erasing, or reading the channel structure). The device 100 can have multiple gap structures (or gate line gap structures). For example, in Figure 1 The device 100 includes two slot structures 20a-20b. The slot structures 20a-20b may be made of a conductive material and are located on the array common source (ACS) region 16 to function as contacts. The ACS region is formed in the substrate 10 to function as a common source for the device 100.

[0043] Figure 2A 、 2B 2C are cross-sectional views of forming a stepped region 200 in a related 3D-NAND memory device. Figure 2A As shown in FIG, in the stepped region 200, a stack of alternating insulating layers 201a-201d and sacrificial layers 202a-202d is formed on a substrate (not shown). Figure 2A In an exemplary embodiment of the present invention, the insulating layers 201a-201d may be oxide layers (e.g., SiO layers), and the sacrificial layers 202a-202d may be SiN layers. In addition, a plurality of steps 206-212 may be formed in the stack. Each of the steps 206-212 may include a corresponding pair of insulating layers and sacrificial layers, wherein the sacrificial layers are located above the insulating layers. For example, step 206 may include insulating layer 201d and sacrificial layer 202d located above insulating layer 201d. Each of steps 206, 208, 210, and 212 may include a horizontal plate and a vertical plate. For example, step 206 may include a horizontal plate 206b and a vertical plate 206a. Step 208 may include a horizontal plate 208b and a vertical plate 208a. In addition, a dielectric layer 204 may be formed along the steps and cover the horizontal plates and vertical plates of the steps. The dielectric layer 204 may include SiO or SiN, etc. In the embodiment of the present invention, the insulating layers 201a-201d may be oxide layers (e.g., SiO layers) and sacrificial layers (e.g., SiN layers) may be located above the insulating layers. Figure 2A In an exemplary embodiment, dielectric layer 204 may be SiN.

[0044] exist Figure 2B In the embodiment, a selective etching process may be performed to remove portions of dielectric layer 204 formed along the risers of steps 206, 208, 210, and 212 and retain portions of dielectric layer 204 formed on the runners 206b, 208b, 210b, and 212b.

[0045] exist Figure 2CIn the embodiment, the sacrificial layers 202a-202d and the portions of the dielectric layer 204 remaining on the horizontal plates 206b, 208b, 210b, and 212b can be removed by an etching process. Accordingly, spaces (not shown) are formed between the insulating layers 201a-201d. Each of these spaces can have a first portion having a first height D1 measured between two adjacent insulating layers and a second portion having a second height D2 measured at the horizontal plate of the corresponding step. The first height D1 can be approximately equal to the thickness of the corresponding sacrificial layer being removed. The second height D2 at the horizontal plate can be equal to the thickness of the corresponding sacrificial layer plus the thickness of the portion of the dielectric layer 204 located on the horizontal plate. Therefore, the second height D2 can be greater than the first height D1. A conductive material such as W, Co, or Ru can then be deposited to fill the spaces. Accordingly, a plurality of word line layers 203a-203d separated from each other by the insulating layers 201a-201d can be formed.

[0046] Still refer to Figure 2C Each wordline layer 203a-203c may have a first portion located between two adjacent insulating layers and a second portion located at the corresponding cross-plate. The first portion of the wordline may be formed by filling the first portion of the space with a conductive material, and the second portion of the wordline may be formed by filling the second portion of the space with a conductive material. As mentioned above, the first portion of the space may have a first height D1, and the second portion of the space may have a second height D2, where D1 is less than D2. Accordingly, the first portion of the wordline layer is thinner than the second portion of the wordline layer. For example, wordline layer 203a has a second portion 203a_2 located at cross-plate 212b, which is thicker than the first portion 203a_1 located between two adjacent insulating layers 201a and 201b. Multiple wordline contacts 214 may be formed to extend from the cross-plates of steps 208, 210, and 212. The wordline contacts 214 may also extend into the wordline layers 203a-203c at the cross-plates. In a related 3D-NAND memory device, the thickness of the word line layers 203 a - 203 c at the horizontal planes of the steps 206 , 208 , 210 , and 212 may be increased, which in turn prevents the word line contacts 214 from penetrating the word line layers 203 a - 203 c .

[0047] As stated above, in order to form Figure 2C The structure requires high-standard process control to control the selective formation of the SiN layer (e.g., 204) on the horizontal plate of the step. For example, the SiN layer on the vertical plate needs to be removed by precise etching, requiring the step profile angle to be close to 90 degrees and the wet etching concentration / etching time to be within a small range, which in turn brings more challenges and difficulties to the subsequent manufacturing process.

[0048] Figure 3A 、3B 3C and 3D are cross-sectional views of various intermediate steps in fabricating a stepped region 300 of a 3D-NAND memory device. Figure 3A As shown in , in the stepped region 300, a stack of alternating insulating layers 302a-302b and sacrificial layers 304a-304b is formed on a substrate (not shown). In addition, a plurality of steps 306-308 can be formed in the stack. Each of the steps 306 and 308 can include a corresponding pair of insulating layers and sacrificial layers, wherein the sacrificial layers are located above the insulating layers. For example, step 306 can include an insulating layer 302b and a sacrificial layer 304b located above the insulating layer 302b. Each of the steps 306 and 308 can include a horizontal plate and a vertical plate. For example, step 306 can include a horizontal plate 306b and a vertical plate 306a. Step 308 can include a horizontal plate 308b and a vertical plate 308a. It should be noted that Figure 3A This is just an example. The stack may include any number of insulating layers and sacrificial layers, and any number of steps may be formed in the stack accordingly.

[0049] exist Figure 3A In an exemplary embodiment, the insulating layers 302a-302b may be silicon oxide (SiO) layers, and the sacrificial layers 304a-304b may be silicon nitride (SiN) layers. Of course, the insulating layers and the sacrificial layers may include any suitable dielectric material. The insulating layers and the sacrificial layers may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, sputtering, diffusion, or any combination thereof.

[0050] exist Figure 3B In the embodiment, the dielectric layer 310 can be selectively formed along the steps and cover the horizontal and vertical plates of the steps. The dielectric layer 310 can include SiO, SiN or other suitable dielectric materials. Figure 3A In an exemplary embodiment of the present invention, the dielectric layer 310 may be SiN doped with one or a combination of carbon (C), phosphorus (P), boron (B), arsenic (Ar), and oxygen (O). The dielectric layer 310 may be formed by any suitable deposition process, such as ALD, plasma-enhanced CVD, etc. In order to form the doped SiN, a process gas precursor containing one or a combination of carbon, phosphorus, arsenic, and oxygen may be applied to form the doped SiN. Accordingly, in the example, the SiN layer 310 doped with carbon may be formed by a process gas precursor including tetramethylsilane (C4H 12In another example, the SiN layer 310 doped with oxygen may be formed by a process gas including SiH4 and N2O. In another example, the SiN layer 310 doped with phosphorus and / or boron may be formed. In another example, the SiN layer 310 doped with carbon and oxygen may be formed by a process gas including SiH4, N2O, and C2F6. In yet another example, the SiN layer 310 doped with one of P, B, or Ar, or a combination thereof, may be formed.

[0051] It should be pointed out that in Figure 3B In the example of FIG, dielectric layer 310 is a silicon nitride-based dielectric layer doped with one or a combination of C, P, B, O, and Ar. Therefore, the doping elements (e.g., C, P, B, O, and Ar) have a lower atomic concentration in dielectric layer 310 than silicon nitride.

[0052] exist Figure 3C In the embodiment, the sacrificial layers 304a-304b may be removed by an etching process (eg, wet etching). The wet etching process may use wet acid to remove the sacrificial layers 304a-304b and form a space (not shown) between the insulating layers 302a-302b. Figure 3C In the example of , the wet acid may be H3PO4 acid. The doped SiN layer 310 may have a lower etching rate in the wet acid than the sacrificial layers 304a-304b. Therefore, during the removal of the sacrificial layers 304a-304b, the doped SiN layer 310 can remain on the steps of the staircase. In addition, a conductive material may be filled in these spaces to form a plurality of word line layers 312a-312b separated from each other by the insulating layers 302a-302b. Figure 3C In an example, the conductive material may include tungsten (W), cobalt (Co), ruthenium (Ru), etc.

[0053] exist Figure 3D In the embodiment, a plurality of word line contacts may be formed that extend from the word line layer at the step and also extend through the dielectric layer 310. Figure 3D As shown in FIG, an exemplary word line contact 314 is formed to be located on the word line layer 312a and extend through the dielectric layer 310. The doped SiN layer 310 located on the steps (e.g., 306 and 308) can act as an etch stop layer to prevent the word line contact (e.g., 314) from penetrating the word line layer (e.g., 312a) at the steps. Accordingly, the control of the manufacturing process for forming the stepped region 300 can be much easier.

[0054] Still refer to Figure 3DTo form wordline contacts (e.g., 314), an interlayer dielectric (ILD) 316 may be formed to cover steps 306 and 308. A patterning process may also be applied to form contact openings (not shown) in the ILD 316. The patterning process may include a photolithography process to form a patterned mask having a pattern and an etching process to transfer the pattern of the patterned mask to the ILD 316 to form the contact openings. The etching process may also etch through the doped SiN layer 310 to expose the wordline layer (e.g., 312a). The contact openings may also be filled with a conductive material by a deposition process such as CVD, PVD, ALD, diffusion, or the like. The conductive material may include W, Co, Ru, Cu, Al, or the like.

[0055] Figure 4 Shows that it can be based on Figures 3A-3D A cross-sectional view of a first exemplary stepped region 400 of a 3D-NAND memory device formed by a manufacturing process in FIG. Figure 4 As shown in FIG, a stepped region 400 may be formed into a stack of alternating insulating layers 402a-402d and wordline layers 404a-404d and include a plurality of steps 412, 414, 416, and 418. Each of the plurality of steps 412, 414, 416, and 418 may include a corresponding pair of insulating layers and wordline layers. For example, step 412 may include insulating layer 402d and wordline layer 404d. A dielectric layer 406 may be formed along steps 412, 414, 416, and 418 and serve as an etch stop layer. Dielectric layer 406 may be composed of SiN doped with one or a combination of carbon, phosphorus, boron, arsenic, and oxygen. In addition, a plurality of wordline contacts 410a-410c may be formed in ILD layer 408. The word line contacts 410 a - 410 c may extend from the word line layers 404 a - 404 d at steps 412 , 414 , 416 , and 418 in a direction perpendicular to the substrate (eg, the Z direction) and also extend through the dielectric layer 406 .

[0056] Figure 5 It can be based on Figures 3A-3D A cross-sectional view of a second exemplary stepped region 500 of a 3D-NAND memory device formed by the manufacturing process in FIG. Figure 5As shown in FIG, a stepped region 500 may be formed into a stack of alternating insulating layers 502a-502d and wordline layers 504a-504d and include a plurality of steps 512, 514, 516, and 518. Each of the plurality of steps 512, 514, 516, and 518 may include a corresponding pair of insulating layers and wordline layers, as well as horizontal and vertical plates. For example, step 518 may include horizontal plates 518b and vertical plates 518a formed in insulating layers 502a and wordline layers 504a. A dielectric layer 506 may be formed along steps 512-518 and serve as an etch stop layer. Dielectric layer 506 may be composed of SiN doped with one or a combination of carbon, phosphorus, boron, arsenic, and oxygen. In addition, a plurality of wordline contacts 510a-510c may be formed in ILD layer 508. The word line contacts 510a-510c can extend from the word line layers 504a-504d at the horizontal plates of the steps 512-518 in a direction perpendicular to the substrate (e.g., the Z direction) and also extend through the dielectric layer 506. For example, the word line contact 510c can extend from the word line layer 504a located at the horizontal plate 518b of the step 518.

[0057] In order to form the stepped region 500, when removing the sacrificial layer (e.g., 304a-304b) by wet etching, the wet acid, the wet acid concentration, or the wet etching time can be adjusted so as to remove the sacrificial layer and the portion of the dielectric layer 506 that is in contact with the sacrificial layer to form a space between the insulating layers. Subsequently, the spaces can be filled with a conductive material to form a stepped region 500. Figure 5 The word line layer shown in .

[0058] Compared to step region 400, step region 500 may have different characteristics. For example, in each of steps 512, 514, 516, and 518, wordline layers 504a-504d may extend further into dielectric layer 506 in a direction parallel to the substrate (e.g., the Y direction) than insulating layers 502a-502d. Furthermore, the portion of the wordline layer covered by the overlying insulating layer of the stack has a thickness less than the portion of the wordline layer at the cross plate. For example, wordline layer 504d in step 512 may extend W1 further into dielectric layer 506. W1 may be in the range of 5 nm to 100 nm. The portion of wordline layer 504c covered by the overlying insulating layer 502d may have a thickness less than W2 of the portion of wordline layer 504c located at cross plate 514d of step 514. W2 may be in the range of 5 nm to 100 nm.

[0059] Figure 66 is a flow chart of a process 600 for manufacturing a disclosed 3D-NAND memory device according to some embodiments of the present disclosure. Process 600 begins at step S602 and proceeds to step S604. In step S604, a stack of alternating insulating layers and sacrificial layers may be formed over a substrate. To form the stack of alternating insulating layers and sacrificial layers, insulating layers comprising SiO and sacrificial layers comprising SiN may be alternately deposited on the substrate, such that the sacrificial layers are disposed between the insulating layers.

[0060] Then, the process 600 proceeds to S606. In S606, a staircase having a plurality of steps may be formed in the stack, wherein each of the plurality of steps may have a horizontal plate and a vertical plate, and further includes a corresponding pair of an insulating layer and a sacrificial layer for the corresponding step, the sacrificial layer being located above the insulating layer. In some embodiments, the steps described in reference to FIG. Figure 3A Steps S604 and S606 are illustrated.

[0061] In S608, a dielectric layer may be formed along the horizontal and vertical plates of the plurality of steps. The dielectric layer may be doped with one of carbon, phosphorus, boron, arsenic and oxygen or a combination thereof. In some embodiments, the dielectric layer may be doped with carbon, phosphorus, boron, arsenic and oxygen or a combination thereof. Figure 3B The illustrated execution step S608.

[0062] In some embodiments, a SiN layer may be formed to form the dielectric layer, and the SiN layer may be doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof.

[0063] In some embodiments, a SiN layer may be formed to form the dielectric layer, and the SiN layer may be doped with carbon using a process gas including tetramethylsilane and NH 3 .

[0064] In some embodiments, a SiN layer may be formed to form the dielectric layer, and the SiN layer may be doped with oxygen using a process gas including SiH 4 and N 2 O.

[0065] In S610, the sacrificial layer may be replaced by a conductive material to form a word line layer disposed between the insulating layers. Figure 3C The illustrated execution step S610.

[0066] In an example, to replace the sacrificial layer, the sacrificial layer may be removed through an etching process, wherein the dielectric layer may have a lower etching rate than the sacrificial layer in the etching process.

[0067] In an example, to replace the sacrificial layer, the sacrificial layer may be removed to form spaces between the insulating layers, and the spaces may be filled with the conductive material to form word line layers between the insulating layers.

[0068] In another example, to replace the sacrificial layer, the sacrificial layer and the portion of the dielectric layer in contact with the sacrificial layer may be removed to form spaces between the insulating layers. Subsequently, the spaces may be filled with the conductive material to form a word line layer between the insulating layers.

[0069] In some embodiments, in each of the multiple steps, the word line layer may extend further into the dielectric layer in a direction parallel to the substrate compared to the insulating layer, and a portion of the word line layer covered by the insulating layer of an overlying step of the multiple steps may have a smaller thickness than a portion of the word line layer at the horizontal plate.

[0070] In S612, a plurality of word line contacts may be formed to extend from the word line layer of the plurality of steps and further extend through the dielectric layer. In the method, each of the plurality of word line contacts may extend from a corresponding word line layer at a horizontal plate of the plurality of steps and further extend through the dielectric layer in a direction perpendicular to the substrate. In some embodiments, the method may be described as referring to Figure 3D The illustrated execution step S612.

[0071] It should be noted that additional steps may be provided before, during, and after process 600, and that some of the steps described may be replaced, deleted, or performed in a different order for other embodiments of process 600. For example, a channel structure may be formed in the array region of the initial stack before replacing the sacrificial layer with a wordline layer. Furthermore, a slit structure may be formed before replacing the sacrificial layer with a wordline layer. Furthermore, various additional interconnect structures (e.g., metallization layers with conductive lines and vias) may be formed above the wordline contacts of the 3D-NAND memory device. Such interconnect structures electrically connect the 3D-NAND memory device to other contact structures and / or active devices to form functional circuits. Additional device features such as passivation layers, input / output structures, etc. may also be formed.

[0072] The various embodiments described herein offer several advantages over methods described in related examples for manufacturing 3D-NAND memory devices. To prevent wordline contacts from penetrating the wordline layer at the steps of the staircase region, in related examples, high standards are required to control the selective formation of the dielectric layer, which in turn introduces additional challenges and difficulties into the subsequent manufacturing process. In the present disclosure, a doped dielectric layer is formed along the steps of the staircase region, thereby acting as one or more etch stop layers to prevent wordline contacts from penetrating the wordline layer at the steps. Accordingly, control over the manufacturing process for forming the wordline contacts can be made much easier.

[0073] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will recognize that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent designs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a staircase having a plurality of steps in the stack, the steps comprising corresponding insulating layers and sacrificial layers, the sacrificial layers being located on the insulating layers; forming a dielectric layer on the plurality of steps, wherein the dielectric layer is doped with one of carbon, phosphorus, boron, arsenic and oxygen or a combination thereof; replacing the sacrificial layer with a conductive material to form a word line layer disposed between the insulating layers; as well as forming a plurality of word line contacts extending from the word line layer of the plurality of steps and also extending through the dielectric layer, Wherein, replacing the sacrificial layer further comprises: removing the sacrificial layer and a portion of the dielectric layer in contact with the sacrificial layer to form a space between the insulating layers; and Filling the conductive material in the space to form the word line layer located between the insulating layers, Wherein, in each of the plurality of steps: The word line layer extends further into the dielectric layer than the insulating layer in a direction parallel to the substrate, and A portion of the word line layer covered by the insulating layer overlying a step among the plurality of steps has a thickness smaller than at least a portion of the word line layer not covered by the insulating layer overlying a step among the plurality of steps.

2. The method according to claim 1, wherein Forming the dielectric layer further includes: A SiN layer doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof, is formed.

3. The method according to claim 1, wherein Forming the dielectric layer further includes: The SiN layer doped with carbon is formed by a process gas including tetramethylsilane and NH 3 .

4. The method according to claim 1, wherein Forming the dielectric layer further includes: The oxygen-doped SiN layer is formed by a process gas including SiH 4 and N 2 O.

5. The method according to claim 1, wherein Each of the plurality of word line contacts extends from a corresponding word line layer at at least a portion of the plurality of steps not covered by the insulating layer of an overlying step of the plurality of steps and further extends through the dielectric layer in a direction perpendicular to the substrate.

6. The method according to claim 1, wherein Replacing the sacrificial layer further includes: The sacrificial layer is removed by an etching process, and the dielectric layer has a lower etching rate than the sacrificial layer in the etching process.

7. The method according to claim 1, wherein Forming the stack of alternating insulating layers and sacrificial layers further comprises: The insulating layers including SiO and the sacrificial layers including SiN are alternately deposited on the substrate to dispose the sacrificial layers between the insulating layers.

8. A semiconductor device comprising: a stack of alternating insulating and wordline layers overlying the substrate; a staircase having a plurality of steps formed in the stack, the steps comprising corresponding insulating layers and word line layers, the word line layers being located above the insulating layers; a dielectric layer formed on the plurality of steps; as well as a plurality of word line contacts extending from the word line layer of the plurality of steps and also extending through the dielectric layer, Wherein, in each of the plurality of steps: The word line layer extends further into the dielectric layer than the insulating layer in a direction parallel to the substrate, and A portion of the word line layer covered by the insulating layer overlying a step among the plurality of steps has a thickness smaller than at least a portion of the word line layer not covered by the insulating layer overlying a step among the plurality of steps.

9. The semiconductor device according to claim 8, wherein The dielectric layer includes a SiN layer doped with one of carbon, phosphorus, boron, arsenic, and oxygen, or a combination thereof.

10. The semiconductor device according to claim 8, wherein The dielectric layer includes a SiN layer doped with carbon by a process gas including tetramethylsilane and NH 3 .

11. The semiconductor device according to claim 8, wherein The dielectric layer includes a SiN layer doped with oxygen by a process gas including SiH 4 and N 2 O.

12. The semiconductor device according to claim 8, wherein Each of the plurality of word line contacts extends from a corresponding word line layer at at least a portion of the plurality of steps not covered by the insulating layer of an overlying step of the plurality of steps and further extends through the dielectric layer in a direction perpendicular to the substrate.

13. A method for manufacturing a semiconductor device, comprising: forming a stack of alternating oxide layers and first nitride layers over the substrate; Etching the stack to form a staircase having a plurality of steps in the stack, the steps including corresponding oxide layers and the first nitride layer, the first nitride layer being located on the oxide layer; forming a second nitride layer on the plurality of steps, wherein the second nitride layer is doped with one of carbon, phosphorus, boron, arsenic and oxygen, or a combination thereof; removing portions of the first nitride layer and the second nitride layer contacting the first nitride layer by an etching process to form a space between the oxide layers, and filling the space with a conductive material to form a word line layer disposed between the oxide layers; as well as forming a plurality of word line contacts extending from the word line layer of the plurality of steps and also extending through the second nitride layer, Wherein, in each of the plurality of steps: The word line layer further extends into the second nitride layer in a direction parallel to the substrate than the oxide layer, and A portion of the word line layer covered by the oxide layer of an overlying step among the plurality of steps has a thickness smaller than at least a portion of the word line layer not covered by the oxide layer of the overlying step among the plurality of steps.

14. The method according to claim 13, wherein: Forming the second nitride layer further includes one of the following operations: forming a SiN layer doped with carbon by a process gas including tetramethylsilane and NH 3 ; and The oxygen-doped SiN layer is formed by a process gas including SiH 4 and N 2 O.

Images