Processing system for monitoring cell voltage, related battery monitoring system and electric vehicle

Abstract

Various embodiments of the present disclosure relate to processing systems for monitoring cell voltages, related battery monitoring systems, and electric vehicles. An embodiment processing system includes a terminal configured to connect to a cell of a rechargeable battery to receive the cell voltage, a digital processing circuit, a serial communication interface, and a transmission queue that interfaces the digital processing circuit with the serial communication interface for parallel operation. The digital processing circuit synchronously acquires a given number of digital samples of each cell voltage and stores them in a memory. The digital processing circuit encodes the digital samples stored in the memory via a data compression module, and stores the encoded data in the transmission queue. For example, the data compression module can generate encoded data by subtracting a given offset from each digital sample to generate a value indicating the dynamic change of each sample relative to the offset, and removing a given number of most significant bits from each value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102020000017581, filed on Jul. 20, 2020, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present description relate to a monitoring and / or management system for a high voltage rechargeable battery including a plurality of cells, such as lithium-ion cells. Background Art

[0004] Figure 1 A typical electronic system, such as that of a vehicle, is shown, comprising a plurality of processing systems 10, such as embedded systems or integrated circuits, for example, field programmable gate arrays (FPGAs), digital signal processors (DSPs), or microcontrollers (eg, specific to the automotive market).

[0005] For example, in Figure 1 In FIG. 1 , three processing systems 101 , 102 and 103 connected via a suitable communication system 20 are shown.

[0006] For example, for an electric vehicle, the communication system 20 may include a vehicle control bus, such as a controller area network (CAN) bus, and may include a multimedia bus, such as a media oriented systems transport (MOST) bus, connected to the vehicle control bus via a gateway. Typically, the processing system 10 is located at different locations in the vehicle and may include, for example, an engine control unit (ECU), a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system.

[0007] For electric vehicles, including all-electric, plug-in hybrid and non-plug-in hybrid vehicles, such as electric cars, trucks, motorcycles, bicycles, scooters, etc., the vehicle also includes a rechargeable battery 30 and a processing system 10 that implements a battery management system 40.

[0008] For example, Figure 2 An example of a battery management system 40 is shown that is configured to monitor a rechargeable battery 30, such as a lithium-ion (Li-Ion) battery. As described above, such a battery management system 40 can be used in an electric vehicle. However, the battery management system 40 can also be used in other energy storage applications, such as for home energy storage.

[0009] Specifically, in the example considered, the rechargeable battery 30 comprises a plurality of cells C connected in series. For example, such cells C are usually organized in the form of cell groups, for example in the form of battery modules, wherein each cell group usually comprises the same number n of cells. Figure 2 In the embodiment, the cells are organized into m groups, each of which includes n cells, that is, the battery 30 includes a first cell group C 1,1 ..C 1,n 、Last unit group C m,1 ..C m,n and optionally one or more intermediate unit groups, where unit group C 1,1 ..C 1,n to C m,1 ..C m,n Series connection.

[0010] Typically, such a battery management system 40 includes a method for providing a battery 30 (particularly the first cell C 1,1 and the final unit C m,n ) and two terminals 404 and 406 for connection to a load and charging circuit. Typically, the load and charging circuit include switching circuits, for example, in the form of an electrical (usually electronic) converter / inverter configured to receive energy from at least one power source and provide energy to an electrical load. For example, in an electric vehicle, terminals 404 and 406 can be connected to the vehicle's electric traction motor via a power controller. Conversely, in a home energy storage application, terminals 404 and 406 can be connected to an inverter that is configured to:

[0011] receiving energy from the mains / grid or a local generator (such as one or more photovoltaic panels), and

[0012] Provides energy to loads in a domestic environment or to the grid.

[0013] exist Figure 2 In FIG. 1 , the battery management system 40 includes a digital processing system 42 configured to monitor and / or control one or more parameters of the battery 30 .

[0014] For example, Figure 3A block diagram of an exemplary digital processing system 42, such as a microcontroller, is shown. In the example considered, the processing system 42 includes at least one digital processing circuit 422, such as a microprocessor, typically a central processing unit (CPU), which is programmed via software instructions. Typically, the software executed by the processing unit 422 is stored in a program memory 424, such as a non-volatile memory, such as flash memory or an electrically erasable programmable read-only memory (EEPROM). Typically, the memory 424 can be integrated with the processing unit 422 in a single integrated circuit, or the memory 424 can take the form of a separate integrated circuit and be connected to the processing unit 422, for example, via traces of a printed circuit board. Thus, typically, the memory 424 contains firmware for the processing unit 422, where the term firmware includes software for a microprocessor and programming data for a programmable logic circuit such as an FPGA.

[0015] In the example considered, the processing unit 422 may have associated one or more resources 426, such as:

[0016] One or more communication interfaces, such as a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface Bus (SPI), an Inter-Integrated Circuit (I 2 C), Controller Area Network (CAN) bus, Ethernet and / or debug interface; and / or

[0017] one or more analog-to-digital and / or digital-to-analog converters; and / or

[0018] One or more dedicated digital components, such as hardware timers and / or counters, or a cryptographic coprocessor; and / or

[0019] One or more analog components, such as comparators, sensors, such as temperature sensors, etc.; and / or

[0020] One or more mixed-signal components, such as a PWM (Pulse Width Modulation) driver.

[0021] For example, by using resources 426 and via appropriate programming of digital processing circuitry 422, battery management system 40 may be configured to manage one or more of the following functions:

[0022] exchanging data with other processing systems 10 of the electronic system, for example, via a communication channel 20;

[0023] actuating one or more electrical or electronic switches 410 and 412 to selectively connect the battery 30 to the terminals 404 and 406 , e.g., based on the vehicle state (driving, parked, charging, etc.);

[0024] actuating and / or monitoring a thermal fuse 414, for example, the thermal fuse 414 providing emergency disconnection of the battery 30 in the event of an accident, isolation breach, or other malfunction; and

[0025] The current flowing through the battery 30 is monitored, for example, via a current sensor 418 (such as a shunt resistor or a Hall sensor) and an optional current sensor circuit 416 that has performed pre-processing of the signal provided by the current sensor 418, for example, to determine whether the measured current exceeds a given threshold.

[0026] Furthermore, if the rechargeable battery 30 includes a plurality of cells, such as high voltage lithium-ion batteries, the battery management system 40 is typically configured to:

[0027] monitoring the voltage at the individual cells C of the battery 30; and

[0028] Optionally, monitoring the temperature of individual cells C or groups of cells of the battery 30; and

[0029] Optionally, the charge levels of the individual cells C of the battery are balanced.

[0030] For example, Figure 2 As shown, these battery management functions are usually not implemented directly in the digital processing circuit / system 42, but in additional processing circuits / systems 441..44 m , wherein each processing system 44 performs the above operations for a corresponding group of units, for example, the processing system 441 manages the unit C 1,1 ..C 1,n And processing system 44 m Snap-in C m,1 ..C m,n .

[0031] In the example considered, an additional processing system 44, such as an integrated circuit, is then connected to the digital processing system 42 via a suitable communication channel 48. The digital processing system 42 may be configured to receive measured cell voltages from the various processing circuits 44, for example.

[0032] For example, Figure 4 One known solution is shown.In the example considered, a processing system 44 (eg an integrated circuit L9963 from STMicroelectronics) is configured to be connected to a given number n of cells C, eg up to 14 cells C, and to generate digital samples of the respective cell voltages.

[0033] For example, Figure 5 As shown, for this purpose, the processing system 44 may include a given number n+1 of pins CP0..CP n, where each pin CP is configured to be connected to a corresponding terminal of a cell, for example, pin CP0 may be connected to the negative terminal of a first cell C1, pin CP1 may be connected to the positive terminal of the first cell C1 corresponding to the negative terminal of a second cell C2, and so on. Thus, the voltage between two pins CP corresponds to the voltage of a given cell C. Typically, an analog filter such as an RC low-pass filter may also be connected in parallel with each cell, where pins CP0..CP n A filtered version of the cell voltage is received.

[0034] In the example considered, the voltage is provided to one or more differential analog-to-digital converters (ADC) 448, such as delta-sigma converters. For this purpose, the processing system 44 may also include a switching circuit 446, for example, including one or more multiplexers, the switching circuit 446 being configured to connect a given pair of pins CP to a given analog-to-digital converter 448. In general, the switching circuit 446 is completely optional, since the processing system 44 may also include n analog-to-digital converters, i.e., one ADC for each cell C of the corresponding cell group. In the example considered, the digital samples are provided to a digital processing circuit 444 of the processing system 44. In general, the digital processing circuit 444 may be any hardware and / or software digital processing circuit, such as an integrated finite state machine (e.g., implemented with hardware sequential logic circuits) or a microprocessor programmed via software instructions.

[0035] The processing system 44 (e.g., digital processing circuit 444) is also configured to transmit the digital samples to the digital processing system 42, such as a microcontroller. To this end, the processing system 44 includes a communication interface 440. For example, in the case of the L9963 circuit, the communication interface 440 supports two communication modes: a serial peripheral interface (SPI), or isolated communication via capacitive or inductive coupling. However, in general, other communication protocols, such as I 2 C. UART or CAN bus.

[0036] In addition, for example, in the case of the L9963 circuit, multiple processing circuits 44 can be connected in series to form a daisy chain. Specifically, for this purpose, each processing system 44 can include an additional communication interface 442 configured to be connected to the communication interface 440 of the subsequent / downstream processing circuit 44. Therefore, in this case, the digital processing circuit 444 can also manage the data exchange between the interface 440 and the interface 442 of the corresponding processing circuit 44.

[0037] Thus, the digital processing system 42 may include a communication interface 426 configured to connect to the communication channel 48:

[0038] For example, when isolated communication with a daisy chain is used, the interface 440 to the first processing circuit 441; or

[0039] For example, when SPI communications are used, each interface 440 to various processing circuits 44 .

[0040] Typically, in the event that interface 426 is incompatible with interface 440, a bridge circuit 46 may be used to interface interface 426 with interface 440. For example, such a bridge circuit 46 may include a first interface 460 (such as an SPI interface) for connection to interface 426 and a second interface 462 for connection to interface 440. For example, bridge circuit 46 may be an integrated circuit L9963T from STMicroelectronics.

[0041] Therefore, in Figure 4 in (and similarly in Figure 2 In the embodiment of the present invention, the processing system 44 is configured to acquire the voltage at the cell C of the battery (or a filtered version thereof) via the analog-to-digital converter 448, and transmit the digital sample of the cell voltage (e.g., via other processing systems 44 and / or the bridge circuit 46) to the digital processing system 42. For example, when each cell group includes the same number n of cells C, up to n×m samples must be acquired and transmitted. For example, the voltage of a typical vehicle battery 30 may be in the range of 200V to 1000V, typically between 400V and 800V. In this regard, a typical lithium-ion battery has a voltage of about 3.7V. For example, this means that at least 108 cells C need to be connected in series to acquire a voltage of 400V. Therefore, in this case, 8 STM L9963s are required to monitor the corresponding cells C. Obviously, in the case of an 800V system, the number must be doubled. Therefore, in a typical application, 50 to 250 cell voltages must be acquired. For example, the cell voltage can be sampled with an ADC 448 having 16 bits.

[0042] Preferably, the number of ADCs 448 in the processing system 44 corresponds to (or is greater than) the number n, to allow the cell voltages at the cells (at least the same group of cells, preferably all cells of the battery 30) to be sampled at the same time. For example, for this purpose, the digital processing system 42 may send a synchronization trigger signal or some other synchronization signal to the processing system 44, for example, including a sampling period.

[0043] In addition, as described above, the processing system 44 may also implement other operations, such as temperature monitoring of the corresponding battery modules or cells, and / or balancing functions. To this end, additional data may be exchanged between the digital processing system 42 and the processing system 44.

[0044] However, due to the use of a serial communication channel 48, for example in the form of a daisy chain, preferably in the form of a galvanically isolated communication channel, the data transmission has a limited bandwidth. This means, for example, that the sampling cycle is slow, especially in the case of a high-voltage battery comprising at least 50 cells C connected in series. Summary of the invention

[0045] In view of the foregoing, various embodiments provide a more efficient communication of the voltages of cells of a rechargeable battery, such as a high voltage lithium-ion vehicle battery.

[0046] According to one or more embodiments, one or more of the above objects are achieved by a processing system for monitoring cell voltage of a rechargeable battery, the processing system having unique elements specifically described in the present invention. Embodiments also relate to related battery monitoring systems and electric vehicles.

[0047] As described above, various embodiments of the present disclosure relate to a processing system, such as a processing system implemented in an integrated circuit, which is configured to monitor the cell voltages of a given number of cells of a rechargeable battery. For example, such a processing system can be used for battery monitoring and an optional management system that includes a further processing system, such as a microprocessor, configured to be connected to the terminals of the rechargeable battery and configured to receive the cell voltages from the processing system. For example, such a battery monitoring system can be used to monitor a rechargeable (traction) battery of an electric vehicle.

[0048] In various embodiments, a processing system includes a terminal configured to be connected to a cell to receive a cell voltage, and at least one analog-to-digital converter configured to generate digital samples of the cell voltage, wherein each digital sample has a given number of bits.

[0049] In various embodiments, the processing system further includes a digital processing circuit, a serial communication interface, and a transmission queue for interfacing the serial communication interface with the digital processing circuit. Specifically, in various embodiments, the serial communication interface is configured to sequentially transmit the stored data to the transmission queue, so that the digital processing circuit and the serial communication interface can operate in parallel.

[0050] Specifically, in various embodiments, the digital processing circuit includes a (e.g., volatile) memory and a data compression module (such as a software module and / or a dedicated hardware circuit), and the digital processing circuit is configured to synchronously acquire a given number of digital samples of each of a given number of cell voltages, and store the acquired digital samples in the memory. Next, the digital processing circuit encodes the given number of digital samples of the given number of cell voltages stored in the memory via the data compression module, thereby generating encoded data, and stores the encoded data in a transmission queue. Therefore, in various embodiments, the serial communication interface is configured to transfer the stored (encoded) data to the transmission queue when the digital processing circuit acquires a new digital sample.

[0051] Generally, a data compression module may be configured to implement various lossy or lossless data compression operations.

[0052] For example, in various embodiments, the data compression module is configured to generate encoded data by a dynamic range reduction operation. In various embodiments, during the dynamic range reduction operation, the data compression module is configured to subtract a given offset from each digital sample, thereby generating a value indicating the dynamic change of each sample relative to the offset. Next, the data compression module causes the encoded data to be generated by removing a given number of most significant bits from each value indicating the dynamic change of each sample relative to the given offset. Therefore, in this case, another processing system can reconstruct the original sample by adding the given offset to the received value. In various embodiments, the given offset is programmable, for example, the digital processing circuit can be configured to receive the given offset, for example, from another processing system via a serial communication interface.

[0053] In various embodiments, the given number of most significant bits may also be programmable, for example, the digital processing circuit may be configured to receive the given number of most significant bits via a serial communication interface, for example from another processing system.

[0054] In various embodiments, during the dynamic range reduction operation, the data compression module is further configured to generate encoded data by removing a given number of least significant bits from each value indicating the dynamic change of each sample relative to the offset. In addition, the given number of least significant bits can be programmable, for example, the digital processing circuit can be configured to receive the given number of least significant bits via a serial communication interface, for example, from another processing system.

[0055] Therefore, in various embodiments, the value range of the sample is reduced. The inventors have observed that this means that the value of the sample may also be outside the value range, for example, in the case of a fault. To this end, in various embodiments, the data compression module is configured to determine whether each digital sample of a given number of digital samples of a given number of cell voltages is between a minimum threshold and a maximum threshold. In the case where one or more digital samples are not between the minimum threshold and the maximum threshold, the data compression module may store the (original) value of the one or more digital samples that are not between the minimum threshold and the maximum threshold, and store data identifying that one or more digital samples are not between the minimum threshold and the maximum threshold to the encoded data. For example, the data compression module may write a default value to the encoded data or set a flag in a data packet transmitted to another processing system.

[0056] Thus, based on these data, the further processing system may determine that the encoded data is invalid and send a retransmission request to the processing system. Thus, the digital processing circuit / data compression module may be configured to receive the retransmission request and, in response to the retransmission request, transmit at least one value of one or more digital samples that are not between the minimum threshold and the maximum threshold via the serial communication interface, for example, by storing the (original) stored value to a transmission queue.

[0057] Additionally or alternatively, the data compression module can support other data compression modes. For example, in various embodiments, the data compression module is configured to support multiple encoding modes, wherein the data compression module is configured to generate encoded data according to a selected encoding mode, wherein the selected encoding mode is programmable. For example, the digital processing circuit can be configured to receive the selected encoding mode via a serial communication interface, for example from another processing system.

[0058] For example, in various embodiments, in addition to or in lieu of dynamic range reduction, the encoding mode may include at least one of the following:

[0059] a delta encoding mode, wherein the data compression module is configured to generate delta encoded values ​​of the digital samples relative to one or more reference values; and

[0060] A 2D discrete Fourier transform mode, wherein the data compression module is configured to apply the 2D discrete Fourier transform mode to a given number of digital samples of a given number of cell voltages.

[0061] For example, the data compression module can be configured to generate a delta-encoded value for a given cell voltage in the following manner:

[0062] selecting a first digital sample of a given number of digital samples of a given cell voltage as a reference value and generating a delta encoded value by calculating the difference of each subsequent digital sample of the given cell voltage relative to the reference value; or

[0063] selecting a first digital sample of a given number of digital samples of a given cell voltage as a reference value and generating a delta encoded value by calculating a difference between a subsequent digital sample of the given cell voltage and a previous digital sample of the given cell voltage; or

[0064] The value of a reference curve is determined from the digital samples, and a delta-encoded value is generated by calculating the difference between each digital sample of a given cell voltage relative to the value of the reference curve.

[0065] In various embodiments, the data compression module may also support multiple of these delta encoding modes, and the delta encoding mode may be selected by programming the selected encoding mode.

[0066] Furthermore, in various embodiments, the data compression module may be configured to receive data in an identification value format and generate a delta-encoded value from the data in the identification value format by encoding the delta-encoded value using a linear value encoding or encoding the delta-encoded value using a mantissa and an exponent.

[0067] Thus, in various embodiments, the processing system / data compression module supports multiple encoding modes and / or formats, and the additional processing system can program the selected encoding mode and / or format via the serial communication interface. For example, in this manner, the additional processing system can be configured to determine whether the rechargeable battery is in a charging state or a discharging state, and select a first encoding mode and / or format when the rechargeable battery is in a charging state, and select a second encoding mode and / or format when the rechargeable battery is in a discharging state (which generally indicates a higher variability in the cell voltage).

[0068] In various embodiments, the processing system may also be configured to form a daisy chain with other processing systems. In this case, the processing system may include another transmission queue, another serial communication interface configured to receive data (from another processing system) in sequence and store the received data in the other transmission queue. Therefore, in this case, the multiplexer / arbiter may be configured to connect the serial communication interface to the transmission queue or another transmission queue, so that the serial communication interface is configured to transmit the stored data to the transmission queue or another transmission queue in sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Embodiments of the present disclosure will now be described with reference to the drawings of the accompanying drawings, which are provided purely by way of non-limiting examples and in which:

[0070] The characteristics and advantages of the invention will become apparent from the following detailed description of a practical embodiment of the invention shown by way of non-limiting example, in the accompanying drawings, in which:

[0071] Figure 1 An example of an electronic system is shown;

[0072] Figure 2 An example of a battery management system for a rechargeable battery is shown;

[0073] Figure 3 Shows the application Figure 2 An example of a digital processing system for a battery management system;

[0074] Figure 4 An example of implementing a battery management function via an additional battery management module is shown;

[0075] Figure 5 Shows Figure 4 An example of a battery management module;

[0076] Figure 6 An example of the operation of a battery management module is shown;

[0077] Figure 7 An embodiment of the operation of a battery management module according to the present disclosure is shown;

[0078] Figure 8 is a block diagram illustrating an embodiment of a battery management module according to the present disclosure;

[0079] Fig. 9 is a flow chart illustrating an embodiment of the operation of a battery management module according to the present disclosure;

[0080] Fig.10 An embodiment of data acquired by a battery management module of the present disclosure is shown;

[0081] Fig.11 Shows Figure 8 An embodiment of the operation of the communication interface of the battery management module; and

[0082] Figures 12 to 15 An embodiment of a data compression operation suitable for implementation within a battery management module according to the present disclosure is shown. DETAILED DESCRIPTION

[0083] In the following description, various specific details are explained to enable a deeper understanding of the embodiments. Embodiments may be provided without one or more specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0084] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment", "in one embodiment", etc. that may appear in various places in this specification do not necessarily refer to the same embodiment. In addition, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0085] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0086] Described below Figures 6 to 15 In, reference has been made Figures 1 to 5 The parts, elements or components described are indicated by the same reference numerals used previously in these figures. The description of these elements has been made and will not be repeated below to avoid burdening this detailed description.

[0087] As described above, various embodiments of the present disclosure relate to solutions for transferring the voltage of cells of a rechargeable battery, such as a high voltage lithium-ion battery, such as a traction battery of an electric vehicle. In this regard, reference may be made to the previous description of a battery management system.

[0088] Figure 6 It shows that Figure 2 , 4 The operation of the processing system 44 is shown in FIG. 5 .

[0089] Specifically, in Figure 6 , the analog-to-digital converter 448 is configured to detect the voltage V at the corresponding cell C. C (i.e., pins CP0..CP n Usually, such analog-to-digital conversion takes time T CONV As described above, in various embodiments, each processing system 44 includes n analog-to-digital converters 448, because this allows the conversion of the cell voltage to be performed in parallel at the same time, and the total conversion time T CONVFor example, in various embodiments, the conversion time of ADC 448 is in the range of 100 us to 2 ms, preferably between 200 and 400 us.

[0090] Once digital processing circuit 444 has acquired a digital sample of the cell voltage, digital processing circuit 444 transmits one or more data packets to digital processing circuit 42 via communication interface 440, for example, by using a digital signal such as Figure 4 Thus, one or more data packets typically include n samples, where each sample has a number of bits N corresponding to the number of bits of ADC 448. ADC The corresponding number of digits N ADC , such as 16 bits. Therefore, each processing system 44 must transmit at least a given number of bits (n×N ADC ).

[0091] For example, the L9963 chip supports a burst mode in which a sequence of n data packets is transmitted. Specifically, each data packet has 40 bits, of which only 16 bits are used to transmit the actual sample, while the other bits contain additional data, such as a device ID that identifies the number of one of the processing systems 44 in the daisy chain. In addition, the transmission may also add additional error detection and / or error correction bits, such as cyclic redundancy check (CRC) bits. For example, typically, the transmission time T for transmitting the values ​​of all cells of a battery is 40 bits. TX In the range between 4 and 8ms.

[0092] Therefore, the transmission of the cell voltages of all processing systems requires a given time T TX , where the transmission time T TX It also depends on the number m of cell groups.

[0093] For example, when using Figure 4 and 5 When the daisy chain is shown, the digital processing circuit 42 can send a command requesting sampling of the cell voltage to the processing system 44 via the communication interface 426, and in response to the command, each processing system 44 can sample the corresponding cell voltage.

[0094] In various embodiments, the processing system 44 may automatically transmit the corresponding data, and / or may wait for the digital processing unit 42 to send a command including a read request.

[0095] For example, in the latter case, the digital processing unit 42 may send a read request to each processing system 44 (e.g., by including an identification of the corresponding processing system 44 in the command), and in response, the corresponding processing system 44 may transmit one or more data packets containing sampled data. Typically, when a daisy chain is used, the read request and sampled data may be transmitted via the intermediate processing system 44, i.e., each processing system 44 may be configured to:

[0096] receiving data via communication interface 440 and retransmitting data via communication interface 442; and

[0097] Data is received via communication interface 442 and data is retransmitted via communication interface 440 .

[0098] In contrast, in the former case, the processing system 44 may automatically generate the sequence of data packets. For example, in this case, the last processing system 44 m One or more data packets including corresponding sample data may be transmitted to the previous processing system 44 via the interface 440 m-1 , the previous processing system 44 m-1 Thus, the data packet is received via the interface 442, the corresponding sample data is appended, and the new data packet is transmitted to the previous processing system 44 via the interface 440. m-2 ,etc.

[0099] Regardless of the specific solution used to transmit the data packets, the total conversion time T CONV and the transmission time T TX Defines the minimum sampling period T between two consecutive conversions / transfers SAMPLE , that is, T SAMPLE >T CONV +T TX .

[0100] Therefore, in these solutions, all n×m digital samples of the cell voltage must be transmitted to the digital processing circuit 42. During this time, the processing system 44 performs no further analog-to-digital conversion.

[0101] However, the inventors have observed that for high-power rechargeable batteries, such as lithium-ion traction batteries for electric vehicles, sampling times T between a few milliseconds and tens of milliseconds SAMPLE may be too high. Specifically, Figure 6 As shown, between two consecutive analog-to-digital conversions, one or more cell voltages may change within a critical range without being detected. In fact, as mentioned above, the minimum sampling time depends mainly on the communication bandwidth and the amount of data, which in turn depends on the number n×m of cells C. On the contrary, the ADC usually has a higher performance, which will allow a better sampling speed.

[0102] Therefore, in the case where interference exceeds the Nyquist criteria, the interference may not be detected even if the ADC 448 can be used with higher performance.

[0103] A fairly straightforward solution to this problem is to divide the communication channel 48 into several parallel communication channels, thereby reducing the number of data to be transmitted on each communication channel. However, this means that the digital processing circuit 42 will also require several communication interfaces 426 and additional pins, and must manage multiple parallel communications.

[0104] on the contrary, Figure 7 An embodiment of the operation of the processing system 44a according to the present disclosure is shown.

[0105] Specifically, in the embodiment considered, the processing system 44a is configured to sample each of the n cell voltages at a sampling period T SAMPLE k analog-to-digital conversions are performed during this period. Figure 7 , the processing system 44a approximately at a time interval T ADC =T SAMPLE / k performs three analog-to-digital conversions, where T ADC >T CONV .

[0106] Next, the processing system 44a is configured to generate one or more data packets including data determined by performing lossless and / or lossy data compression on the k digital samples of the n cell voltages, and transmit the one or more data packets. Figure 7 As shown, in various embodiments, the transmission can be performed while the next analog-to-digital conversion is being performed, and the only limitation is that the transmission time T of the data packet (compressed data including multiple digital samples) is TX Less than sampling time T SAMPLE , and vice versa, the sampling time T SAMPLE Must be greater than the transmission time T TX .

[0107] Figure 8 An embodiment of a processing system 44a is shown. Specifically, in the embodiment under consideration, the processing system 44a has the same Figure 5 The same basic architecture of the processing system 44 described above. Specifically, in this case, the processing system 44a also includes:

[0108] Given number n+1 pins CP0..CP n , for n units C1..C n connection;

[0109] A plurality of (preferably n) analog-to-digital converters 448 are configured to generate two pins CP0..CP connected to the same unit C. n digital samples of the voltage between cells C1..C n a digital sample of the voltage at (or a filtered version thereof);

[0110] An optional multiplexer 446 is used to connect pins CP0..CP n connected to analog-to-digital converter 448;

[0111] Communication interface 440, for transmitting digital data;

[0112] optional additional communication interface 442 in the case where the processing systems 44a may be connected in cascade to form a daisy chain; and

[0113] Digital processing unit 444a.

[0114] Specifically, about Figure 5 , the digital processing unit 444a is configured to implement a data compression unit 450. Generally, the data compression unit 450 may be a dedicated hardware circuit and / or implemented using computer instructions executed via a programmable microprocessor 444a.

[0115] Fig. 9 An embodiment of the operation of the digital processing unit 444a is shown.

[0116] Specifically, after starting step 1000, the digital processing unit 444a proceeds to step 1002, where the digital processing unit 444a waits for a new sampling interval T SAMPLE For example, the digital processing unit 444a may wait for a triggering event at step 1002, such as:

[0117] a trigger signal received from the digital processing unit 42 (possibly via other processing system 44a); or

[0118] The trigger signal generated in the processing system 44a, for example, via a timer circuit (which may also be implemented in the digital processing unit 444a), indicates, for example, the time T SAMPLE It's over.

[0119] For example, in various embodiments, each processing system 44a includes a corresponding timer circuit that can be started (or reset) in response to a synchronization signal received from the digital processing circuit 42. In this case, the time T SAMPLE It can also be programmable.

[0120] Typically, this step is completely optional, since the digital processing unit 444a may also immediately start a new sampling interval TSAMPLE , and the sampling interval T SAMPLE The duration of may be defined by other delays, as will be described, for example, with respect to step 1008 .

[0121] Once a new sampling interval is detected at step 1002 (or generally at the beginning), the digital processing unit 444a proceeds to step 1004, where the digital processing unit 444a acquires a digital sample of the cell voltage via the analog-to-digital converter 448. For example, the digital processing unit 444a may start an analog conversion at step 1004 and wait for the analog-to-digital converter 448 to signal that the corresponding conversion has been completed. In the case where the number of analog-to-digital converters 448 is less than n, the digital processing unit 444a may also set the multiplexer 446 and start a new analog-to-digital conversion.

[0122] Thus, at the end of step 1004, the digital processing unit 444a has acquired a digital sample of the cell voltage for a given sampling instant.

[0123] Then, the digital processing unit 444a proceeds to a verification step 1006. Basically, the digital processing unit 444a verifies in step 1006 whether an additional sampling operation should be performed for the same sampling interval. In fact, as described above, in various embodiments, the data packet to be transmitted is determined based on k samples of each cell voltage, such as three samples. For example, in various embodiments, the digital processing unit 444a can be configured so that the value k is programmable. For example, for this purpose, the value k can be stored in a programmable (volatile or non-volatile) memory, and the digital processing unit 444a can be configured to receive a new value via the communication interface 440 (or 442) and overwrite the stored value k.

[0124] In particular, in the embodiment under consideration, in the case where more samples have to be acquired (output “N” of verification step 1006 ), the digital processing unit 444a proceeds to a waiting step 1008 , in which the digital processing unit 444a waits for the next sampling instant.

[0125] For example, the digital processing unit 444a may wait for the indicated time T in step 1008. ADC Once the digital processing unit 444a detects the next sampling instant, the digital processing unit 444a proceeds to step 1004 again to obtain the next sample of the cell voltage. For example, at different times, each processing system 44a includes a ADC When the time T has passed, a corresponding timer circuit is generated to trigger. For example, such a timer circuit can be started (or reset) in step 1004 or 1008 (based on the time T ADCDoes it refer to the time between two consecutive start instances of A / D conversion or the time between the end of an A / D conversion and the start of the next A / D conversion? In this case, the time T ADC It can also be programmable.

[0126] Typically, the waiting step 1008 is also completely optional, and the time T ADC Can correspond to the conversion time T of A / D conversion CONV For example, in this case, the sampling period T SAMPLE can have (approximately) time k T CONV For example, in various embodiments, ADC 448 may be configured such that the conversion time or “conversion window” T CONV is programmable. For example, the Σ-Δ ADC works in a way that results in the voltage being averaged during the window. This means that the voltage curve is smoothed, but the information itself is not lost.

[0127] Conversely, if a given number k of samples have been acquired (verification step 1006 output "Y"), the digital processing unit 444a proceeds to step 1010, where the digital processing unit 444a generates one or more data packets via lossless and / or lossy data compression operations. Fig.10 As shown, the digital processing circuit 444a is configured to obtain a data set DATA, for example, in the form of a matrix, for each cell voltage, the data set DATA includes a set of corresponding k samples, that is, a sample S of the voltage for the cell C1 (connected between the pins CP0 to CP1). 1,1 ..S 1,k and for unit C n (Connect to pin CP n-1 To CP n The voltage sample S n,1 ..S n,k ; and generating one or more data packets to be transmitted based on the data set DATA.

[0128] Next, the digital processing unit 444a proceeds to step 1012, where the digital processing unit 444a sets a transmission flag indicating that one or more data packets are ready for transmission, and the digital processing unit 444a returns to step 1002 to wait for the next sampling period T SAMPLE The beginning of.

[0129] For example, in various embodiments, in response to the transmission flag, the processing system 44a may:

[0130] Automatically transmit the data packets to the digital processing circuit 42;

[0131] Waiting for a transmission request from the digital processing circuit 42 and transmitting the data packet to the digital processing circuit 42 in response to the transmission request; or

[0132] Waits for one or more data packets to be received via interface 442 (from another processing system 44 ), appends data packets to the received data packets, and transmits new data packets via interface 440 (to subsequent processing system 42 , digital processing circuit 42 , or bridge circuit 46 ).

[0133] For example, the first two options may also apply to the last processing system 44m of the daisy chain.

[0134] As described above, in various embodiments, communication interface 440 (and 442) may operate in parallel with analog-to-digital converter 448. For example, Fig.11 As shown, for this purpose, the digital processing circuit 444a, particularly the encoder circuit 450, can store the encoded data packets to a transmission queue 452, such as a FIFO memory, and the communication interface 440 can automatically read the data from the transmission queue 452 and transmit the data.

[0135] Specifically, in various embodiments, the processing system 44a includes a first queue 452, such as a first FIFO memory, wherein the encoder circuit 450 is configured to store the encoded data packet (indicating n×k samples) to the first queue 452. In addition, the processing system 44a includes a second queue 454, such as a second FIFO memory, wherein the communication interface 442 is configured to store the received data (i.e., the data received from another processing system 44) to the second queue 452. For example, in various embodiments, the first queue 452 has sufficient dimensions to store at least the compressed data (generated according to the n×k samples S), and preferably stores the complete data packet. In contrast, the second queue may also include only a single register.

[0136] Thus, by using multiplexer 456, communication interface 440 may sequentially transmit the stored data to queues 452 and / or 454. For example, when the transmit flag is set and upon receiving data via communication interface 442 (which may be detected because queue 454 contains data), communication interface 440 may:

[0137] first transferring the stored data to queue 454 and then transferring the stored data to queue 452, i.e. appending the encoded data packet to the received data; or

[0138] The stored data is first transferred to queue 452 and then transferred to queue 454, ie the received data is appended to the encoded data packet.

[0139] In various embodiments, as described above, the last processing system 44m may directly transfer the stored data to the queue 452 in response to the transfer flag.

[0140] As described above, in various embodiments, the transfer of stored data to queue 452 may also be initiated in response to a request received from processing unit 42 (rather than using automatic transfer). Thus, in this case, interface 440 may be configured to always transfer stored data to queue 454 (bypass functionality) and to transfer stored data to queue 452 only in response to a read request.

[0141] Possible embodiments of the operation of the data compression unit 450 will be described below. Generally, as described above, the data compression unit 450 is configured to process a data set DATA including k samples for each of the n cell voltages, i.e. ... 1,1 ..S 1,k To S n,1 ..S n,k One or more data packets are generated for transmission. For example, as described above, these data packets (or processed / compressed data) can be stored in queue 452. To describe the operation applied to a given sequence, reference will be made to a generic sample S1..S corresponding to one of the n sequences. k sequence.

[0142] Fig.12 A first embodiment of the operation of the data compression unit 450 is shown ( Fig. 9 , step 1010 in FIG.

[0143] Specifically, after starting step 2000, the data compression unit 450 is configured to compare the value of each sample S with a given upper threshold TH in step 2002. H and the lower threshold TH L Make a comparison.

[0144] Specifically, in this regard, Fig.13 A possible discharge curve of a lithium-ion cell C, such as a lithium-ion cell C based on manganese oxide, is shown. Specifically, Fig.13 The cell voltage V is shown for different C-rates such as 0.05C, 0.1C, 0.5C and 1C. C Curve expressed in percentage relative to the unit charge CH.

[0145] like Fig.13 As shown, in normal operation, the cell voltage is maintained at the upper threshold TH H With the lower threshold TH L between, such as at an upper threshold TH corresponding to a voltage of 4.2VH and the lower threshold TH corresponding to the voltage 3.0V L In general, specific values ​​may vary based on the unit chemistry.

[0146] Therefore, in all samples S 1,1 ..S 1,k To S n,1 ..S n,k The values ​​are all above the upper threshold TH H With the lower threshold TH L In the case of the data compression unit 450, the data compression unit 450 proceeds to step 2004, wherein the data compression unit 450 reduces the sample S 1,1 ..S 1,k To S n,1 ..S n,k Specifically, in various embodiments, the data compression unit 450 subtracts a given constant offset OFF from each sample S, such as a lower threshold TH L , and a given number of most significant bits are removed. In various embodiments, the offset OFF may be programmable, for example, to allow the same processing system 44a to be used with different units having different voltage ranges.

[0147] For example, in L9963, ADC 448 has 16 bits and a resolution of 89uV. For example, for the above voltage range (3.0-4.2V) and resolution (89uV), 12 bits (i.e., 2048) are sufficient to transmit the value of sample S, i.e., once the offset OFF is subtracted, the data compression unit 450 can remove the 4 most significant bits of each sample S. In fact, in order to reconstruct the original value of the sample, it is sufficient for the digital processing circuit 42 to add the value OFF to each transmitted value again. In various embodiments, the number of most significant bits to be removed is programmable.

[0148] In addition, the inventors have observed that, although ADC 448 can indeed support a resolution of 89uV and a fast conversion speed in the range of 300us, this resolution is generally not sufficient for actual measurements, and in practice, the two least significant bits may be meaningless. Therefore, in various embodiments, the data compression unit 450 may also remove a given number of least significant bits in step 2004. In various embodiments, the number of least significant bits to be removed is programmable. For example, the number of least significant bits that may be "useless" may depend on the (fixed or programmed) conversion time T CONV , for example, as the conversion time increases, the lower least significant bits should be removed. Therefore, in various embodiments, the conversion time T CONV The data compression unit 450 may be programmable and may be configured to be used according to the conversion time T for the ADCCONV The data to be programmed determines the number of least significant bits to be removed. However, in various embodiments, the number of least significant bits to be removed can also be independently programmed.

[0149] Thus, essentially, step 2004 reduces the number of bits of the sample S of the data structure DATA to, for example, 10 bits, without affecting (significantly) the original precision of the sampled data. For example, in the case where the processed sample S has 10 bits, for each of the n cell voltages, the data packet will include a total of k×10 bits.

[0150] On the contrary, if samples S1..S k To S n,1 ..S n,k At least one of the values ​​is greater than the upper threshold TH H Or less than the lower threshold TH L , the data compression unit 450 proceeds to step 2006. Specifically, this situation usually only occurs in the case of a fault. Usually, in this case, it is impossible to transmit samples with a reduced dynamic range.

[0151] In the first embodiment, the data compression unit 450 is configured to set the threshold value TH L With TH H The values ​​between are replaced with the reduced length bit sequences described with respect to step 2004. Conversely, the data compression unit 450 may store values ​​exceeding the thresholds and replace these values ​​with default values, e.g., a bit sequence of "0" for samples less than the lower threshold and a bit sequence of "1" for samples greater than the upper threshold. Thus, the digital processing unit 42 may easily determine that a given value is out of range and may possibly request transmission of the corresponding (stored) original value.

[0152] In contrast, in other embodiments, the data compression unit 450 may switch to a different data packet format. For example, such a different data packet format may be indicated by using a data packet that also includes a header, which may include a field for storing a value indicating the data packet format. Alternatively, the data packet may begin with a predetermined bit sequence that is not normally possible when using the operations indicated at step 2004, such as a bit sequence of a predetermined length with all values ​​set to "0" or "1".

[0153] For example, in this case, the data packet may include:

[0154] For each cell voltage selected among the k samples S of each cell voltage, there is only one value (with full resolution), such as one sample among the samples exceeding the upper threshold TH H In case the maximum value or one of the samples exceeds the lower threshold THH or

[0155] For each cell voltage, all k values ​​(full resolution), since in case of a fault it may not be necessary to keep the same sampling frequency.

[0156] For example, it is often sufficient to transmit a default value or a single value, since this situation already indicates the presence of a fault. In fact, it is often only necessary to transmit multiple values ​​of each cell voltage to determine rapid changes during normal operation of the battery.

[0157] In both cases (steps 2004 and 2006 ), the data compression unit proceeds to stop step 2008 .

[0158] Fig.14 A second embodiment is shown, which can also be used with respect to Fig.12 and 13 The described embodiments are combined.

[0159] Specifically, Fig.14 The embodiment shown can be used for a case where k samples S1..S must be transmitted for the same cell voltage. k (with full resolution or reduced resolution) and may therefore also be used after steps 2004 and / or 2006 described above.

[0160] Specifically, Fig.15 As shown, in the embodiment considered, the data compression unit 450 is configured to perform an incremental encoding operation. Specifically, in this case, each sequence S1..S k One sample of is kept as a reference value, for example, each sequence S1..S k The first sample S1 (such as Fig.14 as shown) or the last sample S k , and the other samples are used to calculate (k-1) incremental values ​​D1..D k-1 , that is, the increment value D of all n units 1,1 ..D 1,k-1 To D n,1 ..D n,k-1 .

[0161] Specifically, each increment value D i (where i = 1..(k-1)) can be determined by calculating the difference between the value of the corresponding sample and the reference value, for example, D i =S i+1 -S1, or each increment value D i It can be determined by calculating the difference between the value of the corresponding sample and the value of the previous sample, for example, D i =S i+1-S i .

[0162] Therefore, the incremental values ​​D1..D k-1 Reflects the sample sequence S1..S k The absolute change (relative to a reference value) or relative change (relative to a previous value) of a value.

[0163] In general, the battery 30 can be in a charging state or a discharging state, and the inventors have observed that the maximum change in the cell voltage depends on the state. For example, the inventors have observed that in the charging state, when the cell voltage is increased with a period T of less than 10 ms, the cell voltage is increased with a period T of less than 10 ms. ADC When taking samples, the cell voltage usually varies only in the mV range. In this case, the incremental value can be encoded with a bit sequence having 4 to 6 bits, for example.

[0164] Similar to About Fig.12 With the described operation, the difference between two samples may also be outside the possible range, for example, -7 to 7 (for 4 bits) or 31 to 31 (for 6 bits).

[0165] Therefore, after starting step 2020, the data compression unit 450 can verify (similar to step 2002) whether all the increment values ​​D are within the maximum threshold TH H Or minimum threshold TH L between.

[0166] For example, if all increment values ​​D are within the maximum value TH H With minimum TH L Between (verifying the output "Y" of step 2022), the data compression unit 450 can encode the delta value with reduced bit resolution in step 2024 (similar to step 2004), for example, by using two's complement binary encoding.

[0167] On the contrary, if the increment value is greater than the maximum value TH H Or less than the minimum value TH L (verify the output "N" of step 2022), the data compression unit 450 can proceed to step 2026 (similar to step 2006).

[0168] Typically, step 2026 is used to signal that one or more incremental values ​​are outside the allowed range. For example, as described with respect to step 2006, in this case, the data compression unit 450 can store the corresponding incremental values ​​and replace the incremental values ​​outside the range with a default value, such as the maximum value TH H (e.g. +7) or minimum TH L(e.g., 7) corresponding bit sequence value (similar to step 2006). Alternatively, the data compression unit 450 can switch to a different data packet format and insert in the data packet:

[0169] For each cell voltage selected in the sample S of each cell voltage, there is only one value (with full resolution), such as a maximum or minimum value; or

[0170] For each cell voltage, all k samples (full resolution).

[0171] Likewise, in this case (for both steps 2024 and 2026 ), the data compression unit 450 proceeds to stop step 2028 .

[0172] Therefore, when combined with the dynamic range solution ( Fig.12 ) and incremental value solution ( Fig.14 ), the data compression unit 450 generates a data packet, which, for each unit, includes a first absolute value, for example, with 10 bits, and then (k-1) incremental values, for example, with 4 bits. For example, in the case of k=3, it is sufficient to transmit 18 bits, which is close to the 16 bits used in the conventional L9963 chip.

[0173] For example, in various embodiments, processing system 44a may support (at least) two data packet formats having the same number of bits, such as 40 bits:

[0174] The first format, in which each cell voltage is only ADC , for example 16 bits) to transmit a single measured value (essentially corresponding to the solution currently employed in the L9963 circuit); and

[0175] The second format, in which compressed data is transmitted.

[0176] In this case, the processing system 42 may be configured to send a command to the data processing system 44a indicating which format should be used, which format may be a common format for all processing systems 44a, or the processing system 42 may send a command indicating the corresponding format to each processing system 44a. In various embodiments, the command may also include data indicating which compression format (e.g., dynamic range reduction and / or delta encoding) should be used, and possible corresponding parameters (offset, number or MSBs and / or LSBs to be removed, number of bits for delta encoding, etc.).

[0177] Therefore, in various embodiments, the data compression unit 450 can be configured to generate data packets according to the corresponding configuration. As described above, when one or more values ​​are out of range (out of the dynamic range or the incremental encoding range), the data compression unit 450 can insert data identifying this fact into the data packet. For example, the data compression unit 450 can set a flag or insert a given predetermined value in the data packet. For example, as described above, the data packet may include 16 bits for transmitting measurement data. In order to insert the compressed data into these 16 bits, the data compression unit 450 can periodically insert an incrementally encoded reference value (e.g., having 10 bits after dynamic range reduction) into the data packet (associated with a given sampling interval), and then transmit only the incrementally encoded value (preferably with the previous dynamic range reduction) for a given number of data packets (associated with subsequent sampling intervals). For example, as described above, when using incrementally encoded values ​​(relative to a reference value or relative to a previous value), each value can have 4 bits. Therefore, three samples will require 12 bits, which also allows the remaining (16-12) = 4 bits to be used for one or more flags to indicate whether one or more values ​​are out of range. For example, a corresponding bit of the 4 remaining bits may be associated with each delta-encoded value.

[0178] Thus, in the event that processing system 42 determines that one or more values ​​are out of range, processing system 42 may request retransmission of the corresponding absolute values ​​by using the first data packet format.

[0179] The inventors have observed that the described incremental encoding scheme (possibly in combination with dynamic range compression) is particularly useful when the battery 30 is being charged, since typically only a low dynamic range can be expected. Specifically, it can be assumed that during charging, the cell voltage will vary within a limited range, and that the voltage is primarily a function of the battery capacity (which may vary over the lifetime and during aging), the battery charge level, and the current charging the cell. However, jumps in voltage levels typically do not occur. For example, consider the previous ADC example with a resolution of 0.089mV, with dynamic range reduction and incremental encoding, where two LSBs are removed, 4 bits are used to transmit the incremental value, and an incremental range of 2^6*0.089mV=5.6mV (e.g., + / -2.8mV) is used. As described above, the range can apply to the difference relative to a reference value or only to the difference between two consecutive samples.

[0180] As mentioned above, this does not necessarily apply when the battery is discharged, for example when the vehicle is being driven or other highly dynamic load changes are similar. However, the inventors have observed that in this case, the voltages of the n cells generally have similar variability. In fact, the voltage drop may not only be observed in the individual cell, but also in the other cells connected in series, since they all have to provide the same current (see Fig.13 Therefore, a larger range is required, but the changes in cell voltage of the individual cells are correlated.

[0181] For example, in this case, instead of using a linear incremental value, the incremental value can be encoded as an exponent and a mantissa. For example, in this case, only a limited number of exponents are used for all incremental values. Therefore, by associating possible exponent value bit sequences with having a reduced number of bits, these exponents can be abbreviated (similar to Huffman coding), and the data compression unit can insert the coded exponent value and mantissa with a given number of bits into the data packet. For example, consider the previous example, in which 16 bits are used to transmit coded data, and for each of 3 samples, the data packet can include 2 bits for the mantissa and 3 bits for the coded exponent. The remaining bits can be used to indicate whether one or more values ​​are out of range. In this case, one or more additional data packets can also store data indicating the mapping between the coded exponent value and the decoded exponent value.

[0182] Alternatively, a given cell j of a given set of n cells may represent a reference cell, such as the first (j=1) or last cell (j=n). In this case, the data compression unit 450 may be configured to transmit the absolute value or delta value of the reference cell at a higher resolution (possibly with a previous dynamic range reduction). For example, the data compression unit may transmit a value S encoded with 10 bits. j,1 , and then transmit the 8-bit incremental encoding value D j,1 To D j,k-1 Instead, samples from other units are transmitted via:

[0183] For each other cell i, calculate the first sample S of the corresponding cell i,1 The first sample S relative to the reference cell j,1 The offset O i , where the offset O i represents the offset of the voltage of cell i relative to the voltage of cell j:

[0184] O i =S i,1 -S j,1 ;

[0185] The increment value D of the other samples of the corresponding unit is calculated according to the following equation i,h , where h = 1..(k-1):

[0186] D i,h =S i,h+1 -S j,h+1 -O i .

[0187] Thus, once the samples of reference cell j have been reconstructed, processing system 42 may calculate the other samples via the following equations:

[0188] S i,1 =S j,1 +O i ;

[0189] S i,h+1 =S j,h+1 +O i +D i,h .

[0190] Therefore, in this case, the processing system 42 may periodically transmit the offset value with a higher bit number (e.g., 8 bits), but the increment value D i,j Again it should have limited range and can be transmitted with a lower number of bits (eg 4 bits).

[0191] Thus, in the considered embodiment, basically, the samples of the reference cell j represent a reference shape / curve of the behavior of the cell voltage, and the offset O i The expected waveform of the voltage shape for a given cell i is determined, and the delta value is used to provide information on the displacement of the actual value of a given sample from the expected value. Thus, instead of using the samples of a predetermined cell as reference sample, a new reference sample can also be calculated, for example by calculating the average of the samples at a given moment, or by dynamically selecting the cell with the smallest value as reference cell, for example, allowing only positive encoding offset values ​​to be used, thereby allowing an improved value range.

[0192] In various embodiments, more complex compression algorithms can also be used, which take into account that the voltage variation of a given cell is not only related to the values ​​of neighboring samples of the same cell (row), but also to the voltage variations of neighboring cells (columns). For example, a similar situation exists in conventional image compression algorithms, where the compression algorithm uses the fact that the value of a given pixel (essentially corresponding to one of the samples) is usually associated with the values ​​of the surrounding pixels. For example, also in the present case, the amount of data can be reduced by applying a 2D discrete Fourier transform to the data DATA.

[0193] Generally, the data compression unit 450 may also support a variety of previously described data compression methods, that is, the data compression unit 450 may include one or more circuits configured to perform one or more of the following operations:

[0194] Dynamic range reduction, which can also be used in conjunction with other compression methods;

[0195] Simple incremental encoding relative to a reference value of samples of the same unit;

[0196] complex delta encoding relative to a reference curve including, for example, a reference sample of a reference cell;

[0197] Delta encoding using mantissa and coded exponent; and

[0198] Two-dimensional discrete Fourier transform.

[0199] Therefore, in various embodiments, the processing unit 42 or the processing system 44 can determine whether the battery is in a charging state or a discharging state, for example by receiving corresponding information from the ECU for the vehicle, and select a first data compression format (e.g., simple incremental encoding) in the charging state and a second data compression format in the discharging state.

[0200] Thus, the embodiments described herein allow monitoring of cell voltages even while data communication is ongoing. Furthermore, due to the proposed data compression, sampling can be performed at a higher frequency. This allows, for example, the implementation of new battery models and new methods of calculating battery parameters that do not rely on snapshot measurements but on a time series of multiple signals.

[0201] Of course, without prejudice to the principle of the invention, the details of construction and of the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined in the appended claims.

Claims

1. A processing system configured to monitor a cell voltage of a rechargeable battery, the rechargeable battery comprising a first given number of cell groups, each cell group comprising a second given number of cells, wherein the processing system comprises: a terminal configured to be connected to the cell so as to receive a given number of the cell voltages; at least one analog-to-digital converter configured to generate a given number of digital samples of said cell voltage, each digital sample having a given number of bits; Transmission queue; A digital processing circuit, comprising a data compression module, wherein the digital processing circuit is configured to perform the following steps multiple times: synchronously acquiring a given number of digital samples of the digital samples of each of a given number of the cell voltages; storing the acquired digital samples in a memory; receiving a given offset via a serial communication interface; encoding a given number of the digital samples of the given number of the cell voltages stored in the memory using a dynamic range reduction operation by the data compression module to generate encoded data, the dynamic range reduction operation comprising: subtracting the given offset from each digital sample of a given number of the digital samples of a given number of the cell voltages, thereby generating a value indicative of a dynamic change of each sample relative to the offset, and removing a given number of most significant bits from each of said values ​​indicating said dynamic change of each sample relative to said offset; and storing the encoded data in the transmission queue; and The serial communication interface is configured to sequentially transmit the encoded data stored in the transmission queue when the digital processing circuit acquires a new digital sample. 2 . The processing system of claim 1 , wherein the digital processing circuit is configured to receive a given number of the most significant bits via the serial communication interface.

3. The processing system of claim 1 , wherein the data compression module is configured to generate the encoded data by: removing a given number of least significant bits from each of said values ​​indicating said dynamic change of each sample relative to said offset; Wherein the digital processing circuit is configured to receive a given number of the least significant bits via the serial communication interface.

4. The processing system of claim 1 , wherein the data compression module is configured to: determining whether each of a given number of said digital samples of a given number of said cell voltages is between a minimum threshold and a maximum threshold, If one or more digital samples are not between the minimum threshold and the maximum threshold, then: storing values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold, storing, to the encoded data, further data identifying that one or more of the digital samples are not between the minimum threshold and the maximum threshold, receiving a retransmission request via the serial communication interface, and In response to the retransmission request, at least one of the values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold is transmitted via the serial communication interface.

5. The processing system of claim 1 , wherein the data compression module is configured to support multiple encoding modes, wherein the data compression module is configured to generate the encoded data according to a selected encoding mode, and wherein the digital processing circuit is configured to receive the selected encoding mode via the serial communication interface.

6. The processing system of claim 5, wherein in addition to the dynamic range reduction operation, the encoding mode further comprises at least one of the following: a delta encoding mode, wherein the data compression module is configured to generate delta encoded values ​​of the digital samples relative to one or more reference values; or A 2D discrete Fourier transform mode, wherein the data compression module is configured to apply the 2D discrete Fourier transform mode to a given number of the digital samples of a given number of the cell voltages.

7. The processing system of claim 6, wherein the data compression module is configured to generate the incremental encoded value for a given cell voltage by at least one of: selecting a first digital sample of a given number of the digital samples of the given cell voltage as a reference value, and generating the incremental encoded value by calculating a difference of each subsequent digital sample of the given cell voltage relative to the reference value; or selecting a first digital sample of a given number of the digital samples of the given cell voltage as a reference value and generating the incremental encoded value by calculating a difference between a subsequent digital sample of the given cell voltage and a previous digital sample of the given cell voltage; or A value of a reference curve is determined from the digital samples, and the delta encoded value is generated by calculating the difference between each digital sample of the given cell voltage relative to the value of the reference curve.

8. The processing system of claim 6, wherein the data compression module is configured to receive data identifying a value format and generate the delta-encoded value from the data identifying the value format by: encoding the delta-encoded value using a linear value encoding, or The delta-encoded value is encoded using a mantissa and an exponent.

9. The processing system of claim 1, wherein the processing system comprises: Additional transmission queues; a further serial communication interface configured to sequentially receive further data and store the further data in the further transmission queue; as well as A multiplexer is configured to connect the serial communication interface to the transmission queue or the further transmission queue, so that the serial communication interface is configured to sequentially transmit the encoded data stored in the transmission queue or the further data stored in the further transmission queue.

10. A battery monitoring system comprising: two terminals configured to be connected to a rechargeable battery; a plurality of processing systems, each of the processing systems being configured to monitor a cell voltage of the rechargeable battery, the rechargeable battery comprising a first given number of cell groups, each cell group comprising a second given number of cells, wherein each of the processing systems comprises: a further terminal configured to be connected to the cell so as to receive a given number of the cell voltages; at least one analog-to-digital converter configured to generate a given number of digital samples of said cell voltage, each digital sample having a given number of bits; Transmission queue; A digital processing circuit, comprising a data compression module, wherein the digital processing circuit is configured to perform the following steps multiple times: synchronously acquiring a given number of digital samples of the digital samples of each of a given number of the cell voltages; storing the acquired digital samples in a memory; receiving a given offset via a serial communication interface; encoding a given number of the digital samples of the given number of the cell voltages stored in the memory using a dynamic range reduction operation by the data compression module to generate encoded data, the dynamic range reduction operation comprising: subtracting the given offset from each of the given number of the digital samples of the given number of the cell voltages to generate a value indicative of a dynamic change of each sample relative to the offset, and removing a given number of most significant bits from each of the values ​​indicative of the dynamic change of each sample relative to the offset; and storing the encoded data in the transmission queue; and The serial communication interface is configured to sequentially transmit the encoded data stored in the transmission queue when the digital processing circuit acquires a new digital sample; and Another processing system is configured to receive the encoded data from the plurality of processing systems. 11 . The battery monitoring system of claim 10 , wherein the digital processing circuit is configured to receive a given number of the most significant bits via the serial communication interface.

12. The battery monitoring system according to claim 10, wherein the data compression module is configured to generate the encoded data in the following manner: removing a given number of least significant bits from each of said values ​​indicating said dynamic change of each sample relative to said offset; Wherein the digital processing circuit is configured to receive a given number of the least significant bits via the serial communication interface.

13. The battery monitoring system according to claim 10, wherein the data compression module is configured to: determining whether each of a given number of said digital samples of a given number of said cell voltages is between a minimum threshold and a maximum threshold, If one or more digital samples are not between the minimum threshold and the maximum threshold, then: storing values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold, storing, to the encoded data, further data identifying that one or more of the digital samples are not between the minimum threshold and the maximum threshold, receiving a retransmission request via the serial communication interface, and In response to the retransmission request, at least one of the values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold is transmitted via the serial communication interface.

14. The battery monitoring system of claim 10, wherein the data compression module is configured to support a plurality of encoding modes, wherein the data compression module is configured to generate the encoded data according to a selected encoding mode, and wherein the digital processing circuit is configured to receive the selected encoding mode via the serial communication interface.

15. The battery monitoring system of claim 14, wherein in addition to the dynamic range reduction operation, the encoding mode further comprises at least one of the following: a delta encoding mode, wherein the data compression module is configured to generate delta encoded values ​​of the digital samples relative to one or more reference values; or A 2D discrete Fourier transform mode, wherein the data compression module is configured to apply the 2D discrete Fourier transform mode to a given number of the digital samples of a given number of the cell voltages.

16. The battery monitoring system of claim 15, wherein the data compression module is configured to generate the incremental encoded value for a given cell voltage by at least one of: selecting a first digital sample of a given number of the digital samples of the given cell voltage as a reference value, and generating the incremental encoded value by calculating a difference of each subsequent digital sample of the given cell voltage relative to the reference value; or selecting a first digital sample of a given number of the digital samples of the given cell voltage as a reference value and generating the incremental encoded value by calculating a difference between a subsequent digital sample of the given cell voltage and a previous digital sample of the given cell voltage; or A value of a reference curve is determined from the digital samples, and the delta encoded value is generated by calculating the difference between each digital sample of the given cell voltage relative to the value of the reference curve.

17. The battery monitoring system of claim 15, wherein the data compression module is configured to receive data identifying a value format and generate the incremental encoded value from the data identifying the value format by: encoding the delta-encoded value using a linear value encoding, or The delta-encoded value is encoded using a mantissa and an exponent.

18. The battery monitoring system of claim 10, wherein each of the processing systems comprises: Additional transmission queues; a further serial communication interface configured to sequentially receive further data and store the further data in the further transmission queue; as well as A multiplexer is configured to connect the serial communication interface to the transmission queue or the further transmission queue, so that the serial communication interface is configured to sequentially transmit the encoded data stored in the transmission queue or the further data stored in the further transmission queue.

19. An electric vehicle comprising: Rechargeable batteries; as well as Battery monitoring system, including: two terminals connected to the rechargeable battery; a plurality of processing systems, each of the processing systems being configured to monitor a cell voltage of the rechargeable battery, the rechargeable battery comprising a first given number of cell groups, each cell group comprising a second given number of cells, wherein each of the processing systems comprises: a further terminal configured to be connected to the cell so as to receive a given number of the cell voltages; at least one analog-to-digital converter configured to generate a given number of digital samples of said cell voltage, each digital sample having a given number of bits; Transmission queue; A digital processing circuit, comprising a data compression module, wherein the digital processing circuit is configured to perform the following steps multiple times: synchronously acquiring a given number of digital samples of the digital samples of each of a given number of the cell voltages; storing the acquired digital samples in a memory; receiving a given offset via a serial communication interface; encoding a given number of the digital samples of the given number of the cell voltages stored in the memory using a dynamic range reduction operation by the data compression module to generate encoded data, the dynamic range reduction operation comprising: subtracting the given offset from each of the given number of the digital samples of the given number of the cell voltages to generate a value indicative of a dynamic change of each sample relative to the offset, and removing a given number of most significant bits from each of the values ​​indicative of the dynamic change of each sample relative to the offset; and storing the encoded data in the transmission queue; and The serial communication interface is configured to sequentially transmit the encoded data stored in the transmission queue when the digital processing circuit acquires a new digital sample; and Another processing system is configured to receive the encoded data from the plurality of processing systems.

20. The electric vehicle of claim 19, wherein the digital processing circuit is configured to receive a given number of the most significant bits via the serial communication interface.

21. The electric vehicle of claim 19, wherein the data compression module is configured to generate the encoded data by: removing a given number of least significant bits from each of said values ​​indicating said dynamic change of each sample relative to said offset; Wherein the digital processing circuit is configured to receive a given number of the least significant bits via the serial communication interface.

22. The electric vehicle of claim 19, wherein the data compression module is configured to: determining whether each of a given number of said digital samples of a given number of said cell voltages is between a minimum threshold and a maximum threshold, If one or more digital samples are not between the minimum threshold and the maximum threshold, then: storing values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold, storing, to the encoded data, further data identifying that one or more of the digital samples are not between the minimum threshold and the maximum threshold, receiving a retransmission request via the serial communication interface, and In response to the retransmission request, at least one of the values ​​of the one or more of the digital samples that are not between the minimum threshold and the maximum threshold is transmitted via the serial communication interface.

23. The electric vehicle of claim 19, wherein the data compression module is configured to support a plurality of encoding modes, wherein the data compression module is configured to generate the encoded data according to a selected encoding mode, and wherein the digital processing circuit is configured to receive the selected encoding mode via the serial communication interface.

Images