Parallel Acquisition, Processing and Storage Method for Aeronautical Radar Countermeasure Reconnaissance Signals

Abstract

Parallel acquisition, processing and storage method for airborne radar countermeasure reconnaissance signals, the steps are as follows: The broadband signal received by the antenna is amplified by a low-noise amplifier; The broadband signal with a total bandwidth of 16 GHz received is divided into 4 segments, each segment having a bandwidth of 4 GHz, and the 4 segments of signals are all transformed into the range of 2-6 GHz; Then the 4 segments of 2-6 GHz signals are divided into 16 segments, each segment having a bandwidth of 1 GHz, and the 16 segments of signals are all transformed into the range of 2-3 GHz; 10 channels of 2-3 GHz signals are selected through a 16-to-10 radio frequency matrix switch, and after fixed frequency conversion, they are sent to the signal processing unit as baseband signals; The signal processing unit compresses the received 10 GHz bandwidth data and then stores it in the data storage unit in parallel. The present invention can perform parallel acquisition and storage of airborne radar countermeasure reconnaissance signals, has an instantaneous frequency coverage range of 10 GHz, and meets the requirements of high-speed real-time acquisition.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic reconnaissance in electronic countermeasures, and relates to the improvement of radar signal data compression and storage performance. Specifically, it is a parallel acquisition, processing and storage method for airborne radar countermeasure reconnaissance signals. Background Art

[0002] The signal environment faced by airborne radar countermeasure reconnaissance covers a wide frequency range. The instantaneous acquisition bandwidth and data rate are 10-100 times that of the radar, and the typical working bandwidth reaches more than 16 GHz. To collect and store all radar signals within such a wide bandwidth with high fidelity. First of all, extremely high requirements are put forward for the sampling frequency, and the corresponding sampling rate is required to reach more than 30 GHz. At present, a single sampling chip far fails to meet such a high sampling frequency. Secondly, the high sampling rate brings the problems of high-speed large-capacity data transmission and storage at the same time. In the current complex radar signal environment, due to the need for high-speed sampling and long-time signal storage, the recorded radar signal data is often very large. Taking 4 hours of storage time as an example, if no compression processing is done, the amount of data to be stored will be as high as dozens of TByte.

[0003] Most traditional compression algorithms are based on linear coding compression algorithms. By analyzing the data, the redundant data is encoded in the form of a linear code group to remove the redundancy of the data and achieve the purpose of data compression. For example, each bit of the radar signal sampled by ADC does not always change in adjacent cycles. There may be several bits of data that are the same in several adjacent sampling cycles, or the collected data may have several regular situations (such as all 0s, all 1s, 01 alternation, etc.), or there may be a phenomenon that some bits repeat according to a certain period. Traditional linear compression methods have the advantages of simple algorithm and fast compression speed, and are easy to be implemented in engineering, but the compression ratio is relatively low. At the same time, the error tolerance rate is very low. Once several important components are lost during the transmission process, the restored data will have a large error.

[0004] The emerging compressive sensing signal processing algorithm (CS algorithm) utilizes the sparse characteristics of the signal and can save a large amount of redundant data in high-speed acquisition. The signal passes through a sparse matrix to obtain the sparse representation of the signal, and the low-dimensional projection observation value of the signal is obtained through an observation matrix, which can effectively relieve the pressure brought by high frequency and high bandwidth and reduce the storage and transmission costs. However, in the initial stage of compression based on the compressive sensing signal processing algorithm (abbreviated as CS algorithm), it is necessary to find the corresponding sparse representation basis in a certain transform domain according to the signal, which leads to a long operation time in the initial stage of compression and the compression ratio cannot reach the ideal state.

[0005] Existing wideband signal acquisition and storage devices are found in single ultra-wideband radars and are used for the acquisition, signal processing, and storage of radar echoes. The current achievable instantaneous bandwidth is about 1 GHz, the sampling accuracy is 8 bits, and the sampling rate is 2 - 5 Gsps. Common implementation schemes mainly adopt the time-domain segmentation-interleaved sampling method based on multi-channel or multi-chip AD, and use multiple chips of AD together to complete the acquisition task in a delayed manner. There is also multi-channel sampling based on frequency-band segmentation, and multiple chips of AD are used to complete data acquisition by means of mixing. The above two acquisition methods both belong to multi-channel data acquisition and use multiple chips of AD to achieve high-rate data acquisition.

[0006] The wideband signal acquisition and storage device used in ultra-wideband radars is mainly used for the acquisition of the signals of a single radar itself and is difficult to adapt to the signal environment of radar countermeasure reconnaissance. First, it does not have the ability to receive signals from multiple radars with complex and no prior information, and its RF front-end cannot meet the requirements of wide-open reception. Second, the sampling rate and instantaneous bandwidth are one order of magnitude lower than the instantaneous bandwidth required for radar countermeasure reconnaissance. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for parallel acquisition, processing, and storage of airborne radar countermeasure reconnaissance signals, which is used to solve the problem that the existing airborne radar countermeasure reconnaissance signals cannot be effectively acquired and stored due to their large working bandwidth and huge data volume.

[0008] To achieve the purpose of the present invention, the following technical solutions are adopted:

[0009] The method for parallel acquisition, processing, and storage of airborne radar countermeasure reconnaissance signals is as follows:

[0010] S1. The wideband signal received by the antenna is amplified by a low-noise amplifier to increase the signal level.

[0011] S2. Through filtering and mixing processing, the wideband signal with a total bandwidth of 16 GHz received is divided into 4 segments, each with a bandwidth of 4 GHz, and all these 4 segments of signals are transformed into the range of 2 - 6 GHz.

[0012] S3. Through filtering and mixing processing again, the 4 segments of 2 - 6 GHz signals are divided into 16 segments, each with a bandwidth of 1 GHz, and all these 16 segments of signals are transformed into the range of 2 - 3 GHz.

[0013] S4. Select 10 channels of 2 - 3 GHz signals through a 16-to-10 RF matrix switch, and then after fixed frequency conversion, they are changed into baseband signals and sent to the signal processing unit to parallelly cover a 10 GHz signal bandwidth.

[0014] S5. The signal processing unit compresses the received data with a 10GHz bandwidth, and then stores it in the data storage unit in parallel, realizing the real-time acquisition and storage of wide-open airborne radar countermeasure reconnaissance signals.

[0015] To further achieve the object of the present invention, the following technical solutions may also be adopted:

[0016] For the above-mentioned method for parallel acquisition, processing and storage of airborne radar countermeasure reconnaissance signals, the signal processing unit includes 5 sets of signal processing modules. Each set of signal processing modules is composed of a high-speed A / D converter and a programmable logic device FPGA. The high-speed A / D converter is used to complete the data reception and signal acquisition of the 10GHz bandwidth data, and the programmable logic device FPGA is used to complete the data compression after signal acquisition and transmit it to the data storage unit through the VPX bus.

[0017] For the above-mentioned method for parallel acquisition, processing and storage of airborne radar countermeasure reconnaissance signals, the data compression includes data compression preprocessing and secondary compression coding based on a compressive sensing signal processing algorithm.

[0018] For the above-mentioned method for parallel acquisition, processing and storage of airborne radar countermeasure reconnaissance signals, the data compression preprocessing includes the following steps:

[0019] A1. The preprocessing FPGA automatically executes a system reset operation after power-on. After the system reset is completed, it receives the data quantized by the high-speed A / D converter;

[0020] A2. Then, data noise reduction processing, preliminary amplitude and phase compensation preprocessing are performed. The preprocessed data is sent to the digital processing module and then through the signal analog processing module, and the output signal amplitude is sent to the detection module and the pulse stream statistics module; the detection module determines the presence or absence of the signal, and the pulse stream statistics module calculates the pulse width and the duration of the signal and counts the flow rate of the corresponding pulses;

[0021] A3. The formed result is sent to the information coding module for parallel output for use by the data storage unit. At the same time, the preprocessing FPGA orthogonalizes the signal in the transform domain according to the subsequent compressed and optimized characteristic parameters and outputs the digital orthogonal signal to the compression coding FPGA for secondary compression coding.

[0022] For the above-mentioned method for parallel acquisition, processing and storage of airborne radar countermeasure reconnaissance signals, the secondary compression coding includes the following steps:

[0023] B1. The compression coding FPGA receives the pulse information from the preprocessing FPGA, realizes the duty cycle compression in the time domain, and at the same time performs linear coding compression and secondary compression based on the transform domain on the received data;

[0024] B2. When just starting up, the compression-encoding FPGA adopts linear encoding compression and time-domain duty cycle compression; when the main control board forms the corresponding sparse expression in the transform domain after working for a period of time, it then adopts the combined compression method of time-domain duty cycle compression, linear encoding compression, and quadratic compression based on the transform domain for compression;

[0025] B3. The compression-encoding FPGA simultaneously feeds back and transmits the existing compression efficiency and compression parameter information to the sparse calculation FPGA of the main control board to update the corresponding sparse expression in the transform domain.

[0026] For the parallel acquisition, processing, and storage method of airborne radar countermeasure reconnaissance signals as described above, the data storage unit includes 11 storage single boards with storage chips mounted on both the front and back. Each storage single board is provided with 64 Flash storage chips, and every 8 chips are grouped for parallel data reading and writing.

[0027] For the parallel acquisition, processing, and storage method of airborne radar countermeasure reconnaissance signals as described above, 10 storage single boards are used to record the radar data received at high speed, and the other 1 storage single board is used to record the inertial navigation data of the aircraft.

[0028] For the parallel acquisition, processing, and storage method of airborne radar countermeasure reconnaissance signals as described above, the signal processing unit and the data storage unit communicate with the main control logic unit through the VPX bus; the signal processing unit transmits the collected digital signals to the main control logic unit through the VPX bus, and the main control logic unit re-compresses and processes the data and then transmits it to the data storage unit through the VPX bus to control the reading and writing of the memory.

[0029] For the parallel acquisition, processing, and storage method of airborne radar countermeasure reconnaissance signals as described above, the number of bits n of the high-speed A / D converter is 12 bits.

[0030] Compared with the prior art, the advantages of the present invention are as follows:

[0031] 1. The present invention can parallelly acquire and store airborne radar countermeasure reconnaissance signals, has an instantaneous frequency coverage range of 10 GHz, and meets the requirements of high-speed real-time acquisition.

[0032] 2. Utilizing the source synchronous transmission protocol based on the VPX bus to meet the requirements of high-speed large-capacity data caching and transmission. The broadband signal acquisition can intercept different types of radar signals, can adapt to dense signal environments and complex electronic environments, has a high intercept probability, high sensitivity, high frequency measurement accuracy, and the ability to acquire signals arriving simultaneously, and can adaptively or manually switch the working mode according to the characteristics of the actual external radar environment.

[0033] 3. The compression processing of the data in the present invention utilizes the time-domain duty cycle compression, linear coding compression, and quadratic compression mechanism based on the transform domain, which not only ensures the real-time performance of compression but also meets the requirements of high compression ratio. The sparse matrix compression and decompression method based on the eigenbasis realizes the high compression of broadband radar countermeasure reconnaissance signals; it realizes the real-time compression and storage of airborne radar countermeasure reconnaissance signals, greatly reducing the demand for data storage units, which can reduce the volume and weight of the equipment and meet the low-load requirements in the airborne environment.

[0034] 4. The data compression processing ability of the present invention is independent of the bandwidth of the signal. As long as the signal itself has a low sparsity, the signal can be compressed at a certain compression ratio. This compression technology has great significance in the field of broadband radar signals. In addition, compression reconstruction itself is also a denoising process, and compressing signals using the principle of compressive sensing has a certain degree of anti-noise ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art.

[0036] Figure 1 is the flow block diagram of the present invention;

[0037] Figure 2 is Figure 1 the system block diagram of the local oscillator unit described in

[0038] Figure 3 is Figure 1 the system block diagram of the data storage unit described in

[0039] Figure 4 is Figure 1 the data compression preprocessing system block diagram of the signal processing unit described in

[0040] Figure 5 is Figure 1 the quadratic compression coding system block diagram of the signal processing unit described in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0042] As Figures 1-5 shown, this embodiment discloses a method for parallel acquisition, processing, and storage of airborne radar countermeasure reconnaissance signals, and the steps are as follows:

[0043] S1. Amplify the broadband signal received by the antenna through low-noise amplification to increase the signal level;

[0044] S2. Through filtering and mixing processing, divide the received broadband signal with a total bandwidth of 16 GHz into 4 segments, each with a bandwidth of 4 GHz, and transform all these 4 segments of signals to the range of 2 - 6 GHz;

[0045] S3. Through filtering and mixing processing again, divide these 4 segments of 2 - 6 GHz signals into 16 segments, each with a bandwidth of 1 GHz, and transform all these 16 segments of signals to the range of 2 - 3 GHz;

[0046] S4. Select 10 channels of 2 - 3 GHz signals through a 16 - to - 10 radio frequency matrix switch, and then after fixed frequency conversion, convert them into baseband signals and send them to the signal processing unit to cover a 10 GHz signal bandwidth in parallel;

[0047] S5. The signal processing unit performs compression processing on the received 10 GHz bandwidth data, and then stores it in the data storage unit in parallel to achieve real - time acquisition and storage of wide - open airborne radar countermeasure reconnaissance signals.

[0048] Specifically, in this embodiment, the hardware system for implementing this parallel acquisition, processing, and storage method consists of an antenna, a radio frequency unit, a signal processing unit, and a data storage unit. Except for the power supply, the component modules of each other unit are inserted into the chassis through the chassis slots, connected through the motherboard, and the data transmission adopts the VPX bus transmission mode.

[0049] 1. Radio Frequency Unit

[0050] The radio frequency unit includes 2 modules, namely the local oscillator unit and the radio frequency channel. Among them, the local oscillator unit mainly provides clock signals and local oscillator signals; the radio frequency channel receives broadband radar countermeasure reconnaissance signals, divides the broadband signal into 16 channels with a bandwidth of 1 GHz through mixing and filtering methods, and then selects 10 signals through the matrix switch and sends them to the signal acquisition unit.

[0051] (1) Local Oscillator Unit

[0052] The local oscillator unit mainly provides clock signals and local oscillator signals.

[0053] As Figure 2 shown, the 100 MHz crystal oscillator is the only reference source of the device. The high - frequency local oscillator required for frequency conversion uses a phase - locked source, and the reference signal is obtained by power splitting of the 100 MHz crystal oscillator. A single 1 - way 100 MHz signal is used as the reference for the final stage mixing and AD clock.

[0054] (2) Radio Frequency Channel

[0055] The RF channel is used to receive wideband radar countermeasure reconnaissance signals. The wideband signal is segmented into 16 channels with a bandwidth of 1 GHz through mixing and filtering, and then 10 signals are selected by a matrix switch and sent to the signal acquisition unit.

[0056] First, the wideband signal received by the antenna is amplified by a low-noise amplifier, and the signal level is increased as much as possible on the premise of ensuring that the maximum normal operating signal requirement is not compressed.

[0057] Then, the received wideband signal is divided into four. The wideband signal with a total bandwidth of 16 GHz is segmented into four segments through a filter, each with a bandwidth of 4 GHz. And through segmented mixing, the four segments of signals are all transformed into the range of 2 - 6 GHz for further processing in the same way, reducing the equipment complexity and cost.

[0058] Next, the four segments of 2 - 6 GHz signals are again divided into four. The signals are segmented into segments with a bandwidth of 1 GHz each through a filter. And through segmented mixing, the 16 segments of signals are all transformed into the range of 2 - 3 GHz.

[0059] Immediately following, through a 16-to-10 RF matrix switch, which can give full play to the parallel fault tolerance ability of the system.

[0060] Finally, after the 10 channels of 2 - 3 GHz signals pass through a one-to-two power divider respectively, one path is connected to a high-sensitivity DLVA to provide a criterion for backend storage management, and the other path is converted into a baseband signal through fixed frequency conversion and sent to a parallel ADC chip, covering a 10 GHz signal bandwidth in parallel. Then through backend processing and using narrowband reception technology, high-sensitivity reception of the signal is achieved.

[0061] 2. Signal Processing Unit

[0062] As Figure 1 shown, the signal processing unit includes 5 modules, and each module has the same function. Each component module consists of a high-speed A / D converter and a programmable logic device FPGA, mainly completing data reception, signal acquisition, and compression processing of signal data. After the signal compression processing, it is transmitted to the signal storage unit for signal storage through the VPX bus method.

[0063] The high-speed large-dynamic signal acquisition circuit inside each signal processing unit includes two parts: a high-speed A / D converter and a data compression processing module.

[0064] (1) High-speed A / D Converter

[0065] The performance of the high-speed A / D converter directly determines the overall performance of this system. The resolution or number of bits of the high-speed A / D converter determines the dynamic range of the system. After the signal passes through the high-speed A / D converter, due to the influence of its quantization error, the noise of the system will increase.

[0066] As can be seen from the above formula, increasing the number of bits can improve the signal-to-noise ratio of the high-speed A / D converter, and at the same time increase the dynamic range of the receiver. Considering the actual requirements of the radar countermeasure reconnaissance electromagnetic environment and the ability to detect and store multiple signals, the quantization bit number of the high-speed A / D converter chip adopted in the present invention is 12 bits, which meets the needs of a large dynamic range.

[0067] (2)Data compression processing

[0068] In the current complex radar countermeasure environment, due to the need for high-speed sampling and long-time signal storage, the recorded radar signal data is often very large. Taking a 4-hour storage time as an example, if no compression processing is done, the amount of data to be stored will be as high as dozens of TBytes, which is a very, very large amount of data. Therefore, it is absolutely necessary to compress these signals. In fact, most radar signals are pulse signals, which have the characteristics of being discontinuous in the time domain and appearing periodically. There is a high degree of redundancy in the data characteristics, and the actual storage capacity can be reduced through compression.

[0069] In this method, data compression adopts two-level buffered compression. When the high-bandwidth high-speed radar sampling data is sent to the data storage unit, the compression coding FPGA first performs primary compression in the way of linear coding compression and stores the pre-compressed signal in real time. When the amount of stored signal reaches a certain threshold, the control FPGA starts secondary compression, finds the corresponding sparse representation in a certain transform domain according to the existing information, calculates and saves the measurement basis, and starts further compression of the compression coding FPGA to achieve the purpose of compressing data. After calculation, the average data compression ratio after compression can reach 7:1.

[0070] The data compression processing in this embodiment includes data compression preprocessing and secondary coding compression, and the specific process is as follows:

[0071] ① Data compression preprocessing

[0072] Such as Figure 4As shown in the figure, the preprocessing FPGA automatically performs a system reset operation after the system is powered on. After the system reset is completed, it receives the data quantized by the high-speed A / D converter and first performs data preprocessing. The data preprocessing includes: data noise reduction processing, preliminary amplitude and phase compensation processing, etc. After the preprocessed data is sent to the modulo calculation module for processing, the output signal amplitude is sent to the detection module and the pulse stream statistics module. The detection module determines the presence or absence of a signal. The pulse stream statistics module calculates the pulse width and the signal duration and counts the flow rate of relevant pulses. The formed result is sent to the information encoding module for parallel output for use by the data storage unit. At the same time, the preprocessing FPGA orthogonalizes the signal in the corresponding transform domain according to the subsequent compressed and optimized characteristic parameters and outputs a digital orthogonal signal to the compression coding FPGA for secondary compression processing.

[0073] The functions of each sub-module are as follows:

[0074] The data preprocessing module mainly performs windowing, cutting, compression, stretching, and noise reduction processing on the data according to the needs of the system to improve the signal-to-noise ratio of the signal. The data preprocessing module also completes preliminary amplitude and phase compensation.

[0075] The digital processing module based on the sparse expression is the main processing module of the system. It orthogonalizes the signal in the corresponding transform domain according to the compressed and optimized characteristic parameters and outputs a digital orthogonal signal.

[0076] The modulo calculation module converts the received radar digital signal into the amplitude data of the signal. The amplitude data is used to detect the presence of the signal, the signal duration, confirm the peak value of the signal, start and pause pulse data compression, etc.

[0077] The detection module adopts a time-domain detection method based on the sum method and the voting method. The threshold uses a combination of an adaptive threshold of noise statistics and a secondary threshold. Different matching criteria are used for signals with narrow and wide pulse widths respectively. It has higher sensitivity to longer input pulses.

[0078] The pulse stream statistics module detects the signal duration and the pulse width and performs certain statistics on the same signal. The pulse amplitude is obtained by accumulating and averaging the pulse amplitude values passing through the threshold value; the leading edge moment corresponding to half of the pulse amplitude is the pulse arrival time, and the time interval between the front and rear edges is the pulse width. At the same time, according to the analyzed information, the pulse width, arrival time, and pulse amplitude are provided to the compression coding FPGA to complete further compression reference.

[0079] ② Secondary compression coding

[0080] Such as Figure 5As shown in the figure, the compression encoding FPGA receives the pulse information from the preprocessing FPGA to achieve duty cycle compression in the time domain. At the same time, linear encoding compression and secondary compression based on the transform domain are performed on the received data. When the system is just started, the compression encoding FPGA mainly uses linear encoding compression + time domain duty cycle compression. After the main control board forms the corresponding sparse expression in the transform domain after working for a period of time, the time domain duty cycle compression, linear encoding compression, and secondary compression based on the transform domain are used for combined compression. The compression encoding FPGA also feeds back and transmits information such as the existing compression efficiency and compression parameters to the sparse calculation FPGA on the main control board to further optimize and update the corresponding sparse expression in the transform domain.

[0081] The functions of each sub-module are as follows:

[0082] Duty cycle compression module. Since the received ADC data is continuous and the radar signal actually has a certain duty cycle (10%), this module retains the valid radar data according to the detection result formed by the upper-level FPGA.

[0083] Sparse matrix compression, decompression, data stream comparison, and compression parameter update and transmission module based on the eigenbasis. Based on the secondary compression FPGA compression module, the data based on the eigenbasis formed by the preprocessing FPGA is compressed and sent to the next-level linear encoding compression module. At the same time, further decompression work is performed on the compression result to judge the compression efficiency, evaluate the effectiveness of the compression parameters, and report the error information of the eigenbasis to the sparse calculation FPGA on the main control board to further optimize the eigenbasis parameters. This module needs to be automatically started after the eigenbasis is formed.

[0084] Linear encoding compression module. The traditional linear encoding and compression module has a lower compression rate than the compression based on the eigenbasis, but due to its simple algorithm and good real-time performance, it always works in this system.

[0085] 3. Data storage unit

[0086] The data storage unit is a storage module with a large storage capacity and high transmission bandwidth. In the present invention, a total of 11 storage single boards are designed to record data. The storage single board is mounted with storage chips on both sides, and the recording capacity of a single board can reach the Tbytes level. Among them, 10 storage single boards are used to record the radar data received at high speed, and the other 1 storage single board is used to separately record the inertial navigation data of the aircraft. The storage board adopts an independent modular design, supports plug-and-play operations, and is convenient for ground data unloading and playback.

[0087] Adopt a buffer processing technology based on high-speed FLASH technology. At the same time, divide 64 Flash chips into 8 groups, with 8 chips in each group for parallel reading and writing of FLASH chips. The pipeline design algorithm is adopted for simultaneous reading and writing of data to fully improve the writing efficiency. A master-slave control protocol is adopted between two FPGAs, and the empty Flash is alternately written with data through the ping-pong mechanism to further improve the writing speed.

[0088] (4)Master control logic unit

[0089] The master control logic unit consists of 1 logic control board. The signal processing unit and the data storage unit communicate with the master control logic unit through the VPX bus. The signal processing unit transmits the collected digital signals to the master control logic unit through the VPX bus. The master control logic unit processes the data by re-compression and then transmits it to the data storage unit through the VPX bus to control the reading and writing of the memory. Among them, the high-speed digital signal transmission bus adopts the VPX bus, and its main function is to connect the digital signal processing unit and the signal storage unit to achieve high-speed digital transmission.

[0090] In the present invention, a total of 1 master control logic main board, 5 signal processing modules, 10 signal storage single boards and 1 single board for storing inertial navigation information are connected to the VPX bus. Each board uses the VPX high-speed bus for data communication. Since the signal processing module and the storage single board need to adopt a modular pluggable design, a two-level bus structure is adopted for interconnection with the master control logic main board.

[0091] In the present invention, the communication between modules and each board is realized through a custom protocol, and the interface protocol is designed through FPGA logic. This custom protocol adopts a source synchronous transmission protocol. The protocol defines clock, data and frame synchronization signals. According to the principle of source synchronous transmission, the clock signal and the data signal should have the same time delay on the board, and the data and clock trace lengths of each group of transmission paths need to be strictly consistent in the PCB design.

Claims

1. A parallel acquisition, processing, and storage method for airborne radar countermeasure reconnaissance signals, characterized in that The steps are as follows: S1. The broadband signal received by the antenna is amplified by a low-noise amplifier to increase the signal level; S2. Through filtering and mixing processing, the broadband signal with a total bandwidth of 16 GHz received is divided into 4 segments, each with a bandwidth of 4 GHz, and all these 4 segments of signals are transformed into the range of 2 - 6 GHz; S3. Through filtering and mixing processing again, these 4 segments of 2 - 6 GHz signals are divided into 16 segments, each with a bandwidth of 1 GHz, and all these 16 segments of signals are transformed into the range of 2 - 3 GHz; S4. 10 paths of 2 - 3 GHz signals are selected by a 16-to-10 radio frequency matrix switch, and then after fixed frequency conversion, they become baseband signals and are sent to the signal processing unit to cover a 10 GHz signal bandwidth in parallel; S5. The signal processing unit performs compression processing on the received 10 GHz bandwidth data, and then stores it in the data storage unit in parallel to achieve real-time acquisition and storage of the wide-open airborne radar countermeasure reconnaissance signal; The signal processing unit includes 5 sets of signal processing modules, and each set of signal processing modules is composed of a high-speed A / D converter and a programmable logic device FPGA. The high-speed A / D converter is used to complete data reception and signal acquisition of the 10 GHz bandwidth data, and the programmable logic device FPGA is used to complete data compression after signal acquisition and transmit it to the data storage unit through the VPX bus; The data compression includes data compression preprocessing and secondary compression coding based on the compressive sensing signal processing algorithm; The data compression preprocessing includes the following steps: A1. The preprocessing FPGA automatically performs a system reset operation after power-on. After the system reset is completed, it receives the data quantized by the high-speed A / D converter; A2. Then, data noise reduction processing, preliminary amplitude and phase compensation preprocessing are carried out. The preprocessed data is sent to the digital processing module and then through the signal analog processing module, the output signal amplitude is sent to the detection module and the pulse stream statistics module; the detection module judges the presence or absence of the signal, and the pulse stream statistics module calculates the pulse width and the duration of the signal and counts the flow of the corresponding pulses; A3. The formed result is sent to the information coding module for parallel output for use by the data storage unit. At the same time, the preprocessing FPGA orthogonalizes the signal in the transform domain according to the subsequent compressed and optimized characteristic parameters and outputs a digital orthogonal signal to the compression coding FPGA for secondary compression coding; The secondary compression coding includes the following steps: B1. The compression coding FPGA receives the pulse information from the preprocessing FPGA, realizes duty cycle compression in the time domain, and at the same time performs linear coding compression and secondary compression based on the transform domain on the received data; B2. When just starting up, the compression coding FPGA adopts linear coding compression and time-domain duty cycle compression; when the main control board forms the corresponding sparse expression in the transform domain after working for a period of time, it adopts a combined compression method of time-domain duty cycle compression, linear coding compression, and secondary compression based on the transform domain for compression; B3. The compression coding FPGA simultaneously feeds back and transmits the existing compression efficiency and compression parameter information to the main control board sparse calculation FPGA to update the corresponding sparse expression in the transform domain.

2. The parallel acquisition, processing and storage method of the airborne radar countermeasure reconnaissance signal according to claim 1, characterized in that The data storage unit includes 11 storage single boards with storage chips mounted on both the front and back. Each storage single board is provided with 64 Flash storage chips, and every 8 chips form a group for parallel data reading and writing.

3. The parallel acquisition, processing and storage method of the airborne radar countermeasure reconnaissance signal according to claim 2, characterized in that Among them, 10 storage single boards are used to record the radar data received at high speed, and the other 1 storage single board is used to record the inertial navigation data of the aircraft.

4. The parallel acquisition, processing and storage method of the aviation radar countermeasure reconnaissance signal according to claim 1, characterized in that, The signal processing unit and the data storage unit communicate with the main control logic unit through the VPX bus; the signal processing unit transmits the collected digital signals to the main control logic unit through the VPX bus, the main control logic unit processes the data by re-compression, and then transmits it to the data storage unit through the VPX bus to control the reading and writing of the memory.

5. The parallel acquisition, processing and storage method of the airborne radar countermeasure reconnaissance signal according to claim 1, characterized in that The number of bits n of the high-speed A / D converter is 12 bits.

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