A method and apparatus for step-by-step synthesis of a clock tree

Abstract

The application provides a clock tree synthesis method, comprising: obtaining a plurality of synchronous unit groups of a same target clock source; each of the synchronous unit groups comprises at least one synchronous unit; for each of the plurality of synchronous unit groups, a virtual clock source is set at a side of each synchronous unit in the synchronous unit group away from the target clock source along a common path of the synchronous unit to the target clock source; and a layout and routing tool is used to make clock delays of each synchronous unit in the synchronous unit group to the virtual clock source equal. By setting a virtual clock source on the synchronous unit groups belonging to different functional targets under the same clock source, the synchronous unit groups belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, so that the quality of the clock tree on the chip is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a clock tree step-by-step synthesis method and device. BACKGROUND

[0002] For a clock network relatively simple, the design is not particularly high performance requirements, the traditional approach of back-end engineers often start directly from the clock source tree, and the PR tool will start directly from the clock source tree, and the PR tool will make the same clock source to all synchronization units (the PR tool will consider that all synchronization units of the same clock source are the same synchronization unit group), but in fact, the synchronization unit group for implementing different functions under the same clock source will not exchange data, so the synchronization unit group that originally has a very short delay will be pulled very long, and a large amount of delay will be added to the clock tree to compensate, and the constraint requirements of the design constraint file (sdc) are also relatively strict. SUMMARY

[0003] Therefore, the present application provides a clock tree step-by-step synthesis method and device, which sets a virtual clock source on the synchronization unit group belonging to different functional targets under the same clock source, so that the synchronization unit group belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, thereby greatly improving the quality of the clock tree on the chip.

[0004] In a first aspect, the present application provides a clock tree synthesis method, which is used for synthesizing clock synchronization units on a chip, and includes the following steps:

[0005] Obtaining a plurality of synchronization unit groups of a same target clock source, wherein each synchronization unit group includes at least one synchronization unit, and each synchronization unit in the same synchronization unit group is used for implementing the same function;

[0006] For each synchronization unit group in the plurality of synchronization unit groups, a virtual clock source is set at an end away from the target clock source on a common path from each synchronization unit in the synchronization unit group to the target clock source;

[0007] Using a layout and routing tool to make the clock delay of each synchronization unit in each synchronization unit group to the corresponding virtual clock source of the synchronization unit group equal.

[0008] Optionally, the intermediate unit can be a combination logic unit or a gated clock unit.

[0009] Optionally, the step of setting a virtual clock source between the synchronization unit and the target intermediate unit includes:

[0010] a virtual clock source is set at the output end of the target intermediate unit.

[0011] Optionally, the step of using the layout and routing tool to make the clock delay of each synchronization unit in each of the at least one group of synchronization units to the virtual clock source corresponding to the group of synchronization units equal comprises:

[0012] acquiring the clock delay of each synchronization unit in the group of synchronization units to the virtual clock source;

[0013] selecting the clock delay with the largest clock delay value from the clock delays as a standard clock delay;

[0014] setting a buffer between the synchronization unit and the virtual clock source so that the clock delay of each synchronization unit in the group of synchronization units to the virtual clock source is equal to the standard clock delay.

[0015] Optionally, when there is a first group of synchronization units in the multiple groups of synchronization units that has data exchange with a block module on the chip, after the step of using the layout and routing tool to make the clock delay of each synchronization unit in each of the at least one group of synchronization units to the virtual clock source corresponding to the group of synchronization units equal, the method comprises:

[0016] acquiring a first clock delay inside the block module and a second clock delay of the block module to the target clock source;

[0017] acquiring a third clock delay of each synchronization unit in the first group of synchronization units to the virtual clock source and acquiring a fourth clock delay of the virtual clock source to the target clock source;

[0018] using the layout and routing tool to make the third clock delay equal to the first clock delay and the fourth clock delay equal to the second clock delay.

[0019] Optionally, the step of using the layout and routing tool to make the third clock delay equal to the first clock delay comprises:

[0020] setting a buffer between the synchronization unit and the virtual clock source corresponding to the synchronization unit so that the third clock delay is equal to the first clock delay;

[0021] the step of using the layout and routing tool to make the fourth clock delay equal to the second clock delay comprises:

[0022] a buffer is set between the virtual clock source and the target clock source to equalize the fourth clock delay and the second clock delay, or a buffer is set between the block module and the target clock source to equalize the fourth clock delay and the second clock delay.

[0023] In a second aspect, the embodiments of the present application provide a clock tree step-by-step synthesis device, comprising:

[0024] a collection unit configured to acquire a plurality of synchronous unit groups of a same target clock source, wherein each of the synchronous unit groups comprises at least one synchronous unit, and each of the synchronous unit groups is configured to implement a same function;

[0025] the collection unit is configured to set a virtual clock source at an end of a common path from each of the synchronous units in each of the synchronous unit groups to the target clock source, and away from the target clock source.

[0026] the processing unit is further configured to equalize a clock delay from each of the synchronous units in each of the synchronous unit groups to the corresponding virtual clock source by using a layout and routing tool.

[0027] Optionally, the collection unit is further configured to acquire the clock delay from each of the synchronous units in each of the synchronous unit groups to the virtual clock source.

[0028] the processing unit is further configured to select a clock delay with a largest value from the clock delays as a standard clock delay, and set a buffer between the synchronous unit and the virtual clock source to equalize the clock delay from each of the synchronous units in the synchronous unit group to the virtual clock source to the standard clock delay.

[0029] Optionally, when a first synchronous unit group in the plurality of synchronous unit groups exchanges data with a block module on the chip, the collection unit is further configured to acquire a first clock delay inside the block module and a second clock delay from the block module to the target clock source, acquire a third clock delay from each of the synchronous units in the first synchronous unit group to the virtual clock source, and acquire a fourth clock delay from the virtual clock source to the target clock source.

[0030] the processing unit is further configured to equalize the third clock delay to the first clock delay and the fourth clock delay to the second clock delay by using the layout and routing tool.

[0031] Optionally, the processing unit is further configured to set a buffer between the respective synchronization unit and the virtual clock source corresponding to the respective synchronization unit, so as to equalize the third clock delay and the first clock delay; set a buffer between the virtual clock source and the target clock source, so as to equalize the fourth clock delay and the second clock delay, or set a buffer between the block module and the target clock source, so as to equalize the fourth clock delay and the second clock delay.

[0032] The embodiment of the present application provides a step-by-step clock tree synthesis method and device, which adopts a step-by-step method to perform clock tree synthesis on synchronization units belonging to the same functional target. By setting a virtual clock source on a synchronization unit group belonging to different functional targets under the same clock source, the synchronization unit group belonging to different functional targets under the same clock source can be independently synthesized, instead of starting from the clock source, thereby greatly improving the quality of the clock tree on the chip. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0034] Figure 1 A clock layout structure diagram on a chip;

[0035] Figure 2 A flowchart of a step-by-step clock tree synthesis method provided by the embodiment of the present application;

[0036] Figure 3 A flowchart of another step-by-step clock tree synthesis method provided by the embodiment of the present application;

[0037] Figure 4 A clock layout structure diagram on a chip provided by the embodiment of the present application;

[0038] Figure 5 A structure diagram of a step-by-step clock tree synthesis device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions of the present application will be further described in detail below with the drawings and embodiments.

[0040] Clock Tree Synthesis (CTS) is an important part of integrated circuit design. Clock Tree Synthesis refers to the clock buffer or inverter tree from the root node of a clock to each leaf node. Therefore, it can be known that the goals of clock tree synthesis include:

[0041] (1) clock skew is as small as possible.

[0042] (2) clock latency is as short as possible.

[0043] Figure 1 A clock distribution diagram on a chip is shown. As shown in Figure 1 To achieve equal clock latency from the clock source to the same function related target synchronization unit, the prior art creates a clock at the clock source clk1, clk2, clk3, clk4 to constrain the clock source clk1, clk2, clk3, clk4, which requires a high design constraint file. Because creating a clock for clk1, clk2, clk3, clk4 requires defining four clocks, and these four clocks are selected by different data selectors to reach different functional synchronization units, and there is no relationship between the four clocks, which makes the constraints of the design constraint file more complex, but some constraints of the design constraint file may affect the timing repair of the backend clock tree synthesis.

[0044] Defining a clock on clk1 in the prior art will cause the layout and routing tool to equalize the clock latency of group1 and group2. Group1 and group2 are independent, that is, there is no data exchange between group1 and group2. However, the synchronization unit that the layout and routing tool can see is group1 and group2. Therefore, the tool will equalize the clock latency from the clock source to group1 and group2. That is, it will increase a large number of buffers on the path from the clock source to group to increase the latency of the group with shorter clock latency, thereby affecting the quality of the entire clock tree.

[0045] A step-by-step synthesis method of a clock tree is provided in the embodiments of the present application, as shown in Figure 2 The method comprises:

[0046] Step S201, obtaining a plurality of synchronization unit groups of the same target clock source; wherein each synchronization unit group comprises at least one synchronization unit; and in each synchronization unit group, the at least one synchronization unit is used to implement the same function.

[0047] Step S202, for each of the plurality of synchronization unit groups, setting a virtual clock source at an end of a common path of each synchronization unit in the synchronization unit group to the target clock source, which is away from the target clock source.

[0048] A plurality of synchronization unit groups are provided under the same target clock source, each of the synchronization unit groups comprises a plurality of synchronization units, for each of the plurality of synchronization unit groups, there is a common path in a path of each synchronization unit in the synchronization unit group to the target clock source, and a virtual clock source is set at an end of the common path, which is away from the clock source.

[0049] Step S203, using a layout and routing tool to make the clock delay of each synchronization unit in at least one of the synchronization unit groups to the corresponding virtual clock source of the synchronization unit group equal.

[0050] The clock tree of each synchronization unit in at least one of the synchronization unit groups to the corresponding virtual clock source of the synchronization unit group is synthesized by using a layout and routing tool. Specifically, the clock delay of each synchronization unit in the synchronization unit group to the virtual clock source is obtained, and the maximum clock delay is selected as a standard clock delay. Then, the clock delay of each synchronization unit in the synchronization unit group to the virtual clock source is made equal by adding a buffer on the path of the synchronization unit to the virtual clock source.

[0051] In one example, when there is data exchange between at least one of the plurality of synchronization unit groups deployed on a chip and a block module deployed on the chip, taking one of the synchronization unit groups as an example, the method further comprises:

[0052] Step S204, obtaining the clock delay inside the block and the delay of the block to the target clock source.

[0053] The block is the smallest storage and processing unit in the database, and contains header information data or PL / SQL code of the block itself.

[0054] Step S205, using a layout and routing tool to make the clock delay of each synchronization unit in the synchronization unit group interacting with the block module to the corresponding virtual clock source equal to the clock delay inside the block.

[0055] In step S206, the clock delay from the virtual clock source corresponding to the synchronous unit group having data interaction with the block module to the target clock source is equal to the clock delay from the block module to the target clock source by using a layout routing tool.

[0056] Specifically, the clock delay inside the block module can be taken as the first clock delay, and the clock delay from the block module to the target clock source can be taken as the second clock delay. The clock delay from each synchronous unit in the synchronous unit group having data interaction with the block module to the corresponding virtual clock source can be taken as the third clock delay, and the clock delay from the virtual clock source corresponding to the synchronous unit group to the target clock source can be taken as the fourth clock delay.

[0057] In one example, when the synchronous unit group having data interaction with the block module is only one group, since the first clock delay is already determined, a buffer can be set between each synchronous unit and the corresponding virtual clock source to make the third clock delay equal to the first clock delay.

[0058] The second clock delay is compared with the fourth clock delay. When the second clock delay is less than the fourth clock delay, a buffer can be added on the path from the block module to the target clock source to make the second clock delay equal to the fourth clock delay. When the second clock delay is greater than the fourth clock delay, a buffer can be set between the virtual clock source corresponding to the synchronous unit group and the target clock source to make the fourth clock delay equal to the second clock delay.

[0059] In one example, when the synchronous unit group having data interaction with the block module is multiple groups, it is required to make the third clock delay of the multiple synchronous unit groups equal to the first clock delay, and the fourth clock delay equal to the second clock delay.

[0060] In the embodiment of the present application, a step-by-step method is adopted to perform clock tree synthesis on the synchronous units under the same functional target. By setting a virtual clock source on the synchronous unit group belonging to different functional targets under the same clock source, the synchronous unit group belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, which greatly improves the quality of the clock tree on the chip.

[0061] In the embodiment of the present application, a step-by-step synthesis method of a clock tree is further provided. As shown in Figure 3 the method comprises:

[0062] In step S301, a plurality of synchronous unit groups of the same target clock source are acquired, wherein each synchronous unit group comprises at least one synchronous unit, and the at least one synchronous unit in each synchronous unit group is used to implement the same function.

[0063] In step S302, at least one same intermediate unit on the path from each synchronization unit in each of the at least one synchronization unit group to the target clock source is obtained.

[0064] A plurality of synchronization unit groups are provided under the same target clock source, each of the synchronization unit groups includes a plurality of synchronization units, and a plurality of intermediate units are provided on the path from each synchronization unit in each of the plurality of synchronization unit groups to the target clock source. One same intermediate unit can be provided on a plurality of paths. That is, the plurality of paths intersect at the same intermediate unit.

[0065] In one example, the intermediate unit can be any one of a combinational logic unit, a gated clock unit, and a digital selector.

[0066] In step S303, a target intermediate unit is determined from the at least one same intermediate unit, the target intermediate unit being the intermediate unit farthest from the target clock source in the path.

[0067] In step S304, a virtual clock source is provided between the synchronization unit group and the target intermediate unit.

[0068] In one example, a virtual clock source can be provided at the output end of the target intermediate unit.

[0069] In step S305, a layout and routing tool is used to make the clock delay of each synchronization unit in each of the at least one synchronization unit group to the corresponding virtual clock source of the synchronization unit group equal. Figure 4 A clock tree synthesis diagram provided by an embodiment of the present application is shown in FIG. 1. Figure 4 In the clock tree layout shown in FIG. 1, data exchange exists between the synchronization unit group group1 and the block module, the clock source is clk1, and the following purposes need to be achieved when synthesizing the block module and the group1:

[0070] T1 / delay+T2 / delay+T6 / delay=T1 / delay+T3 / delay+mux1 / delay+T4 / delay+mux5 / delay+clock gate1 / delay+T5 / delay

[0071] That is, in the first step, the following needs to be achieved: Figure 4The clock delay of T5 in the block module and T6 inside the block module is equal, so that T5 / delay=T6 / delay, and the back-end engineer only needs to set a virtual clock source clk_group1 and clk_group2 at the output end of clock gate 1 and clock gate 2 respectively, so that the layout tool only starts a respective long tree at the two points of clk_group1 and clk_group2, and the delay of the clk_group1 clock tree is equal to the delay of T6.

[0072] The second step is to make T1 / delay+T2 / delay=T1 / delay+T3 / delay+mux1 / delay+T4 / delay+mux5 / delay+clock gate 1 / delay. The back-end engineer needs to create a clock clk1 at clk1 to define the clock, but needs to set a constraint to prevent the layout tool from seeing the real synchronous unit (i.e. the input end of the register). Therefore, the point before clk1_group needs to be set as a synchronous unit, i.e. the input end of clock gate 1 and the input end of the block are set as synchronous units. In this way, the layout tool only makes the clock delay of clk1 to the two synchronous units equal. It should be noted that the delay of the clock gate itself is not considered here, so a constraint needs to be set to make the delay of T1+T2 one clock gate 1 delay more than the delay of T1+T3+mux1+T4+mux5, or vice versa.

[0073] It should be noted that, in the embodiment of the present application, when the clock tree synthesis is performed on the block module and group1 under the clock source clk1, the clock delay of the plurality of registers in group1 has been synthesized, so that the clock delay T5 of clk_group1 to each register in group1 is equal. The specific synthesis process and steps S201-S203 are the same, and will not be described here.

[0074] The clock tree on the chip is synthesized step by step, so that when a certain synchronous unit group on the chip is synthesized, the clock delay of other synchronous unit groups under the same clock source is not affected. The clock delay of other synchronous unit groups under the same clock source is not affected when a certain synchronous unit group under the same clock source is synthesized in the prior art. By distributing the synthesis of the clock on the chip, the clock is greatly simplified, and the sdc constraint is relatively simple, avoiding the tool to fix the delay of some useless paths.

[0075] The present application also provides a clock tree step-by-step synthesis device, as shown in Figure 5 The device comprises a collection unit 501 and a processing unit 502.

[0076] The collection unit 501 is configured to acquire a plurality of groups of synchronization unit groups of the same target clock source, wherein each group of the synchronization unit groups comprises at least one synchronization unit, and the at least one synchronization unit is configured to implement the same function.

[0077] Further, the collection unit 501 is further configured to acquire at least one same intermediate unit possessed by each synchronization unit in the synchronization unit group on a path to the target clock source. The intermediate unit can be a combinational logic unit or a gated clock unit.

[0078] The processing unit 502 is configured to determine a target intermediate unit from the at least one same intermediate unit acquired by the collection unit 501, and set a virtual clock source between the synchronization unit group and the target intermediate unit. The target intermediate unit is an intermediate unit with the longest path to the target clock source among the at least one intermediate unit.

[0079] In one example, a virtual clock source can be set at an output end of the target intermediate unit.

[0080] The processing unit 502 is further configured to use a layout and routing tool to equalize clock delays of each synchronization unit in the synchronization unit group to the corresponding virtual clock source. Specifically, the collection unit 501 acquires a clock delay of each synchronization unit in the synchronization unit group to the virtual clock source. The processing unit 502 selects a clock delay with the largest clock delay value from the acquired clock delays as a standard clock delay. Then, the layout and routing tool is used to set a buffer between the synchronization unit and the virtual clock source, so that the clock delay of each synchronization unit in the synchronization unit group to the virtual clock source is equal to the standard clock delay.

[0081] In one example, when a first synchronization unit group in the plurality of groups of synchronization unit groups exists data exchange with a block module on the chip, the collection unit 501 is further configured to acquire a first clock delay in the block module, a second clock delay from the block module to the target clock source, a third clock delay from each synchronization unit in the first synchronization unit group to the virtual clock source, and a fourth clock delay from the virtual clock source to the target clock source.

[0082] The processing unit 502 utilizes the place and route tool to equalize the third clock latency to the first clock latency and the fourth clock latency to the second clock latency. Specifically, the processing unit 502 utilizes the place and route tool to place a buffer between each of the synchronization units of the first synchronization unit group and its corresponding virtual clock source to equalize the third clock latency to the first clock latency. And the processing unit 502 utilizes the place and route tool to place a buffer between the virtual clock source and the target clock source to equalize the fourth clock latency to the second clock latency, or to place a buffer between the block module and the target clock source to equalize the fourth clock latency to the second clock latency.

[0083] Those skilled in the art should be aware that, in the one or more examples described above, the functions described with reference to the present application can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium.

[0084] The above detailed description merely describes the specific implementation of the present application, and is not intended for limiting the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific implementation of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the present application shall be included in the protection scope of the present application.

Claims

1. A method of synthesis of a clock tree, characterized in that, The method is used for synthesizing a clock synchronization unit on a chip, and the method comprises: acquiring a plurality of synchronization unit groups of a same target clock source, wherein each synchronization unit group comprises at least one synchronization unit, and the at least one synchronization unit in each synchronization unit group is used for realizing the same function; for each synchronization unit group in the plurality of synchronization unit groups, a virtual clock source is arranged at a side far away from the target clock source on a common path of each synchronization unit in the synchronization unit group to the target clock source; when a first synchronization unit group in the plurality of synchronization unit groups exists data exchange with a block module on the chip, acquiring a first clock delay inside the block module and a second clock delay of the block module to the target clock source; acquiring a third clock delay of each synchronization unit in the first synchronization unit group to the virtual clock source and a fourth clock delay of the virtual clock source to the target clock source; using a layout and routing tool to make the third clock delay equal to the first clock delay and the fourth clock delay equal to the second clock delay.

2. The method of claim 1, wherein, The using of the layout and routing tool to make the third clock delay equal to the first clock delay comprises: arranging a buffer between the each synchronization unit and the corresponding virtual clock source of the each synchronization unit, so as to make the third clock delay equal to the first clock delay. The using of the layout and routing tool to make the fourth clock delay equal to the second clock delay comprises: arranging a buffer between the virtual clock source and the target clock source, so as to make the fourth clock delay equal to the second clock delay, or arranging a buffer between the block module and the target clock source, so as to make the fourth clock delay equal to the second clock delay.

3. An apparatus for synthesizing a clock tree, the apparatus comprising: comprise: an acquisition unit, configured to acquire a plurality of synchronization unit groups of a same target clock source, wherein each synchronization unit group comprises at least one synchronization unit, and the at least one synchronization unit in each synchronization unit group is used for realizing the same function; the acquisition unit is further configured to, for each synchronization unit group in the plurality of synchronization unit groups, arrange a virtual clock source at a side far away from the target clock source on a common path of each synchronization unit in the synchronization unit group to the target clock source; when a first synchronization unit group in the plurality of synchronization unit groups exists data exchange with a block module on the chip, the acquisition unit is further configured to acquire a first clock delay inside the block module and a second clock delay of the block module to the target clock source, acquire a third clock delay of each synchronization unit in the first synchronization unit group to the virtual clock source, and acquire a fourth clock delay of the virtual clock source to the target clock source; a processing unit, configured to use a layout and routing tool to make the third clock delay equal to the first clock delay and the fourth clock delay equal to the second clock delay.

4. The apparatus of claim 3, wherein, The collection unit is also configured to acquire a clock delay of each synchronization unit in the synchronization unit group to the virtual clock source; The processing unit is also configured to select a clock delay with the largest clock delay value from the clock delays as a standard clock delay, and set a buffer between the synchronization unit and the virtual clock source, so that the clock delay of each synchronization unit in the synchronization unit group to the virtual clock source is equal to the standard clock delay.

5. The apparatus of claim 3, wherein, The processing unit is also configured to set a buffer between the respective synchronization unit and the virtual clock source corresponding to the respective synchronization unit, so that the third clock delay is equal to the first clock delay. A buffer is set between the virtual clock source and the target clock source to make the fourth clock delay equal to the second clock delay, or a buffer is set between the block module and the target clock source to make the fourth clock delay equal to the second clock delay.

Images