RF level indicator

Abstract

A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier configured to receive an input RF signal and generate an amplified RF signal based on the input RF signal, wherein the gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined at least in part based on the comparison result signals.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority and benefit to U.S. Patent Application No. 17 / 351,192, filed June 17, 2021, entitled "RADIO FREQUENCY LEVEL INDICATOR," and U.S. Provisional Application No. 63 / 152,839, filed February 23, 2021, entitled "RADIO FREQUENCY LEVEL INDICATOR." The entire contents of the aforementioned patent applications are incorporated herein by reference as part of the disclosure of this patent document. Technical Field

[0003] This article describes topics related to RF level indicators, and more specifically to RF level indicator circuits that provide improved sampling performance. Background Technology

[0004] Receiver circuits with variable gain LNA circuits can be affected by, for example, blocking signals that may saturate the LNA circuit output. Insufficient sampling capability of the receiver circuit to the LNA output can prevent proper gain control, leading to insufficient LNA gain and increased noise at the receiver output, or excessive gain, resulting in clipping of the LNA output. Summary of the Invention

[0005] One inventive aspect is a radio frequency (RF) receiver circuit comprising: a variable gain amplifier configured to receive an input RF signal and generate an amplified RF signal based on the input RF signal, wherein the gain of the variable gain amplifier is variable; and an RF level indicator circuit configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals and compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals, wherein the gain of the variable gain amplifier is determined at least in part based on the comparison result signals.

[0006] In some embodiments, the gain of the variable gain amplifier is reduced in response to a comparison result signal indicating that the amplified RF signal is out of range.

[0007] In some embodiments, the RF receiver circuitry further includes a sampling clock generator configured to generate a sampling clock based on a periodic reference clock, wherein the RF level indicator circuitry is configured to generate the sampled RF signal in response to each pulse of a series of pulses of the sampling clock.

[0008] In some embodiments, the sampling clock is aperiodic.

[0009] In some embodiments, the pulses of the sampling clock have substantially the same duration.

[0010] In some embodiments, the difference between the maximum duration from the first sampling time to the first subsequent consecutive sampling time and the minimum duration from the second sampling time to the second subsequent consecutive sampling time is less than 1 / 2 of the period of the periodic reference clock.

[0011] In some embodiments, the RF receiver circuitry further includes: a mixer configured to receive the amplified RF signal and generate a baseband signal based on the amplified RF signal; a filter configured to receive the baseband signal and generate a filtered baseband signal based on the baseband signal from the mixer; an analog-to-digital converter configured to receive the filtered baseband signal and generate a digital version of the filtered baseband signal based on the filtered baseband signal; and a controller configured to receive the digital version of the filtered baseband signal.

[0012] In some embodiments, the controller is configured to selectively cause the RF level indicator circuit to generate the comparison result signal or not generate the comparison result signal.

[0013] In some embodiments, the controller is configured to selectively cause the RF level indicator circuit to generate the comparison result signal when the variable gain amplifier receives information that encodes one or more preamplifier bits of an information packet.

[0014] In some embodiments, the controller is configured to selectively prevent the RF level indicator circuit from generating the comparison result signal after the variable gain amplifier stops receiving information that encodes the preamplifier bit of the packet.

[0015] Another inventive aspect is a method using a radio frequency (RF) receiver circuit including a variable gain amplifier and an RF level indicator circuit, wherein the gain of the variable gain amplifier is variable, the method comprising: receiving an input RF signal using the variable gain amplifier; generating an amplified RF signal based on the input RF signal using the variable gain amplifier; sampling the amplified RF signal at non-periodic sampling intervals using the RF level indicator circuit to generate a plurality of sampled RF signals; and comparing the sampled RF signals with one or more thresholds using the RF level indicator circuit to generate a plurality of comparison result signals, wherein the gain of the variable gain amplifier is determined at least in part based on the comparison result signals.

[0016] In some embodiments, the method further includes reducing the gain of the variable gain amplifier in response to a comparison result signal indicating that the amplified RF signal is out of range.

[0017] In some embodiments, the RF receiver circuitry further includes a sampling clock generator, and the method further includes: generating a sampling clock based on a periodic reference clock using the sampling clock generator; and generating the sampled RF signal in response to each pulse of a series of pulses of the sampling clock using the RF level indicator circuitry.

[0018] In some embodiments, the sampling clock is aperiodic.

[0019] In some embodiments, the pulses of the sampling clock have substantially the same duration.

[0020] In some embodiments, the difference between the maximum duration from the first sampling time to the first subsequent consecutive sampling time and the minimum duration from the second sampling time to the second subsequent consecutive sampling time is less than 1 / 2 of the period of the periodic reference clock.

[0021] In some embodiments, the RF receiver circuitry further includes a mixer, a filter, an analog-to-digital converter (ADC), and a controller, and the method further includes: receiving the amplified RF signal using the mixer; generating a baseband signal based on the amplified RF signal using the mixer; receiving the baseband signal using the filter; generating a filtered baseband signal based on the baseband signal from the mixer using the filter; receiving the filtered baseband signal using the ADC; generating a digital version of the filtered baseband signal based on the filtered baseband signal using the ADC; and receiving the digital version of the filtered baseband signal using the controller.

[0022] In some embodiments, the method further includes using the controller to selectively cause the RF level indicator circuit to generate the comparison result signal or not generate the comparison result signal.

[0023] In some embodiments, the method further includes using the controller to selectively cause the RF level indicator circuit to generate the comparison result signal when the variable gain amplifier receives information that encodes one or more preamplifier bits of an information packet.

[0024] In some embodiments, the method further includes: using the controller to selectively prevent the RF level indicator circuit from generating the comparison result signal after the variable gain amplifier no longer receives information encoding the preamplifier bit of the packet. Attached Figure Description

[0025] The accompanying drawings, which are included in and form a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help to explain some principles associated with the disclosed embodiments.

[0026] Figure 1 This is a schematic diagram of an embodiment of a receiver circuit with an LNA circuit.

[0027] Figure 2 This is a schematic diagram of an embodiment of an RF level indicator circuit.

[0028] Figure 3 It is a display Figure 2 The waveform diagram shows the function of the RF level indicator circuit.

[0029] Figure 4 This is a schematic diagram of an embodiment of a variable delay sampling pulse generator.

[0030] Figure 5 It is a display Figure 4 The waveform diagram of the sampling pulse generator function.

[0031] Figure 6 This is a schematic diagram of an embodiment of a variable clock delay circuit.

[0032] Figure 7 This is a schematic diagram of an embodiment of a delay selection circuit.

[0033] Figure 8 It is for demonstration and use. Figure 7 The delay selection circuit Figure 6 The waveform diagram of the function of the variable clock delay circuit.

[0034] In practice, similar reference numerals in drawings indicate similar structures, features, or elements. Detailed Implementation

[0035] This document describes specific embodiments of the invention in conjunction with the accompanying drawings.

[0036] Various details are set forth herein because they relate to certain embodiments. However, the invention may also be practiced in ways different from those described herein. Modifications to the discussed embodiments can be made by those skilled in the art without departing from the invention. Therefore, the invention is not limited to the specific embodiments disclosed herein.

[0037] This document describes, with reference to certain embodiments, the circuit features of a radio frequency level indicator (RFLI) circuit that provides excellent RF signal sampling performance. As discussed in more detail below, the RFLI circuit is capable of quickly sampling the RF input to determine whether the amplitude of the RF input exceeds a threshold. Furthermore, the RFLI circuit provides good sampling performance over a wide input bandwidth. Some features of the RFLI circuit are shown in the accompanying drawings. Figure 1 An embodiment of a receiver circuit with an LNA circuit is shown. Figure 2 and 3 An embodiment of an RF level indicator circuit and its function are shown. Figure 4 and 5 The variable delay sampling pulse generator and its functions are demonstrated. Figure 6-8 The variable clock delay circuit and its function are demonstrated.

[0038] Figure 1 This is a schematic diagram of an embodiment of receiver circuit 100, which includes a variable gain LNA circuit 110, a mixer 120 that receives oscillator signals from an oscillator (LO) 130, a low-pass filter (LPF) 140, a variable gain amplifier (VGA) 150, an analog-to-digital converter (ADC) 160, a controller 170, an RFLI circuit 180, and a gain control 190.

[0039] The variable gain low-noise amplifier 110 is configured to receive a high-frequency carrier signal modulated by a low-frequency information signal. The received signal may also include a blocking signal (such as an irrelevant signal) different from the information signal, having a frequency close to but outside the receiver's frequency bandwidth, wherein the irrelevant signal also modulates the high-frequency carrier signal. The blocking signal may have higher power than the information signal and may occur at any frequency. As will be understood by those skilled in the art, the variable gain low-noise amplifier 110 may have the characteristics of any low-noise amplifier or an amplifier with variable gain.

[0040] The RFLI circuit 180, discussed in further detail below, is configured to determine whether the minimum and / or maximum value of the output from the variable gain low-noise amplifier 110 exceeds a desired range threshold. In response to determining that the minimum and / or maximum value of the output from the variable gain low-noise amplifier 110 exceeds the desired range threshold, the RFLI circuit 180 generates an out-of-range signal for the gain control circuit 190.

[0041] At least for the reasons discussed below, the RFLI circuit 180 is able to quickly sample the RF input to determine whether the minimum and / or maximum values ​​of the output from the variable gain low-noise amplifier 110 exceed a desired range threshold. Additionally, at least for the reasons discussed below, the RFLI circuit 180 provides good sampling performance over a wide input bandwidth.

[0042] Therefore, the RFLI circuit 180 is particularly effective for determining whether the minimum and / or maximum values ​​of the output from the variable gain low noise amplifier 110 exceed a desired range threshold (e.g., due to a blocking signal), as the gain control circuit is able to quickly sample and modify the gain of the variable gain low noise amplifier 110, and has sampling performance that is independent or substantially independent of the frequency of the output of the variable gain low noise amplifier 110, at least for frequencies at or near the carrier signal.

[0043] For example, conventional methods for determining whether the minimum and / or maximum values ​​of the output from a variable gain low-noise amplifier exceed a desired range threshold can be slow, requiring, for example, hundreds of samples. Other conventional methods for determining whether the minimum and / or maximum values ​​of the output from the variable gain low-noise amplifier 110 exceed a desired range threshold fail for specific frequencies. This becomes particularly problematic for blocking signals with unknown frequencies.

[0044] Gain control 190 is configured to generate a gain control signal for low-noise amplifier 110. For example, in response to receiving an out-of-range signal from RFLI circuit 180, gain control circuit 190 can reduce the gain of variable gain low-noise amplifier 110.

[0045] For example, controller 170 can determine that RFLI circuitry 180 will be used to adjust the gain of variable gain low-noise amplifier 110. For example, controller 170 can determine that receiver circuitry 100 is receiving or will receive a packet with multiple preamble bits received before the payload data bits of the information packet. Controller 170 can cause RFLI circuitry 180 to detect whether the output of variable gain low-noise amplifier 110 has moved out of a desired range, for example, when variable gain low-noise amplifier 110 receives information encoded with the preamble bits. In some embodiments, once one or more preamble bits are received, controller 170 causes RFLI circuitry 180 to no longer affect gain control circuitry 190.

[0046] In some embodiments, a gain control loop including a variable gain low-noise amplifier 110, an RFLI circuit 180, and a gain control circuit 190 is capable of adjusting the gain of the variable gain low-noise amplifier 110 such that, by sampling 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 bits, the minimum and / or maximum values ​​of the output of the variable gain low-noise amplifier 110 do not exceed a desired range threshold. In some embodiments, the gain control loop is capable of adjusting the gain of the variable gain low-noise amplifier 110 such that, by sampling another number of bits, the minimum and / or maximum values ​​of the output of the variable gain low-noise amplifier 110 do not exceed a desired range threshold.

[0047] In some embodiments, each bit can be sampled multiple times. For example, depending on the difference between the sampling rate and the bit rate, each prep bit can be sampled approximately 3, 4, 5, 10, 15, 20, 25, 35, 50, 75, 100, or other times.

[0048] In some embodiments, the sampled bits are prep bits. In some embodiments, at least some bits are not prep bits. In some embodiments, at least some bits are data bits. At least as discussed above, rapid determination of the appropriate gain for the variable gain low-noise amplifier 110 is advantageous.

[0049] In some embodiments, gain control 190 receives input from sources other than RFLI circuit 180, and additionally generates gain control signals for low-noise amplifier 110 based on input from other sources, for example using circuit techniques understood by those skilled in the art.

[0050] In response to the output of the variable gain low noise amplifier 110 and the oscillator signal, the mixer 120 down-converts the signal from the variable gain low noise amplifier 110. The resulting baseband signal includes information from the low-frequency information signal.

[0051] As those skilled in the art will understand, the baseband signal is then processed by the low-pass filter 140.

[0052] As will be understood by those skilled in the art, the output of the low-pass filter 140 is then processed by the variable gain amplifier 150.

[0053] As those skilled in the art will understand, the output of the variable gain amplifier 150 is then processed by the analog-to-digital converter 160, which provides a digital representation of the information signal to the controller 170.

[0054] Alternatively or additionally, one or more additional level indicator circuits having features similar to or identical to those discussed herein with reference to RFLI circuit 180 may be used in receiver circuit 100. For example, as those skilled in the art will understand, one or more additional level indicator circuits may receive input signals from the outputs of mixer 120, low-pass filter 140, and variable gain amplifier 150, respectively, and may generate outputs that affect the gain of any of mixer 120, low-pass filter 140, and variable gain amplifier 150.

[0055] Figure 2 This is a schematic diagram of an embodiment of the RF level indicator circuit 200. The RF level indicator circuit 200 can be used as... Figure 1 The RFLI circuit 180. Other RF level indicator circuits with similar or identical characteristics to the RF level indicator circuit 200 can be used as... Figure 1 RFLI circuit 180.

[0056] The RF level indicator circuit 200 includes an input capacitor Cin, a bias resistor R, a sampling switch Sw, a sampling capacitor Cs, a high reference comparator 210, a low reference comparator 220, and a sampling clock generator 230.

[0057] As those skilled in the art will understand, the RF signal at node RFin is capacitively coupled to the input node of the sampling switch Sw, which is biased to the bias voltage at node Vcm via a bias resistor R.

[0058] As those skilled in the art will understand, based on the sampling clock signal at the gate of the sampling switch Sw, the sampling switch Sw selectively transmits the capacitively coupled RF signal to the node RFSamp. Furthermore, as those skilled in the art will understand, in response to the sampling clock signal that turns the sampling switch Sw off, the sampled voltage at the node RFSamp is kept substantially constant by the sampling capacitor Cs.

[0059] The sampling clock generator 230 receives the clock signal at node ClockIn. The frequency of the clock signal is equal to the nominal sampling frequency.

[0060] When the sampled voltage at node RFSamp is held by the sampling capacitor Cs, the comparator clock signal at node CompClk causes the high-reference comparator 210 to compare the sampled voltage at node RFSamp with the high reference voltage at node RefHigh. In response to the sampled voltage at node RFSamp being greater than the high reference voltage, the high-reference comparator 210 sets the voltage at output node OUTH high. In response to the sampled voltage at node RFSamp being less than the high reference voltage, the high-reference comparator 210 sets the voltage at output node OUTH low.

[0061] When the sampled voltage at node RFSamp is held by the sampling capacitor Cs, the comparator clock signal at node CompClk causes the low-reference comparator 220 to compare the sampled voltage at node RFSamp with the low-reference voltage at node RefLow. In response to the sampled voltage at node RFSamp being greater than the low-reference voltage, the low-reference comparator 220 sets the voltage at output node OUTL low. In response to the sampled voltage at node RFSamp being less than the low-reference voltage, the low-reference comparator 220 sets the voltage at output node OUTL high.

[0062] A high voltage at either the output nodes OUTH or OUTL indicates that the RF signal received at node RFin is out of range.

[0063] The high reference voltage can be generated using any circuit and is not limited thereto. In some embodiments, as those skilled in the art will understand, the high reference voltage is generated by a resistor ladder. In some embodiments, the high reference voltage is programmable. For example, controller 170 can cause one of a plurality of reference voltages, such as those generated by a resistor ladder, to be provided to node RefHigh as the high reference voltage.

[0064] The low reference voltage can be generated using any circuit and is not limited thereto. In some embodiments, as those skilled in the art will understand, the low reference voltage is generated by a resistive ladder. In some embodiments, the low reference voltage is programmable. For example, controller 170 can provide one of a plurality of reference voltages, such as those generated by a resistive ladder, to node RefLow as a low reference voltage.

[0065] In some embodiments, the resistance ladder for the high reference voltage may be the same resistance ladder as the resistance ladder for the low reference voltage, or an extension of the same resistance ladder. In some embodiments, the resistance ladders for both the high and low reference voltages also generate a bias voltage at node Vcm, wherein the bias voltage at node Vcm is the average of the high and low reference voltages.

[0066] Figure 3 It is a display Figure 2 The waveform diagram shows the function of the RF level indicator circuit.

[0067] The RF signal at node RFin is capacitively coupled to the input node of the sampling switch Sw. At time T1, the sampling clock signal at node Sample Clock causes the sampling switch Sw to transfer the capacitively coupled RF signal to node RFSamp. Additionally, at time T2, the sampling clock signal causes the sampling switch Sw to become non-conductive. Thereafter, the voltage at node RFSamp remains essentially constant through the sampling capacitor Cs.

[0068] When the sampled voltage at node RFSamp is held by the sampling capacitor Cs, at T3, the comparator clock signal at node CompClk causes the high reference comparator 210 to compare the sampled voltage at node RFSamp with the high reference voltage at node RefHigh. In response to the sampled voltage at node RFSamp being less than the high reference voltage, such as... Figure 3 As shown, the high reference comparator 210 sets the voltage at the output node OUTH to low.

[0069] When the sampled voltage at node RFSamp is held by the sampling capacitor Cs, at T3, the comparator clock signal at node CompClk causes the low-reference comparator 220 to compare the sampled voltage at node RFSamp with the low-reference voltage at node RefLow. In response to the sampled voltage at node RFSamp being less than the low-reference voltage, the low-reference comparator 220 sets the voltage at output node OUTL high.

[0070] A high voltage at the output node OUTL indicates that the RF signal received at node RFin is out of range.

[0071] As those skilled in the art will understand, because the RF signal at node RFI is periodic, if the sampling clock is also periodic, the sampled voltage at node RFSamp will also be periodic or DC. This is problematic for some ratios of the RF signal period to the sampling clock period. For example, for ratios equal to or approximately equal to integers, the sampled voltage at node RFSamp forms a DC or approximately DC signal, which may be insufficient to determine whether the RF signal is out of range. Other reasonable ratios may also provide sampled voltages at node RFSamp that are insufficient to determine whether the RF signal is out of range.

[0072] To reduce or eliminate the possibility of insufficient sampling voltage, in some embodiments, the sampling clock is generated to be non-periodic or non-periodic during the gain adjustment duration.

[0073] Figure 4 This is a schematic diagram of an embodiment of a variable delay sampling pulse generator 400. The variable delay sampling pulse generator 400 can be used as... Figure 2 The clock generator circuit 230. Other clock generator circuits can be used alternatively. Figure 2 Clock generator circuit 230.

[0074] The variable delay sampling pulse generator 400 includes a variable delay circuit 410, a delay circuit 420, an inverter 430, and an AND gate 440.

[0075] The variable-delay sampling pulse generator 400 receives the input clock signal at node ClockIn. The frequency of the input clock signal is equal to the nominal sampling frequency. For each cycle of the input clock signal, the variable-delay sampling pulse generator 400 generates a sampling pulse. However, as discussed below, the timing relationship between each generated sampling pulse and the specific input clock cycle that makes the sampling pulse is variable.

[0076] The variable delay circuit 410 receives the input clock signal at node ClockIn. The variable delay circuit 410 generates a delayed version of the input clock signal for the delay circuit 420 and AND gate 440. Non-limiting examples of the variable delay circuit 410 are discussed below.

[0077] The timing relationship between each specific period of the delayed version of the input clock signal and a specific input clock signal period that makes the delayed version of the input clock signal change. For example, a first time delay between the first input clock signal period and the first delayed input clock signal period is less than a second time delay between the second input clock signal period and the second delayed input clock signal period, for example, as referred to below. Figure 6-8 The example embodiments discussed herein.

[0078] Delay circuit 420 receives a delayed version of the input clock signal from variable delay circuit 410 and generates a further delayed version of the input clock signal for inverter 430. In some embodiments, the delay of delay circuit 420 is substantially constant. In some embodiments, as those skilled in the art will understand, the delay of delay circuit 420 is programmable, for example by a controller (such as controller 170), using techniques similar to or the same as those discussed elsewhere regarding variable delay circuit 410.

[0079] In some embodiments, the delay circuit 420 is programmable and has features similar to or the same as those discussed elsewhere regarding the variable delay circuit 410, and the variable delay circuit 410 is omitted, such that the input clock signal is provided to the programmable delay circuit 420 and to the AND gate 440.

[0080] In the illustrated embodiment, inverter 430 receives a further delayed version of the input clock signal from delay circuit 420 and generates an inverted clock signal for AND gate 440.

[0081] AND gate 440 receives a delayed version of the input clock signal from variable delay circuit 410 and an inverted clock signal from inverter 430. Based on the received delayed versions of the input clock signal and the inverted clock signal, AND gate 440 generates a sampling clock pulse at the output Sample Clock. As those skilled in the art will understand, AND gate 440 generates a sampling clock pulse at the output SampleClock for each rising edge of the delayed version of the input clock signal.

[0082] In some embodiments, inverter 430 is replaced by an AND gate configured to receive a further delayed version of the input clock signal from delay circuit 420 at one of its inputs and an enable signal from a controller (such as controller 170 of receiver circuit 100) at the other of its inputs.

[0083] In embodiments of the receiver circuit 100 using inverter 430, controller 170 can control an enable signal to selectively cause RFLI circuit 180 to sample the output of variable gain low noise amplifier 110 to detect whether the output of variable gain low noise amplifier 110 has moved out of a desired range, for example, when variable gain low noise amplifier 110 receives information encoded with a preamble. In these embodiments, after receiving one or more preambles, controller can control the enable signal so that RFLI circuit 180 no longer samples the output of variable gain low noise amplifier 110 to affect gain control circuit 190.

[0084] As will be understood by those skilled in the art, other pulse generator circuits with similar or identical features to the variable delay sampling pulse generator 400 may be used.

[0085] Figure 5 It is a display Figure 4 Waveform diagram of the function of the variable delay sampling pulse generator 400.

[0086] At time T1, the input clock signal at node ClockIn goes high.

[0087] Before time T2, the output of inverter 430 at node Inv is high because of the previous low state of the delayed version of the input clock signal at node DelayedClockIn.

[0088] After a first delay time D1 determined by the variable delay circuit 410, at time T2, the delayed version of the input clock signal at node DelayedClockIn goes high. Additionally, in response to the delayed version of the input clock signal at node DelayedClockIn going high, the sampling clock output goes high. Therefore, after a first delay time D1 following the input clock signal at node ClockIn going high, the sampling clock output goes high.

[0089] Then, as those skilled in the art will understand, a substantially fixed delay time D4 after time T2 occurs because the output of inverter 430 at node Inv turns low and the input clock signal at node ClockIn turns low due to the high state of the delayed version of the input clock signal at node DelayedClockIn. The substantially fixed delay time D4 is determined by the combined delay of delay circuit 420, inverter 430 and AND gate 440.

[0090] At time T3, the input clock signal at node ClockIn goes high again.

[0091] Before time T4, the output of inverter 430 at node Inv is high because of the previous low state of the delayed version of the input clock signal at node DelayedClockIn.

[0092] After a second delay time D2 determined by the variable delay circuit 410, at time T4, the delayed version of the input clock signal at node DelayedClockIn goes high. Additionally, in response to the delayed version of the input clock signal at node DelayedClockIn going high, the sampling clock output goes high. Therefore, at a second delay time D2 after the input clock signal at node ClockIn goes high, the sampling clock output goes high.

[0093] Then, as those skilled in the art will understand, at a substantially fixed delay time D4 after time T4, because of the high state of the delayed version of the input clock signal at node DelayedClockIn, the output of inverter 430 at node Inv goes low, and the input clock signal at node ClockIn goes low, wherein the substantially fixed delay time D4 is determined by the combined delay of delay circuit 420, inverter 430 and AND gate 440.

[0094] At time T5, the input clock signal at node ClockIn goes high again.

[0095] Before time T6, the output of inverter 430 at node Inv is high because of the previous low state of the delayed version of the input clock signal at node DelayedClockIn.

[0096] After a third delay time D3 determined by the variable delay circuit 410, at time T6, the delayed version of the input clock signal at node DelayedClockIn goes high. Additionally, in response to the delayed version of the input clock signal at node DelayedClockIn going high, the sampling clock output goes high. Therefore, at a third delay time D3 after the input clock signal at node ClockIn goes high, the sampling clock output goes high.

[0097] Then, as those skilled in the art will understand, at a substantially fixed delay time D4 after time T6, because of the high state of the delayed version of the input clock signal at node DelayedClockIn, the output of inverter 430 at node Inv goes low, and the input clock signal at node ClockIn goes low, wherein the substantially fixed delay time D4 is determined by the combined delay of delay circuit 420, inverter 430 and AND gate 440.

[0098] As shown, the first delay time D1, the second delay time D2, and the third delay time D3 are different, where delay time D2 > delay time D1 and delay time D3 > delay time D2.

[0099] Figure 6 This is a schematic diagram of an embodiment of the variable clock delay circuit 600. The variable clock delay circuit 600 can be used as the variable delay circuit 410 of the variable delay sampling pulse generator 400. In some embodiments, as those skilled in the art will understand, other variable clock delay circuits having similar or identical features to the variable clock delay circuit 600 can be used as the variable delay circuit 410 of the variable delay sampling pulse generator 400.

[0100] The variable clock delay circuit 600 receives the input clock signal at node ClockIn. The variable clock delay circuit 600 also generates a delayed version of the input clock signal at the output node DelayedClockIn based on the received input clock signal.

[0101] The variable clock delay circuit 600 includes a counter 610 and a delay selection circuit 620.

[0102] Counter 610 receives the input clock signal at node ClockIn. Counter 610 also generates a counting output for delay selection circuit 620 at node Cnt based on the received input clock signal. Counter 610 can have any features of a counter circuit known in the art and is not limited thereto. As those skilled in the art will understand, counter 610 can have multiple bits corresponding to the number of selectable delay circuits in delay selection circuit 620, as discussed in further detail below. For example, as those skilled in the art will understand, counter 610 can have three bits and delay selection circuit 620 can have eight selectable delay circuits.

[0103] The delay selection circuit 620 receives the input clock signal at node ClockIn and the count output from counter 610 at node Cnt. Additionally, the delay selection circuit 620 generates a delayed version of the input clock signal as the output clock at the output node DelayedClockIn, wherein the delay between the received input clock signal and the output clock is programmable and based on the count output of counter 610, for example, as described below. Figure 7 The delay selection circuit 700 is discussed.

[0104] Figure 7 This is a schematic diagram of an embodiment of the delay selection circuit 700. The delay selection circuit 700 can be used as the delay selection circuit 620 of the variable clock delay circuit 600. In some embodiments, as those skilled in the art will understand, other delay selection circuits having similar or identical features to the delay selection circuit 700 can be used as the delay selection circuit 620 of the variable clock delay circuit 600.

[0105] The delay selection circuit 700 includes N delay circuits 710 and a multiplexer circuit 720.

[0106] Each of the N delay circuits 710 receives the input clock signal at node ClockIn and generates a delayed version of the input clock signal based on the received input clock signal. Each of the N delayed versions of the input clock signal can be delayed for a different duration.

[0107] For example, delay circuit 1 can generate a delayed version of the input clock signal that is delayed by a first propagation delay time (such as approximately 1 ns), and delay circuit 2 can generate a delayed version of the input clock signal that is delayed by approximately 1%, approximately 2%, approximately 3%, approximately 4%, or approximately 5% more or less than the first propagation delay time of delay circuit 1. In some embodiments, the relationship between three or more consecutive or all different propagation delay times of the N delay circuits 710 is linear or approximately linear. In some embodiments, the relationship between three or more consecutive or all different propagation delay times of the N delay circuits 710 is not linear. In some embodiments, the relationship between three or more consecutive or all different propagation delay times of the N delay circuits 710 is logarithmic.

[0108] In some embodiments, the propagation delay of the delay circuit 710 with the longest propagation delay is less than half the period of the input clock signal at node ClockIn, which is less than half the propagation delay of the delay circuit 710 with the shortest propagation delay. In some embodiments, the propagation delay of the delay circuit 710 with the longest propagation delay is less than a quarter the period of the input clock signal at node ClockIn, which is less than the propagation delay of the delay circuit 710 with the shortest propagation delay.

[0109] Therefore, the sampling pulses of the sampling clock do not appear at periodic intervals. As a result, this set of sampled voltages is neither DC nor periodic. At least for reasons discussed elsewhere in this document, aperiodic sampling pulses are advantageous, for example, to ensure proper adjustment of the gain of the variable delay low-noise amplifier 110, e.g., when the variable delay low-noise amplifier 110 receives the preamplifier bit of the data packet and before the data payload of the data packet.

[0110] Each of the N delay circuits 710 may include an inverter or two or more inverters connected in series, wherein the total propagation delay of each of the N delay circuits 710 is different. In some embodiments, as those skilled in the art will understand, the propagation delay of the N delay circuits 710 is different because the respective inverters of the N delay circuits 710 have different sizes. In some embodiments, as those skilled in the art will understand, the propagation delay of the N delay circuits 710 is different because the respective inverters of the N delay circuits 710 have different capacitances. In some embodiments, as those skilled in the art will understand, the propagation delay of the N delay circuits 710 is different because the respective number of inverters of the N delay circuits 710 is different.

[0111] In an alternative embodiment, as those skilled in the art will understand, one or more delayed versions of the input clock signal are generated by a single delay line having multiple taps.

[0112] Multiplexer 720 receives each delayed version of the input clock signal from N delay circuits 710. Additionally, multiplexer 720 receives the count output from counter 610 at input node CountIn. Furthermore, as those skilled in the art will understand, multiplexer 720 generates an output clock at output node DelayedClockIn based on a selected delayed version of the input clock signal, wherein the selection of the delayed version among the delayed versions of the input clock signal is determined based on the count output at input node CountIn. Any multiplexer circuit can be used.

[0113] Figure 8 This is a waveform diagram demonstrating the function of the variable clock delay circuit 600 using the delay selection circuit 700.

[0114] At time T1, as the output of counter 610 at node Cnt equals 0, the input clock signal at node ClockIn goes high.

[0115] After the first delay time D1, at time T2, the delayed version of the input clock signal at node DelayedClockIn goes high. The specific first delay time D1 is determined by the delay selection circuit 620 based on the count output at node Cnt being equal to 0.

[0116] At time T3, as the counter 610's count output at node Cnt equals 0, the input clock signal at node ClockIn goes low. In response to the input clock signal at node ClockIn going low, counter 610 increments the count output at node Cnt to 1.

[0117] At time T4, as the output of counter 610 at node Cnt equals 1, the input clock signal at node ClockIn goes high.

[0118] After the second delay time D2, at time T5, the delayed version of the input clock signal at node DelayedClockIn goes high. The specific second delay time D2 is determined by the delay selection circuit 620 based on the count output at node Cnt being equal to 1.

[0119] At time T6, as the counter 610's count output at node Cnt equals 1, the input clock signal at node ClockIn goes low. In response to the input clock signal at node ClockIn going low, counter 610 increments the count output at node Cnt to 2.

[0120] At time T7, as the output of counter 610 at node Cnt equals 2, the input clock signal at node ClockIn goes high.

[0121] After the third delay time D3, at time T8, the delayed version of the input clock signal at node DelayedClockIn goes high. The specific third delay time D3 is determined by the delay selection circuit 620 based on the count output at node Cnt being equal to 2.

[0122] At time T9, as the counter 610's count output at node Cnt equals 2, the input clock signal at node ClockIn goes low. In response to the input clock signal at node ClockIn going low, counter 610 increments the count output at node Cnt to 3.

[0123] As shown, the first delay time D1, the second delay time D2, and the third delay time D3 are different, where delay time D2 > delay time D1 and delay time D3 > delay time D2.

[0124] As those skilled in the art will understand, this pattern continues until the counter reaches its maximum count value. Subsequently, as those skilled in the art will understand, the counter flips to a count value equal to 0, and the pattern repeats.

[0125] In the foregoing description and claims, phrases such as “at least one of…” or “one or more of…” may appear after a list of combinations of elements or features. The term “and / or” may also appear in a list of two or more elements or features. Unless implied or explicitly contradicted by the context in which it is used, such phrases are intended to mean any element or feature listed individually, or any of the listed elements or features combined with any other listed element or feature. For example, the phrases “at least one of A and B;”, “one or more of A and B;”, and “A and / or B” are all intended to mean “A alone, B alone, or A and B together.” A similar interpretation applies to lists comprising three or more items. For example, the phrases “at least one of A, B, and C;”, “one or more of A, B, and C;”, and “A, B, and / or C” are all intended to mean “A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together.” The term “based on” as used in the foregoing and claims is intended to mean “at least partially based on,” allowing for the inclusion of unlisted features or elements.

[0126] Depending on the desired configuration, the subject matter described herein can be embodied in systems, apparatus, methods, and / or articles of art. The embodiments given in the foregoing description do not represent all embodiments consistent with the subject matter described herein. Rather, they are merely some examples consistent with aspects related to the described subject matter. Although some variations have been described in detail above, other modifications or additions are possible. In particular, further features and / or variations may be provided in addition to those set forth herein. For example, the embodiments described above can be for various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several further features disclosed above. Furthermore, the logical flows depicted in the drawings and / or described herein do not necessarily require the specific order or sequence shown to achieve the desired results. Other embodiments are within the scope of the following claims.

Claims

1. A radio frequency (RF) receiver circuit, comprising: A variable gain amplifier configured to receive an input RF signal and generate an amplified RF signal based on the input RF signal, wherein the gain of the variable gain amplifier is variable; as well as An RF level indicator circuit is configured to sample the amplified RF signal at non-periodic sampling intervals to generate multiple sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate multiple comparison result signals. The gain of the variable gain amplifier is determined at least in part based on the comparison result signal; The receiver circuitry further includes a sampling clock generator configured to generate a sampling clock based on a periodic reference clock; wherein the RF level indicator circuitry is configured to generate the sampled RF signal in response to each pulse of a series of pulses of the sampling clock. The difference between the maximum duration from the first sampling time to the first subsequent consecutive sampling time and the minimum duration from the second sampling time to the second subsequent consecutive sampling time is less than 1 / 2 of the period of the periodic reference clock.

2. The receiver circuit as described in claim 1, wherein, In response to a comparison result signal indicating that the amplified RF signal is out of range, the gain of the variable gain amplifier is reduced.

3. The receiver circuit as described in claim 1, wherein, The sampling clock is non-periodic.

4. The receiver circuit as described in claim 1, wherein, The pulses of the sampling clock have substantially the same duration.

5. The receiver circuit as claimed in claim 1, further comprising: A mixer configured to receive the amplified RF signal and generate a baseband signal based on the amplified RF signal; A filter configured to receive the baseband signal and generate a filtered baseband signal based on the baseband signal from the mixer; An analog-to-digital converter configured to receive the filtered baseband signal and generate a digital version of the filtered baseband signal based on the filtered baseband signal; as well as A controller configured to receive the digital version of the filtered baseband signal.

6. The receiver circuit as described in claim 5, wherein, The controller is configured to selectively cause the RF level indicator circuit to generate the comparison result signal or not generate the comparison result signal.

7. The receiver circuit as described in claim 6, wherein, The controller is configured to selectively cause the RF level indicator circuit to generate the comparison result signal when the variable gain amplifier receives information that encodes one or more preamplifier bits of an information packet.

8. The receiver circuit as described in claim 7, wherein, The controller is configured to selectively prevent the RF level indicator circuit from generating the comparison result signal after the variable gain amplifier stops receiving information that encodes the preamplifier bit of the packet.

9. A method of using an RF receiver circuit, the RF receiver circuit including a variable gain amplifier and an RF level indicator circuit, wherein, The gain of the variable gain amplifier is variable, and the method includes: The variable gain amplifier is used to receive the input RF signal; The variable gain amplifier is used to generate an amplified RF signal based on the input RF signal; Using the aforementioned RF level indicator circuit, the amplified RF signal is sampled at non-periodic sampling intervals to generate multiple sampled RF signals; and Using the RF level indicator circuit, the sampled RF signal is compared with one or more thresholds to generate multiple comparison result signals. The gain of the variable gain amplifier is determined at least in part based on the comparison result signal; The RF receiver circuit further includes a sampling clock generator, and the method further includes: Using the sampling clock generator, a sampling clock is generated based on a periodic reference clock; and The sampled RF signal is generated using the RF level indicator circuit in response to each pulse of a series of pulses of the sampling clock. The difference between the maximum duration from the first sampling time to the first subsequent continuous sampling time and the minimum duration from the second sampling time to the second subsequent continuous sampling time is less than 1 / 2 of the period of the periodic reference clock.

10. The method of claim 9, further comprising reducing the gain of the variable gain amplifier in response to a comparison result signal indicating that the amplified RF signal is out of range.

11. The method of claim 9, wherein, The sampling clock is non-periodic.

12. The method of claim 9, wherein, The pulses of the sampling clock have substantially the same duration.

13. The method of claim 9, wherein, The RF receiver circuit further includes a mixer, a filter, an analog-to-digital converter, and a controller, and the method further includes: The amplified RF signal is received using the mixer. Using the mixer, a baseband signal is generated based on the amplified RF signal; The baseband signal is received using the filter. Using the filter, a filtered baseband signal is generated based on the baseband signal from the mixer; The filtered baseband signal is received using the analog-to-digital converter. Using the analog-to-digital converter, a digital version of the filtered baseband signal is generated based on the filtered baseband signal; and The controller is used to receive the digital version of the filtered baseband signal.

14. The method of claim 13, wherein the controller is used to selectively cause the RF level indicator circuit to generate the comparison result signal or not generate the comparison result signal.

15. The method of claim 14, wherein the controller is used to selectively cause the RF level indicator circuit to generate the comparison result signal when the variable gain amplifier receives information that encodes one or more preamplifier bits of an information packet.

16. The method of claim 15, wherein the controller selectively prevents the RF level indicator circuit from generating the comparison result signal after the variable gain amplifier no longer receives information encoding the preamplifier bit of the packet.

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