Wafer transverse impact testing device and wafer strength testing method

Abstract

A wafer transverse impact testing device and a wafer strength testing method are disclosed. The wafer transverse impact testing device includes a support base and an impactor. The wafer strength testing method includes a first preparation step and a first impact step. The first preparation step sets a wafer to be tested horizontally on the support base, and makes a pre-impact edge region of the wafer to be tested correspond to an impact port of the support base. The first impact step makes the impactor pass through the impact port along a predetermined plane perpendicular to a normal vector of the wafer to be tested, and impact the pre-impact edge region of the wafer to be tested, so as to make the wafer to be tested break into two half-wafers along a crystal direction. Each half-wafer includes a breakage edge parallel to the crystal direction. One of the beneficial effects of the present invention is that the wafer transverse impact testing device and the wafer strength testing method can impact the pre-impact edge region along the predetermined plane where the wafer to be tested is located, so as to test the testing strength required for the wafer to be tested to break along the crystal direction.

Description

TECHNICAL FIELD

[0001] The present application relates to a wafer testing device and a wafer testing method, in particular, to a wafer lateral impact testing device and a wafer strength testing method. BACKGROUND

[0002] As shown in Figure 1 , the known wafer strength testing device and wafer strength testing method are often used to test the mechanical strength of a single wafer in the direction perpendicular to the wafer surface (see Chinese Patent Publication No. CN105181462A and Figure 1 ), but this kind of test has gradually failed to meet the current wafer strength testing requirements. Therefore, how to overcome the above-mentioned defects through the structural design improvement of the wafer impact testing device or the design or improvement of the wafer strength testing method has become one of the important issues to be solved in this industry. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a wafer lateral impact testing device and a wafer strength testing method to improve the deficiencies of the prior art.

[0004] One embodiment of the present application discloses a wafer lateral impact testing device, comprising: a bearing seat having an impact port located on a predetermined plane; wherein the bearing seat is used to place a wafer to be tested flat on the predetermined plane, and the wafer to be tested defines a crystal direction through its center; and an impactor corresponding to the impact port is arranged, and the impactor can operate along the predetermined plane; wherein the impact direction of the impactor is parallel to the crystal direction; wherein when the wafer to be tested is placed flat on the bearing seat, the impactor can pass through the impact port along the predetermined plane and impact a pre-impact edge area of the wafer to be tested along the crystal direction, so that the wafer to be tested is broken into two half-wafers along the crystal direction; wherein the pre-impact edge area is the edge part of the wafer to be tested located at the impact port.

[0005] Preferably, the wafer lateral impact testing device further comprises a support frame movably mounted on the bearing seat, and the support frame can be used to abut and position a broken edge of any one of the half-wafers.

[0006] Preferably, the wafer lateral impact testing device further comprises a crystal direction sensor mounted on the bearing seat, and the crystal direction sensor and the impact port are respectively located on opposite sides of the bearing seat; wherein when the wafer to be tested is placed flat on the bearing seat, the crystal direction sensor can measure the crystal direction of the wafer to be tested along the predetermined plane.

[0007] Preferably, the impactor comprises an impact head facing the impact port, and an outer surface of the impact head is spherical to enable the impact head to impact the pre-impact edge region in a point contact manner.

[0008] Preferably, a radius of the impact head is greater than a thickness of the wafer under test.

[0009] Preferably, the carrier comprises a wafer stage forming the impact port and an impactor stage connected to the wafer stage, and the impactor is fixed to the impactor stage with the impact head being suspended.

[0010] Preferably, the wafer lateral impact testing device further comprises a force controller connected to the impactor, and the force controller is capable of controlling a force released by the impactor when the impactor is in operation.

[0011] One embodiment of the present application discloses a wafer strength testing method, comprising: a first preparation step of placing a wafer under test horizontally on a carrier with a pre-impact edge region of the wafer under test corresponding to an impact port of the carrier; wherein the wafer under test comprises a first crystal orientation and a second crystal orientation being non-parallel to the first crystal orientation; and a first impact step of impacting the pre-impact edge region of the wafer under test along the first crystal orientation by an impactor passing through the impact port along a predetermined plane perpendicular to a normal vector of the wafer under test to break the wafer under test into two half-wafers along the first crystal orientation; wherein an impact direction of the impactor is parallel to the first crystal orientation; wherein each of the half-wafers comprises a breakage edge parallel to the first crystal orientation, and the two half-wafers are defined as a first half-wafer and a second half-wafer respectively; and wherein the pre-impact edge region is an edge portion of the wafer under test located at the impact port.

[0012] Preferably, the wafer strength testing method further comprises: a second preparation step of placing the first half-wafer horizontally on the carrier with a support frame mounted on the carrier abutting and positioning the breakage edge of the first half-wafer to make a pre-impact edge region of the first half-wafer corresponding to the impact port of the carrier; wherein the second crystal orientation is located at the pre-impact edge region; and a second impact step of impacting the pre-impact edge region of the first half-wafer along the second crystal orientation by the impactor passing through the impact port along the predetermined plane to break the first half-wafer along the second crystal orientation.

[0013] Preferably, the wafer under test further comprises a third crystal orientation, and the third crystal orientation is not more than 90 degrees from the first crystal orientation and the second crystal orientation, respectively. The wafer strength testing method further comprises a third preparation step of placing the second wafer half flat on the support seat and using the support frame to abut and position the fractured edge of the second wafer half, so that a pre-strike edge region of the second wafer half corresponds to the strike opening of the support seat; and a third striking step of using the striker to strike the pre-strike edge region of the second wafer half along the third crystal orientation through the strike opening along the predetermined plane, so that the second wafer half is fractured along the third crystal orientation.

[0014] One of the advantages of the present application is that the wafer transverse striking testing device and wafer strength testing method can use the striker to strike the pre-strike edge region along the predetermined plane in which the wafer under test is located, so as to test the testing strength required for the wafer under test to be fractured along the crystal orientation.

[0015] For a more complete understanding of the features and technical content of the present application, please refer to the following detailed description of the present application and the accompanying drawings. However, these descriptions and drawings are only used to illustrate the present application, and do not limit the scope of protection of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 Schematic diagram of the operation of a known wafer strength testing device.

[0017] Figure 2 Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0018] Figure 3 Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0019] Figure 4 Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0020] Figure 5A Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0021] Figure 5B Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0022] Figure 6 Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0023] Figure 7 Schematic diagram of the wafer transverse striking testing device of the first embodiment of the present application.

[0024] Figure 8 A schematic view of the impactor of the first embodiment of the present application.

[0025] Figure 9 A schematic view of the impactor of the first embodiment of the present application. Figure 7 A schematic view of the impactor of the first embodiment of the present application.

[0026] Figure 10 A schematic view of the impactor of the first embodiment of the present application.

[0027] Figure 11 A schematic view of the impactor of the first embodiment of the present application.

[0028] Figure 12 A schematic view of the impactor of the first embodiment of the present application.

[0029] Figure 13A A schematic view of the impactor of the first embodiment of the present application.

[0030] Figure 13B A schematic view of the impactor of the first embodiment of the present application. DETAILED DESCRIPTION

[0031] The following is a detailed description of the application disclosed herein, which is presented only by way of illustration to enable a person skilled in the art to practice the application. The application can be practiced in a variety of embodiments and the details disclosed herein are not intended to limit the scope of the application. The drawings are not to scale and are intended only as illustrative representations of the structures described herein. The following detailed description is not intended to limit the scope of the application as described in the claims.

[0032] It should be understood that although the terms "first", "second", "third", etc. can be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein should be understood to mean a combination of any one or more of the associated listed items.

[0033] [First Embodiment]

[0034] Please refer to Figures 2 to 10As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application.

[0035] Referring to Figure 2 and Figure 3 As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application.

[0036] As Figure 2 and Figure 7 As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application.

[0037] As Figure 5A As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application. Figure 5B As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application.

[0038] As shown in the first embodiment of the present application, it is to be noted that the relevant quantities and shapes mentioned in the accompanying drawings are only used to specifically illustrate the embodiments of the present application, so as to facilitate the understanding of the content of the present application, and are not used to limit the protection scope of the present application.

[0039] It is to be noted that the wafer to be tested 200 is preferably an epitaxial wafer in the present embodiment. The size of the wafer to be tested 200 is preferably 6 inches, but the present embodiment is not limited thereto. For example, the wafer to be tested 200 can also be a polished wafer or other types of silicon wafers, and the size of the wafer to be tested 200 can also be 8 inches or 12 inches or other sizes.

[0040] As shown in Figure 3 and Figure 4 , the wafer carrier 11 has a bottom surface 112 in a circular shape, a side wall 113 arranged around the edge of the bottom surface 112, a plurality of bearing bumps 114 arranged at the edge of the bottom surface 112 and abutting against the side wall 113, and a mounting block 115 arranged on the side of the side wall 113 away from the plurality of bearing bumps 114. The predetermined plane 13 is located above the plurality of bearing bumps 114, and the impact port 111 is formed in the side wall 113. The plurality of bearing bumps 114 are located between the bottom surface 112 and the predetermined plane 13, and the bottom surface 112 and the predetermined plane 13 are parallel to each other. The mounting block 115 is used for locking and fixing the support frame 5, but the present application is not limited thereto.

[0041] It is to be noted that the bottom surface 112 has a thickness and a plurality of locking holes in the present embodiment, which are used to lock and fix with the impactor carrier 12. The edge of the bottom surface 112 adjacent to the impact port 111 is linear, and the number of locking holes is preferably 4, but the present application is not limited thereto. For example, in other embodiments not shown in the present application, the edge of the impact port 111 can also be in an arc shape, and the number of locking holes can also be more than 3.

[0042] As shown in Figure 3 and Figure 6 , the impactor carrier 12 is fixed with the impactor 2. The impactor carrier 12 has a recess 121 and a bearing portion 122. In more detail, one end of the recess 121 is connected with the wafer carrier 11 (inserted into the impact port 111 of the wafer carrier 11 and clamped to the bottom surface 112), and the other end of the recess 121 is connected with the bearing portion 122. It is to be noted that the impactor carrier 12 is integrally formed in the present embodiment. That is, there is no gap at the connection between the recess 121 and the bearing portion 122, but the present application is not limited thereto. For example, the impactor carrier 12 can also not be integrally formed, so that the recess 121 and the bearing portion 122 can be connected with each other in a combined manner.

[0043] More specifically, the recess 121 has an insertion plate 1211 and a support portion 1212 connected to the support portion 122. The insertion plate 1211 has multiple locking holes and is suspended above the ground relative to the support portion 1212, with the support portion 1212 and the support portion 122 forming a stepped structure. Further, the distance by which the support portion 1212 is suspended above the ground is approximately equal to the thickness of the bottom surface 112 of the wafer stage 11.

[0044] When the recessed portion 121 is inserted into the impact port 111, the insertion plate 1211 is located on the bottom surface 112 of the wafer stage 11, and the straight edge of the bottom surface 112 engages with the support portion 1212. A plurality of locking holes correspond to a plurality of locking holes on the bottom surface 112 and can be fixed together by a plurality of screws. Preferably, there are four locking holes, but the invention is not limited thereto. For example, in other embodiments not shown in this invention, the number of locking holes may be three or more.

[0045] like Figure 6 and Figure 7 As shown, the supporting part 122 is a cuboid and has an impactor supporting track 1221. The impactor supporting track 1221 is recessed from both ends of the supporting part 122 along its length, forming a long, recessed track. In this embodiment, the impactor supporting track 1221 preferably accommodates half the volume of the impactor 2, and the impactor supporting track 1221 has a recess 12211 for engaging and fixing the impactor 2; however, the invention is not limited thereto. For example, in other embodiments not shown in this invention, the impactor supporting track 1221 may also accommodate more than half the volume of the impactor 2.

[0046] like Figure 3 and Figure 10 As shown, the impactor 2 is disposed on the impactor stage 12 corresponding to the impact port 111, and the impactor 2 can operate along the predetermined plane 13 (e.g., the impactor 2 impacts the wafer 200 to be tested disposed on the predetermined plane 13). More specifically, when the wafer 200 to be tested is disposed flat on the support 1, the impactor 2 can pass through the impact port 111 along the predetermined plane 13 and impact the pre-impact edge region of the wafer 200 to be tested along the first crystal direction 201 (that is, the impact direction of the impactor 2 is parallel to the first crystal direction 201), so that the wafer 200 to be tested is broken into two half-wafers 204 and 205 along the first crystal direction 201.

[0047] like Figure 7 andFigure 8 As shown, the impactor 2 comprises an impact head 21 facing the impact port 111, and an impact rod 22 integrally formed with the impact head 21. The impact rod 22 is combined with the force controller 3. When the impactor 2 is disposed on the impactor stage 12, the impact head 21 and the impact rod 22 are in a suspended state.

[0048] The impact rod 22 is used to be pushed by the force controller 3, so as to make the impact head 21 impact the pre-impact edge region of the wafer under test 200. One end of the impact rod 22 is connected to the impact head 21, and the other end of the impact rod 22 is combined with the force controller 3. The impact path of the impact rod 22 is in line with the first crystal direction 201.

[0049] As shown in Figure 7 and Figure 9 The outer surface of the impact head 21 is spherical, so that the impact head 21 can keep impacting the pre-impact edge region (i.e. the impact point) of the wafer under test 200 in a point contact manner at the moment of impact. The impact point and the center of the impact head 21 are located on a straight line connecting the two ends of the impact rod 22. It should be noted that the radius of the impact head 21 is greater than the thickness of the wafer under test 200.

[0050] As shown in Figure 8 and Figure 10 The force controller 3 can be used to control the force released by the impactor 2 when operating. In more detail, the impactor 2 can control the impact force of the wafer under test 200 by the force controller 3, so as to accurately measure the strength of the wafer under test 200. In this embodiment, the force controller 3 can measure the strength value of the wafer under test 200 by increasing the impact force by 50 grams (g) each time. Figure 10 As shown, the force controller 3 first controls the impactor 2 to impact the wafer under test 200 with an impact force of 600 grams (g), and then increases the impact force by 50 grams (g) each time, until the force controller 3 controls the impactor 2 to impact the wafer under test 200 with an impact force of 700 grams (g) and the wafer under test 200 is broken, and the strength of the wafer under test 200 is also measured. However, the present application is not limited thereto, and the force controller 3 can adjust the impact force each time according to the needs of the operator, and is not limited to adjusting the impact force by 50 grams (g) each time.

[0051] As shown in Figure 8As shown, the force controller 3 includes a tension spring 31, a force scale indicator 32, and a hook 33. One end of the tension spring 31 is connected to the impact rod 22, and the other end is connected to the hook 33. The force scale indicator 32 is mounted on the hook 33. In this embodiment, the operator can use the hook 33 to stretch the tension spring 31 so that its length corresponds to a specific scale on the force scale indicator 32 to control the force when the tension spring 31 is released. However, the invention is not limited to this. For example, in other embodiments of the invention not shown, the force controller 3 can also be a gear-controlled electronic device that controls the impact force, and the gear-controlled electronic device further includes a device to prevent secondary collisions, which can prevent secondary collisions of the impactor 2 during impact from affecting the test results.

[0052] like Figure 4 As shown in Figure 5, the crystal orientation sensor 4 in this embodiment is an infrared sensor and there are three of them, but the present invention is not limited thereto. For example, in other embodiments of the present invention not shown, the number of crystal orientation sensors 4 may also be more than three. The crystal orientation sensor 4 is disposed on (or embedded in) the sidewall 113 of the wafer stage 11 and corresponds to the impact port 111. Further, the crystal orientation sensor 4 and the impact port 111 are located on opposite sides of the support 1. Wherein, when the wafer 200 to be tested is laid flat on the support 1, the crystal orientation sensor 4 can measure the first crystal orientation 201, the second crystal orientation 202, and the third crystal orientation 203 of the wafer 200 to be tested along the predetermined plane 13.

[0053] like Figure 7 and Figure 12 As shown, the support frame 5 has two locking fasteners 51, a support arm 52 locked by the two locking fasteners 51, and a push rod 53 disposed on the support arm 52. The push rod 53 can be used to abut and position a broken edge of any of the half-wafers 204 and 205 (for ease of explanation, the push rod 53 is...). Figure 12 (The fractured edge of the half-wafer 204 is positioned in the middle). It should be noted that, in this embodiment, the abutment rod 53 abuts against and positions the half-wafer 204, and the support frame 5 is locked and fixed to the mounting block 115 of the wafer stage 11 by any one of the locking fasteners 51, and the other locking fastener 51 is locked and fixed to the end of the support arm 52 that is relatively away from the mounting block 115. However, the present invention is not limited to this. For example, in other embodiments of the present invention not shown, the other locking fastener 51 and the abutment rod 53 may also be movable on the support arm 52 and then fixed according to the size of the half-wafer 204.

[0054] [Second Embodiment]

[0055] Referring to Figures 11 to 13B illustrated in the accompanying drawings, which is a second embodiment of the present application. It is to be noted that the second embodiment is similar to the first embodiment described above, and thus the same parts of the two embodiments will not be described again. Furthermore, the related quantities and shapes mentioned in the accompanying drawings of the second embodiment are used only to specifically describe the embodiments of the present application, so as to make the content of the present application clear, but not to limit the protection scope of the present application.

[0056] The present embodiment discloses a wafer strength test method, which can perform wafer strength test on the same wafer at least three times. As shown in Figure 11 the wafer strength test method comprises the following steps in sequence: a first preparation step S1, a first impact step S2, a second preparation step S3, a second impact step S4, a third preparation step S5, and a third impact step S6. The first wafer strength test is performed by the first preparation step S1 and the first impact step S2, the second wafer strength test is performed by the second preparation step S3 and the second impact step S4, and the third wafer strength test is performed by the third preparation step S5 and the third impact step S6.

[0057] It is to be noted that the wafer strength test method in the present embodiment is implemented by the wafer transverse impact test device 100 in the first embodiment described above, and thus the description of the wafer transverse impact test device 100 in the present embodiment also refers to the first embodiment and the drawings thereof. Figures 2 to 10 However, the wafer strength test method of the present application is not limited to be implemented by the wafer transverse impact test device 100.

[0058] The first preparation step S1: the wafer under test 200 is placed horizontally on the wafer stage 11 of the carrier seat 1, and the pre-impact edge area of the wafer under test 200 corresponds to the impact port 111 of the carrier seat 1 for impact by the impactor 2. The wafer under test 200 has the first crystal direction 201 and the second crystal direction 202 and the third crystal direction 203 which are formed at an angle of not more than 90 degrees with the first crystal direction 201, but the present application is not limited thereto. For example, as shown in Figure 5B the wafer under test 200 can only include the first crystal direction 201 and the second crystal direction 202 which is formed at an angle of not parallel with the first crystal direction 201.

[0059] The first impact step S2: the impactor 2 passes through the impact port 111 along the predetermined plane 13 perpendicular to the normal vector of the wafer to be tested 200, and impacts the pre-impact edge region of the wafer to be tested 200 along the first crystal direction 201, and the first crystal direction 201 is located at the pre-impact edge region, so that the wafer to be tested 200 is broken into two half-wafers 204, 205 along the first crystal direction 201. Wherein the impact direction of the impactor 2 is parallel to the first crystal direction 201. Wherein the two half-wafers 204, 205 formed by the breaking of the wafer to be tested 200 are arranged in mirror symmetry with each other. Each of the half-wafers 204, 205 contains a broken edge parallel to the first crystal direction 201, and the two half-wafers 204, 205 are defined as a first half-wafer 204 and a second half-wafer 205 respectively.

[0060] As shown in Figure 12 and Figure 13A The second preparation step S3: the first half-wafer 204 is placed flat on the wafer carrier 1 (the wafer carrier 11), and the support frame 5 mounted on the wafer carrier 1 abuts and positions the broken edge of the first half-wafer 204, so that a pre-impact edge region of the first half-wafer 204 corresponds to the impact port 111 of the wafer carrier 1. Wherein part of the pre-impact edge region abuts the side wall 113 of the wafer carrier 11.

[0061] The second impact step S4: the impactor 2 passes through the impact port 111 along the predetermined plane 13, and impacts the pre-impact edge region of the first half-wafer 204 along the second crystal direction 202, and the second crystal direction 202 is located at the pre-impact edge region, so that the first half-wafer 204 is broken along the second crystal direction 202. Wherein the impact path of the impactor 2 is in line with the second crystal direction 202, and the impact force of the impactor 2 in the second impact step S4 is different from the impact force of the impactor 2 in the first impact step S2.

[0062] As shown in Figure 12 and Figure 13B The third preparation step S5: the second half-wafer 205 is placed flat on the wafer carrier 1 (the wafer carrier 11), and the support frame 5 abuts and positions the broken edge of the second half-wafer 205, so that a pre-impact edge region of the second half-wafer 205 corresponds to the impact port 111 of the wafer carrier 1. Wherein part of the pre-impact edge region abuts the side wall 113 of the wafer carrier 11.

[0063] The third impact step S6: the impactor 2 passes through the impact port 111 along the predetermined plane 13 and impacts the pre-impact edge region of the second wafer half 205 along the third crystal direction 203, and the third crystal direction 203 is located at the pre-impact edge region, so that the second wafer half 205 is fractured along the third crystal direction 203. Wherein, the impact path of the impactor 2 is in line with the third crystal direction 203, and the impact force of the impactor 2 in the third impact step S6 is different from the impact force of the impactor 2 in the first impact step S2 and the second impact step S4.

[0064] [Advantages of the embodiments]

[0065] One of the advantages of the present application is that the wafer transverse impact test device and wafer strength test method can impact the impactor along the predetermined plane where the wafer to be tested is located, so as to test the test strength required for the wafer to be tested to be fractured along the crystal direction.

[0066] Furthermore, the wafer transverse impact test device and wafer strength test method provided by the present application can improve the test frequency of the wafer transverse impact test device and greatly save the time and cost required by the wafer strength test method through the technical solutions of "the carrier seat with the impact port located on the predetermined plane and the impactor corresponding to the impact port", "laying the wafer to be tested on the carrier seat in the first preparation step, and making the pre-impact edge region of the wafer to be tested correspond to the impact port of the carrier seat", and "passing through the impact port along the predetermined plane perpendicular to the normal vector of the wafer to be tested, and impacting the pre-impact edge region of the wafer to be tested in the first impact step, so as to fracture the wafer to be tested into two wafer halves along the first crystal direction".

[0067] The above disclosure is only the preferred feasible embodiments of the present application, and is not limited by the claims of the present application, so any equivalent technical changes made according to the content of the present application and the drawings are included in the claims of the present application.

Claims

1. A wafer lateral impact testing device, characterized by, The wafer transverse impact testing device comprises: a supporting base having an impact opening on a predetermined plane; wherein the supporting base is used to place a wafer to be tested horizontally on the predetermined plane, and the wafer to be tested is defined with a crystal direction through its center; a crystal direction sensor installed on the supporting base; a supporting frame movably installed on the supporting base; and an impactor corresponding to the impact opening and capable of operating along the predetermined plane; wherein the impact direction of the impactor is parallel to the crystal direction; wherein when the wafer to be tested is placed horizontally on the supporting base, the crystal direction sensor and the impact opening are respectively located on opposite sides of the supporting base, the crystal direction sensor can measure the crystal direction of the wafer to be tested along the predetermined plane, and the impactor can pass through the impact opening along the predetermined plane and impact a pre-impact edge region of the wafer to be tested along the crystal direction, so that the wafer to be tested is broken into two wafer halves along the crystal direction; wherein the pre-impact edge region is an edge portion of the wafer to be tested located at the impact opening; wherein the supporting frame can be used to abut and position a broken edge of any one of the wafer halves; The wafer transverse impact testing device further comprises a force controller connected to the impactor, and the force controller can be used to control the force released by the impactor when operating.

2. The wafer lateral impact testing device of claim 1, wherein, The impactor comprises an impact head facing the impact opening, and the outer surface of the impact head is spherical, so that the impact head can be used to impact the pre-impact edge region in a point contact manner.

3. The wafer lateral impact testing device of claim 2, wherein, The radius of the impact head is greater than the thickness of the wafer to be tested.

4. The wafer lateral impact testing device of claim 2, wherein, The supporting base comprises a wafer table forming the impact opening and an impactor table connected to the wafer table, and the impactor is fixed to the impactor table, and the impact head is in a suspended state.

5. A wafer strength test method, characterized by, The wafer strength testing method comprises: a first preparation step: placing a wafer to be tested horizontally on a supporting base, and making a pre-impact edge region of the wafer to be tested correspond to an impact opening of the supporting base; wherein the wafer to be tested comprises a first crystal direction and a second crystal direction which is non-parallel to the first crystal direction; wherein when the wafer to be tested is placed horizontally on the supporting base, a crystal direction sensor installed on the supporting base can measure the first crystal direction and the second crystal direction of the wafer to be tested along a predetermined plane, and the crystal direction sensor and the impact opening are respectively located on opposite sides of the supporting base; a first impact step: passing through the impact opening along the predetermined plane perpendicular to the normal vector of the wafer to be tested with an impactor, and impacting the pre-impact edge region of the wafer to be tested along the first crystal direction, so that the wafer to be tested is broken into two wafer halves along the first crystal direction; wherein the impact direction of the impactor is parallel to the first crystal direction; wherein each of the wafer halves comprises a fractured edge parallel to the first crystal orientation, and the two wafer halves are defined as a first wafer half and a second wafer half, respectively; wherein the pre-strike edge region is an edge portion of the wafer under test located at the impact port of the carrier seat; a second preparation step of placing the first wafer half flat on the carrier seat with a support frame mounted on the carrier seat abutting and positioning the fractured edge of the first wafer half such that a pre-strike edge region of the first wafer half corresponds to the impact port of the carrier seat; wherein the second crystal orientation is located at the pre-strike edge region; and a second impact step of impacting the pre-strike edge region of the first wafer half along the second crystal orientation with the impactor along the predetermined plane through the impact port to fracture the first wafer half along the second crystal orientation.

6. The wafer strength test method of claim 5, wherein, The wafer under test further comprises a third crystal orientation, and the third crystal orientation is respectively included at an angle of no more than 90 degrees with the first crystal orientation and the second crystal orientation, and the wafer strength test method further comprises: a third preparation step of placing the second wafer half flat on the carrier seat with the support frame abutting and positioning the fractured edge of the second wafer half such that a pre-strike edge region of the second wafer half corresponds to the impact port of the carrier seat; and a third impact step of impacting the pre-strike edge region of the second wafer half along the third crystal orientation with the impactor along the predetermined plane through the impact port to fracture the second wafer half along the third crystal orientation.

Images