Display device

Abstract

A display device includes a display panel including a plurality of pixels, a plurality of data lines extending in a first direction and connected to the plurality of pixels, a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels, and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines, a data driver to supply data voltages to the plurality of pixels through the plurality of data lines, and a scan driver to sequentially supply scan signals to the plurality of pixels in a row unit through the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip to output the data voltages and the scan signals.

Description

Technical Field

[0001] The present invention relates to a display device, and more specifically, to a display device including a data-scanning integrated chip. Background Technology

[0002] The display device includes: a display panel including a plurality of pixels; a scan driver that provides a scan signal to pixels in a selected row of the plurality of pixels via a selected scan line; and a data driver that provides a data voltage to the pixels in the selected row via a plurality of data lines. The pixels in the selected row may store the data voltage provided by the data driver during receiving the scan signal provided by the scan driver, and emit light based on the stored data voltage.

[0003] Typically, the scan driver is configured on at least one first side of the display panel, and the data driver is configured on at least one second side of the display panel, different from the first side. This limits the ability to reduce the bezel width of the display panel. Summary of the Invention

[0004] One object of the present invention is to provide a display device in which a data driver and a scan driver are disposed on the same side of a display panel and implemented as a data-scan integrated chip.

[0005] However, the technical problem to be solved by the present invention is not limited to the technical problem mentioned above, and various extensions can be made without exceeding the scope of the concept and field of the present invention.

[0006] To achieve an objective of the present invention, a display device according to an embodiment of the present invention includes: a display panel, comprising: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines; a data driver providing data voltage to the plurality of pixels via the plurality of data lines; and a scan driver providing scan signals sequentially to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signals.

[0007] In one embodiment, at least one of the plurality of data lines may be arranged between two adjacent pairs of the plurality of second scan lines.

[0008] In one embodiment, the data-scan integrated chip may include: a plurality of data output pads connected to the plurality of data lines; and a plurality of scan output pads connected to the plurality of second scan lines.

[0009] In one embodiment, at least one of the plurality of data output pads may be arranged between two adjacent scan output pads.

[0010] In one embodiment, the data-scanning integrated chip may output the data voltage related to the pixels of the row selected from the plurality of pixels to the plurality of data lines in a first interval, and in a second interval following the first interval, the data-scanning integrated chip may float the plurality of data lines and output the scan signal to the second scan line corresponding to the selected row among the plurality of second scan lines.

[0011] In one embodiment, the data voltage may be charged to the plurality of data lines during the first interval, and the data voltage charged to the plurality of data lines may be stored in the pixel of the selected row during the second interval.

[0012] In one embodiment, the data-scan integrated chip may include: a first shift register for generating a sampling signal based on a data clock signal; a latch array for storing image data in response to the sampling signal; a first level shifter array for shifting the voltage level of the latch output signal output from the latch array; a digital-to-analog converter array for performing digital-to-analog conversion on the shifter output signal output from the first level shifter array; a first output buffer array for outputting the converter output signal output from the digital-to-analog converter array as the data voltage; a plurality of data output pads connected to the plurality of data lines; a data output switch array for selectively connecting the first output buffer array to the plurality of data output pads in response to a selection signal; a second shift register for generating the scan signal based on a scan clock signal; a second level shifter array for shifting the voltage level of the scan signal output from the second shift register; a second output buffer array for outputting the scan signal output from the second level shifter array; and a plurality of scan output pads connected to the second output buffer array and the plurality of second scan lines.

[0013] In one embodiment, the data-scan integrated chip may include at least one component shared by the data driver and the scan driver.

[0014] In one embodiment, the data-scan integrated chip may include a first shift register, a latch array, a digital-to-analog converter array, and a first output buffer array for the data driver, and a second shift register and a second output buffer array for the scan driver, and further includes a shared level shifter array shared by the data driver and the scan driver.

[0015] In one embodiment, the shared level shifter array may include: a plurality of level shifters; a shifter input switch array that connects the output terminal of the latch array to the input terminal of the plurality of level shifters in response to a selection signal, and connects the output terminal of the second shift register to the input terminal of the plurality of level shifters in response to an inverse selection signal; and a shifter output switch array that connects the output terminals of the plurality of level shifters to the input terminal of the digital-to-analog converter array in response to the selection signal, and connects the output terminals of the plurality of level shifters to the input terminal of the second output buffer array in response to the inverse selection signal.

[0016] In one embodiment, the shared level shifter array may further include: a first shifter high power switch, which transmits a data shifter high power supply voltage to the high power line of the shared level shifter array in response to the selection signal; a second shifter high power switch, which transmits a scan shifter high power supply voltage to the high power line of the shared level shifter array in response to the inverse selection signal; a first shifter low power switch, which transmits a data shifter low power supply voltage to the low power line of the shared level shifter array in response to the selection signal; and a second shifter low power switch, which transmits a scan shifter low power supply voltage to the low power line of the shared level shifter array in response to the inverse selection signal.

[0017] In one embodiment, the data-scan integrated chip may include a first shift register, a latch array, a first level shifter array, and a digital-to-analog converter array for the data driver, and a second shift register and a second level shifter array for the scan driver, and further include a shared output buffer array shared by the data driver and the scan driver.

[0018] In one embodiment, the data-scan integrated chip may further include: a plurality of data output pads connected to the plurality of data lines; and a plurality of scan output pads connected to the plurality of second scan lines. The shared output buffer array includes: a plurality of output buffers; a buffer input switch array that connects the output terminal of the digital-to-analog converter array to the input terminal of the plurality of output buffers in response to a selection signal, and connects the output terminal of the second level shifter array to the input terminal of the plurality of output buffers in response to an inverted selection signal; and a buffer output switch array that connects the output terminals of the plurality of output buffers to the plurality of data output pads in response to the selection signal, and connects the output terminals of the plurality of output buffers to the plurality of scan output pads in response to the inverted selection signal.

[0019] In one embodiment, the voltage level of the high power supply voltage of the plurality of output buffers may be determined as the voltage level of the higher voltage among the high power supply voltage of the data buffer and the high power supply voltage of the scan buffer, and the voltage level of the low power supply voltage of the plurality of output buffers may be determined as the voltage level of the lower voltage among the low power supply voltage of the data buffer and the low power supply voltage of the scan buffer.

[0020] In one embodiment, the data-scan integrated chip may include a first shift register, a latch array, and a digital-to-analog converter array for the data driver, and a second shift register for the scan driver, and further include a shared level shifter array and a shared output buffer array shared by the data driver and the scan driver.

[0021] In one embodiment, the data-scan integrated chip may further include: a plurality of data output pads connected to the plurality of data lines; and a plurality of scan output pads connected to the plurality of second scan lines. The shared level shifter array includes: a plurality of level shifters; a shifter input switch array that, in response to a selection signal, connects the output terminal of the latch array to the input terminal of the plurality of level shifters, and in response to an inverted selection signal, connects the output terminal of the second shift register to the input terminal of the plurality of level shifters; and a shifter output switch array that, in response to the selection signal, connects the output terminal of the plurality of level shifters to the input terminal of the digital-to-analog converter array, and in response to the inverted selection signal, connects the output terminal of the second shift register to the input terminal of the plurality of level shifters. The output terminals of the plurality of level shifters are connected to the input terminals of the shared output buffer array, the shared output buffer array comprising: a plurality of output buffers; a buffer input switch array that, in response to the selection signal, connects the output terminals of the digital-to-analog converter array to the input terminals of the plurality of output buffers, and in response to the inverse selection signal, connects the output terminals of the shared level shifter array to the input terminals of the plurality of output buffers; and a buffer output switch array that, in response to the selection signal, connects the output terminals of the plurality of output buffers to the plurality of data output pads, and in response to the inverse selection signal, connects the output terminals of the plurality of output buffers to the plurality of scan output pads.

[0022] To achieve an objective of the present invention, a display device according to an embodiment of the present invention includes: a display panel, comprising: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines; a data driver providing data voltage to the plurality of pixels via the plurality of data lines; and a scan driver providing scan signals sequentially to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signals. The data-scan integrated chip includes at least one component shared by the data driver and the scan driver.

[0023] In one embodiment, the at least one component may include a shared level shifter array shared by the data driver and the scan driver.

[0024] In one embodiment, the at least one component may include a shared output buffer array shared by the data driver and the scan driver.

[0025] In one embodiment, the at least one component may include a shared level shifter array and a shared output buffer array shared by the data driver and the scan driver.

[0026] (The effect of the invention)

[0027] In a display device according to an embodiment of the present invention, the data driver and the scan driver can be configured on the same side of the display panel. This allows for a reduction in the bezel width of the display panel.

[0028] Furthermore, in the display device according to an embodiment of the present invention, the data driver and the scan driver can be implemented as a data-scan integrated chip. This allows for a reduction in the chip size or IC size of the chip or integrated circuit used to drive the display panel.

[0029] Furthermore, in the display device according to embodiments of the present invention, the data-scan integrated chip may include at least one component shared by the data driver and the scan driver (e.g., a level shifter array and / or an output buffer array). This allows for a further reduction in the chip size or IC size of the chip or IC used to drive the display panel, and also reduces power consumption.

[0030] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the concept and scope of the present invention. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0032] Figure 2 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment of the present invention.

[0033] Figure 3 This is a diagram illustrating an example of a display panel included in a display device according to an embodiment of the present invention.

[0034] Figure 4 This is a diagram illustrating another example of a display panel included in a display device according to an embodiment of the present invention.

[0035] Figure 5 This is a diagram illustrating an example of at least one data-scanning integrated chip connected to a display panel.

[0036] Figure 6 This is another example illustrating that at least one data-scanning integrated chip is connected to a display panel.

[0037] Figure 7 This is a block diagram illustrating a data-scan integrated chip according to an embodiment of the present invention.

[0038] Figure 8 This is a timing diagram illustrating an example of the operation of a data-scan integrated chip according to an embodiment of the present invention.

[0039] Figure 9 This is a block diagram illustrating a data-scan integrated chip according to another embodiment of the present invention.

[0040] Figure 10 This is a circuit diagram illustrating an example of a level shifter included in a data-scan integrated chip according to an embodiment of the present invention.

[0041] Figure 11 This is a timing diagram illustrating an example of the operation of a data-scan integrated chip according to an embodiment of the present invention.

[0042] Figure 12 This is a block diagram illustrating a data-scan integrated chip according to yet another embodiment of the present invention.

[0043] Figure 13 This is a block diagram illustrating an example of an output buffer included in a data-scan integrated chip according to an embodiment of the present invention.

[0044] Figure 14 This is a block diagram illustrating a data-scan integrated chip according to yet another embodiment of the present invention.

[0045] Figure 15 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0046] (Explanation of reference numerals in the attached diagram)

[0047] 100: Display device

[0048] 110, 110a, 110b: Display panels

[0049] 120, 210, 610: Data drives

[0050] 130, 260, 660: Scan driver

[0051] 150, 151, 152, 154, 200, 400, 500, 600: Data-Scanning Integrated Chips

[0052] 170: Controller

[0053] 290: Data Output Switch Array

[0054] 310, 410, 510, 710: First shift register

[0055] 320, 420, 520, 720: Latch arrays

[0056] 330, 530: First level shifter array

[0057] 340, 440, 540, 730: Digital-to-Analog Converter Arrays

[0058] 350, 450: First output buffer array

[0059] 360, 460, 560, 750: Second shift register

[0060] 370, 570: Second level shifter array

[0061] 380, 480: Second output buffer array

[0062] 490, 770: Shared level shifter array

[0063] 590, 790: Shared output buffer array Detailed Implementation

[0064] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

[0065] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 2 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment of the present invention. Figure 3 This figure illustrates an example of a display panel included in a display device according to an embodiment of the present invention. Figure 4 This figure illustrates another example of a display panel included in a display device according to an embodiment of the present invention. Figure 5 This diagram illustrates an example of at least one data-scanning integrated chip connected to a display panel. Figure 6 This is another example illustrating that at least one data-scanning integrated chip is connected to a display panel.

[0066] Reference Figure 1According to an embodiment of the present invention, the display device 100 may include: a display panel 110 including a plurality of pixels PX; a data driver 120 providing a data voltage DV to the plurality of pixels PX; a scan driver 130 providing a scan signal SCAN to the plurality of pixels PX; and a controller 170 controlling the data driver 120 and the scan driver 130.

[0067] The display panel 110 may include: a plurality of pixels PX; a plurality of data lines DL connected to the plurality of pixels PX; a plurality of first scan lines HSL connected to the plurality of pixels PX; and a plurality of second scan lines VSL connected to the plurality of first scan lines HSL. The plurality of data lines DL may extend in a first direction, the plurality of first scan lines HSL may extend in a second direction different from the first direction, and the plurality of second scan lines VSL may extend in the first direction. In one embodiment, the first direction may be a vertical direction, and the plurality of second scan lines VSL may be a plurality of vertical scan lines VSL; the second direction may be a horizontal direction, and the plurality of first scan lines HSL may be a plurality of horizontal scan lines HSL, but this is not limited to this. Hereinafter, an example will be described where the first direction is the vertical direction and the second direction is the horizontal direction, where the first scan lines HSL are named horizontal scan lines HSL, and the second scan lines VSL are named vertical scan lines VSL.

[0068] In one embodiment, the display panel 110 may be an OLED display panel in which each pixel PX includes an organic light-emitting diode (OLED). For example, such as Figure 2 As shown, each pixel PX may include a driving transistor TDR, a switching transistor TSW, a storage capacitor CST, and an organic light-emitting diode EL.

[0069] The storage capacitor CST can store the data voltage DV transmitted via the data line DL. In one embodiment, the storage capacitor CST may have: a first electrode connected to the gate of the driving transistor TDR; and a second electrode connected to the source of the driving transistor TDR.

[0070] The switching transistor TSW can respond to the scan signal SCAN received from the scan driver 130 via the vertical scan line VSL and the horizontal scan line HSL, and transfer the data voltage DV of the data line DL to the first electrode of the storage capacitor CST. In one embodiment, in a first interval, the data driver 120 outputs the data voltage DV to the data line DL, and the data line DL and / or the parasitic capacitor CDL of the data line DL are charged to have the data voltage DV. In a second interval after the first interval, the data line DL is floated, the switching transistor TSW transfers the data voltage DV charged in the data line DL, and the storage capacitor CST stores the data voltage DV. In another embodiment, the switching transistor TSW may have: a gate for receiving the scan signal SCAN; a drain connected to the data line DL; and a source connected to the first electrode of the storage capacitor CST and the gate of the driving transistor TDR.

[0071] The driving transistor TDR can generate a driving current based on the data voltage DV stored in the storage capacitor CST. In one embodiment, the driving transistor TDR may have: a gate, connected to the first electrode of the storage capacitor CST; a drain, receiving a first power supply voltage (e.g., a high power supply voltage) ELVDD; and a source, connected to the second electrode of the storage capacitor CST.

[0072] An organic light-emitting diode (OLED) EL can emit light in response to the drive current generated by a drive transistor TDR. In one embodiment, the OLED EL may have: a positive terminal connected to the source of the drive transistor TDR; and a negative terminal receiving a second power supply voltage (e.g., a low power supply voltage) ELVSS.

[0073] On the other hand, despite Figure 2 The illustration shows an example where each pixel PX has a 2T1C structure, but the pixel PX according to embodiments of the present invention is not limited to... Figure 2 The exemplary structure shown can have various structures.

[0074] In another embodiment, the display panel 110 may be a liquid crystal display (LCD) panel in which each pixel PX includes a switching transistor and a liquid crystal capacitor connected to the switching transistor. However, the display panel 110 is not limited to the LCD panel and the OLED panel, and may be any display panel.

[0075] In one embodiment, the plurality of horizontal scan lines HSL and the plurality of vertical scan lines VSL can be connected one-to-one, but are not limited thereto. For example, the number of the plurality of horizontal scan lines HSL can be the same as the number of the plurality of vertical scan lines VSL, but are not limited thereto.

[0076] Figure 3 An example of a display panel 110a is shown to illustrate an example of the configuration of multiple data lines DL, multiple horizontal scan lines HSL, and multiple vertical scan lines VSL. The display panel 110a may include N (N is an integer greater than 2) data lines DL1, DL2, DL3, DL4, DL5, DL6, ..., DLN-5, DLN-4, DLN-3, DLN-2, DLN-1, DLN, M (M is an integer greater than 2) horizontal scan lines HSL1, HSL2, ..., HSLM-1, HSLM, and M vertical scan lines VSL1, VSL2, ..., VSLM-1, VSLM. The M horizontal scan lines HSL1 to HSLM may extend in the horizontal direction, and the N data lines DL1 to DLN and the M vertical scan lines VSL1 to VSLM may extend parallel to each other in the vertical direction. In one embodiment, at least one of the N data lines DL1 to DLN may be arranged between two adjacent pairs of the M vertical scan lines VSL1 to VSLM. For example, fourth, fifth, and sixth data lines DL4, DL5, and DL6 can be arranged between the first vertical scan line VSL1 and the second vertical scan line VSL2, and N-2, N-1, and N data lines DLN-2, DLN-1, and DLN can be arranged between the M-1 vertical scan line VSLM-1 and the M vertical scan line VSLM. On the other hand, Figure 3 The example shown illustrates three data lines (e.g., DL4, DL5, DL6) configured between two adjacent vertical scan lines (e.g., VSL1, VSL2), but the number of data lines configured between two adjacent vertical scan lines is not limited to this. Figure 3 Examples.

[0077] In one embodiment, M horizontal scan lines HSL1 to HSLM may be disposed on a first layer, and M vertical scan lines VSL1 to VSLM may be disposed on a second layer different from the first layer. The M horizontal scan lines HSL1 to HSLM and the M vertical scan lines VSL1 to VSLM may be connected respectively through M contact holes. For example, as shown... Figure 3 As shown, the first to the Mth horizontal scan lines HSL1 to HSLM can be connected to the first to the Mth vertical scan lines VSL1 to VSLM, respectively. In this case, the M contact holes can be arranged diagonally within the display panel 110a, but are not limited thereto.

[0078] Figure 4 Another example of a display panel 110b is shown, illustrating another example of the connection relationship between multiple horizontal scan lines HSL and multiple vertical scan lines VSL. For example, as... Figure 4As shown, the odd-numbered horizontal scan lines HSL1, HSL3, ..., HSLM-3, HSLM-1 can be connected to the vertical scan lines VSL1, VSL2, ..., VSLM / 2-1, VSLM / 2 on the left half, and the even-numbered horizontal scan lines HSL2, HSL4, ..., HSLM-2, HSLM can be connected to the vertical scan lines VSLM / 2+1, VSLM / 2+2, ..., VSLM-1, VSLM on the right half. In this case, the M contact holes used to connect the M horizontal scan lines HSL1 to HSLM and the M vertical scan lines VSL1 to VSLM can be arranged in a V-shape within the display panel 110b, but are not limited to this configuration.

[0079] on the other hand, Figure 3 and Figure 4 The diagram illustrates an example of the configuration and connection relationships of multiple data lines (DL), multiple horizontal scan lines (HSL), and multiple vertical scan lines (VSL). However, the configuration and connection relationships of the lines (DL), HSL, and VSL) of the display panel 110 are not limited to this example. Figure 3 as well as Figure 4 Examples.

[0080] The data driver 120 can generate a data voltage DV based on image data IDAT received from the controller 170 and a data control signal, and provide the data voltage DV to multiple pixels PX through multiple data lines DL. In one embodiment, the data control signal may include a data clock signal DCLK and a load signal LOAD, but is not limited thereto.

[0081] The scan driver 130 can generate a scan signal SCAN based on a scan control signal received from the controller 170, and sequentially provide the scan signal SCAN to multiple pixels PX in row units through multiple vertical scan lines VSL and multiple horizontal scan lines HSL. The scan control signal may include a scan clock signal SCLK. In one embodiment, the scan control signal may also include a scan start signal, etc., but is not limited thereto.

[0082] like Figure 1 As shown, since the scan driver 130 provides the scan signal SCAN to multiple pixels PX via multiple vertical scan lines VSL and multiple horizontal scan lines HSL, the scan driver 130 can also be configured on one side (e.g., the lower side) of the display panel 110 where the data driver 120 is configured. This reduces the bezel width on the three sides of the display panel 110 where the data driver 120 and scan driver 130 are not configured. On the other hand, a structure where the data driver 120 and scan driver 130 are configured only on one side of the display panel 110 can be called a single-side driving (SSD) structure.

[0083] The data driver 120 and the scan driver 130 can be implemented as at least one data-scan integrated chip (or integrated circuit (IC)) 150. That is, a single data-scan integrated chip 150 can output not only the data voltage DV but also the scan signal SCAN. As a result, the chip size (or IC size) of the chip (or IC) used to drive the display panel 110 can be reduced.

[0084] At least one data-scanning integrated chip 150 may be connected to the display panel 110. In one embodiment, such as Figure 5 As shown, the data driver 120 and the scan driver 130 can be implemented as K data-scan integrated chips 151, 152, ..., 154 (K is an integer greater than or equal to 1). These K data-scan integrated chips 151, 152, ..., 154 can be mounted on the display panel 110 using either a chip-on-glass (COG) or chip-on-plastic (COP) method. In another embodiment, as... Figure 6 As shown, K films 141, 142, ..., 144 are connected to the display panel 110, and K data-scanning integrated chips 151, 152, ..., 154 are connected to the display panel 110 via the K films 141, 142, ..., 144 in a chip-on-film (COF) manner.

[0085] In one embodiment, the data-scan integrated chip 150 may include at least one component shared by the data driver 120 and the scan driver 130. In one example, such as... Figure 9 As shown, the data-scan integrated chip 400 may include a shared level shifter array 490 shared by the data driver 120 and the scan driver 130. In another example, as Figure 12 As shown, the data-scan integrated chip 500 may include a shared output buffer array 590 shared by the data driver 120 and the scan driver 130. In yet another example, as Figure 14 As shown, the data-scan integrated chip 600 may include a shared level shifter array 770 and a shared output buffer array 790 shared by the data drivers 120, 610 and the scan drivers 130, 660. In this case, the chip size (or IC size) of the chip (or IC) used to drive the display panel 110 can be further reduced, and power consumption can be reduced.

[0086] Controller 170 (e.g., a timing controller (TCON)) can receive image data IDAT and control signals CTRL from an external host (e.g., a graphics processing unit (GPU), graphics card, etc.). For example, image data IDAT may be RGB image data including red, green, and blue image data, but is not limited thereto. Additionally, control signals CTRL may include, for example, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a master clock signal, etc., but are not limited thereto. In one embodiment, controller 170 can perform image processing on the image data IDAT received from the external host and provide the processed image data IDAT to data driver 120. Furthermore, controller 170 can generate the data control signal and the scan control signal based on the control signal CTRL. Controller 170 can provide the image data IDAT and the data control signal to data driver 120 to control the operation of data driver 120, and provide the scan control signal to scan driver 130 to control the operation of scan driver 130.

[0087] As described above, in the display device 100 according to an embodiment of the present invention, the data driver 120 and the scan driver 130 can be configured on the same side of the display panel 110. This reduces the bezel width of the display panel 110. Furthermore, in the display device 100 according to an embodiment of the present invention, the data driver 120 and the scan driver 130 can be implemented as a data-scan integrated chip 150. This reduces the chip size (or IC size) of the chip (or IC) used to drive the display panel 110. In one embodiment, at least one component of the data-scan integrated chip 150 can be shared by the data driver 120 and the scan driver 130. In this case, the chip size (or IC size) can be further reduced, and power consumption can be reduced.

[0088] Figure 7 This is a block diagram illustrating a data-scan integrated chip according to an embodiment of the present invention. Figure 8 This is a timing diagram illustrating an example of the operation of a data-scan integrated chip according to an embodiment of the present invention.

[0089] Reference Figure 7According to an embodiment of the present invention, a data-scan integrated chip 200 may include a first shift register 310, a latch array 320, a first level shifter array 330, a digital-to-analog converter (DAC) array 340, and a first output buffer array 350 for a data driver 210, and a second shift register 360, a second level shifter array 370, and a second output buffer array 380 for a scan driver 260, and includes a data output switch array 290, a plurality of data output pads DP1, DP2, DP3, DP4, DP5, DP6, ..., DPN-2, DPN-1, DPN, and a plurality of scan output pads SP1, SP2, ..., SPM.

[0090] This can be achieved by connecting multiple data output pads DP1 to DPN to multiple data lines on the display panel, and multiple scan output pads SP1 to SPM to multiple vertical scan lines on the display panel. In one embodiment, as... Figure 7 As shown, the data-scan integrated chip 200 may include N (N is an integer greater than 2) data output pads DP1 to DPN and M (M is an integer greater than 2) scan output pads SP1 to SPM. In one example, N may be greater than M, but is not limited thereto. Furthermore, in one embodiment, at least one of the N data output pads DP1 to DPN may be configured between two adjacent pairs of the M scan output pads SP1 to SPM. For example, fourth, fifth, and sixth data output pads DP4, DP5, and DP6 may be configured between the first scan output pad SP1 and the second scan output pad SP2. On the other hand, Figure 7 The example shown illustrates three data output pads (e.g., DP4, DP5, DP6) configured between two adjacent scan output pads (e.g., SP1, SP2), but the number of data output pads configured between two adjacent scan output pads is not limited to this. Figure 7 Examples.

[0091] The first shift register 310 can sequentially generate the sampling signal SS based on the data clock signal CLK. In one embodiment, the first shift register 310 may include multiple flip-flops that sequentially generate the sampling signal SS, but is not limited thereto.

[0092] The latch array 320 can sequentially store image data IDAT in response to a sampling signal SS, and output image data IDAT related to a row of pixels or a latch output signal in response to a load signal LOAD. In one embodiment, the latch array 320 may include: a plurality of sampling latches that sequentially store image data IDAT in response to a sampling signal SS; and / or a plurality of holding latches that store and output image data IDAT related to a row of pixels stored in the plurality of sampling latches in response to a load signal LOAD.

[0093] The first level shifter array 330 can shift the voltage level of the latch output signal output from the latch array 320. For example, the first level shifter array 330 can shift the voltage level of the latch output signal to a voltage level suitable for the digital-to-analog converter array 340. In one embodiment, the first level shifter array 330 may include multiple level shifters performing the shifting operation.

[0094] The digital-to-analog converter array 340 can perform digital-to-analog conversion on a shifter output signal output from the first level shifter array 330. In one embodiment, the digital-to-analog converter array 340 may include a plurality of digital-to-analog converters performing the digital-to-analog conversion.

[0095] The first output buffer array 350 can use the converter output signal from the digital-to-analog converter array 340 as... Figure 1 The data voltage DV output is shown in the figure. In one embodiment, the first output buffer array 350 may include a plurality of output buffers for buffering the data voltage DV.

[0096] The data output switch array 290 can selectively connect the first output buffer array 350 to a plurality of data output pads DP1 to DPN in response to a selection signal SEL. In one embodiment, the data output switch array 290 may include a plurality of switches that perform connection operations in response to the selection signal SEL. According to an embodiment, the selection signal SEL can be... Figure 1 The controller 170 shown in the figure generates the data, or it is generated via the data-scan integrated chip 200.

[0097] The selection signal SEL can be high in the first interval and low in the second interval following the first interval. In this case, the data output switch array 290 can connect the first output buffer array 350 to multiple data output pads DP1 to DPN in the first interval, and disconnect the first output buffer array 350 from the multiple data output pads DP1 to DPN in the second interval. Thus, the data-scan integrated chip 200 can output the data voltage DV in the first interval. Figure 1 The multiple data lines DL shown are floated in the second interval following the first interval.

[0098] The second shift register 360 can sequentially generate the scan signal SCAN based on the scan clock signal SCLK. In one embodiment, the second shift register 360 may include multiple stages for sequentially generating the scan signal SCAN, but is not limited thereto.

[0099] The second level shifter array 370 can shift the voltage level of the scan signal SCAN output from the second shift register 360. For example, the second level shifter array 370 can shift the voltage level of the scan signal SCAN to a voltage level suitable for the switching transistors of a plurality of pixels PX. In one embodiment, the second level shifter array 370 may include a plurality of level shifters performing the shifting operation.

[0100] The second output buffer array 380 can output the scan signal SCAN from the second level shifter array 370. In one embodiment, the second output buffer array 380 may include multiple output buffers for buffering the scan signal SCAN.

[0101] It is possible that the scan signal SCAN output through the second output buffer array 380 is provided to multiple scan output pads SP1 to SPM. Figure 1 The multiple vertical scan lines (VSLs) shown in the diagram provide a scan signal (SCAN) through the multiple vertical scan lines (VSLs). Figure 1 The multiple horizontal scan lines HSL shown are provided for multiple pixels PX.

[0102] The following is for reference Figure 1 , Figure 2 , Figure 7 as well as Figure 8 The following describes an example of the operation of the data-scanning integrated chip 200 according to an embodiment of the present invention.

[0103] Reference Figure 1 , Figure 2 , Figure 7 as well as Figure 8Each frame interval FP can include: a first interval P11, P21, ..., PM1, which outputs a data voltage DV for multiple pixels PX; and a second interval P12, P22, ..., PM2, where the data voltage DV is stored in multiple pixels PX. In each first interval P11 to PM1, the data-scan integrated chip 200 can output the data voltage DV related to the pixel PX of the selected row to multiple data lines DL, and the data voltage DV charges the multiple data lines DL. Furthermore, in the corresponding second intervals P12 to PM2 after the first intervals P11 to PM1, the data-scan integrated chip 200 can float the multiple data lines DL, outputting a scan signal SCAN to the vertical scan line VSL corresponding to the selected row, and the data voltage DV charged by the multiple data lines DL is stored in the pixel PX of the selected row.

[0104] For example, such as Figure 8 As shown, the controller 170 can provide image data DAT1 related to the pixels PX in the first row of a plurality of pixels PX as image data IDAT to the data-scan integrated chip 200. Alternatively, the first shift register 310 can generate a sampling signal SS, and the latch array 320 can sequentially store the image data DAT1 related to the pixels PX in the first row in response to the sampling signal SS.

[0105] Alternatively, in the first interval P11 related to the pixels PX of the first row, latch array 320 outputs image data DAT1 related to the pixels PX of the first row in response to load signal LOAD. First level shifter array 330 shifts the voltage level of the image data DAT1 related to the pixels PX of the first row. Digital-to-analog converter array 340 converts the image data DAT1 related to the pixels PX of the first row into a first data voltage DV1 related to the pixels PX of the first row. First output buffer array 350 outputs the first data voltage DV1 related to the pixels PX of the first row. Data output switch array 290 connects the first output buffer array 350 to multiple data output pads DP1 to DPN in response to a high-level selection signal SEL. Thus, in the first interval P11 related to the pixels PX of the first row, the first data voltage DV1 related to the pixels PX of the first row can be output to multiple data lines DL through multiple data output pads DP1 to DPN. Therefore, multiple data lines DL and / or the parasitic capacitors CDL of multiple data lines DL can be charged so that the voltage V_DL of the multiple data lines DL becomes the first data voltage DV1 related to the pixel PX of the first row.

[0106] Alternatively, in the second interval P12 following the first interval P11 and relating to the pixels PX of the first row, the selection signal SEL is at a low level. The data output switch array 290 responds to the low-level selection signal SEL by disconnecting the first output buffer array 350 from the multiple data output pads DP1 to DPN. This allows the multiple data lines DL, charged to the first data voltage DV1 related to the pixels PX of the first row, to be floated. Alternatively, the second shift register 360 generates a first scan signal SCAN1 related to the pixels PX of the first row based on the scan clock signal SCLK. The second level shifter array 370 shifts the voltage level of the first scan signal SCAN1, and the second output buffer array 380 outputs the first scan signal SCAN1. Therefore, in the second interval P12 related to the pixels PX of the first row, the first scan signal SCAN1 can be provided to the pixels PX of the first row via the first scan output pad SP1, the first vertical scan line VSL, and the first horizontal scan line HSL. Therefore, during the second interval P12 associated with the pixel PX of the first row, the storage capacitor CST of the pixel PX of the first row can store the first data voltage DV1 charged in the multiple data lines DL. In addition, within the second interval P12 associated with the pixel PX of the first row, the latch array 320 can store image data DAT2 associated with the pixel PX of the second row.

[0107] Alternatively, in the first interval P21 following the second interval P12 and relating to the pixels PX of the second row, the first output buffer array 350 outputs a second data voltage DV2 related to the pixels PX of the second row. The data output switch array 290, in response to a selection signal SEL having a high level, connects the first output buffer array 350 to multiple data output pads DP1 to DPN. Consequently, in the first interval P21 related to the pixels PX of the second row, multiple data lines DL and / or their parasitic capacitors CDL can be charged, so that the voltage V_DL of the multiple data lines DL becomes the second data voltage DV2 related to the pixels PX of the second row.

[0108] Alternatively, in the second interval P22 following the first interval P21 and relating to the pixels PX of the second row, the output switch array 290 responds to the low-level selection signal SEL by disconnecting the first output buffer array 350 from the multiple data output pads DP1 to DPN, allowing the multiple data lines DL, charged to the second data voltage DV2 related to the pixels PX of the second row, to be floated. Furthermore, the second shift register 360, the second level shifter array 370, and the second output buffer array 380 can output the second scan signal SCAN2. Therefore, in the second interval P22 related to the pixels PX of the second row, the second scan signal SCAN2 can be provided to the pixels PX of the second row via the second scan output pad SP2, the second vertical scan line VSL, and the second horizontal scan line HSL. Thus, during the second interval P22 related to the pixels PX of the second row, the storage capacitor CST of the pixels PX of the second row can store the second data voltage DV2 charged in the multiple data lines DL. Additionally, within the second interval P22 related to the pixels PX in the second row, the latch array 320 can store image data DAT3 related to the pixels PX in the third row.

[0109] Furthermore, in the first interval PM1 related to the pixel PX in the Mth row, multiple data lines DL and / or the parasitic capacitors CDL of multiple data lines DL can be charged so that the voltage V_DL of the multiple data lines DL becomes the Mth data voltage DVM related to the pixel PX in the Mth row. Additionally, in the second interval PM2 following the first interval PM1 and related to the pixel PX in the Mth row, the multiple data lines DL charged to the Mth data voltage DVM related to the pixel PX in the Mth row can be floated. Furthermore, the second shift register 360, the second level shifter array 370, and the second output buffer array 380 can output the Mth scan signal SCANM. Therefore, in the second interval PM2 related to the pixel PX in the Mth row, the Mth scan signal SCANM can be provided to the pixel PX in the Mth row through the Mth scan output pad SPM, the Mth vertical scan line VSL, and the Mth horizontal scan line HSL. Therefore, during the second interval PM2 associated with pixel PX in row M, the storage capacitor CST of pixel PX in row M can store the Mth data voltage DVM charged in multiple data lines DL. In this way, the data voltage DV can be stored sequentially in multiple pixels PX row by row, and the multiple pixels PX can emit light based on the stored data voltage DV.

[0110] Figure 9 This is a block diagram illustrating a data-scan integrated chip according to another embodiment of the present invention. Figure 10 This is a circuit diagram illustrating an example of a level shifter included in a data-scan integrated chip according to an embodiment of the present invention. Figure 11This is a timing diagram illustrating an example of the operation of a data-scan integrated chip according to an embodiment of the present invention.

[0111] Reference Figure 9 According to another embodiment of the present invention, the data-scan integrated chip 400 may include a first shift register 410, a latch array 420, a digital-to-analog converter array 440 and a first output buffer array 450 for a data driver, and a second shift register 460 and a second output buffer array 480 for a scan driver, and also includes a shared level shifter array 490 shared by the data driver and the scan driver. Figure 9 The data-scan integrated chip 400, in addition to including a shared level shifter array 490 to replace the first level shifter array 330 and the second level shifter array 370, can have the same... Figure 7 The data-scanning integrated chip 200 has a similar structure and similar operation. In one embodiment, although... Figure 9 Not shown, but the data-scan integrated chip 400 may also include selectively connecting the first output buffer array 450 to a plurality of data output pads in response to a selection signal SEL. Figure 7 The data output switch array 290 shown in the figure.

[0112] The shared level shifter array 490 may include multiple level shifters LS1, LS2, LS3, ..., LSN-2, LSN-1, LSN, a shifter input switch array 492, and a shifter output switch array 493. In one embodiment, when the display device includes N data lines and M vertical scan lines, where N is greater than M, the shared level shifter array 490 may include N level shifters LS1 to LSN. On the other hand, as... Figure 7 As shown, when the data-scan integrated chip 200 includes a first level shifter array 330 for the data driver and a second level shifter array 370 for the scan driver, the data-scan integrated chip 200 can include N+M level shifters. However, since the data-scan integrated chip 400 includes a shared level shifter array 490 shared by the data driver and the scan driver, the data-scan integrated chip 400 can include only N level shifters LS1 to LSN, thereby further reducing the chip size (or IC size) of the data-scan integrated chip 400.

[0113] In one embodiment, such as Figure 10As shown, each level shifter LS may include: first to third transistors T1, T2, and T3, connected in series between the high power supply line VDDL and the inverted output terminal of the output inverted output voltage VOUTB; a fourth transistor T4, connected between the inverted output terminal and the low power supply line VSSL; fifth to seventh transistors T5, T6, and T7, connected in series between the high power supply line VDDL and the output terminal of the output voltage VOUT; and an eighth transistor T8, connected between the output terminal and the low power supply line VSSL. Alternatively, the first to third and fifth to seventh transistors T1, T2, T3, T5, T6, and T7 may be implemented as PMOS transistors, and the fourth and eighth transistors T4 and T8 may be implemented as NMOS transistors. Alternatively, the first and second transistors T1 and T2 may be turned on in response to a low-level input voltage VIN, the third transistor T3 may be turned on in response to a low-level output voltage VOUT, and the eighth transistor T8 may be turned on in response to a high-level inverted input voltage VINB. Therefore, the level shifter LS can respond to a low-level input voltage VIN and a high-level inverted input voltage VINB, respectively outputting the low power supply voltage DSVSS / SSVSS of the low power supply line VSSL and the high power supply voltage DSVDD / SSVDD of the high power supply line VDDL as output voltage VOUT and inverted output voltage VOUTB. Alternatively, the fifth and sixth transistors T5 and T6 can be turned on in response to the low-level inverted input voltage VINB, the seventh transistor T7 can be turned on in response to the low-level inverted output voltage VOUTB, and the fourth transistor T4 can be turned on in response to the high-level input voltage VIN. Therefore, the level shifter LS can respond to the high-level input voltage VIN and the low-level inverted input voltage VINB, respectively outputting the high power supply voltage DSVDD / SSVDD of the high power supply line VDDL and the low power supply voltage DSVSS / SSVSS of the low power supply line VSSL as output voltage VOUT and inverted output voltage VOUTB. On the other hand, although Figure 10 The example shown is of a level shifter LS receiving differential input voltages VIN and VINB and outputting differential output voltages VOUT and VOUTB. However, the inputs and outputs of the level shifter LS are not limited to this example. Figure 10 For example, a level shifter LS can receive a single (or single-ended) input signal and output a single (or single-ended) output signal. Additionally, although... Figure 10 An example of the structure of a level shifter LS is shown, but the level shifter LS included in the data-scan integrated chip 400 according to embodiments of the present invention is not limited to... Figure 10 Examples.

[0114] Refer again Figure 9The shifter input switch array 492 can connect the output terminals of the latch array 420 to the input terminals of a plurality of level shifters LS1 to LSM in response to the selection signal SEL, and connect the output terminal of the second shift register 460 to the input terminals of the plurality of level shifters LS1 to LSM in response to the inverted selection signal SELB. In one embodiment, the shifter input switch array 492 may include: N input switches that perform connection operations in response to the selection signal SEL; and M input switches that perform connection operations in response to the inverted selection signal SELB. Additionally, the shifter output switch array 493 can connect the output terminals of a plurality of level shifters LS1 to LSM to the input terminals of the digital-to-analog converter array 440 in response to the selection signal SEL, and connect the output terminals of the plurality of level shifters LS1 to LSM to the input terminals of the second output buffer array 480 in response to the inverted selection signal SELB. In one embodiment, the shifter output switch array 493 may include: N output switches that perform connection operations in response to the selection signal SEL; and M output switches that perform connection operations in response to the inverse selection signal SELB. Thus, the shared-level shifter array 490 can be connected between the latch array 420 and the digital-to-analog converter array 440 for the data driver during the period when the selection signal SEL is high, and connected between the second shift register 460 and the second output buffer array 480 for the scan driver during the period when the inverse selection signal SELB is high.

[0115] In one embodiment, the shared level shifter array 490 may further include: a first shifter high power switch 496, which transmits the data shifter high power voltage DSVDD to the high power line VDDL of the shared level shifter array 490 in response to a select signal SEL; a second shifter high power switch 497, which transmits the scan shifter high power voltage SSVDD to the high power line VDDL of the shared level shifter array 490 in response to an inverse select signal SELB; a first shifter low power switch 498, which transmits the data shifter low power voltage DSVSS to the low power line VSSL of the shared level shifter array 490 in response to a select signal SEL; and a second shifter low power switch 499, which transmits the scan shifter low power voltage SSVSS to the low power line VSSL of the shared level shifter array 490 in response to an inverse select signal SELB. Therefore, during the period when the selection signal SEL is high, the data shifter high power supply voltage DSVDD and the data shifter low power supply voltage DSVSS for the level shifter of the data driver are supplied to multiple level shifters LS1 to LSM; and during the period when the inverse selection signal SELB is high, the scan shifter high power supply voltage SSVDD and the scan shifter low power supply voltage SSVSS for the level shifter of the scan driver are supplied to multiple level shifters LS1 to LSM.

[0116] As described above, the data-scan integrated chip 400 according to another embodiment of the present invention may include a shared level shifter array 490 shared by the data driver and the scan driver. This allows for a further reduction in the chip size (or IC size) of the data-scan integrated chip 400 according to another embodiment of the present invention, thereby reducing power consumption.

[0117] The following is for reference Figure 9 as well as Figure 11 An example of the operation of the data-scanning integrated chip 400 according to another embodiment of the present invention will be described later.

[0118] Reference Figure 9 as well as Figure 11 Alternatively, in the first interval P11 related to the pixel PX of the first row, the selection signal SEL is high and the inverse selection signal SELB is low. Therefore, the shared level shifter array 490 can be connected between the latch array 420 and the digital-to-analog converter array 440. Thus, the data-scan integrated chip 400 can output a first data voltage DV1 related to the pixel PX of the first row to multiple data lines DL, and the multiple data lines DL are charged to the first data voltage DV1 related to the pixel PX of the first row.

[0119] Alternatively, in a second interval P12 following the first interval P11 and relating to the pixels PX of the first row, the selection signal SEL is low and the inverse selection signal SELB is high. Therefore, the shared-level shifter array 490 can be connected between the second shift register 460 and the second output buffer array 480. Furthermore, the multiple data lines DL charged to the first data voltage DV1 relating to the pixels PX of the first row can be... Figure 7 The data output switch array 290 shown is floating. Alternatively, the data-scan integrated chip 400 may provide a first scan signal SCAN1 to the pixels PX of the first row, and the pixels PX of the first row store a first data voltage DV1 charged in multiple data lines DL.

[0120] Alternatively, in the first interval P21 following the second interval P12 and related to the pixels PX of the second row, the selection signal SEL is high, the inverse selection signal SELB is low, and the shared level shifter array 490 is connected between the latch array 420 and the digital-to-analog converter array 440. Alternatively, the data-scan integrated chip 400 outputs the second data voltage DV2 related to the pixels PX of the second row to multiple data lines DL, and the multiple data lines DL are charged to the second data voltage DV2 related to the pixels PX of the second row. Alternatively, in the second interval P22 following the first interval P21 and related to the pixels PX of the second row, the selection signal SEL is low, the inverse selection signal SELB is high, the shared level shifter array 490 is connected between the second shift register 460 and the second output buffer array 480, and the multiple data lines DL are floated. Alternatively, the data-scan integrated chip 400 can provide a second scan signal SCAN2 to the pixels PX of the second row, and the pixels PX of the second row can store a second data voltage DV2 charged in multiple data lines DL.

[0121] Alternatively, in the first interval PM1 related to the pixel PX in the Mth row, the selection signal SEL is high and the inverse selection signal SELB is low, with a shared level shifter array 490 connected between the latch array 420 and the digital-to-analog converter array 440. Alternatively, the data-scan integrated chip 400 outputs the Mth data voltage DVM related to the pixel PX in the Mth row to multiple data lines DL, which are charged to the Mth data voltage DVM related to the pixel PX in the Mth row. Alternatively, in the second interval PM2 related to the pixel PX in the Mth row after the first interval PM1, the selection signal SEL is low and the inverse selection signal SELB is high, with a shared level shifter array 490 connected between the second shift register 460 and the second output buffer array 480, and the multiple data lines DL are floated. Alternatively, the data-scan integrated chip 400 provides the Mth scan signal SCANM to the pixels PX in the Mth row, and the pixels PX in the Mth row store the Mth data voltage DVM charged in multiple data lines DL. In this way, the data voltages DV1, DV2, ..., DVM can be stored sequentially in multiple pixels PX in row units, and the multiple pixels PX can emit light based on the stored data voltages DV1, DV2, ..., DVM.

[0122] Figure 12 This is a block diagram illustrating a data-scan integrated chip according to yet another embodiment of the present invention. Figure 13 This is a block diagram illustrating an example of an output buffer included in a data-scan integrated chip according to an embodiment of the present invention.

[0123] Reference Figure 12 According to yet another embodiment of the present invention, the data-scan integrated chip 500 may include a first shift register 510, a latch array 520, a first level shifter array 530, and a digital-to-analog converter array 540 for a data driver, and a second shift register 560 and a second level shifter array 570 for a scan driver, and also includes a shared output buffer array 590 shared by the data driver and the scan driver. Figure 12 The data-scan integrated chip 500, in addition to including a shared output buffer array 590 to replace the first output buffer array 350 and the second output buffer array 380, can have the same... Figure 7 The data scan integrated chip 200 has a similar structure and similar operation.

[0124] The shared output buffer array 590 may include multiple output buffers OB1, OB2, OB3, ..., OBN-2, OBN-1, OBN, a buffer input switch array 592, and a buffer output switch array 593. In one embodiment, when the display device includes N data lines and M vertical scan lines, where N is greater than M, the shared output buffer array 590 may include N output buffers OB1 to OBN. On the other hand, as... Figure 7 As shown, when the data-scan integrated chip 200 includes a first output buffer array 350 for the data driver and a second output buffer array 380 for the scan driver, the data-scan integrated chip 200 may include N+M output buffers. However, since the data-scan integrated chip 500 includes a shared output buffer array 590 shared by the data driver and the scan driver, the data-scan integrated chip 500 may include only N output buffers OB1 to OBN, thereby further reducing the chip size (or IC size) of the data-scan integrated chip 500.

[0125] In one embodiment, such as Figure 13 As shown, each output buffer OB may include an amplifier AMP having an input terminal, an inverting input terminal, and an output terminal. The amplifier AMP can receive an input voltage VIN from the input terminal, and the inverting input terminal and the output terminal are connected to each other. The amplifier AMP can output an output voltage VOUT at the output terminal that is substantially the same as the input voltage VIN. Additionally, the amplifier AMP can receive a high supply voltage VDD and a low supply voltage VSS. In one embodiment, the voltage level of the high supply voltage VDD of the amplifier AMP may be determined as the higher of the high supply voltage of the data buffer for the output buffer of the data driver and the high supply voltage of the scan buffer for the output buffer of the scan driver, and the voltage level of the low supply voltage VSS of the amplifier AMP may be determined as the lower of the low supply voltage of the data buffer for the output buffer of the data driver and the low supply voltage of the scan buffer for the output buffer of the scan driver. Thus, each output buffer OB can function normally as both the output buffer of the data driver and the output buffer of the scan driver. On the other hand, although... Figure 13 An example of the structure of the output buffer OB is shown, but the output buffer OB included in the data-scan integrated chip 500 according to embodiments of the present invention is not limited to... Figure 13 Examples.

[0126] Refer again Figure 12The buffer input switch array 592 can connect the output terminals of the digital-to-analog converter array 540 to the input terminals of multiple output buffers OB1 to OBN in response to the selection signal SEL, and connect the output terminals of the second level shifter array 570 to the input terminals of the multiple output buffers OB1 to OBN in response to the inverted selection signal SELB. In one embodiment, the buffer input switch array 592 may include: N input switches that perform connection operations in response to the selection signal SEL; and M input switches that perform connection operations in response to the inverted selection signal SELB. Additionally, the buffer output switch array 593 can connect the output terminals of multiple output buffers OB1 to OBN to multiple data output pads DP1 to DPN in response to the selection signal SEL, and connect the output terminals of multiple output buffers OB1 to OBN to multiple scan output pads SP1 to SPM in response to the inverted selection signal SELB. In one embodiment, the buffer output switch array 593 may include: N output switches that perform connection operations in response to the selection signal SEL; and M output switches that perform connection operations in response to the inverted selection signal SELB. Thus, the shared output buffer array 590 can be connected between the digital-to-analog converter array 540 for the data driver and the plurality of data output pads DP1 to DPN during the period when the selection signal SEL is high, and between the second level shifter array 570 for the scan driver and the plurality of scan output pads SP1 to SPM during the period when the inverse selection signal SELB is high.

[0127] As described above, the data-scan integrated chip 500 according to another embodiment of the present invention may include a shared output buffer array 590 shared by the data driver and the scan driver. This allows for a further reduction in the chip size (or IC size) of the data-scan integrated chip 500 according to another embodiment of the present invention, thereby reducing power consumption.

[0128] The following is for reference Figure 11 as well as Figure 12 The following describes an example of the operation of the data-scanning integrated chip 500 according to another embodiment of the present invention.

[0129] Reference Figure 11 as well as Figure 12Alternatively, in a first interval P11 related to the pixels PX of the first row, the selection signal SEL is high and the inverse selection signal SELB is low, with a shared output buffer array 590 connected between the digital-to-analog converter array 540 and multiple data output pads DP1 to DPN. Alternatively, the data-scan integrated chip 500 outputs a first data voltage DV1 related to the pixels PX of the first row to multiple data lines DL, and the multiple data lines DL are charged to the first data voltage DV1 related to the pixels PX of the first row. Alternatively, in a second interval P12 related to the pixels PX of the first row after the first interval P11, the selection signal SEL is low and the inverse selection signal SELB is high, with a shared output buffer array 590 connected between a second level shifter array 570 and multiple scan output pads SP1 to SPM, and the multiple data lines DL are floated. It is possible that the data-scan integrated chip 500 provides the first scan signal SCAN1 to the pixels PX of the first row, and the pixels PX of the first row store the first data voltage DV1 charged in multiple data lines DL.

[0130] Alternatively, in the first interval P21 following the second interval P12 and related to the pixels PX of the second row, the selection signal SEL is high, the inverse selection signal SELB is low, and the shared output buffer array 590 is connected between the digital-to-analog converter array 540 and multiple data output pads DP1 to DPN. Alternatively, the data-scan integrated chip 500 outputs a second data voltage DV2 related to the pixels PX of the second row to multiple data lines DL, and the multiple data lines DL are charged to the second data voltage DV2 related to the pixels PX of the second row. Alternatively, in the second interval P22 following the first interval P21 and related to the pixels PX of the second row, the selection signal SEL is low, the inverse selection signal SELB is high, the shared output buffer array 590 is connected between the second level shifter array 570 and multiple scan output pads SP1 to SPM, and the multiple data lines DL are floated. Alternatively, the data-scan integrated chip 500 can provide a second scan signal SCAN2 to the pixels PX of the second row, and the pixels PX of the second row can store a second data voltage DV2 charged in multiple data lines DL.

[0131] Alternatively, in the first interval PM1 related to the pixel PX in the Mth row, the selection signal SEL is high and the inverse selection signal SELB is low, and the shared output buffer array 590 is connected between the digital-to-analog converter array 540 and multiple data output pads DP1 to DPN. Alternatively, the data-scan integrated chip 500 outputs the Mth data voltage DVM related to the pixel PX in the Mth row to multiple data lines DL, and the multiple data lines DL are charged to the Mth data voltage DVM related to the pixel PX in the Mth row. Alternatively, in the second interval PM2 related to the pixel PX in the Mth row after the first interval PM1, the selection signal SEL is low and the inverse selection signal SELB is high, the shared output buffer array 590 is connected between the second level shifter array 570 and multiple scan output pads SP1 to SPM, and the multiple data lines DL are floated. Alternatively, the data-scan integrated chip 500 provides the Mth scan signal SCANM to the pixels PX in the Mth row, and the pixels PX in the Mth row store the Mth data voltage DVM charged in multiple data lines DL. In this way, the data voltages DV1, DV2, ..., DVM can be stored sequentially in multiple pixels PX in row units, and the multiple pixels PX can emit light based on the stored data voltages DV1, DV2, ..., DVM.

[0132] Figure 14 This is a block diagram illustrating a data-scan integrated chip according to yet another embodiment of the present invention.

[0133] Reference Figure 14 According to yet another embodiment of the present invention, the data-scan integrated chip 600 may include a first shift register 710, a latch array 720, and a digital-to-analog converter array 730 for a data driver 610, and a second shift register 750 for a scan driver 660, and also includes a shared level shifter array 770 and a shared output buffer array 790 shared by the data driver 610 and the scan driver 660. Figure 14 The data-scan integrated chip 600, in addition to including a shared level shifter array 770 instead of the first level shifter array 330 and the second level shifter array 370, and including a shared output buffer array 790 instead of the first output buffer array 350 and the second output buffer array 380, can have the same... Figure 7 The data scan integrated chip 200 has a similar structure and similar operation.

[0134] The shared level shifter array 770 may include a plurality of level shifters 771, a shifter input switch array 772, and a shifter output switch array 773. The shifter input switch array 772 may connect the output terminal of the latch array 720 to the input terminal of the plurality of level shifters 771 in response to a selection signal, and connect the output terminal of the second shift register 750 to the input terminal of the plurality of level shifters 771 in response to an inverted selection signal. The shifter output switch array 773 may connect the output terminals of the plurality of level shifters 771 to the input terminal of the digital-to-analog converter array 730 in response to the selection signal, and connect the output terminals of the plurality of level shifters 771 to the input terminal of the shared output buffer array 790 in response to the inverted selection signal.

[0135] The shared output buffer array 790 may include a plurality of output buffers 791, a buffer input switch array 792, and a buffer output switch array 793. The buffer input switch array 792 may connect the output terminals of the digital-to-analog converter array 730 to the input terminals of the plurality of output buffers 791 in response to the selection signal, and connect the output terminals of the shared level shifter array 770 to the input terminals of the plurality of output buffers 791 in response to the inverted selection signal. The buffer output switch array 793 may connect the output terminals of the plurality of output buffers 791 to a plurality of data output pads 620 in response to the selection signal, and connect the output terminals of the plurality of output buffers 791 to a plurality of scan output pads 670 in response to the inverted selection signal.

[0136] As described above, the data-scan integrated chip 600 according to another embodiment of the present invention may include a shared level shifter array 770 and a shared output buffer array 790 shared by the data driver 610 and the scan driver 660. This allows for a further reduction in the chip size (or IC size) of the data-scan integrated chip 600 according to another embodiment of the present invention, thereby reducing power consumption.

[0137] Figure 15 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0138] Reference Figure 15 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 may also include multiple ports capable of communicating with display cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0139] Processor 1110 can perform specific calculations or tasks. According to embodiments, processor 1110 can be a microprocessor, central processing unit (CPU), etc. Processor 1110 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0140] The memory device 1120 can store the data required for the operation of the electronic device 1100. For example, memory device 1120 may include non-volatile memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), and / or volatile memory devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and mobile DRAM.

[0141] Storage device 1130 may include a solid-state drive (SSD), a hard disk drive (HDD), an optical disc read-only memory (CD-ROM), etc. Input / output device 1140 may include input components such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output components such as speakers, printers, etc. Power supply 1150 can supply the power required for the operation of electronic device 1100. Display device 1160 can be connected to other components via the bus or other communication links.

[0142] In the display device 1160, the data driver and the scan driver can be configured on the same side of the display panel. This reduces the bezel width of the display panel. Furthermore, in the display device 1160, the data driver and the scan driver can be implemented as a data-scan integrated chip. This reduces the chip size or IC size of the chip used to drive the display panel. Moreover, in the display device 1160, the data-scan integrated chip can include at least one component shared by the data driver and the scan driver (e.g., a level shifter array and / or an output buffer array). This further reduces the chip size or IC size of the chip used to drive the display panel, thereby reducing power consumption.

[0143] According to the embodiments, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital television, 3D television, personal computer (PC), home electronic device, laptop computer, tablet computer, mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0144] (Industry availability)

[0145] This invention can be applied to any display device and electronic devices including thereof. For example, it can be applied to any electronic device including a television, digital television, 3D television, mobile phone, smartphone, tablet computer, laptop computer, personal computer (PC), home electronic device, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0146] The above description refers to embodiments of the present invention. However, those skilled in the art will understand that various modifications and alterations can be made to the present invention without departing from the scope and concept of the invention as set forth in the claims.

Claims

1. A display device, characterized in that, include: A display panel includes: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines. A data driver provides data voltage to the plurality of pixels via the plurality of data lines; and The scan driver sequentially provides scan signals to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signal. The data driver and the scan driver share at least one of the level shifter array and the output buffer array of the data-scan integrated chip.

2. The display device according to claim 1, characterized in that, At least one of the plurality of data lines is arranged between two adjacent second scan lines.

3. The display device according to claim 1, characterized in that, The data-scan integrated chip includes: multiple data output pads connected to the multiple data lines; and multiple scan output pads connected to the multiple second scan lines.

4. The display device according to claim 3, characterized in that, At least one of the plurality of data output pads is arranged between two adjacent scan output pads.

5. The display device according to claim 1, characterized in that, In the first interval, the data-scan integrated chip outputs the data voltage related to the pixels of the row selected from the plurality of pixels to the plurality of data lines. In the second interval following the first interval, the data-scan integrated chip floats the plurality of data lines and outputs the scan signal to the second scan line corresponding to the selected row among the plurality of second scan lines.

6. The display device according to claim 5, characterized in that, During the first interval, the data voltage charges the plurality of data lines. During the second interval, the data voltage charged in the plurality of data lines is stored in the pixel of the selected row.

7. The display device according to claim 1, characterized in that, The data-scan integrated chip includes: The first shift register generates a sampling signal based on the data clock signal; A latch array, in response to the sampling signal, stores image data; The first level shifter array shifts the voltage level of the latch output signal output from the latch array; A digital-to-analog converter array performs digital-to-analog conversion on the shifter output signal output from the first level shifter array; The first output buffer array takes the converter output signal from the digital-to-analog converter array as the data voltage output; Multiple data output pads are connected to the multiple data lines; A data output switch array, in response to a selection signal, selectively connects the first output buffer array to the plurality of data output pads; The second shift register generates the scan signal based on the scan clock signal; The second level shifter array shifts the voltage level of the scan signal output from the second shift register; A second output buffer array outputs the scan signal from the second level shifter array; and Multiple scan output pads are connected to the second output buffer array and the multiple second scan lines.

8. A display device, characterized in that, include: A display panel includes: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines. A data driver provides data voltage to the plurality of pixels via the plurality of data lines; and The scan driver sequentially provides scan signals to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signal. The data-scan integrated chip includes a first shift register, a latch array, a digital-to-analog converter array, and a first output buffer array for the data driver, and a second shift register and a second output buffer array for the scan driver, and also includes a shared level shifter array shared by the data driver and the scan driver.

9. The display device according to claim 8, characterized in that, The shared level shifter array includes: Multiple level shifters; A shifter input switch array, in response to a selection signal, connects the output terminals of the latch array to the input terminals of the plurality of level shifters, and in response to an inverted selection signal, connects the output terminal of the second shift register to the input terminals of the plurality of level shifters; and The shifter output switch array connects the output terminals of the plurality of level shifters to the input terminals of the digital-to-analog converter array in response to the selection signal, and connects the output terminals of the plurality of level shifters to the input terminals of the second output buffer array in response to the inverse selection signal.

10. The display device according to claim 9, characterized in that, The shared level shifter array also includes: The first shifter high power switch, in response to the selection signal, transmits the data shifter high power voltage to the high power line of the shared level shifter array; The second shifter high power switch, in response to the reverse selection signal, transmits the scan shifter high power supply voltage to the high power line of the shared level shifter array; A first shifter low power switch, in response to the selection signal, transmits a data shifter low power voltage to the low power line of the shared level shifter array; and The second shifter low power switch, in response to the reverse selection signal, transmits the scan shifter low power supply voltage to the low power line of the shared level shifter array.

11. A display device, characterized in that, include: A display panel includes: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines. A data driver provides data voltage to the plurality of pixels via the plurality of data lines; and The scan driver sequentially provides scan signals to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signal. The data-scan integrated chip includes a first shift register, a latch array, a first level shifter array, and a digital-to-analog converter array for the data driver, and a second shift register and a second level shifter array for the scan driver, and also includes a shared output buffer array shared by the data driver and the scan driver.

12. The display device according to claim 11, characterized in that, The data-scan integrated chip further includes: multiple data output pads connected to the multiple data lines; and multiple scan output pads connected to the multiple second scan lines. The shared output buffer array includes: Multiple output buffers; A buffer input switch array, in response to a selection signal, connects the output terminals of the digital-to-analog converter array to the input terminals of the plurality of output buffers, and in response to an inverted selection signal, connects the output terminals of the second level shifter array to the input terminals of the plurality of output buffers; and The buffer output switch array connects the output terminals of the plurality of output buffers to the plurality of data output pads in response to the selection signal, and connects the output terminals of the plurality of output buffers to the plurality of scan output pads in response to the reverse selection signal.

13. The display device according to claim 12, characterized in that, The voltage level of the high power supply voltage of the plurality of output buffers is determined to be the higher voltage level of the high power supply voltage of the data buffer and the high power supply voltage of the scan buffer. The voltage level of the low power supply voltage of the plurality of output buffers is determined to be the lower voltage level of the low power supply voltage of the data buffer and the low power supply voltage of the scan buffer.

14. A display device, characterized in that, include: A display panel includes: a plurality of pixels; a plurality of data lines extending in a first direction and connected to the plurality of pixels; a plurality of first scan lines extending in a second direction different from the first direction and connected to the plurality of pixels; and a plurality of second scan lines extending in the first direction and connected to the plurality of first scan lines. A data driver provides data voltage to the plurality of pixels via the plurality of data lines; and The scan driver sequentially provides scan signals to the plurality of pixels in row units via the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented as a data-scan integrated chip that outputs the data voltage and the scan signal. The data-scan integrated chip includes a first shift register, a latch array, and a digital-to-analog converter array for the data driver, and a second shift register for the scan driver, and also includes a shared level shifter array and a shared output buffer array shared by the data driver and the scan driver.

15. The display device according to claim 14, characterized in that, The data-scan integrated chip further includes: multiple data output pads connected to the multiple data lines; and multiple scan output pads connected to the multiple second scan lines. The shared level shifter array includes: Multiple level shifters; A shifter input switch array, in response to a selection signal, connects the output terminals of the latch array to the input terminals of the plurality of level shifters, and in response to an inverted selection signal, connects the output terminal of the second shift register to the input terminals of the plurality of level shifters; and A shifter output switch array, in response to the selection signal, connects the output terminals of the plurality of level shifters to the input terminals of the digital-to-analog converter array, and in response to the inverted selection signal, connects the output terminals of the plurality of level shifters to the input terminals of the shared output buffer array. The shared output buffer array includes: Multiple output buffers; A buffer input switch array, in response to the selection signal, connects the output terminals of the digital-to-analog converter array to the input terminals of the plurality of output buffers, and in response to the inverted selection signal, connects the output terminals of the shared level shifter array to the input terminals of the plurality of output buffers; and The buffer output switch array connects the output terminals of the plurality of output buffers to the plurality of data output pads in response to the selection signal, and connects the output terminals of the plurality of output buffers to the plurality of scan output pads in response to the reverse selection signal.

Images