Pixels and display devices with pixels

Abstract

A pixel and a display device are provided. The pixel includes a light-emitting element, a first transistor, a first capacitor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, and an eighth transistor. The first transistor is connected between a first power supply and a second node. The first capacitor is connected to either the first node or the second node and the third node. The second transistor is located between the third node and a data line and is turned on by a first scan signal. The third transistor is located between the first node and the second node and is turned on by a second scan signal. The fifth transistor is located between the first power supply and the first transistor and is turned on by a first transmit control signal. The sixth transistor is located between the second node and the light-emitting element and is turned on by a second transmit control signal. The eighth transistor is located between the second node and a second transmit control line and is turned on by a fourth scan signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0091872, filed with the Korean Intellectual Property Office on July 23, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to pixels and display devices having pixels. Background Technology

[0004] Typically, a display device is an output device used to present information in a visual form. With the development of information technology, the importance of display devices as a connection medium between users and information has increased.

[0005] Display devices typically include multiple pixels. Each of the multiple pixels includes multiple transistors, a light-emitting element electrically connected to the transistors, and a capacitor. The transistors turn on in response to a signal provided through a line (e.g., a scan line or a data line) to generate a drive current. The light-emitting element emits light corresponding to the drive current.

[0006] Display devices can be driven at low frequencies to improve driving efficiency and minimize power consumption. However, when a display device is driven at a low frequency, display quality may be compromised. Summary of the Invention

[0007] According to an embodiment of the present invention, a pixel is provided, comprising: a light-emitting element, a first transistor, a first capacitor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, and an eighth transistor. The first transistor is connected between a first power supply and a second node, and the first transistor controls the driving current supplied to the light-emitting element. The first capacitor includes a first electrode connected to one of the first and second nodes and a second electrode connected to a third node. The second transistor is connected between the third node and a data line, and the second transistor is turned on by a first scan signal. The third transistor is connected between the first node and the second node, and the third transistor is turned on by a second scan signal. The fifth transistor is connected between the first power supply and the first transistor, and the fifth transistor is turned on by a first transmit control signal. The sixth transistor is connected between the second node and the light-emitting element, and the sixth transistor is turned on by a second transmit control signal. The eighth transistor is connected between the second node and a second transmit control line, and the eighth transistor is turned on by a fourth scan signal.

[0008] The pixel may also include a fourth transistor and a second capacitor. The fourth transistor is connected between a reference power supply and a third node and is turned on by a third scan signal. The second capacitor is connected between a first power supply and a first node, wherein the first electrode of the first capacitor is connected to the second node.

[0009] The pixel may also include a seventh transistor connected between the light-emitting element and the initialization power supply, the seventh transistor being turned on by a third scan signal.

[0010] A frame may include an initialization period, a compensation period, a write period, a bias period, and an emission period. During the initialization period, initialization power is supplied to the first node and the fourth node between the light-emitting element and the seventh transistor. During the compensation period, the first node and the second node are electrically connected to each other. During the write period, a data signal is supplied to the third node. During the bias period, a bias voltage is supplied to the first transistor. During the emission period, the light-emitting element emits light.

[0011] The bias period may include a conduction bias period during which the first transistor is in a conduction bias state, and during the conduction bias period, the third and sixth transistors are turned off, and the eighth transistor is turned on.

[0012] The bias period may include a turn-off bias period in which the first transistor is in a turn-off bias state, and during the turn-off bias period, the third transistor is turned off and the eighth transistor is turned on.

[0013] The bias period may include a turn-off bias period in which the first transistor is in a turn-off bias state, and during the turn-off bias period, the third transistor is turned off, and the sixth and seventh transistors are turned on.

[0014] In response to the second scan signal, the third transistor can be turned on during the initialization period, the compensation period, and the write period, and turned off during the bias period and the emit period. In response to the third scan signal, the seventh transistor can be turned on during the initialization period and the compensation period, and turned off during the write period, the bias period, and the emit period.

[0015] In response to the second scan signal, the third transistor can be turned on during the initialization period, the compensation period, and the write period, and turned off during the bias period and the emit period. In response to the third scan signal, the seventh transistor can be turned on during the initialization period, the compensation period, and the off-bias period, and turned off during the write period, the bias period excluding the off-bias period, and the emit period.

[0016] The pixel may also include a second capacitor and a fourth transistor, the second capacitor being connected between the first power supply and the third node, the fourth transistor being connected between the reference power supply and the third node, and the fourth transistor being turned on by a second scan signal, wherein the first electrode of the first capacitor is connected to the first node.

[0017] The pixel may also include a seventh transistor connected between the light-emitting element and the initialization power supply, the seventh transistor being turned on by a third scan signal.

[0018] A frame may include an initialization period, a compensation period, a write period, a bias period, and an emission period. During the initialization period, initialization power is supplied to the first node and the fourth node between the light-emitting element and the seventh transistor. During the compensation period, the first node and the second node are electrically connected to each other. During the write period, a data signal is supplied to the third node. During the bias period, a bias voltage is supplied to the first transistor. During the emission period, the light-emitting element emits light.

[0019] The bias period may include a conduction bias period during which the first transistor is in a conduction bias state, and during the conduction bias period, the fifth and sixth transistors are turned off, and the eighth transistor is turned on.

[0020] The bias period may include a turn-off bias period in which the first transistor is in a turn-off bias state, and during the turn-off bias period, the fifth transistor is turned off and the eighth transistor is turned on.

[0021] The bias period may include a conduction bias period during which the first transistor is in a conduction bias state, and during the conduction bias period, the sixth transistor is turned off and the fifth transistor is turned on.

[0022] The bias period may include a turn-off bias period in which the first transistor is in a turn-off bias state, and during the turn-off bias period, the fifth transistor is turned off, and the sixth and seventh transistors are turned off.

[0023] According to an embodiment of the present invention, a display device is provided, comprising a display panel, a scan driver, an emission driver, a data driver, and a timing controller. The display panel includes pixels connected to a first scan line, a second scan line, a third scan line, a first emission control line, a second emission control line, and a data line. The scan driver is configured to supply a first scan signal to the first scan line, a second scan signal to the second scan line, and a third scan signal to the third scan line. The emission driver is configured to supply a first emission control signal to the first emission control line and a second emission control signal to the second emission control line. The data driver is configured to supply a data signal to the data line. The timing controller is configured to control the scan driver, the emission driver, and the data driver. At least one of the plurality of pixels includes a light-emitting element, a first transistor, a first capacitor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The system comprises a transistor and a second capacitor. The first transistor is connected between a first power supply and a second node, controlling the drive current supplied to the light-emitting element. The first capacitor is connected between the second and third nodes. The second transistor is connected between the third node and a corresponding data line among multiple data lines, and is turned on by a first scan signal. The third transistor is connected between the first and second nodes, and is turned on by a second scan signal. The fourth transistor is connected between a reference power supply and the third node, and is turned on by a third scan signal. The fifth transistor is connected between the first power supply and the first transistor, and is turned on by a first transmit control signal. The sixth transistor is connected between the second node and the light-emitting element, and is turned on by a second transmit control signal. The seventh transistor is connected between the light-emitting element and the initialization power supply, and is turned on by a third scan signal. The second capacitor is connected between the first power supply and the first node.

[0024] The scan driver may include a first scan driver, a second scan driver, and a third scan driver. The first scan driver supplies a first scan signal to a first scan line at a second frequency corresponding to the image refresh rate of the pixel. The second scan driver supplies a second scan signal to a second scan line at a second frequency. The third scan driver supplies a third scan signal to a third scan line at a first frequency. The transmit driver may include a first transmit driver and a second transmit driver. The first transmit driver supplies a first transmit control signal to a first transmit control line at a first frequency. The second transmit driver supplies a second transmit control signal to a second transmit control line at a first frequency. The data driver can supply a data signal to a data line according to the second frequency.

[0025] The first scan driver and the second scan driver can supply the first scan signal and the second scan signal during the display scan period in a frame, and not supply the first scan signal and the second scan signal during the self scan period in a frame. During the display scan period, the data signal can be written to the pixel, and during the display scan period and the self scan period, the first transistor can be biased by the initialization power supply, the third scan signal and the second transmit control signal.

[0026] The pixel may also be connected to a fourth scan line, and the scan driver may also include a fourth scan driver that supplies a fourth scan signal to the fourth scan line at a first frequency. At least one of the plurality of pixels may also include an eighth transistor connected between the second node and a corresponding second transmit control line among the plurality of second transmit control lines, the eighth transistor being turned on by the fourth scan signal.

[0027] The first scan driver and the second scan driver can supply the first scan signal and the second scan signal during the display scan period in a frame, and not supply the first scan signal and the second scan signal during the self scan period in a frame. During the display scan period, the data signal can be written to the pixel, and during the display scan period and the self scan period, the first transistor can be biased by the fourth scan signal and the second transmit control signal.

[0028] The image refresh rate of a pixel can decrease as the number of self-scanning periods increases.

[0029] The second frequency can correspond to the divisor of the first frequency.

[0030] According to an embodiment of the present invention, a display device is provided, comprising a display panel, a scan driver, an emission driver, a data driver, and a timing controller. The display panel includes pixels connected to a first scan line, a second scan line, a third scan line, a first emission control line, a second emission control line, and a data line. The scan driver is configured to supply a first scan signal to the first scan line, a second scan signal to the second scan line, and a third scan signal to the third scan line. The emission driver is configured to supply a first emission control signal to the first emission control line and a second emission control signal to the second emission control line. The data driver is configured to supply a data signal to the data line. The timing controller is configured to control the scan driver, the emission driver, and the data driver. At least one of the plurality of pixels includes a light-emitting element, a first transistor, a first capacitor, a second capacitor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The system comprises a transistor, a sixth transistor, and a seventh transistor. A first transistor is connected between a first power supply and a second node, and controls the drive current supplied to the light-emitting element. A first capacitor is connected between the first node and a third node. A second capacitor is connected between the first power supply and the third node. A second transistor is connected between the third node and a corresponding data line among multiple data lines, and receives a first scan signal. A third transistor is connected between the first node and the second node, and receives a second scan signal. A fourth transistor is connected between a reference power supply and the third node, and receives the second scan signal. A fifth transistor is connected between the first power supply and the first transistor, and receives a first transmit control signal. A sixth transistor is connected between the second node and the light-emitting element, and receives a second transmit control signal. A seventh transistor is connected between the light-emitting element and the initialization power supply, and receives a third scan signal.

[0031] The scan driver may include a first scan driver, a second scan driver, and a third scan driver. The first scan driver supplies a first scan signal to a first scan line at a second frequency corresponding to the image refresh rate of the pixel. The second scan driver supplies a second scan signal to a second scan line at a second frequency. The third scan driver supplies a third scan signal to a third scan line at a first frequency. The transmit driver may include a first transmit driver and a second transmit driver. The first transmit driver supplies a first transmit control signal to a first transmit control line at a first frequency. The second transmit driver supplies a second transmit control signal to a second transmit control line at a first frequency. The data driver can supply a data signal to a data line according to the second frequency.

[0032] The first scan driver and the second scan driver can supply the first scan signal and the second scan signal during the display scan period of a frame, and not supply the first scan signal and the second scan signal during the self-scan period of a frame. During the display scan period, data signals can be written to pixels, and during the self-scan period, the first transistor can be biased by the voltage supplied from the first power supply and the first transmit control signal.

[0033] The pixel may also be connected to a fourth scan line, the scan driver may also include a fourth scan driver that supplies a fourth scan signal to the fourth scan line at a first frequency, and at least one pixel may also include an eighth transistor connected between a second node and a corresponding second transmit control line among a plurality of second transmit control lines, the eighth transistor receiving the fourth scan signal.

[0034] The first scan driver and the second scan driver can supply the first scan signal and the second scan signal during the display scan period in a frame, and not supply the first scan signal and the second scan signal during the self scan period in a frame. During the display scan period, the data signal can be written to the pixel, and during the display scan period and the self scan period, the first transistor can be biased by the fourth scan signal and the second transmit control signal.

[0035] The pixel may also be connected to a fourth scan line, the scan driver may also include a fourth scan driver that supplies a fourth scan signal to the fourth scan line at a first frequency, and at least one pixel may also include an eighth transistor connected between a second node and a corresponding first transmit control line, the eighth transistor receiving the fourth scan signal.

[0036] The pixel may also be connected to a fourth scan line, and the scan driver may also include a fourth scan driver that supplies a fourth scan signal to the fourth scan line at a first frequency. At least one pixel may also include an eighth transistor connected between a fifth node between a first transistor and a fifth transistor and a corresponding second transmit control line among a plurality of second transmit control lines, the eighth transistor receiving the fourth scan signal.

[0037] The pixel may also be connected to a fourth scan line, and the scan driver may also include a fourth scan driver that supplies the fourth scan signal to the fourth scan line at a first frequency. At least one pixel may also include an eighth transistor connected between a fifth node between the first transistor and the fifth transistor and a corresponding first transmit control line in the first transmit control line, the eighth transistor receiving the fourth scan signal. Attached Figure Description

[0038] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0039] Figure 2 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention.

[0040] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0041] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0042] Figure 5A This is a diagram illustrating an example of a driving method for a display device based on the image refresh rate.

[0043] Figure 5B This is a diagram illustrating a driving method for a display device based on the image refresh rate.

[0044] Figure 6A It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0045] Figure 6B It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0046] Figure 7A It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0047] Figure 7B It is shown Figure 2 The waveform diagram shows an example of the operation of the pixel shown.

[0048] Figure 8 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention.

[0049] Figure 9A It is shown Figure 8 The waveform diagram shows an example of the operation of the pixel shown.

[0050] Figure 9B It is shown Figure 8 The waveform diagram shows an example of the operation of the pixel shown.

[0051] Figure 10 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention.

[0052] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0053] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0054] Figure 13 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0055] Figure 14 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0056] Figure 15 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0057] Figure 16 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0058] Figure 17 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0059] Figure 18 It is shown Figure 10 The waveform diagram shows an example of the operation of the pixel shown.

[0060] Figure 19 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention.

[0061] Figure 20 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention.

[0062] Figure 21 This is a circuit diagram illustrating a pixel according to an embodiment of the present invention. Detailed Implementation

[0063] Embodiments of the invention will now be described more fully below with reference to the accompanying drawings. However, it will be understood that the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein.

[0064] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Throughout the specification, similar reference numerals may refer to similar elements.

[0065] Unless the context clearly indicates otherwise, the singular form as used herein is intended to include the plural form as well.

[0066] In the specification, when a component is referred to as “connected” or “coupled” to another component, it is able to be directly connected or coupled to the other component, or indirectly connected or coupled to the other component through one or more intermediate components in between.

[0067] Figure 1 This is a block diagram illustrating a display device 1000 according to an embodiment of the present invention.

[0068] Reference Figure 1 The display device 1000 may include a display panel 100, a first scan driver 200, a second scan driver 300, a third scan driver 400 and a fourth scan driver 500, a first transmit driver 600 and a second transmit driver 700, a data driver 800 and a timing controller 900.

[0069] The first scan driver 200, the second scan driver 300, the third scan driver 400, and the fourth scan driver 500 may be four separate scan drivers or part of a single scan driver. The first transmit driver 600 and the second transmit driver 700 may be two separate transmit drivers or part of a single transmit driver. However, the distinction between scan drivers and transmit drivers is for the sake of description, and at least some of the scan drivers and transmit drivers may be integrated into a single drive circuit or a module, etc.

[0070] In embodiments of the present invention, the display device 1000 may further include a power supply that supplies voltages of a first power supply VDD, a second power supply VSS, a third power supply Vref (or a reference power supply), and a fourth power supply Vint (or an initialization power supply) to the display panel 100. The power supply may supply low and high power supplies to the first scan driver 200, the second scan driver 300, the third scan driver 400, and the fourth scan driver 500 and / or the first transmit driver 600 and the second transmit driver 700, whereby the low and high power supplies determine the gate on and gate off levels of scan signals, control signals, and / or transmit control signals. The low power supply may have a voltage level lower than that of the high power supply. However, this is merely illustrative, and at least one of the low and high power supplies may be supplied from a timing controller 900 or a data driver 800.

[0071] In some embodiments of the present invention, a first power supply VDD and a second power supply VSS can generate a voltage for driving a light-emitting element. The first power supply VDD can be provided via a first power line, and the second power supply VSS can be provided via a second power line. In embodiments of the present invention, the voltage level of the second power supply VSS can be lower than the voltage level of the first power supply VDD. For example, the voltage of the first power supply VDD can be a positive voltage, and the voltage of the second power supply VSS can be a negative voltage.

[0072] The reference power supply Vref can be the power supply used to initialize pixel PX. For example, capacitors and / or transistors included in pixel PX can be initialized by the voltage of the reference power supply Vref. The voltage of the reference power supply Vref can be a positive voltage.

[0073] The initialization power supply Vint can be a power supply used to initialize pixel PX. For example, driving transistors and / or light-emitting elements included in pixel PX can be initialized by the voltage of the initialization power supply Vint. The voltage of the initialization power supply Vint can be a negative voltage.

[0074] The display device 1000 can display images at various image refresh rates (e.g., drive frequency or screen refresh rate) depending on different driving conditions. Image refresh rate is the frequency at which data signals are written to the drive transistors of pixels PX. For example, image refresh rate (also called screen scan rate or screen refresh frequency) represents the frequency at which the display screen is reproduced per second.

[0075] In embodiments of the invention, the output frequency of the data driver 800 relative to a horizontal line (or pixel row) and / or the output frequency of the first scan driver 200 for writing scan signals can be determined to correspond to the image refresh rate. For example, the refresh rate for motion picture driving can be a frequency of about 60 Hz or higher (e.g., 120 Hz).

[0076] In embodiments of the present invention, the display device 1000 can adjust the output frequencies of the first scan driver 200, the second scan driver 300, the third scan driver 400, and the fourth scan driver 500 relative to a horizontal line (or pixel row) and the output frequency of the corresponding data driver 800. For example, the display device 1000 can display images corresponding to various image refresh rates from 1Hz to 120Hz. However, this is merely illustrative, and the display device 1000 can display images at image refresh rates of 120Hz or higher (e.g., 240Hz or 480Hz).

[0077] The display panel 100 may include pixels PX connected to data line DL, first scan line SL1, second scan line SL2, third scan line SL3, and fourth scan line SL4, as well as first emission control line EL1 and second emission control line EL2. Pixels PX may be supplied with voltages from an external first power supply VDD, a second power supply VSS, an initialization power supply Vint, and a reference power supply Vref. In an embodiment of the invention, pixels PX arranged in the i-th row and j-th column (i and j are natural numbers) may be connected to the first scan line SL1i, second scan line SL2i, third scan line SL3i, and fourth scan line SL4i corresponding to the i-th pixel row, the first emission control line EL1i and second emission control line EL2i corresponding to the i-th pixel row, and the data line DLj corresponding to the j-th pixel column.

[0078] In this embodiment, the signal lines connected to the pixel PX, such as the first scan line SL1, the second scan line SL2, the third scan line SL3 and the fourth scan line SL4, the first emission control line EL1 and the second emission control line EL2, and the data line DL, can be configured in various ways to correspond to the circuit structure of the pixel PX.

[0079] Corresponding to the externally supplied synchronization signal, the timing controller 900 can generate a first drive control signal SCS1, a second drive control signal SCS2, a third drive control signal SCS3, a fourth drive control signal SCS4, a fifth drive control signal ECS1, a sixth drive control signal ECS2, and a seventh drive control signal DCS. The first drive control signal SCS1 can be supplied to the first scan driver 200, the second drive control signal SCS2 to the second scan driver 300, the third drive control signal SCS3 to the third scan driver 400, the fourth drive control signal SCS4 to the fourth scan driver 500, the fifth drive control signal ECS1 to the first transmit driver 600, the sixth drive control signal ECS2 to the second transmit driver 700, and the seventh drive control signal DCS to the data driver 800. Additionally, the timing controller 900 can rearrange the externally supplied input image data into image data RGB and supply the image data RGB to the data driver 800.

[0080] The first drive control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse controls the first moment of the scan signal output from the first scan driver 200. The clock signal can be used to shift the first scan start pulse.

[0081] The second drive control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse controls the first moment of the scan signal output from the second scan driver 300. The clock signal can be used to shift the second scan start pulse.

[0082] The third drive control signal SCS3 may include a third scan start pulse and a clock signal. The third scan start pulse controls the initial moment of the scan signal output from the third scan driver 400. The clock signal can be used to shift the third scan start pulse.

[0083] The fourth drive control signal SCS4 may include a fourth scan start pulse and a clock signal. The fourth scan start pulse controls the initial moment of the scan signal output from the fourth scan driver 500. The clock signal can be used to shift the fourth scan start pulse.

[0084] The fifth drive control signal ECS1 may include a first transmit control start pulse and a clock signal. The first transmit control start pulse controls the first moment of the transmit control signal output from the first transmit driver 600. The clock signal can be used to shift the first transmit control start pulse.

[0085] The sixth drive control signal ECS2 may include a second transmit control start pulse and a clock signal. The second transmit control start pulse controls the initial timing of the transmit control signal output from the second transmit driver 700. The clock signal can be used to shift the second transmit control start pulse.

[0086] The seventh drive control signal (DCS) may include an active start pulse and a clock signal. The active start pulse controls the start time of data sampling. The clock signal can be used to control the sampling operation.

[0087] The first scan driver 200 may receive a first drive control signal SCS1 from the timing controller 900 and supply a scan signal (e.g., a first scan signal) to the first scan line SL1 based on the first drive control signal SCS1. In other words, the first scan driver 200 may supply the first scan signal in response to the first drive control signal SCS1. For example, the first scan driver 200 may sequentially supply the first scan signal to a plurality of first scan lines SL1. When the first scan signal is supplied sequentially, pixels PX may be selected in units of horizontal lines (or pixel rows), and data signals may be supplied to pixels PX. In other words, the first scan signal may be a signal used for data writing.

[0088] The first scan signal can be configured to have a gate on level (e.g., low voltage). When the first scan signal is supplied, the transistor included in the pixel PX and receiving the first scan signal can be configured to be in the on state.

[0089] In an embodiment of the present invention, corresponding to the i-th first scan line SL1i, the first scan driver 200 can supply a scan signal (e.g., a first scan signal) to one of the plurality of first scan lines SL1 (e.g., the i-th first scan line SL1i) at a frequency (e.g., a second frequency) that is the same as the image refresh rate of the display device 1000. The second frequency can be set as a divisor of the first frequency that drives the first transmitter driver 600 and the second transmitter driver 700.

[0090] The first scan driver 200 can supply scan signals to the first scan lines SL1 during a display scan period of a frame. For example, during the display scan period, the first scan driver 200 can supply at least one scan signal to each of the plurality of first scan lines SL1.

[0091] The second scan driver 300 may receive a second drive control signal SCS2 from the timing controller 900 and supply a scan signal (e.g., a second scan signal) to the second scan lines SL2 based on the second drive control signal SCS2. In other words, the second scan driver 300 may supply the second scan signal in response to the second drive control signal SCS2. For example, the second scan driver 300 may sequentially supply the second scan signal to a plurality of second scan lines SL2. The second scan signal may be supplied to initialize the pixel PX and / or compensate the threshold voltage (Vth). When the second scan signal is supplied, the pixel PX may perform threshold voltage compensation operation and / or initialization operation.

[0092] The second scan signal can be configured to have a gate on level (e.g., low voltage). When the second scan signal is supplied, the transistor included in the pixel PX and receiving the second scan signal can be configured to be in the on state.

[0093] In an embodiment of the present invention, corresponding to the i-th second scan line SL2i, the second scan driver 300 can supply a scan signal (e.g., a second scan signal) to one of the plurality of second scan lines SL2 (e.g., the i-th second scan line SL2i) at the same frequency (e.g., a second frequency) as the output of the first scan driver 200.

[0094] The second scan driver 300 can supply scan signals to the second scan line SL2 during a display scan period of a frame. For example, during the display scan period, the second scan driver 300 can supply at least one scan signal to each of the plurality of second scan lines SL2.

[0095] The third scan driver 400 may receive a third drive control signal SCS3 from the timing controller 900 and supply a scan signal (e.g., a third scan signal) to the third scan line SL3 based on the third drive control signal SCS3. In other words, the third scan driver 400 may supply a third scan signal in response to the third drive control signal SCS3. For example, the third scan driver 400 may sequentially supply the third scan signal to a plurality of third scan lines SL3. The third scan signal may be supplied to initialize the light-emitting elements included in each of a plurality of pixels PX and / or initialize the capacitors included in the pixels PX. When the third scan signal is supplied, the pixels PX may perform the initialization operation of the light-emitting elements and / or the initialization operation of the capacitors.

[0096] The third scan signal can be configured to have a gate on level (e.g., low voltage). When the third scan signal is supplied, the transistor included in the pixel PX and receiving the third scan signal can be configured to be in the on state.

[0097] In an embodiment of the present invention, corresponding to the i-th third scan line SL3i, the third scan driver 400 can supply a scan signal (e.g., a third scan signal) to one of the plurality of third scan lines SL3 (e.g., the i-th third scan line SL3i) at a constant frequency (e.g., a first frequency) that is independent of the frequency of the image refresh rate of the display device 1000.

[0098] Furthermore, the first frequency at which the third scan driver 400 supplies the scan signal can be set to be greater than the second frequency. In embodiments of the present invention, the frequency of the image refresh rate (and the second frequency) can be set as a divisor of the first frequency.

[0099] For example, the third scan driver 400 can perform one scan during the display scan period and at least one scan according to the image refresh rate during the self-scan period, with all driving frequencies capable of driving the display device 1000.

[0100] In other words, the scan signal can be sequentially output to each of the plurality of third scan lines SL3 once during the display scan period, and sequentially output to each of the plurality of third scan lines SL3 at least once during the self-scan period.

[0101] Additionally, when the image refresh rate decreases, the third scan driver 400 can increase the number of times the scan signal is repeatedly supplied to each of the multiple third scan lines SL3 within a frame period.

[0102] The fourth scan driver 500 may receive a fourth drive control signal SCS4 from the timing controller 900 and provide a scan signal (e.g., a fourth scan signal) to the fourth scan line SL4 based on the fourth drive control signal SCS4. In other words, the fourth scan driver 500 may supply the fourth scan signal in response to the fourth drive control signal SCS4. For example, the fourth scan driver 500 may sequentially supply the fourth scan signal to a plurality of fourth scan lines SL4. The fourth scan signal may be supplied to supply a predetermined bias voltage (e.g., a turn-on bias voltage and / or a turn-off bias voltage) to the source and / or drain electrodes of the drive transistors of each of a plurality of pixels PX. When the fourth scan signal is supplied, the pixel PX may perform a bias voltage supply operation.

[0103] The fourth scan signal can be configured to have a gate on level (e.g., low voltage). When the fourth scan signal is supplied, the transistor included in the pixel PX and receiving the fourth scan signal can be configured to be in the on state.

[0104] In an embodiment of the invention, similar to the third scan driver 400, corresponding to the i-th fourth scan line SL4i, the fourth scan driver 500 can supply a scan signal (e.g., a fourth scan signal) at a first frequency to one of the plurality of fourth scan lines SL4 (e.g., the i-th fourth scan line SL4i). Therefore, within a frame period, the scan signal supplied to each of the plurality of fourth scan lines SL4 can be repeatedly supplied for each predetermined period.

[0105] Therefore, when the image refresh rate decreases, the number of times the fourth scan signal is repeatedly supplied within a frame period can be increased.

[0106] The first transmit driver 600 may receive a fifth drive control signal ECS1 from the timing controller 900, and supply a transmit control signal (e.g., a first transmit control signal) to the first transmit control line EL1 based on the fifth drive control signal ECS1. In other words, the first transmit driver 600 may supply the first transmit control signal in response to the fifth drive control signal ECS1. For example, the first transmit driver 600 may sequentially supply the first transmit control signal to a plurality of first transmit control lines EL1.

[0107] The second transmit driver 700 can receive a sixth drive control signal ECS2 from the timing controller 900 and supply a transmit control signal (e.g., a second transmit control signal) to the second transmit control line EL2 based on the sixth drive control signal ECS2. In other words, the second transmit driver 700 can supply the second transmit control signal in response to the sixth drive control signal ECS2. For example, the second transmit driver 700 can sequentially supply the second transmit control signal to multiple second transmit control lines EL2.

[0108] When the first emission control signal and / or the second emission control signal are supplied, pixel PX may not emit light in units of horizontal lines (or pixel rows). To achieve this, the first and second emission control signals may be configured to have gate off levels (e.g., high voltages) capable of turning off the transistors included in each of the plurality of pixels PX. The transistors included in the pixel PX and receiving the first and / or second emission control signals may be turned off when the first and / or second emission control signals are supplied, and otherwise set to an on state.

[0109] The first and second transmission control signals can be used to control the emission time of pixel PX. To achieve this, the first and second transmission control signals can be set to have a width wider than the width of the scan signal.

[0110] In embodiments of the present invention, the first transmit control signal and / or the second transmit control signal may have multiple gate-off level (e.g., high voltage) periods during a frame period. For example, the first transmit control signal and / or the second transmit control signal may include multiple gate-on periods and multiple gate-off periods to perform bias state control, initialization, threshold voltage compensation, etc. of the driving transistor.

[0111] In embodiments of the invention, the second transmit control signal supplied to pixel PX may be a signal shifted from the first transmit control signal by a predetermined horizontal time period (e.g., six horizontal time periods). For example, the second transmit control signal supplied to the nth (n is a natural number) pixel row may have the same waveform as the first transmit control signal supplied to the (n+6)th pixel row. However, this is merely illustrative, and the second transmit control signal may be a signal shifted from the first transmit control signal by six or more horizontal time periods.

[0112] In embodiments of the present invention, the first transmission control signal and the second transmission control signal supplied to pixel PX can be the same signal. For example, the first transmission control signal and the second transmission control signal supplied to the same pixel row can have the same waveform.

[0113] In embodiments of the present invention, similar to the third scan driver 400, corresponding to the i-th first transmit control line EL1i and the i-th second transmit control line EL2i, the first transmit driver 600 and the second transmit driver 700 can supply transmit control signals (e.g., first transmit control signals and second transmit control signals) at a first frequency to one of the plurality of first transmit control lines EL1 (e.g., the i-th first transmit control line EL1i) and one of the plurality of second transmit control lines EL2 (e.g., the i-th second transmit control line EL2i). Therefore, within a frame period, the transmit control signals supplied to the first transmit control line EL1 and the second transmit control line EL2 can be repeatedly supplied for each predetermined period.

[0114] Therefore, when the image refresh rate decreases, the number of times the first transmit control signal and the second transmit control signal are repeatedly supplied within a frame period can be increased.

[0115] The data driver 800 can receive a seventh drive control signal DCS and image data RGB. The data driver 800 can supply a data signal corresponding to the seventh drive control signal DCS to the data line DL. The data signal supplied to the data line DL can be supplied to the pixel PX selected by the scan signal (e.g., a first scan signal). To achieve this, the data driver 800 can supply the data signal to the data line DL synchronously with the scan signal.

[0116] In embodiments of the present invention, corresponding to the image refresh rate, the data driver 800 can supply data signals to the data line DL during a frame period. For example, the data driver 800 can supply data signals synchronously with the scan signal supplied to the first scan line SL1.

[0117] Figure 2 This is a circuit diagram illustrating pixel PX1 according to an embodiment of the present invention.

[0118] For ease of description, Figure 2 The image shows pixel PX1, which is located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line DLj. Figure 2 The pixel PX1 shown can be compared with Figure 1 The pixels PX shown are essentially the same.

[0119] Reference Figure 2 Pixel PX1 may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, a first capacitor C1 and a second capacitor C2.

[0120] In embodiments of the present invention, the first transistor T1 to the eighth transistor T8 may all be transistors of the same type. For example, the first transistor T1 to the eighth transistor T8 may be implemented using a P-channel metal-oxide-semiconductor (PMOS) transistor. The first transistor T1 to the eighth transistor T8 may include an active layer formed of polysilicon semiconductor. For example, the active layer of the first transistor T1 to the eighth transistor T8 may be formed using a low-temperature polysilicon (LTPS) process. However, the present invention is not limited thereto, and at least one of the first transistor T1 to the eighth transistor T8 may be implemented using an N-channel metal-oxide-semiconductor (NMOS) transistor including an oxide active layer.

[0121] The first electrode of the light-emitting element LD can be connected to the second electrode (e.g., the drain electrode) of the first transistor T1 via the sixth transistor T6, and the second electrode of the light-emitting element LD can be connected to the second power supply VSS. For example, the first electrode of the light-emitting element LD can be electrically connected to the second electrode of the first transistor T1 via the fourth node N4, and one electrode of the sixth transistor T6 and one electrode of the seventh transistor T7 are jointly connected to the fourth node N4.

[0122] The light-emitting element (LD) can generate light with a predetermined brightness corresponding to the amount of current (e.g., drive current) supplied from the first transistor T1. In embodiments of the invention, the light-emitting element (LD) may be an organic light-emitting diode (OLED) including an organic light-emitting layer. The first electrode of the light-emitting element (LD) may be an anode, and the second electrode of the light-emitting element (LD) may be a cathode. In alternative embodiments, the first electrode of the light-emitting element (LD) may be a cathode, and the second electrode of the light-emitting element (LD) may be an anode.

[0123] In embodiments of the present invention, the light-emitting element LD may be an inorganic light-emitting element formed of inorganic materials. Alternatively, the light-emitting element LD may include multiple inorganic light-emitting elements connected in parallel or series between the second power supply VSS and the fourth node N4.

[0124] In embodiments of the present invention, the light-emitting element (LD) can be made of a combination of organic and inorganic materials.

[0125] The first transistor T1 is connected to the first power supply VDD via the fifth transistor T5 and to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 generates a drive current and provides this drive current to the light-emitting element LD. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can be used as the driving transistor for pixel PX1. The first transistor T1 can control the amount of current flowing from the first power supply VDD through the light-emitting element LD to the second power supply VSS, corresponding to the voltage applied to the first node N1.

[0126] A first capacitor C1 can be connected between a second node N2 and a third node N3 corresponding to the second electrode of the first transistor T1. The first capacitor C1 can store the voltage corresponding to the voltage difference between the second node N2 and the third node N3.

[0127] The second capacitor C2 can be connected between the first power supply VDD and the first node N1. The second capacitor C2 can store the voltage corresponding to the voltage difference between the first power supply VDD and the first node N1.

[0128] When a data signal is written to pixel PX1, due to charge sharing between the first capacitor C1 and the second capacitor C2, the first node N1 and the second node N2 may have voltages based on the ratio of the capacitances of the first capacitor C1 and the second capacitor C2.

[0129] A second transistor T2 may be connected between the j-th data line DLj and the third node N3. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the i-th first scan line SL1i to receive a first scan signal. When the first scan signal is supplied to the i-th first scan line SL1i, the second transistor T2 may be turned on to electrically connect the j-th data line DLj and the third node N3. Therefore, a data signal (or data voltage) can be transmitted to the third node N3.

[0130] A third transistor T3 may be connected between a first node N1 (connected to the gate electrode of the first transistor T1) and a second node N2 (or the second electrode or drain electrode of the first transistor T1). The third transistor T3 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the third transistor T3 may be connected to the i-th second scan line SL2i to receive a second scan signal. When the second scan signal is supplied to the i-th second scan line SL2i, the third transistor T3 may be turned on to electrically connect the first node N1 and the second node N2. When the third transistor T3 is turned on, the voltage of the initialization power supply Vint may be supplied to the first node N1 (or the gate electrode of the first transistor T1), and the first transistor T1 may have a diode connection.

[0131] When the first transistor T1 has a diode connection, the threshold voltage of the first transistor T1 can be compensated.

[0132] Therefore, the first transistor T1 can generate a drive current as shown in Equation 1 below based on the data signal, the first capacitor C1, and the second capacitor C2.

[0133] Equation 1

[0134] Id = k[a(Vref - Vdata)] 2 a = CC2 / (CC1+CC2)

[0135] In Equation 1, Id can be the driving current, k can be a unique characteristic of the first transistor T1, Vref can be the voltage of the third power supply Vref (or the reference power supply), Vdata can be the voltage corresponding to the data signal, CC1 can be the capacitance of the first capacitor C1, and CC2 can be the capacitance of the second capacitor C2. The light-emitting element LD can emit light with a brightness corresponding to the driving current Id.

[0136] A fourth transistor T4 may be connected between the reference power supply Vref and the third node N3. The fourth transistor T4 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fourth transistor T4 may be connected to the i-th third scan line SL3i to receive the third scan signal. When the third scan signal is supplied to the i-th third scan line SL3i, the fourth transistor T4 may be turned on to electrically connect the reference power supply Vref and the third node N3. Therefore, the voltage of the reference power supply Vref may be supplied to the third node N3. Thus, the voltage of the third node N3 may be initialized to the voltage of the reference power supply Vref.

[0137] In embodiments of the invention, the voltage level of the reference power supply Vref can be set to be equal to the voltage level of the first power supply VDD. To initialize the third node N3, a separate power supply (e.g., the reference power supply Vref) instead of the first power supply VDD is connected to the fourth transistor T4, so that variations in the drive current Id (or brightness variations) based on the voltage drop (e.g., IR drop) of the first power supply VDD, which can occur according to the relative position of the pixel PX1, can be minimized. For example, in Equation 1, the drive current Id includes a portion of Vref that is the voltage of the reference power supply Vref but not the voltage of the first power supply VDD, so that variations in the drive current Id based on the voltage drop (e.g., IR drop) of the first power supply VDD can be minimized.

[0138] Additionally, the fourth transistor T4 can be turned on during the period when the threshold voltage compensation of the first transistor T1 is performed. Therefore, during the period when the threshold voltage compensation is performed, the voltage of the third node N3 can be stably maintained at the voltage of the reference power supply Vref (e.g., direct current, DC voltage).

[0139] A fifth transistor T5 may be connected between the first power supply VDD and the first electrode of the first transistor T1. For example, the fifth transistor T5 may be connected between the first power supply VDD and the source electrode of the first transistor T1. The fifth transistor T5 may include a gate electrode for receiving a transmit control signal. For example, the gate electrode of the fifth transistor T5 may be connected to the i-th first transmit control line EL1i to receive the first transmit control signal. The fifth transistor T5 may be turned off when the first transmit control signal is supplied to the i-th first transmit control line EL1i, and turned on under other conditions. When the fifth transistor T5 is in the turned-on state, it may connect the first electrode of the first transistor T1 to the first power supply VDD.

[0140] A sixth transistor T6 may be connected between a second node N2, corresponding to the second electrode of the first transistor T1, and a light-emitting element LD (or a fourth node N4). The sixth transistor T6 may include a gate electrode for receiving a transmission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the i-th second transmission control line EL2i to receive a second transmission control signal. The sixth transistor T6 may be turned off when the second transmission control signal is supplied to the i-th second transmission control line EL2i, and turned on under other conditions. When in the on state, the sixth transistor T6 may be electrically connected to the second node N2 and the fourth node N4. In other words, when the sixth transistor T6 is on, the first transistor T1 may be connected to the light-emitting element LD.

[0141] In an embodiment of the present invention, the i-th second transmission control line EL2i may be a line branching from the first transmission control line corresponding to a previous horizontal line (e.g., the (i-6)th horizontal line). Display device (e.g., Figure 1 The display device 1000 shown may not separately include an emission driver for supplying a second emission control signal to the pixel PX1 (e.g., Figure 1 The second transmitter driver 700 shown in the figure. Therefore, it is possible to reduce the size of the display device (e.g., Figure 1 The dead zone of the display device 1000 shown.

[0142] However, this is merely illustrative, and the transmit control line branching from the first transmit control line and identified as the i-th second transmit control line EL2i is not limited thereto. For example, the transmit control line branching from the first transmit control line may be determined by the time required to perform threshold voltage compensation, the resolution, the length of a horizontal time period 1H, etc.

[0143] When both the fifth transistor T5 and the sixth transistor T6 are turned on, the light-emitting element LD can emit light with a brightness corresponding to the voltage of the first node N1.

[0144] In an embodiment of the present invention, when the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, threshold voltage compensation of the first transistor T1 can be performed.

[0145] In an embodiment of the present invention, when the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, the initialization operation of the first transistor T1 can be performed.

[0146] The seventh transistor T7 can be connected to the light-emitting element LD (or the fourth node N4) and the initialization power supply Vint. The seventh transistor T7 may include a gate electrode for receiving scan signals. For example, the gate electrode of the seventh transistor T7 can be connected to the i-th third scan line SL3i to receive the third scan signal. When the third scan signal is supplied to the i-th third scan line SL3i, the seventh transistor T7 can be turned on to electrically connect the initialization power supply Vint and the fourth node N4. Therefore, the voltage of the fourth node N4 (or the first electrode of the light-emitting element LD) can be initialized to the voltage of the initialization power supply Vint. When the voltage of the initialization power supply Vint is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Because the residual voltage charged in the parasitic capacitor is discharged (e.g., eliminated or removed), unintentional fine emission can be prevented. Therefore, the black representation capability of pixel PX1 can be improved.

[0147] Furthermore, since the gate electrodes of the fourth transistor T4 and the seventh transistor T7 are connected to the same scan line (e.g., the i-th third scan line SL3i), the fourth transistor T4 and the seventh transistor T7 can be turned off or turned on simultaneously.

[0148] The eighth transistor T8 may be connected between the second electrode (or second node N2) of the first transistor T1 and the i-th second emitter control line EL2i. For example, the eighth transistor T8 may be connected to the second electrode of the first transistor T1. Furthermore, the eighth transistor T8 is connected between one electrode (e.g., the source electrode or drain electrode) and the gate electrode of the sixth transistor T6. The eighth transistor T8 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the eighth transistor T8 may be connected to the i-th fourth scan line SL4i to receive a fourth scan signal. When the fourth scan signal is supplied to the i-th fourth scan line SL4i, the eighth transistor T8 may be turned on to electrically connect the second node N2 and the i-th second emitter control line EL2i.

[0149] In an embodiment of the present invention, when a second emitter control signal having a gate-off level (e.g., a high voltage) is supplied to the i-th second emitter control line EL2i, the eighth transistor T8, which is in the on state, can supply a high voltage to the second electrode of the first transistor T1. Therefore, the first transistor T1 can have an on-biased state.

[0150] In an embodiment of the invention, when a second emitter control signal having a gate on level (e.g., low voltage) is supplied to the i-th second emitter control line EL2i, the eighth transistor T8, which is in the on state, can supply a low voltage to the second electrode (or second node N2) of the first transistor T1. Therefore, the second node N2 can be initialized by the second emitter control signal having a low voltage. Additionally, the first transistor T1 can have a turn-off bias state due to the low voltage supplied to its second electrode.

[0151] By applying a constant voltage bias to the first transistor T1 through the eighth transistor T8, hysteresis characteristics (or threshold voltage shift differences) caused by bias differences between adjacent pixels can be reduced. Therefore, screen attraction (e.g., ghosting) caused by hysteresis variations can be minimized.

[0152] Furthermore, the periods during which the second transistor T2 is turned on, and the periods during which the fourth transistor T4 and the fifth transistor T5 are turned on, do not overlap. For example, when the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, threshold voltage compensation for the first transistor T1 can be performed. When the second transistor T2 and the third transistor T3 are turned on, data writing can be performed. Therefore, the threshold voltage compensation period and the data writing period can be separated from each other.

[0153] In low-frequency drives where the length of a single frame period is extended, hysteresis may occur due to grayscale differences between adjacent pixels. Therefore, differences in the threshold voltage shift between the driving transistors of adjacent pixels may occur, and viewers may perceive screen snagging (e.g., ghosting) caused by these differences in threshold voltage shift.

[0154] In a display device according to an embodiment of the present invention, by using an eighth transistor T8, a bias can be periodically applied to the drain electrode (and / or source electrode) of a driving transistor (e.g., the first transistor T1) at a constant voltage period. Therefore, hysteresis caused by grayscale differences between adjacent pixels can be removed, and thus screen attraction can be reduced (or eliminated).

[0155] According to an embodiment of the present invention, pixel PX1 may include: a light-emitting element LD; a first transistor T1 connected between a first power supply VDD and a second node N2, the first transistor T1 including a gate electrode connected to the first node N1; a second transistor T2 connected between a third node N3 and a j-th data line DLj, the second transistor T2 including a gate electrode connected to the i-th first scan line SL1i; a third transistor T3 connected between the first node N1 and the second node N2, the third transistor T3 including a gate electrode connected to the i-th second scan line SL2i; a fifth transistor T5 connected between the first power supply VDD and the first transistor T1, the fifth transistor T5 including a gate electrode connected to the i-th first emission control line EL1i; a sixth transistor T6 connected between the second node N2 and the light-emitting element LD, the sixth transistor T6 including a gate electrode connected to the i-th second emission control line EL2i; and an eighth transistor T8 connected between the second node N2 and the i-th second emission control line EL2i, the eighth transistor T8 including a gate electrode connected to the i-th fourth scan line SL4i.

[0156] Figures 3A to 3G It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1.

[0157] Reference Figure 2 and Figure 3A During the display scan period DSP, signals for image display can be supplied to pixel PX1. The display scan period DSP may include the period during which the data signal DVj corresponding to the output image is written.

[0158] The first transmit control signal EM1i and the second transmit control signal EM2i can be supplied to the first transmit control line EL1i and the second transmit control line EL2i respectively (also referred to as the i-th first transmit control line and the i-th second transmit control line in this document), and the first scan signal GWi, the second scan signal GCI, the third scan signal EB1i and the fourth scan signal EB2i can be supplied to the first scan line SL1i, the second scan line SL2i, the third scan line SL3i and the fourth scan line SL4i respectively (also referred to as the i-th first scan line, the i-th second scan line, the i-th third scan line and the i-th fourth scan line in this document).

[0159] At the first time t1, the third scan signal EB1i can change from a gate-off level to a gate-on level. For example, the third scan signal EB1i can change from a high level to a low level. Therefore, the seventh transistor T7 can be turned on. Therefore, the voltage of the initialization power supply Vint is supplied to the fourth node N4 (or the first electrode of the light-emitting element LD) so that the fourth node N4 can be initialized to the voltage of the initialization power supply Vint.

[0160] Furthermore, the second scan signal GCI can change from a gate-off level to a gate-on level. For example, the second scan signal GCI can change from a high level to a low level at the same time as the third scan signal EB1i changes from a high level to a low level. Therefore, the third transistor T3 can be turned on. In addition, since the second emit control signal EM2i maintains a gate-on level, the sixth transistor T6 can be turned on or remain on. Therefore, the voltage of the initialization power supply Vint supplied to the fourth node N4 is supplied to the first node N1 (or the gate electrode of the first transistor T1) so that the first node N1 can be initialized to the voltage of the initialization power supply Vint.

[0161] Additionally, the fourth transistor T4 can be turned on by the third scan signal EB1i, which has a gate on level. Therefore, the voltage of the reference power supply Vref is supplied to the third node N3, allowing the third node N3 to be initialized to the voltage of the reference power supply Vref.

[0162] Therefore, in Figure 3B During the first time period P1a, which is highlighted diagonally from the first time t1 to the second time t2, the voltage of the initialization power supply Vint can be supplied to the first node N1, the voltage of the reference power supply Vref can be supplied to the third node N3, and the voltage of the initialization power supply Vint can be supplied to the fourth node N4. In other words, the first time period P1a can be an initialization period (or the first initialization period) for initializing the first electrode (or anode) of the light-emitting element LD, the gate electrode of the driving transistor (e.g., the first transistor T1), and the third node N3.

[0163] At the second time t2, the second transmit control signal EM2i can change from a gate-on level to a gate-off level. In other words, the second transmit control signal EM2i can change from a low level to a high level. Therefore, the sixth transistor T6 can be turned off.

[0164] At the third time t3, the first transmit control signal EM1i can change from a gate-off level to a gate-on level. For example, the first transmit control signal EM1i can have a gate-on level, while the second transmit control signal EM2i has a gate-off level. Because the first transmit control signal EM1i has a gate-on level, the fifth transistor T5 can be turned on. In addition, because the second scan signal GCi maintains a gate-on level, the third transistor T3 can remain on. Therefore, the first transistor T1 can have a diode connection, and the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the second capacitor C2.

[0165] Therefore, in Figure 3CDuring the second time period P2, which is highlighted diagonally from the third time period t3 to the fourth time period t4, the first transistor T1 is configured with a diode connection so that the threshold voltage of the first transistor T1 can be compensated. In other words, the second time period P2 can be a threshold voltage compensation period.

[0166] Additionally, during the second time period P2, threshold voltage compensation can be performed using the voltage of the first power supply VDD. Therefore, the threshold voltage compensation operation can be performed based on a fixed voltage rather than a data signal (e.g., data voltage) that can change according to pixel rows and / or frames.

[0167] Furthermore, during the second time period P2, the third scan signal EB1i maintains the gate on level, and therefore the fourth transistor T4 and the seventh transistor T7 can remain on. Thus, the initialization of the third node N3 and the fourth node N4 can be maintained during the second time period P2.

[0168] At the fourth time point t4, the first transmit control signal EM1i can be changed from the gate on level to the gate off level. Therefore, the fifth transistor T5 can be turned off.

[0169] At the fifth time point t5, the third scan signal EB1i can change from a gate-on level to a gate-off level. Therefore, the fourth transistor T4 and the seventh transistor T7 can be turned off.

[0170] At time t6, the first scan signal GWi changes from a gate-off level to a gate-on level, enabling the second transistor T2 to conduct. Therefore, the data signal DVj can be supplied to the third node N3. Because the second scan signal GCI maintains a gate-on level, the third transistor T3 can remain on. In other words, the gate-on times of the first scan signal GWi and the second scan signal GCI overlap.

[0171] Furthermore, when the data signal DVj is supplied to the third node N3, the voltage of the third node N3 can be reduced from the voltage of the reference power supply Vref to the voltage corresponding to the data signal DVj. Since the voltage of the reference power supply Vref is a fixed voltage (e.g., DC voltage), the reduced voltage of the third node N3 can be determined based on the voltage corresponding to the data signal DVj.

[0172] When the voltage at the third node N3 decreases, the voltage at the second node N2 also decreases accordingly due to the connection of the first capacitor C1.

[0173] Therefore, in Figure 3DDuring the third time period P3, which is highlighted diagonally from the sixth time period t6 to the seventh time period t7, the data signal DVj can be written to pixel PX1, and due to charge sharing, the voltage corresponding to the threshold voltage (Vth) and the data signal DVj can be stored in the second capacitor C2. In other words, the third time period P3 can be the data writing period.

[0174] In embodiments of the present invention, the length of the third time period P3, for example, the length (or pulse width) of the first scan signal GWi, may correspond to a horizontal time period 1H. However, the length of the first scan signal GWi is not limited thereto. For example, the length of the first scan signal GWi may correspond to two or more horizontal time periods 2H.

[0175] At time t7, the first scan signal GWi and the second scan signal GCI can be changed from gate on level to gate off level. Therefore, the second transistor T2 and the third transistor T3 can be turned off.

[0176] At time t8, the fourth scan signal EB2i can change from a gate-off level to a gate-on level. Therefore, the eighth transistor T8 can be turned on. Additionally, at time t8, a second emitter control signal EM2i with a high voltage (or gate-off level) can be supplied to the second emitter control line EL2i. Therefore, the high voltage of the second emitter control signal EM2i can be supplied to the second electrode (or drain electrode) of the first transistor T1.

[0177] Therefore, in Figure 3E During the fourth time period P4a, which is highlighted diagonally from the eighth time period t8 to the ninth time period t9, a conduction bias can be applied to the first transistor T1. In other words, the fourth time period P4a can be a conduction bias period (or the first conduction bias period).

[0178] At the ninth time t9, the second transmit control signal EM2i can be changed from a gate-off level to a gate-on level. In other words, the second transmit control signal EM2i with a low voltage can be supplied through the second transmit control line EL2i. Therefore, the low voltage of the second transmit control signal EM2i can be supplied to the second electrode (or drain electrode) of the first transistor T1.

[0179] Therefore, in Figure 3F During the fifth time period P5a, which is highlighted diagonally from the ninth time period t9 to the tenth time period t10, a turn-off bias can be applied to the first transistor T1. In other words, the fifth time period P5a can be a turn-off bias period (or a first turn-off bias period).

[0180] In the fourth time period P4a and the fifth time period P5a, the turn-on bias and turn-off bias are applied to the first transistor T1 so as to minimize the hysteresis characteristics of the first transistor T1 (e.g., threshold voltage shift).

[0181] Therefore, according to Figure 3A The operation shown refers to the pixel PX1 and the display device. Figure 1 In the 1000 shown, hysteresis characteristics are removed or minimized while removing the threshold voltage change of the first transistor T1. Therefore, image defects (e.g., flicker, color saturation, brightness reduction, etc.) can be minimized.

[0182] Furthermore, during the fifth time period P5a, a low voltage is supplied to the second electrode of the first transistor T1, for example, the second node N2, and thus the second node N2 can be initialized to the low voltage of the second emission control signal EM2i. Therefore, unintentional emission of light from the light-emitting element LD before the emission period due to current caused by the voltage difference between the second node N2 and the fourth node N4 can be prevented.

[0183] exist Figure 3G In the sixth time period P6a, highlighted diagonally after the eleventh time t11, both the first emission control signal EM1i and the second emission control signal EM2i have gate-on levels, and therefore, pixel PX1 can emit light. In other words, both the first emission control signal EM1i and the second emission control signal EM2i have low voltages. In other words, the sixth time period P6a can be an emission period (or the first emission period).

[0184] Figures 4A to 4E It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1.

[0185] Reference Figure 2 , Figure 3A and Figure 4A In order to maintain the brightness of the image output in the display scanning period DSP, the on bias voltage and / or off bias voltage can be applied to the second electrode (e.g., the drain electrode or the second node N2) of the first transistor T1 in the self-scanning period SSP.

[0186] Depending on the image frame rate, a frame may include at least one self-scanning period (SSP). The self-scanning period (SSP) may include the conduction bias period (or second conduction bias period) of the eighth period P4b, the de-off bias period (or second de-off bias period) of the ninth period P5b, and the transmission period (or second transmission period) of the tenth period P6b. Furthermore, besides those used for... Figure 3AApart from the signal supply for threshold voltage compensation in the second time period P2 (or threshold voltage compensation period) and the signal supply for data signal writing in the third time period P3 (or data writing period), Figure 4A The operation of the self-scanning period SSP shown is similar to Figure 3A The operation of the DSP during the display scan period is basically the same as shown.

[0187] In embodiments of the present invention, scan signals are not supplied to the second transistor T2 and the third transistor T3 during the self-scanning period SSP. For example, during the self-scanning period SSP, the first scan signal GWi and the second scan signal GCI supplied to the first scan line SL1i and the second scan line SL2i, respectively, may have a gate-off level (or a high level H). Therefore, the self-scanning period SSP does not include a threshold voltage compensation period (e.g., the second period P2) and a data writing period (e.g., the third period P3).

[0188] Because the third transistor T3 remains off during the self-scanning period (SSP), the voltage of the gate electrode of the first transistor T1 (e.g., the first node N1) is not affected by the drive during the self-scanning period (SSP).

[0189] exist Figure 4B During the seventh period P1b (or the second initialization period), which is highlighted diagonally from the twelfth time t12 to the thirteenth time t13, the seventh transistor T7 can be turned on so that the first electrode (or anode) of the light-emitting element LD is initialized to the voltage of the initialization power supply Vint, and the fourth transistor T4 can be turned on so that the third node N3 is initialized to the voltage of the reference power supply Vref.

[0190] exist Figure 4C During the eighth time period P4b (or the second conduction bias period), highlighted diagonally from the fourteenth time t14 to the fifteenth time t15, the eighth transistor T8 can be turned on so that a conduction bias is applied to the first transistor T1. Figure 4D During the ninth time period P5b (or the second off-bias period), highlighted diagonally from the fifteenth time t15 to the sixteenth time t16, the eighth transistor T8 can be turned on so that an off-bias can be applied to the first transistor T1. Therefore, the hysteresis characteristics of the first transistor T1 can be improved (e.g., threshold voltage shift), and image defects (e.g., flicker, color smudging, reduced brightness, etc.) in low-frequency drive can be minimized.

[0191] exist Figure 4EIn the tenth time period P6b (or the second emission period), which is highlighted diagonally after the seventeenth time period t17, the fifth transistor T5 and the sixth transistor T6 are turned on because both the first emission control signal EM1i and the second emission control signal EM2i have gate on levels, so that the pixel PX1 can emit light.

[0192] The third scan signal EB1i and the fourth scan signal EB2i, as well as the first transmit control signal EM1i and the second transmit control signal EM2i, can be supplied at a first frequency independent of the image refresh rate. Therefore, even when the image refresh rate changes, the initialization operation during the initialization period (e.g., the first period P1a and / or the seventh period P1b), the conduction bias application during the conduction bias period (e.g., the fourth period P4a and / or the eighth period P4b), and the shutdown bias application during the shutdown bias period (e.g., the fifth period P5a and / or the ninth period P5b) can always be performed periodically. Therefore, flicker can be minimized corresponding to various image refresh rates (e.g., low-frequency drive).

[0193] Furthermore, during the self-scanning period of SSP, the data driver ( Figure 1 The 800 shown can not supply any data signal to pixel PX1. Therefore, power consumption can be further reduced.

[0194] Figure 5A This is a diagram illustrating an example of a driving method for a display device 1000 based on an image refresh rate RR. Figure 5B This is a diagram illustrating the driving method of the display device 1000 according to the image refresh rate RR.

[0195] Reference Figures 1 to 5A Pixel PX can be executed in the DSP during the display scan period. Figures 3A to 3G The operations shown are performed during the self-scanning period (SSP). Figures 4A to 4E The operation shown is illustrated.

[0196] In embodiments of the present invention, the output frequencies of the first scan signal GWi and the second scan signal GCI can be changed according to the image refresh rate RR. For example, the first scan signal GWi and the second scan signal GCI can be output at a frequency equal to the image refresh rate RR (e.g., a second frequency).

[0197] In embodiments of the present invention, regardless of the image refresh rate RR, the third scan signal EB1i, the fourth scan signal EB2i, the first transmission control signal EM1i, and the second transmission control signal EM2i can be output at a constant frequency (e.g., a first frequency). For example, the output frequency of the third scan signal EB1i, the fourth scan signal EB2i, the first transmission control signal EM1i, and the second transmission control signal EM2i can be set to twice the maximum refresh rate of the display device 1000.

[0198] In embodiments of the present invention, the lengths of the display scan period (DSP) and the self-scanning period (SSP) can be substantially the same. However, the number of self-scanning periods (SSPs) included in a frame period can be determined based on the image refresh rate (RR).

[0199] like Figure 5A As shown, when the display device 1000 is driven at an image refresh rate RR of 120Hz, a frame period may include a display scan period DSP and a self-scan period SSP. Therefore, when the display device 1000 is driven at an image refresh rate RR of 120Hz, each of the plurality of pixels PX may alternately repeat transmitting and non-transmitting twice during a frame period.

[0200] Furthermore, when the display device 1000 is driven at an image refresh rate RR of 80Hz, a frame period may include one display scan period DSP and two consecutive self-scan period SSPs. For example, a frame period may sequentially include one display scan period DSP and two self-scan period SSPs. Therefore, when the display device 1000 is driven at an image refresh rate RR of 80Hz, each of the plurality of pixels PX may alternately repeat transmitting and non-transmitting three times during a frame period.

[0201] In a similar manner, the display device 1000 adjusts the number of self-scanning periods (SSPs) included in a frame period to drive at drive frequencies such as 60Hz, 48Hz, 24Hz, and 1Hz. In other words, by using a frequency corresponding to a divisor of the first frequency, the display device 1000 is able to support various image refresh rates (RR).

[0202] Furthermore, the number of self-scanning period SSPs increases as the driving frequency decreases, so that a constant amplitude on-bias and / or a constant amplitude off-bias can be applied periodically to each of the plurality of first transistors T1 respectively included in the plurality of pixels PX. For example, when the display device 1000 is driven at an image refresh rate of 60Hz, one frame period may include one display scan period DSP and three self-scanning period SSPs. Alternatively, when the display device 1000 is driven at an image refresh rate of 24Hz, one frame period may include one display scan period DSP and nine self-scanning period SSPs. Therefore, brightness reduction, flicker, or screen trapping in low-frequency driving can be minimized.

[0203] like Figure 5B As shown, the display device 1000 can display an image by using different first start pulses FLM1 and second start pulses FLM2 according to the image refresh rate RR. For example, when the display device 1000 is driven at an image refresh rate RR of 80Hz, the display device 1000 can display an image by using the first start pulse FLM1. When the display device 1000 is driven at an image refresh rate RR of 60Hz, the display device 1000 can display an image by using the second start pulse FLM2. Because the first scan driver 200 and the second scan driver 300 are driven at different frequencies according to the image refresh rate RR, the first start pulse FLM1 and the second start pulse FLM2 can include first scan start pulses and second scan start pulses that are different from each other.

[0204] Figure 6A It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1. Figure 6B It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1.

[0205] Reference Figure 3A , Figure 4A , Figure 6A and Figure 6B ,Apart from Figure 6A and Figure 6B In addition to the second transmit control signal EM2i shown, Figure 6A and Figure 6B The multiple signals EM1i, GWi, GCI, EB1i, EB2i, and DVj shown are... Figure 3A and Figure 4AThe first transmit control signal EM1i, the first scan signal GWi, the second scan signal GCi, the third scan signal EB1i, the fourth scan signal EB2i, and the data signal DVj shown are substantially the same, and therefore, repetition of the description is unnecessary. For example, the second transmit control signal EM2i may transition from a high level to a low level at the twelfth time t12.

[0206] Reference Figure 1 , Figure 2 , Figure 6A and Figure 6B The second emission control line EL2i can be a line branching from the first emission control line corresponding to the previous horizontal line (e.g., the (i-6)th horizontal line). Therefore, the second emission control signal EM2i can be a signal shifted from the first emission control signal EM1i (e.g., shifted by six horizontal time intervals). As described above, the display device 1000 may not separately include an emission driver (e.g., a second emission driver 700) for supplying the second emission control signal EM2i to the pixel PX1. Therefore, the dead zone of the display device 1000 can be reduced.

[0207] Figure 7A It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1. Figure 7B It is shown Figure 2 The waveform diagram shows an example of the operation of pixel PX1.

[0208] Reference Figure 3A , Figure 4A , Figure 7A and Figure 7B ,Apart from Figure 7A Apart from the fifth time period P5a' shown, Figure 7A The pixel operations shown are Figure 3A The pixel operations shown are essentially the same or similar, except that... Figure 7B Apart from the ninth time period P5b' shown, Figure 7B The pixel operations shown are Figure 4A The pixel operations shown are essentially the same or similar. Therefore, repeated descriptions are unnecessary.

[0209] First, refer to Figure 2 and Figure 7AAt the ninth time t9, the third scan signal EB1i can change from a gate-off level to a gate-on level (e.g., transitioning low), and the fourth scan signal EB2i can change from a gate-on level to a gate-off level (e.g., transitioning high). Therefore, the seventh transistor T7 can be turned on. Additionally, the second emitter control signal EM2i can change from a gate-off level to a gate-on level. Therefore, the sixth transistor T6 can be turned on, such that the voltage of the initialization power supply Vint, which has a low voltage, is supplied to the second electrode (or drain electrode) of the first transistor T1. Therefore, during the fifth time period P5a' from the ninth time t9 to the tenth time t10, a turn-off bias can be applied to the first transistor T1 using the voltage of the initialization power supply Vint.

[0210] Similarly, refer to Figure 2 and Figure 7B ,and Figure 7A Similar to the pixel operation shown, in the ninth time period P5b', the voltage of the initialization power supply Vint, which has a low voltage, can be applied to the second electrode of the first transistor T1 so that a turn-off bias can be applied to the first transistor T1. For example, in the ninth time period P5b', the third scan signal EB1i and the fourth scan signal EB2i can have opposite voltage levels.

[0211] Figure 8 This is a circuit diagram illustrating pixel PX2 according to an embodiment of the present invention.

[0212] Reference Figure 1 , Figure 2 and Figure 8 Except that pixel PX2 does not include the eighth transistor T8 and is not connected to the fourth scan line SL4i, Figure 8 The pixel PX2 shown is Figure 2 The pixels PX1 shown are substantially the same or similar, and therefore, repeated descriptions are unnecessary. When the pixels PX included in the display device 1000 are implemented as Figure 8 When the number of pixels PX2 is shown, the display device 1000 may not include the fourth scan driver 500. Therefore, the dead zone of the display device 1000 can be reduced.

[0213] Figure 9A It is shown Figure 8 The waveform diagram shows an example of the operation of pixel PX2. Figure 9B It is shown Figure 8 The waveform diagram shows an example of the operation of pixel PX2.

[0214] Reference Figure 7A , Figure 7B , Figure 9A and Figure 9B ,exist Figure 9A and Figure 9B In addition to Figure 8 The pixel PX2 shown does not include the eighth transistor T8 so that in Figure 8 In the operation of pixel PX2 shown, the fourth scan signal EB2i is not supplied to anything other than pixel PX2. Figure 9A Operations of pixel PX2 in the middle Figure 7A The operation of pixel PX1 in the series is basically the same or similar (except for the fourth time segment P4a), and Figure 9B Operations of pixel PX2 in the middle Figure 7B The operation of pixel PX1 is essentially the same or similar (except for the eighth time segment P4b). Therefore, the repeated description is unnecessary.

[0215] Reference Figure 8 , Figure 9A and Figure 9B Without including any individual transistors (e.g., Figure 2 In the case of the eighth transistor T8 shown, Figure 8 The pixel PX2 shown applies a turn-off bias to the first transistor T1 using the voltage of the initialization power supply Vint, and initializes the second node N2 to the voltage of the initialization power supply Vint. Therefore, the hysteresis characteristics of the first transistor T1 can be improved (e.g., threshold voltage shift), and unintentional emission of the light-emitting element LD before the emission period can be prevented. Thus, the pixel PX2 (or display device) can be simplified. Figure 1 (1000 shown in the figure)

[0216] Figure 10 This is a circuit diagram illustrating pixel PX3 according to an embodiment of the present invention. Figure 10 The pixel PX3 shown can be compared with Figure 1 The pixels PX shown are essentially the same. Furthermore, aside from the connections between transistors and / or capacitors and some operations of pixel PX3, Figure 10 The pixel PX3 shown can be compared with Figure 2 The pixels PX1 shown are essentially the same or similar.

[0217] Reference Figure 10 The pixel PX3 may include a light-emitting element LD, a first transistor T1 to an eighth transistor T8, a first capacitor C1 and a second capacitor C2.

[0218] The first electrode of the light-emitting element LD can be connected to the second electrode (e.g., drain electrode or second node N2) of the first transistor T1 via the sixth transistor T6, and the second electrode of the light-emitting element LD can be connected to the second power supply VSS. For example, the first electrode of the light-emitting element LD can be electrically connected to the second electrode of the first transistor T1 via the fourth node N4, while one electrode of the sixth transistor T6 and one electrode of the seventh transistor T7 are jointly connected to the fourth node N4.

[0219] The first transistor T1 can be connected to the first power supply VDD via the fifth transistor T5, and to the first electrode of the light-emitting element LD via the sixth transistor T6. For example, the first transistor T1 can be connected to the sixth transistor T6 at the second node N2 between the third transistor T3 and the eighth transistor T8. The first transistor T1 can generate a drive current and provide the drive current to the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can be used as the driving transistor for the pixel PX3. The first transistor T1 can control the amount of current flowing from the first power supply VDD through the light-emitting element LD to the second power supply VSS, corresponding to the voltage applied to the first node N1.

[0220] A first capacitor C1 can be connected between a first node N1 and a third node N3 corresponding to the gate electrode of the first transistor T1. In other words, the first capacitor C1 can be directly connected to the gate electrode of the first transistor T1. The first capacitor C1 can store the voltage corresponding to the voltage difference between the first node N1 and the third node N3. In other words, the first capacitor C1 can store the voltage corresponding to the voltage difference between the gate electrode of the first transistor T1 and the third node N3.

[0221] The second capacitor C2 can be connected between the first power supply VDD and the third node N3. For example, one electrode of the second capacitor C2 can be connected to one electrode of the first capacitor C1. The second capacitor C2 can store the voltage corresponding to the voltage difference between the first power supply VDD and the third node N3. When one electrode of the second capacitor C2 is connected to the first power supply VDD, which serves as a static voltage source, and the other electrode of the second capacitor C2 is connected to the third node N3 (or the first capacitor C1), during the self-scan period when no data signal is written, the second capacitor C2 can maintain the data signal (or data voltage) written to the third node N3 by the second transistor T2 during the display scan period. In other words, the second capacitor C2 can stabilize the voltage of the third node N3.

[0222] A second transistor T2 may be connected between the data line DLj and the third node N3. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first scan line SL1i to receive a first scan signal. When the first scan signal is supplied to the first scan line SL1i, the second transistor T2 may be turned on to electrically connect the data line DLj and the third node N3. Therefore, a data signal (or data voltage) can be transmitted to the third node N3.

[0223] A third transistor T3 may be connected between a first node N1 and a second node N2 (or the second electrode or drain electrode of the first transistor T1) corresponding to the gate electrode of the first transistor T1. In other words, the third transistor T3 may be connected to the gate electrode and drain electrode of the first transistor T1. The third transistor T3 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the third transistor T3 may be connected to a second scan line SL2i to receive a second scan signal. When the second scan signal is supplied to the second scan line SL2i, the third transistor T3 may be turned on to electrically connect the first node N1 and the second node N2. When the third transistor T3 is turned on, the voltage of the initialization power supply Vint may be supplied to the first node N1 (or the gate electrode of the first transistor T1), or the first transistor T1 may have a diode connection. When the first transistor T1 has a diode connection, the threshold voltage of the first transistor T1 may be compensated.

[0224] A fourth transistor T4 may be connected between the reference power supply Vref and the third node N3. For example, the fourth transistor T4 may be connected to a terminal of the second capacitor C2. The fourth transistor T4 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fourth transistor T4 may be connected to the second scan line SL2i to receive the second scan signal. When the second scan signal is supplied to the second scan line SL2i, the fourth transistor T4 may be turned on to electrically connect the reference power supply Vref and the third node N3. Therefore, the voltage of the reference power supply Vref may be supplied to the third node N3. Thus, the voltage of the third node N3 may be initialized to the voltage of the reference power supply Vref.

[0225] Because the gate electrodes of the third transistor T3 and the fourth transistor T4 are connected to the same scan line (e.g., the second scan line SL2i), the third transistor T3 and the fourth transistor T4 can be turned off or turned on simultaneously.

[0226] A fifth transistor T5 may be connected between the first power supply VDD and the first electrode of the first transistor T1. The fifth transistor T5 may include a gate electrode for receiving a transmit control signal. For example, the gate electrode of the fifth transistor T5 may be connected to the first transmit control line EL1i to receive the first transmit control signal. The fifth transistor T5 may be turned off when the first transmit control signal is supplied to the first transmit control line EL1i, and turned on under other conditions. In other words, when the first transmit control signal is not supplied to the first transmit control line EL1i, the fifth transistor T5 may remain on. The fifth transistor T5, in the on state, may connect the first electrode of the first transistor T1 to the first power supply VDD.

[0227] A sixth transistor T6 may be connected between the second node N2, corresponding to the second electrode of the first transistor T1, and the light-emitting element LD (or the fourth node N4). The sixth transistor T6 may include a gate electrode for receiving a transmission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the second transmission control line EL2i to receive the second transmission control signal. The sixth transistor T6 may be turned off when the second transmission control signal is supplied to the second transmission control line EL2i, and turned on under other conditions. For example, when the second transmission control signal is not supplied to the second transmission control line EL2i, the sixth transistor T6 may remain on. The sixth transistor T6 in the on state may be electrically connected to the second node N2 and the fourth node N4.

[0228] In embodiments of the present invention, the first transmit control line EL1i and the second transmit control line EL2i may be the same line. In other words, the transmit control signal (or the first transmit control signal) applied to the fifth transistor T5 and the transmit control signal (or the second transmit control signal) applied to the sixth transistor T6 may have the same waveform. (For example, a display device...) Figure 1 The display device 1000 shown may include only one transmit driver, thereby enabling a reduction in the size of the display device (e.g., Figure 1 The dead zone of the display device 1000 shown.

[0229] When both the fifth transistor T5 and the sixth transistor T6 are turned on, the light-emitting element LD can emit light with a brightness corresponding to the voltage of the first node N1.

[0230] In an embodiment of the present invention, when the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, threshold voltage compensation of the first transistor T1 can be performed.

[0231] In an embodiment of the present invention, when the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, the initialization operation of the first transistor T1 can be performed.

[0232] The seventh transistor T7 can be connected to the light-emitting element LD (or the fourth node N4) and the initialization power supply Vint. The seventh transistor T7 may include a gate electrode for receiving scan signals. For example, the gate electrode of the seventh transistor T7 can be connected to the third scan line SL3i to receive the third scan signal. When the third scan signal is supplied to the third scan line SL3i, the seventh transistor T7 can be turned on to electrically connect the initialization power supply Vint and the fourth node N4. Therefore, the voltage of the fourth node N4 (or the first electrode of the light-emitting element LD) can be initialized to the voltage of the initialization power supply Vint. For example, the voltage of the initialization power supply Vint can be provided to the fourth node N4 via the seventh transistor T7. When the voltage of the initialization power supply Vint is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Because the residual voltage charged in the parasitic capacitor is discharged (or eliminated), unintentional fine emissions can be prevented. Therefore, the black representation capability of the pixel PX3 can be improved.

[0233] The eighth transistor T8 may be connected between the second electrode (or second node N2) of the first transistor T1 and the second emitter control line EL2i. The eighth transistor T8 may include a gate electrode for receiving scan signals. For example, the gate electrode of the eighth transistor T8 may be connected to the fourth scan line SL4i to receive a fourth scan signal. When the fourth scan signal is supplied to the fourth scan line SL4i, the eighth transistor T8 may be turned on to electrically connect the second node N2 and the second emitter control line EL2i.

[0234] For reference Figure 2 As described, the eighth transistor T8 can supply a high voltage or a low voltage to the second electrode of the first transistor T1 based on a second emitter control signal having a gate off level (e.g., high voltage) or a gate on level (e.g., low voltage). Therefore, the first transistor T1 can have an on-biased state or an off-biased state.

[0235] Furthermore, the conduction periods of the second transistor T2 do not overlap with those of the third transistor T3, fourth transistor T4, and fifth transistor T5. For example, when the third transistor T3, fourth transistor T4, and fifth transistor T5 are on, threshold voltage compensation for the first transistor T1 can be performed. When the second transistor T2 is on, data writing can be performed. Therefore, the threshold voltage compensation period and the data writing period can be separated from each other.

[0236] In low-frequency drives where the length of a single frame period is extended, hysteresis may occur due to grayscale differences between adjacent pixels. Therefore, differences in the threshold voltage shift between the driving transistors of adjacent pixels may occur, and viewers may perceive screen snagging (e.g., ghosting) caused by these differences in threshold voltage shift.

[0237] In a display device according to an embodiment of the present invention, by using an eighth transistor T8, a bias can be periodically applied to the drain electrode (and / or source electrode) of a driving transistor (e.g., a first transistor T1) at a constant voltage period. Therefore, hysteresis caused by grayscale differences between adjacent pixels can be removed, and thus screen attraction can be reduced (or eliminated).

[0238] Figures 11A to 11F It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0239] Reference Figure 10 and Figure 11A During the display scan period DSP, signals for image display can be supplied to pixel PX3. The display scan period DSP may include the period during which the data signal DVj corresponding to the output image is written.

[0240] The first transmit control signal EM1i and the second transmit control signal EM2i can be supplied to the first transmit control line EL1i and the second transmit control line EL2i, respectively, and the first scan signal GWi, the second scan signal GCI, the third scan signal EB1i and the fourth scan signal EB2i can be supplied to the first scan line SL1i, the second scan line SL2i, the third scan line SL3i and the fourth scan line SL4i, respectively.

[0241] At time t18, the third scan signal EB1i changes from a gate-off level to a gate-on level. Therefore, the seventh transistor T7 can be turned on. Consequently, the voltage of the initialization power supply Vint is supplied to the fourth node N4 (or the first electrode of the light-emitting element LD) so that the fourth node N4 can be initialized to the voltage of the initialization power supply Vint.

[0242] Furthermore, the second scan signal GCI can be changed from a gate-off level to a gate-on level. Therefore, the third transistor T3 can be turned on. Additionally, because the second transmit control signal EM2i maintains a gate-on level, the sixth transistor T6 can be turned on or remain on. Therefore, the initialization power supply Vint supplied to the fourth node N4 is supplied to the first node N1 (or the gate electrode of the first transistor T1) so that the first node N1 can be initialized to the initialization power supply Vint voltage.

[0243] Additionally, the fourth transistor T4 can be turned on by a second scan signal GCi with a gate on level. Therefore, the voltage of the reference power supply Vref is supplied to the third node N3 so that the third node N3 can be initialized to the voltage of the reference power supply Vref.

[0244] Therefore, in Figure 11BDuring the eleventh time period P7a, highlighted diagonally from the eighteenth time t18 to the nineteenth time t19, the voltage of the initialization power supply Vint can be supplied to the first node N1, the voltage of the reference power supply Vref can be supplied to the third node N3, and the voltage of the initialization power supply Vint can be supplied to the fourth node N4. In other words, the eleventh time period P7a can be the initialization period (or the first initialization period) for initializing the first electrode (or anode) of the light-emitting element LD, the gate electrode of the driving transistor (first transistor T1), and the third node N3.

[0245] Because the third scan signal EB1i maintains a gate-on level during the period from the eighteenth time t18 to the twenty-first time t21, the initialization operation of the first electrode of the light-emitting element LD can be performed during this period (i.e., from t18 to t21). Furthermore, because the second scan signal GCI maintains a gate-on level during the period from the eighteenth time t18 to the twenty-third time t23, the voltage of the reference power supply Vref can be supplied to the third node N3 during this period (i.e., from t18 to t23).

[0246] At time t19, the second transmit control signal EM2i can be changed from the gate on level to the gate off level. Therefore, the sixth transistor T6 can be turned off.

[0247] At the twentieth time t20, the first transmit control signal EM1i can be changed from a gate-off level to a gate-on level. Therefore, the fifth transistor T5 is turned on, so that the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD.

[0248] Furthermore, because the second scan signal GCI maintains the gate on level, the third transistor T3 can remain on. Therefore, the first transistor T1 can be in a diode configuration. The voltage corresponding to the difference (or voltage difference) between the voltage of the first power supply VDD and the threshold voltage of the first transistor T1 can be sampled at the first node N1.

[0249] Therefore, in Figure 11C During the twelfth time period P8a, highlighted diagonally from the twentieth time t20 to the twenty-second time t22, the first transistor T1 has a diode connection to enable compensation of the threshold voltage of the first transistor T1. In other words, the twelfth time period P8a can be a threshold voltage compensation period.

[0250] Additionally, in the twelfth time period P8a, threshold voltage compensation can be performed using the voltage of the first power supply VDD. Therefore, the threshold voltage compensation operation can be performed based on a fixed voltage rather than a data signal (e.g., data voltage) that can change according to pixel rows and / or frames.

[0251] At time t21 (the twenty-first time), the third scan signal EB1i can change from the gate on level to the gate off level. Therefore, the seventh transistor T7 can be turned off.

[0252] At time t22, the first transmit control signal EM1i can be changed from the gate on level to the gate off level. Therefore, the fifth transistor T5 can be turned off.

[0253] At time t23, the second scan signal GCI can change from gate on level to gate off level. Therefore, the third transistor T3 and the fourth transistor T4 can be turned off.

[0254] At the twenty-fourth time t24, the first scan signal GWi changes from a gate-off level to a gate-on level, enabling the second transistor T2 to conduct. Therefore, the data signal DVj can be supplied to the third node N3. For example, while the first scan signal GWi has a gate-on level, the data signal DVj is supplied to the third node N3 and thus to the first capacitor C1.

[0255] Because the first node N1 is connected to the third node N3 through the first capacitor C1, voltage changes at the third node N3 (e.g., "DATA-Vref") are reflected in the first node N1. Therefore, the voltage at the first node N1 can be changed to "VDD-Vth+(DATA-Vref)". DATA can be the voltage corresponding to the data signal DVj, Vref can be the voltage of the reference power supply Vref, VDD can be the voltage of the first power supply VDD, and Vth can be the threshold voltage of the first transistor T1.

[0256] Therefore, in Figure 11D During the thirteenth time period P9, highlighted diagonally from the twenty-fourth time t24 to the twenty-fifth time t25, the data signal DVj can be written to pixel PX3. In other words, the thirteenth time period P9 is the data writing period.

[0257] In embodiments of the present invention, the length of the thirteenth time period P9, for example, the length (or pulse width) of the first scan signal GWi, may correspond to a horizontal time period 1H. However, the length of the first scan signal GWi is not limited thereto. For example, the length of the first scan signal GWi may correspond to two or more horizontal time periods 2H.

[0258] At time t25, the first scan signal GWi can change from a gate-on level to a gate-off level. Therefore, the second transistor T2 can be turned off.

[0259] At time t26 (the 26th time), the fourth scan signal EB2i can change from a gate-off level to a gate-on level. Therefore, the eighth transistor T8 can be turned on. Additionally, at time t26 (the 26th time), a second emitter control signal EM2i with a high voltage (or gate-off level) can be supplied to the second emitter control line EL2i. Therefore, the high voltage of the second emitter control signal EM2i can be supplied to the second electrode (or drain electrode) of the first transistor T1.

[0260] Therefore, in Figure 11E During the fourteenth time period P10a, which is highlighted diagonally from the twenty-sixth time t26 to the twenty-seventh time t27, a conduction bias can be applied to the first transistor T1. In other words, the fourteenth time period P10a can be a conduction bias period (or the first conduction bias period).

[0261] At time t27 (the 27th time interval), the fourth scan signal EB2i can change from the gate on level to the gate off level. Therefore, the eighth transistor T8 can be turned off.

[0262] In the fourteenth period P10a, a conduction bias is applied to the first transistor T1 so as to minimize the hysteresis characteristics of the first transistor T1 (e.g., threshold voltage shift).

[0263] Therefore, according to Figure 11A The operation shown is performed by pixel PX3 and display device ( Figure 1 In the 1000 shown, the hysteresis characteristic is removed or minimized while removing the threshold voltage change of the first transistor T1, so that image defects (e.g., flicker, color attraction, brightness reduction, etc.) can be minimized.

[0264] At time t28, the first transmit control signal EM1i and the second transmit control signal EM2i can be changed from gate off level to gate on level. Therefore, the fifth transistor T5 and the sixth transistor T6 can be turned on, and pixel PX3 can be turned on as follows. Figure 11F Light is emitted during the fifteenth time period P11a, which is highlighted diagonally after the twenty-eighth time t28. In other words, the fifteenth time period P11a can be the emission period (or the first emission period).

[0265] Figures 12A to 12E It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0266] Reference Figure 10 , Figure 11A and Figure 12AIn order to maintain the brightness of the image output in the display scanning period DSP, the on bias voltage and / or off bias voltage can be applied to the second electrode (e.g., the drain electrode or the second node N2) of the first transistor T1 in the self-scanning period SSP.

[0267] Depending on the image frame rate, a frame may include at least one self-scanning period (SSP). The self-scanning period (SSP) may include the off-bias period (or first off-bias period) of the sixteenth period (P7b), the on-bias period (or second on-bias period) of the seventeenth period (P8b), the on-bias period (or third on-bias period) of the eighteenth period (P10b), and the transmit period (or second transmit period) of the nineteenth period (P11b). In addition, besides... Figure 11A Apart from the signal supply for threshold voltage compensation in the twelfth time period P8a (or threshold voltage compensation time period) and the signal supply for data signal writing in the thirteenth time period P9 (or data writing time period), Figure 12A The operation of the self-scanning period SSP shown is similar to Figure 11A The operation of the DSP during the display scan period is essentially the same. For example, the first scan signal GWi and the second scan signal GCI remain high.

[0268] In embodiments of the present invention, no signals are supplied to the second transistor T2, the third transistor T3, and the fourth transistor T4 during the self-scanning period SSP. For example, during the self-scanning period SSP, the first scan signal GWi and the second scan signal GCi supplied to the first scan line SL1i and the second scan line SL2i, respectively, may have a gate-off level (or a high level H). Therefore, the self-scanning period SSP does not include a threshold voltage compensation period (e.g., the twelfth period P8a) and a data writing period (e.g., the thirteenth period P9).

[0269] Because Figure 12B During the sixteenth time period P7b (or the first off-bias period), highlighted diagonally from the twenty-ninth time t29 to the thirtieth time t30, a third scan signal EB1i with a gate-on level and a second emitter control signal EM2i with a gate-on level are supplied, so the sixth transistor T6 and the seventh transistor T7 can be turned on or remain on. Therefore, the voltage of the low-voltage initialization power supply Vint is supplied to the second electrode (or drain electrode) of the first transistor T1 so that the first transistor T1 can be in an off-bias state.

[0270] Because Figure 12CDuring the seventeenth time period P8b (or the second conduction bias period), highlighted diagonally from the thirty-first time t31 to the thirty-third time t33, a first emitter control signal EM1i with a gate conduction level is supplied, so the fifth transistor T5 can be turned on or remain in the on state. Therefore, the voltage of the first power supply VDD, which is a high voltage, is supplied to the first electrode (or source electrode) of the first transistor T1 so that the first transistor T1 can have a conduction bias state.

[0271] Furthermore, because the third scan signal EB1i remains at a gate-on level during the period from the twenty-ninth time t29 to the thirty-second time t32, the seventh transistor T7 can be turned on or remain on. Therefore, the voltage of the initialization power supply Vint is supplied to the fourth node N4 (or the first electrode of the light-emitting element LD) so that the fourth node N4 can be initialized to the voltage of the initialization power supply Vint.

[0272] Because Figure 12D During the eighteenth time period P10b (or the third conduction bias period), highlighted diagonally from the thirty-fourth time t34 to the thirty-fifth time t35, a fourth scan signal EB2i with a gate-on level is supplied, so the eighth transistor T8 can be turned on or remain on. The eighteenth time period P10b can be greater than each of the sixteenth time period P7b and the seventeenth time period P8b. Furthermore, a second emitter control signal EM2i with a high voltage (or gate-off level) can be supplied to the second emitter control line EL2i. Therefore, the high voltage of the second emitter control signal EM2i is supplied to the second electrode (or drain electrode) of the first transistor T1, enabling the first transistor T1 to have a conduction bias state.

[0273] Because Figure 12E In the nineteenth time period P11b (or the second emission period), which is highlighted diagonally after the thirty-sixth time period t36, the first emission control signal EM1i and the second emission control signal EM2i have gate on level, so the fifth transistor T5 and the sixth transistor T6 are turned on, so that the pixel PX3 can emit light.

[0274] The third scan signal EB1i and the fourth scan signal EB2i, as well as the first transmission control signal EM1i and the second transmission control signal EM2i, can be supplied at a first frequency independent of the image refresh rate. Therefore, even when the image refresh rate changes, the initialization operation of the light-emitting element (LD), the application of the on-bias during the on-bias periods (e.g., the fourteenth period P10a and / or the seventeenth period P8b and / or the eighteenth period P10b), and the application of the off-bias during the off-bias periods (e.g., the sixteenth period P7b) can always be performed periodically. Therefore, flicker can be minimized corresponding to various image refresh rates (e.g., low-frequency drive).

[0275] Additionally, during the self-scanning period (SSP), the data driver ( Figure 1 The 800 shown can not supply any data signal to the pixel PX3. Therefore, power consumption can be further reduced.

[0276] Figure 13 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0277] Reference Figure 11A and Figure 13 ,Apart from Figure 11A and Figure 13 In addition to the second transmit control signal EM2i shown, Figure 13 The multiple signals EM1i, GWi, GCI, EB1i, EB2i, and DVj shown are... Figure 11A The first transmit control signal EM1i, the first scan signal GWi, the second scan signal GCi, the third scan signal EB1i, the fourth scan signal EB2i, and the data signal DVj shown are substantially the same, and therefore, the repeated descriptions need not be repeated.

[0278] Reference Figure 10 and Figure 13 At the twenty-sixth time t26, the second transmit control signal EM2i can be changed from the gate off level to the gate on level. However, in Figure 11A During this process, the second transmit control signal EM2i maintains the gate off level until the twenty-eighth time t28. Because the eighth transistor T8 is turned on or remains on by the fourth scan signal EB2i with a gate on level, the low voltage (or gate on level) of the second transmit control signal EM2i can be supplied to the second electrode (or drain electrode) of the first transistor T1.

[0279] Therefore, during the fourteenth time period P10a' from the twenty-sixth time t26 to the twenty-seventh time t27, a turn-off bias can be applied to the first transistor T1. Thus, the first transistor T1 can have a turn-off bias state.

[0280] Figure 14 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0281] Reference Figure 13 and Figure 14 ,Apart from Figure 13 and Figure 14 In addition to the fourth scan signal EB2i shown, Figure 14 The multiple signals EM1i, EM2i, GWi, GCI, EB1i, and DVj shown are... Figure 13 The EM1i, EM2i, GWi, GCI, EB1i, and DVj shown are essentially the same, and therefore, there is no need to repeat the redundant descriptions.

[0282] Reference Figure 10 and Figure 14 At time t25, the fourth scan signal EB2i can change from gate off level to gate on level. However, at... Figure 11A During this process, the fourth scan signal EB2i maintains a gate-off level until the twenty-sixth time t26. Therefore, the eighth transistor T8 can be turned on. Because the second emitter control signal EM2i with a high voltage (or gate-off level) is supplied to the second emitter control line EL2i, the high voltage (or gate-off level) of the second emitter control signal EM2i can be supplied to the second electrode (or drain electrode) of the first transistor T1.

[0283] Therefore, during the twentieth time period P12a, from the twenty-fifth time t25 to the twenty-sixth time t26, a conduction bias can be applied to the first transistor T1. In other words, the twentieth time period P12a can be a conduction bias period. As described above, by adjusting the width of the fourth scan signal EB2i, the display device (e.g., Figure 1 The display device 1000 shown is capable of applying both a shutdown bias and a turn-on bias to the first transistor T1 after the data writing period. Furthermore, although already referred to... Figure 14 The description covers the case where the width of the fourth scan signal EB2i is adjusted during the display scan period DSP, but during the self-scan period SSP, the display device (e.g., Figure 1 The display device 1000 shown can apply both a turn-off bias and a turn-on bias to the first transistor T1 by adjusting the width of the fourth scan signal EB2i in the first transistor T1.

[0284] Figure 15 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0285] Reference Figure 12A and Figure 15 ,Apart from Figure 12A and Figure 15 In addition to the first transmit control signal EM1i shown, Figure 15 The multiple signals EM2i, GWi, GCI, EB1i, EB2i, and DVj shown are... Figure 12A The EM2i, GWi, GCI, EB1i, EB2i and DVj shown are essentially the same, and therefore, there is no need to repeat the redundant description.

[0286] Reference Figure 1 , Figure 10 and Figure 15 During the seventeenth time period P8b' from the thirty-first time t31 to the thirty-third time t33, the first transmit control signal EM1i can be maintained at a gate-off level. For example, the first transmit control signal EM1i can be maintained high. Therefore, the display device 1000 may not include the conduction bias period of the seventeenth time period P8b' in the self-scanning time period SSP. However, since the display device 1000 includes the conduction bias period of the eighteenth time period P10b in the self-scanning time period SSP, the conduction bias can be applied to the first transistor T1.

[0287] Figure 16 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0288] Reference Figure 15 and Figure 16 ,Apart from Figure 15 and Figure 16 In addition to the fourth scan signal EB2i shown, Figure 16 The multiple signals EM1i, EM2i, GWi, GCI, EB1i, and DVj shown are... Figure 15 The EM1i, EM2i, GWi, GCI, EB1i, and DVj shown are essentially the same, and therefore, repetition of redundant descriptions is unnecessary. For example, the fourth scan signal EB2i in Figure 16 The level remains high.

[0289] Reference Figure 1 , Figure 10 and Figure 16 During the self-scanning period SSP, the fourth scan signal EB2i supplied to the fourth scan line SL4i may have a gate-off level (or a high level H). Therefore, the display device 1000 may not include a reference. Figure 12A The described eighteenth time period, the conduction bias period of P10b. See reference... Figures 8 to 9B As described, the pixel PX3 may not include the eighth transistor T8, and the display device 1000 may not include the fourth scan driver 500.

[0290] Pixel PX3 applies a turn-off bias voltage to the first transistor T1 in the sixteenth period P7b by using the voltage of the initialization power supply Vint, without including the eighth transistor T8, so as to improve the hysteresis characteristics of the first transistor T1 (e.g., threshold voltage shift).

[0291] Figure 17 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3. Figure 18 It is shown Figure 10 The waveform diagram shows an example of the operation of pixel PX3.

[0292] Reference Figure 15 , Figure 17 and Figure 18 ,Apart from Figure 15 , Figure 17 and Figure 18 In addition to the second transmit control signal EM2i shown, Figure 17 and Figure 18 The multiple signals EM1i, GWi, GCI, EB1i, EB2i, and DVj shown are... Figure 15 The EM1i, GWi, GCI, EB1i, EB2i, and DVj shown are essentially the same, and therefore, duplicate descriptions are unnecessary. For example, in Figure 17 In the process, the second transmit control signal EM2i remains high from the twenty-ninth time t29 to the thirty-sixth time t36, and... Figure 18 In the middle, the second transmit control signal EM2i turns high at the twenty-ninth time t29 and turns low at the thirty-fourth time t34.

[0293] Reference Figure 1 , Figure 10 , Figure 17 and Figure 18 During the sixteenth period P7b', from the twenty-ninth time t29 to the thirtieth time t30, a second emitter control signal EM2i with a gate-off level can be supplied to the second emitter control line EL2i. Therefore, because the sixth transistor T6 is turned off or remains off during the sixteenth period P7b', the voltage of the initialization power supply Vint (e.g., turn-off bias) with a low voltage during the sixteenth period P7b' is not applied to the second electrode (or drain electrode) of the first transistor T1.

[0294] During the eighteenth time period when the fourth scan signal EB2i with gate on level is supplied ( Figure 17 P10b or shown Figure 18During the period shown in P10b”, the eighth transistor T8 is turned on. The display device 1000 supplies power as shown in the figure. Figure 17 The second transmit control signal EM2i shown has a high voltage (or gate off level), or is supplied as such Figure 18 The second emitter control signal EM2i shown has a low voltage (or gate on level) to enable selective application of an on or off bias to the first transistor T1.

[0295] Figure 19 This is a circuit diagram illustrating a pixel PX4 according to an embodiment of the present invention.

[0296] Reference Figure 10 and Figure 19 Apart from the connection relationship of the eighth transistor T8, Figure 19 The pixel PX4 shown is Figure 10 The pixels PX3 shown are essentially the same, and therefore, repetition of the description is unnecessary. Figure 19 For example, the eighth transistor T8 is connected to the first emitter control line EL1i instead of the second emitter control line EL2i.

[0297] Reference Figure 19 The eighth transistor T8 can be connected between the second electrode (or second node N2) of the first transistor T1 and the first emitter control line EL1i. This is because during the period when the fourth scan signal EB2i with a gate-on level is supplied (e.g., Figure 11A The fourteenth time period P10a and / or shown Figure 12A In the eighteenth time period (P10b) shown, the first transmit control signal EM1i and the second transmit control signal EM2i have the same waveform, so that the eighth transistor T8 is turned on. Figure 19 The pixel PX4 shown can perform with Figure 10 The same operation is performed on the pixel PX3 shown.

[0298] Figure 20 This is a circuit diagram illustrating pixel PX5 according to an embodiment of the present invention.

[0299] Reference Figure 10 and Figure 20 Apart from the connection relationship of the eighth transistor T8, Figure 20 The pixel PX5 shown is Figure 10 The pixels PX3 shown are essentially the same, and therefore, there is no need to repeat the description.

[0300] Reference Figure 20The eighth transistor T8 can be connected between the first electrode (or fifth node N5) of the first transistor T1 and the second emitter control line EL2i. During the period when the fourth scan signal EB2i with a gate-on level is supplied to turn on the eighth transistor T8 (e.g., ...), Figure 11A The fourteenth time period P10a and / or shown Figure 12A In the eighteenth time period P10b shown, when a second transmit control signal EM2i with a high voltage (or gate off level) or a second transmit control signal EM2i with a low voltage (or gate on level) is supplied, the high voltage or low voltage is supplied to the first electrode (or source electrode) of the first transistor T1 so that the first transistor T1 can have an on-biased state or an off-biased state.

[0301] Figure 21 This is a circuit diagram illustrating a pixel PX6 according to an embodiment of the present invention.

[0302] Reference Figure 21 The eighth transistor T8 can be connected between the first electrode (or fifth node N5) of the first transistor T1 and the first emitter control line EL1i. (See reference...) Figure 19 and Figure 20 As described, during the period when the fourth scan signal EB2i with a gate on level is supplied to turn on the eighth transistor T8 (e.g., Figure 11A The fourteenth time period P10a and / or shown Figure 12A In the eighteenth time period P10b shown, a high voltage or a low voltage is supplied to the first electrode (or source electrode) of the first transistor T1 by a first transmission control signal EM1i having the same waveform as the second transmission control signal EM2i, so that the first transistor T1 can have a conduction bias state or a turn-off bias state.

[0303] In the pixels and display devices having pixels according to embodiments of the present invention, a frame includes a display scan period and at least one self-scan period, enabling image output using various driving frequencies. Furthermore, the number of self-scan periods increases as the driving frequency decreases, thereby minimizing brightness reduction and flickering during viewing.

[0304] Furthermore, by using the eighth transistor, a constant voltage is applied to the first transistor to improve the hysteresis characteristics (or threshold voltage shift differences) caused by bias differences (and grayscale differences) between adjacent pixels. Therefore, screen attraction (e.g., ghosting) caused by hysteresis variations can be minimized.

[0305] In a display device according to an embodiment of the present invention, the second electrode of the driving transistor is initialized to a low voltage after data is written, so as to prevent unintentional emission of the light-emitting element before the emission period.

[0306] Although the invention has been shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A pixel, comprising: Light-emitting elements; A first transistor is connected between a first power source and a second node, and the first transistor controls the driving current supplied to the light-emitting element. A first capacitor, the first capacitor including a first electrode connected to one of a first node and a second node and a second electrode connected to a third node; The second transistor is connected between the third node and the data line, and the second transistor is turned on by the first scan signal; A third transistor is connected between the first node and the second node, and the third transistor is turned on by a second scan signal; The fifth transistor is connected between the first power supply and the first transistor, and the fifth transistor is turned on by the first transmit control signal; A sixth transistor is connected between the second node and the light-emitting element, and the sixth transistor is turned on by a second emission control signal; as well as The eighth transistor is connected between the second node and the second emitter control line, and the eighth transistor is turned on by the fourth scan signal.

2. The pixel according to claim 1, further comprising: A fourth transistor is connected between the reference power supply and the third node, and the fourth transistor is turned on by a third scan signal; as well as A second capacitor is connected between the first power source and the first node. The first electrode of the first capacitor is connected to the second node.

3. The pixel according to claim 2, further comprising: A seventh transistor is connected between the light-emitting element and the initialization power supply, and the seventh transistor is turned on by the third scan signal.

4. The pixel according to claim 3, wherein, A frame includes an initialization period, a compensation period, a write period, a bias period, and an emission period. During the initialization period, the initialization power is supplied to the first node and the fourth node between the light-emitting element and the seventh transistor. During the compensation period, the first node and the second node are electrically connected to each other. During the write period, a data signal is supplied to the third node. During the bias period, a bias voltage is supplied to the first transistor. During the emission period, the light-emitting element emits light.

5. The pixel according to claim 4, wherein, The bias period includes the conduction bias period during which the first transistor is in a conduction bias state, and During the conduction bias period, the third transistor and the sixth transistor are turned off, and the eighth transistor is turned on.

6. The pixel according to claim 4, wherein, The bias period includes the off-bias period during which the first transistor is in an off-bias state, and During the off-bias period, the third transistor is off and the eighth transistor is on.

7. The pixel according to claim 4, wherein, The bias period includes the off-bias period during which the first transistor is in an off-bias state, and During the off-bias period, the third transistor is off, and the sixth and seventh transistors are on.

8. The pixel according to claim 4, wherein, In response to the second scan signal, the third transistor is turned on during the initialization period, the compensation period, and the write period, and turned off during the bias period and the transmit period. In response to the third scan signal, the seventh transistor is turned on during the initialization period and the compensation period, and turned off during the write period, the bias period and the transmit period.

9. The pixel according to claim 7, wherein, In response to the second scan signal, the third transistor is turned on during the initialization period, the compensation period, and the write period, and turned off during the bias period and the transmit period. In response to the third scan signal, the seventh transistor is turned on during the initialization period, the compensation period, and the off-bias period, and turned off during the write period, the period of the bias period other than the off-bias period, and the transmit period.

10. The pixel according to claim 1, further comprising: A second capacitor is connected between the first power source and the third node; as well as A fourth transistor, connected between the reference power supply and the third node, is turned on by the second scan signal. The first electrode of the first capacitor is connected to the first node.

11. The pixel of claim 10, further comprising: A seventh transistor is connected between the light-emitting element and the initialization power supply, and the seventh transistor is turned on by a third scan signal.

12. The pixel according to claim 11, wherein, A frame includes an initialization period, a compensation period, a write period, a bias period, and an emission period. During the initialization period, the initialization power is supplied to the first node and the fourth node between the light-emitting element and the seventh transistor. During the compensation period, the first node and the second node are electrically connected to each other. During the write period, a data signal is supplied to the third node. During the bias period, a bias voltage is supplied to the first transistor. During the emission period, the light-emitting element emits light.

13. The pixel according to claim 12, wherein, The bias period includes the conduction bias period during which the first transistor is in a conduction bias state, and During the conduction bias period, the fifth and sixth transistors are turned off, and the eighth transistor is turned on.

14. The pixel according to claim 12, wherein, The bias period includes the off-bias period during which the first transistor is in an off-bias state, and During the off-bias period, the fifth transistor is off and the eighth transistor is on.

15. The pixel according to claim 12, wherein, The bias period includes the conduction bias period during which the first transistor is in a conduction bias state, and During the on-bias period, the sixth transistor is turned off and the fifth transistor is turned on.

16. The pixel according to claim 12, wherein, The bias period includes the off-bias period during which the first transistor is in an off-bias state, and During the off-bias period, the fifth transistor is off, and the sixth and seventh transistors are also off.

17. A display device, comprising: The display panel includes pixels connected to a first scan line, a second scan line, a third scan line, a first emission control line, a second emission control line, and a data line; A scan driver configured to supply a first scan signal to a first scan line, a second scan signal to a second scan line, and a third scan signal to a third scan line; A transmit driver configured to supply a first transmit control signal to a first transmit control line and a second transmit control signal to a second transmit control line; A data driver, configured to supply data signals to the data line; and A timing controller configured to control the scan driver, the transmit driver, and the data driver. Wherein, at least one of the plurality of pixels includes: Light-emitting elements; A first transistor is connected between a first power source and a second node, and the first transistor controls the driving current supplied to the light-emitting element. A first capacitor is connected between the second node and the third node; The second transistor is connected between the third node and a corresponding data line among the plurality of data lines, and the second transistor is turned on by the first scan signal; A third transistor is connected between the first node and the second node, and the third transistor is turned on by the second scan signal; A fourth transistor is connected between the reference power supply and the third node, and the fourth transistor is turned on by the third scan signal; The fifth transistor is connected between the first power supply and the first transistor, and the fifth transistor is turned on by the first transmit control signal; The sixth transistor is connected between the second node and the light-emitting element, and the sixth transistor is turned on by the second emission control signal; A seventh transistor, connected between the light-emitting element and the initialization power supply, is turned on by the third scan signal; and A second capacitor is connected between the first power source and the first node; and The at least one of the plurality of pixels further includes an eighth transistor connected between the second node and a corresponding second emission control line among the plurality of second emission control lines, the eighth transistor being turned on by a fourth scan signal.

18. The display device according to claim 17, wherein, The scan driver includes a first scan driver, a second scan driver, and a third scan driver. The first scan driver supplies the first scan signal to the first scan line at a second frequency corresponding to the image refresh rate of the pixel. The second scan driver supplies the second scan signal to the second scan line at the second frequency. The third scan driver supplies the third scan signal to the third scan line at a first frequency. The transmit driver includes a first transmit driver and a second transmit driver. The first transmit driver supplies the first transmit control signal to the first transmit control line at the first frequency, and the second transmit driver supplies the second transmit control signal to the second transmit control line at the first frequency. The data driver supplies the data signal to the data line according to the second frequency.

19. The display device according to claim 18, wherein, The first scan driver and the second scan driver supply the first scan signal and the second scan signal during the display scan period of a frame, and do not supply the first scan signal and the second scan signal during the self-scan period of the frame. During the display scan period, the data signal is written to the pixel, and During the display scan period and the self-scan period, the first transistor is biased by the initialization power supply, the third scan signal and the second transmit control signal.

20. The display device according to claim 18, wherein, The pixel is also connected to a fourth scan line. The scan driver further includes a fourth scan driver that supplies the fourth scan signal to the fourth scan line at the first frequency.

21. The display device according to claim 20, wherein, The first scan driver and the second scan driver supply the first scan signal and the second scan signal during the display scan period of a frame, and do not supply the first scan signal and the second scan signal during the self-scan period of the frame. During the display scan period, the data signal is written to the pixel, and During the display scan period and the self-scan period, the first transistor is biased by the fourth scan signal and the second transmit control signal.

Images