Display device

Abstract

A display device is provided. The display device includes a display panel including a first display area and a second display area and including pixels connected to data lines and scan lines, respectively, a data driving circuit driving the data lines, a scan driving circuit driving the scan lines, a driving controller receiving an image signal and a control signal, controlling the data driving circuit and the scan driving circuit according to an operation mode, and outputting a clock signal. The scan driving circuit includes a first scan driving circuit corresponding to the first display area and a second scan driving circuit corresponding to the second display area. In a multi-frequency mode, the second scan driving circuit sequentially drives first scan lines corresponding to the second display area among the scan lines during a first frame, and sequentially drives second scan lines corresponding to the second display area among the scan lines during a second frame.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0092317, filed on July 24, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0002] This disclosure relates to display devices, and more particularly, to display devices capable of multi-frequency driving. Background Technology

[0003] In display devices, organic light-emitting diodes (OLEDs) are used to display images. OLEDs generate light through the recombination of electrons and holes. Such OLED displays offer advantages such as fast response times and low power consumption.

[0004] An organic light-emitting display device includes pixels connected to data lines and scan lines. Each pixel typically includes an organic light-emitting diode (OLED) and circuitry for controlling the amount of current flowing through the OLED. The circuitry controls the amount of current flowing from a first driving voltage through the OLED to a second driving voltage in response to a data signal. In this case, light with a predetermined brightness is generated in response to the amount of current flowing through the OLED.

[0005] As the applications of display devices diversify, multiple different images can be displayed on a single device. This necessitates technologies to reduce the power consumption of display devices that display multiple images. Summary of the Invention

[0006] This disclosure provides a display device capable of reducing power consumption.

[0007] An embodiment of the present invention provides a display device including a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel defines a first display area and a second display area and includes multiple pixels respectively connected to multiple data lines and multiple scan lines. The data driving circuit drives the multiple data lines, the scan driving circuit drives the multiple scan lines, and the drive controller receives image signals and control signals, controls the data driving circuit and the scan driving circuit according to an operating mode, and outputs multiple clock signals. The scan driving circuit includes a first scan driving circuit corresponding to the first display area and a second scan driving circuit corresponding to the second display area. In a multi-frequency mode, the second scan driving circuit sequentially drives multiple first scan lines corresponding to the second display area during a first frame and sequentially drives multiple second scan lines corresponding to the second display area during a second frame consecutive to the first frame.

[0008] In one embodiment, a plurality of first scan lines and a plurality of second scan lines may extend in a first direction and may be alternately arranged in a second direction intersecting the first direction.

[0009] In one implementation, during normal frequency mode, the second scan drive circuit can sequentially drive a plurality of first scan lines and a plurality of second scan lines in a sequence arranged in a second direction.

[0010] In the implementation, the first frame of the multi-frequency mode may include a first driving period and a second driving period. The second frame, which is continuous with the first frame in the multi-frequency mode, may include a third driving period and a fourth driving period. The multiple clock signals include a first clock signal to a fourth clock signal. The drive controller may output the first clock signal to the fourth clock signal with different phases, output the second clock signal and the fourth clock signal at an inactive level during the second driving period, and output the first clock signal and the third clock signal at an inactive level during the fourth driving period.

[0011] In an implementation, the second scan driving circuit may include a first driving stage and a second driving stage. The first driving stage responds to a first clock signal, a third clock signal, and a carry signal to output a first scan signal to a corresponding first scan line among a plurality of first scan lines. The second driving stage responds to a second clock signal, a fourth clock signal, and a carry signal to output a second scan signal to a corresponding second scan line among a plurality of second scan lines.

[0012] In one implementation, the first scan signal output from the j-th (j is a natural number) first driver stage in the first driver stage can be provided as the carry signal of the (j+1)-th first driver stage in the first driver stage, and the second scan signal output from the j-th (j is a natural number) second driver stage in the second driver stage can be provided as the carry signal of the (j+1)-th second driver stage in the second driver stage.

[0013] In the implementation, the first of the first driving stage and the first of the second driving stage can receive the scan signal output from the first scan driving circuit as their respective carry signals.

[0014] In an implementation, the first scan driving circuit may include driving stages, each of which responds to a clock signal and a carry signal among a plurality of clock signals to output a scan signal to the scan line corresponding to the first display area.

[0015] In one implementation, the drive controller can provide a start signal to the first scan drive circuit, and the first drive stage in the drive stage of the first scan drive circuit can receive the start signal as a carry signal.

[0016] In an implementation, the second scan driving circuit may include a driving stage, each of which responds to a clock signal and a carry signal among a plurality of clock signals to output a scan signal to a corresponding scan line among a plurality of first scan lines and a plurality of second scan lines.

[0017] In one implementation, the first drive stage of the second scan drive circuit can receive the scan signal output from the first scan drive circuit as a carry signal.

[0018] In one implementation, the scan signal output from the j-th (j is a natural number) driving stage of the second scan driving circuit can be provided as the carry signal of the (j+1)-th driving stage.

[0019] In one embodiment, the second display area of ​​the display panel may include a first pixel connected to a plurality of first scan lines and a second pixel connected to a plurality of second scan lines.

[0020] In one implementation, the first pixel and the second pixel may be arranged alternately in a first direction, wherein the first pixel and the second pixel may be arranged alternately in a second direction intersecting the first direction.

[0021] In one implementation, the plurality of first scan lines and the plurality of second scan lines may be arranged alternately in a second direction.

[0022] In an embodiment of the present invention, the display device includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel defines a first non-folding area, a folding area, and a second non-folding area and includes multiple pixels respectively connected to multiple data lines and multiple scan lines. The data driving circuit drives the multiple data lines, and the scan driving circuit drives the multiple scan lines. The drive controller receives image signals and control signals, controls the data driving circuit and the scan driving circuit according to an operating mode, and outputs multiple clock signals. The display panel is divided into a first display area and a second display area. The scan driving circuit includes a first scan driving circuit corresponding to the first display area and a second scan driving circuit corresponding to the second display area. In a multi-frequency mode, the second scan driving circuit sequentially drives multiple first scan lines corresponding to the second display area during a first frame and sequentially drives multiple second scan lines corresponding to the second display area during a second frame consecutive to the first frame.

[0023] In one implementation, a plurality of first scan lines and a plurality of second scan lines may extend in a first direction and be alternately arranged in a second direction intersecting the first direction.

[0024] In the implementation, the first frame of the multi-frequency mode may include a first driving period and a second driving period. The second frame, which is continuous with the first frame in the multi-frequency mode, may include a third driving period and a fourth driving period. The multiple clock signals include a first clock signal to a fourth clock signal. The drive controller may output the first clock signal to the fourth clock signal with different phases, output the second clock signal and the fourth clock signal at an inactive level during the second driving period, and output the first clock signal and the third clock signal at an inactive level during the fourth driving period.

[0025] In an implementation, the second scan driving circuit may include a first driving stage and a second driving stage. The first driving stage outputs a first scan signal to a corresponding first scan line among a plurality of first scan lines in response to a first clock signal, a third clock signal, and a carry signal. The second driving stage outputs a second scan signal to a corresponding second scan line among a plurality of second scan lines in response to a second clock signal, a fourth clock signal, and a carry signal.

[0026] In one embodiment, the second display area of ​​the display panel may include a first pixel connected to a plurality of first scan lines and a second pixel connected to a plurality of second scan lines, wherein the first pixel and the second pixel are alternately arranged in a first direction, and wherein the first pixel and the second pixel are alternately arranged in a second direction intersecting the first direction. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0028] Figure 1 This is a plan view of a display device according to an embodiment of the concept of the present invention;

[0029] Figure 2A and Figure 2B This is a perspective view of a display device according to an embodiment of the concept of the present invention;

[0030] Figure 3 This is a diagram illustrating the operation of the display device in normal frequency mode;

[0031] Figure 4 This is a block diagram of a display device according to an embodiment of the concept of the present invention;

[0032] Figure 5 This is an equivalent circuit diagram of a pixel according to an embodiment of the concept of the present invention;

[0033] Figure 6It is used for explanation Figure 5 The timing diagram of the operations of the pixels shown;

[0034] Figure 7 This is a block diagram of a scan drive circuit according to an embodiment of the concept of the present invention;

[0035] Figure 8 It is used to describe the normal frequency mode. Figure 7 A diagram showing the operation of the scan drive circuit;

[0036] Figure 9A It is used to explain the first frame in multi-frequency mode. Figure 7 A diagram showing the operation of the scan drive circuit;

[0037] Figure 9B It is used to explain the second frame in multi-frequency mode. Figure 7 A diagram showing the operation of the scan drive circuit;

[0038] Figure 10 This is a graph showing the changes in brightness according to the operating mode;

[0039] Figure 11 This is a block diagram of a scan drive circuit according to another embodiment of the concept of the present invention;

[0040] Figure 12 This is a diagram illustrating the connection between pixels and scan lines of a display panel according to an embodiment of the concept of the present invention;

[0041] Figure 13 It is used to describe the normal frequency mode. Figure 11 A diagram showing the operation of the scan drive circuit shown in Figure 12 and the display panel shown in Figure 12; and

[0042] Figure 14 It is used to explain in multi-frequency modes Figure 11 The scan drive circuit shown and Figure 12 The diagram shows the operation of the display panel. Detailed Implementation

[0043] In this specification, when an element (or area, layer, part, etc.) is referred to as being "on", "connected to", or "attached to" another element, it means that it can be placed directly on, directly connected to, or directly attached to the other element, or that a third element can be arranged between them.

[0044] Similar reference numerals refer to similar elements. Additionally, in the drawings, the thickness, scale, and dimensions of components are exaggerated for effective description. Technical terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless otherwise clearly indicated, the singular forms “a,” “an,” and “the” as used herein are also intended to include the plural forms, thus including “at least one.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” “And / or” includes all of one or more combinations defined by the relevant components.

[0045] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the invention, and vice versa. Unless otherwise specified, singular terms may include plural forms.

[0046] Additionally, terms such as “below,” “lower side,” “upper,” and “upper side” are used to describe the relationships between the structures shown in the figure. These terms are described as relative concepts based on the directions shown in the figure.

[0047] In various embodiments of the present invention, the terms "include", "comprise", "including" or "comprising" specify attributes, areas, fixed numbers, steps, processes, elements and / or components, but do not exclude other attributes, areas, fixed numbers, steps, processes, elements and / or components.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the concepts of this invention pertain. Furthermore, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and unless explicitly defined herein, terms shall not be interpreted in an ideal or overly formal sense.

[0049] In the following description, embodiments of the concept of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1 This is a plan view of a display device DD according to an embodiment of the concept of the present invention.

[0051] Reference Figure 1A portable terminal according to an embodiment of the present invention is shown as an example of a display device DD. Portable terminals may include tablet PCs, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, and watch-type electronic devices. However, the present invention is not limited thereto. The present invention can be used in large electronic devices such as televisions or billboards, as well as small and medium-sized electronic devices such as personal computers, laptops, vending machines, car navigation units, and cameras. These are merely examples and can be used in other electronic devices without departing from the concept of the present invention.

[0052] like Figure 1 As shown, the display surface displaying the first image IM1 and the second image IM2 is parallel to a plane defined by the first direction DR1 and the second direction DR2. The display device DD includes a plurality of regions divided on the display surface. The display surface includes a display area DA for displaying the first image IM1 and the second image IM2 and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. For example, the display area DA may have a rectangular shape. The non-display area NDA surrounds the display area DA. Furthermore, although not shown in the figure, for example, the display device DD may have a partially curved shape. As a result, a region of the display area DA may have a curved shape.

[0053] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. For example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or text information that does not change over a relatively long period of time compared to the moving image.

[0054] According to the embodiment, the display device DD can drive the first display area DA1, which displays moving images, at a normal frequency, and drive the second display area DA2, which displays still images, at a lower frequency than the normal frequency. The display device DD can reduce power consumption by reducing the driving frequency of the second display area DA2.

[0055] The first display area DA1 and the second display area DA2 may each have a preset size, and their sizes can be changed by an application. In one embodiment, when the first display area DA1 displays a still image and the second display area DA2 displays a moving image, the first display area DA1 may be driven at a low frequency, and the second display area DA2 may be driven at a normal frequency. In another embodiment, the display area DA may be divided into three or more display areas, and the driving frequency of each of the multiple divided display areas may be determined according to the type of image (e.g., still image or moving image) displayed on each divided display area.

[0056] Figure 2A and Figure 2B This is a perspective view of a display device DD2 according to an embodiment of the concept of the present invention. Figure 2A The image shows the display device DD2 in its unfolded state, and Figure 2B The image shows the display device DD2 folded in the middle.

[0057] like Figure 2A and Figure 2B As shown, the display device DD2 includes a display area DA and a non-display area NDA. The display device DD2 can display images through the display area DA. When the display device DD2 is unfolded, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD2 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Accordingly, a front (in other words, upper) surface and a rear (in other words, lower) surface of the components constituting the display device DD2 may be defined relative to the third direction DR3. The non-display area NDA may be referred to as a border area. For example, the display area DA may have a rectangular shape. The non-display area NDA surrounds the display area DA.

[0058] The display area DA may include a first non-foldable area NFA1, a foldable area FA, and a second non-foldable area NFA2. The foldable area FA may be bendable relative to a folding axis FX extending along a first direction DR1.

[0059] When the display device DD2 is fully folded, the first non-folded region NFA1 and the second non-folded region NFA2 can face each other. Accordingly, in the fully folded state, the display area DA may not be exposed to the outside, and this type of folding may be referred to as "inward folding". However, this is exemplary, and the operation of the display device DD2 according to the present invention is not limited thereto.

[0060] For example, in another embodiment of the present invention, when the display device DD2 is fully folded, the first non-folded region NFA1 and the second non-folded region NFA2 may be opposite each other. Accordingly, in the folded state, the first non-folded region NFA1 may be exposed to the outside, and this folding type may be referred to as "outward fold".

[0061] The display device DD2 may perform only one of the inward or outward folding operations. Alternatively, the display device DD2 may perform both inward and outward folding operations. In this case, the same area of ​​the display device DD2 (e.g., the folding area FA) may be folded inward and outward. Alternatively, some areas of the display device DD2 may be folded inward, and other areas may be folded outward.

[0062] exist Figure 2A and Figure 2B For example, a folded region and two non-folded regions are shown, but the number of folded and non-folded regions according to the invention is not limited thereto. For example, the display device DD2 may include more than two non-folded regions and multiple folded regions arranged between adjacent non-folded regions.

[0063] Figure 2A and Figure 2B An illustrative example shows the folding axis FX parallel to the minor axis (i.e., the horizontal axis) of the display device DD2, but the concept of the invention is not limited thereto. In another embodiment, for example, the folding axis FX may extend along the major axis (i.e., the vertical axis) of the display device DD2 (e.g., a direction parallel to the second direction DR2). In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially along the first direction DR1.

[0064] The display area DA of the display device DD2 can be defined as multiple display areas DA1 and DA2. Figure 2A The example shows two display areas DA1 and DA2, but the number of display areas according to the present invention is not limited thereto.

[0065] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area displaying a second image IM2, but the concept of the present invention is not limited thereto. For example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or an image that does not change over a relatively long period of time compared to the moving image (text information, etc.).

[0066] The display device DD2 according to the embodiment can operate differently depending on the operating mode. The operating mode may include a normal frequency mode and a multi-frequency mode. During the normal frequency mode, the display device DD2 can drive the first display area DA1 and the second display area DA2 at a normal frequency. In the display device DD2 according to the embodiment, during the multi-frequency mode, the first display area DA1 displaying the first image IM1 is driven at a first driving frequency, and the second display area DA2 displaying the second image IM2 can be driven at a second driving frequency lower than the normal frequency. In the embodiment, the first driving frequency may be the same as the normal frequency.

[0067] The sizes of the first display area DA1 and the second display area DA2 can be preset and can be changed by an application. In an embodiment, the first display area DA1 can correspond to the first non-folding area NFA1, and the second display area DA2 can correspond to the second non-folding area NFA2. Additionally, the first portion of the folding area FA can correspond to the first display area DA1, and the second portion of the folding area FA can correspond to the second display area DA2.

[0068] In another embodiment, all of the folded areas FA may correspond to only one of the first display area DA1 and the second display area DA2.

[0069] In another embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the area of ​​the first display area DA1 may be smaller than the area of ​​the second display area DA2.

[0070] In another embodiment, the first display area DA1 corresponds to a first portion of the first non-folded area NFA1, the folded area FA, and the second non-folded area NFA2, and the second display area DA2 may correspond to a second portion of the second non-folded area NFA2. That is, the area of ​​the second display area DA2 may be smaller than the area of ​​the first display area DA1.

[0071] like Figure 2B As shown, in the folded state of the folded area FA, the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the folded area FA and the second non-folded area NFA2.

[0072] although Figure 2A and Figure 2BThe display device DD2, having one folded region FA, is shown as an example of a display device, but the concept of the invention is not limited thereto. In another embodiment, for example, the concept of the invention can be applied to display devices having two or more folded regions, multi-surface display devices having two or more display surfaces, rollable display devices, slider display devices, or the like.

[0073] In the following description, Figure 1 The display device DD shown is described as an example, but can be equivalently applied to other devices. Figure 2A and Figure 2B The display device DD2 shown is shown.

[0074] Figure 3 This is a diagram illustrating the operation of the display device DD in normal frequency mode NFM.

[0075] Reference Figure 3 The first image IM1 displayed on the first display area DA1 is a moving image, and the second image IM2 displayed on the second display area DA2 may be a still image or an image that does not change over a relatively long period of time compared to the moving image (e.g., the UI of a keyboard used for game control). Figure 3 The first image IM1 displayed in the first display area DA1 and the second image IM2 displayed in the second display area DA2 shown are merely examples, and various images can be displayed on the display device DD.

[0076] In Normal Frequency Mode (NFM), the driving frequency of the first display area DA1 and the second display area DA2 of the display device DD is the normal frequency. For example, the normal frequency can be 60 Hz. In Normal Frequency Mode (NFM), the images from the first frame F1 to the 60th frame F60 are displayed in the first display area DA1 and the second display area DA2 of the display device DD for 1 second (sec).

[0077] Although not shown in the figures, in multi-frequency mode, the display device DD can set the driving frequency of the first display area DA1 that displays the first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of the second display area DA2 that displays the second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. In an embodiment, when the normal frequency is 60Hz, the first driving frequency can be 60Hz, and the second driving frequency can be 30Hz.

[0078] In multi-frequency mode, when the first driving frequency is 60Hz and the second driving frequency is 30Hz, the first image IM1 is displayed for 1 second on the first display area DA1 of the display device DD during the first frame F1 to the 60th frame F60. This is in contrast to the multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn of the second display area DA2 (see...). Figure 7 The corresponding pixels can be displayed only in multiple odd-numbered frames F1, F3, F5, ..., F59 for the second image IM2. Additionally, multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 of the second display area DA2 (see...) Figure 7 The corresponding pixels can display the second image IM2 only in multiple even-numbered frames F2, F4, F6, ..., F60. The operation of the display device DD in multi-frequency mode will be described in detail later.

[0079] Figure 4 This is a block diagram of a display device DD according to an embodiment of the concept of the present invention.

[0080] Reference Figure 4 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0081] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates the image data signal DATA, which is obtained by converting the data format of the image signal RGB into a format that meets the specifications of the interface with the data drive circuit 200. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a transmit control signal ECS.

[0082] The data drive circuit 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0083] The display panel DP includes multiple scan lines GL0 to GLn+1, multiple emission control lines EML1 to EMLn, multiple data lines DL1 to DLm, and multiple pixels PX. Here, m and n are positive integers. The display panel DP may also include a scan drive circuit SD and an emission drive circuit EDC. In an embodiment, the scan drive circuit SD is arranged on a first side of the display panel DP. The multiple scan lines GL0 to GLn+1 extend from the scan drive circuit SD in a first direction DR1.

[0084] The transmit drive circuit EDC is arranged on the second side of the display panel DP. The second side is opposite to the first side relative to the display panel DP. Multiple transmit control lines EML1 to EMLn extend from the transmit drive circuit EDC in a direction opposite to the first direction DR1.

[0085] Multiple scan lines GL0 to GLn+1 and multiple transmit control lines EML1 to EMLn are arranged spaced apart from each other in the second direction DR2. Multiple data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are arranged spaced apart from each other in the first direction DR1.

[0086] exist Figure 4 In the example shown, the scan drive circuit SD and the emission drive circuit EDC are arranged facing each other with the pixel PX between them, but the concept of the invention is not limited thereto. In another embodiment, for example, the scan drive circuit SD and the emission drive circuit EDC may be arranged adjacent to each other on one of the first and second sides of the display panel DP. In an exemplary embodiment, the scan drive circuit SD and the emission drive circuit EDC may be constructed as a single circuit.

[0087] Multiple pixels PX are electrically connected to multiple scan lines GL0 to GLn+1, multiple emission control lines EML1 to EMLn, and multiple data lines DL1 to DLm. Each of the multiple pixels PX can be electrically connected to three scan lines and one emission control line. For example, as... Figure 4 As shown, the pixel PX in the first row can be connected to multiple scan lines GL0, GL1, and GL2, as well as the emission control line EML1. Similarly, the pixel PX in the second row can be connected to multiple scan lines GL1, GL2, and GL3, as well as the emission control line EML2.

[0088] Each of the multiple pixels PX includes a light-emitting diode (ED) (see Figure 5 ) and the pixel circuit unit PXC that controls the emission of the light-emitting diode ED (see Figure 5 The pixel circuit unit (PXC) may include at least one transistor and at least one capacitor. The scan drive circuit (SD) and the emitter drive circuit (EDC) may include transistors formed using the same process as the pixel circuit unit (PXC).

[0089] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0090] The scan drive circuit SD receives the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD outputs scan signals to multiple scan lines GL0 to GLn+1. The circuit structure and operation of the scan drive circuit SD will be described in detail later.

[0091] According to the embodiment, the drive controller 100 divides the display panel DP into a first display area DA1 based on the image signal RGB (see [link]). Figure 1 ) and the second display area DA2 (see Figure 1 The drive controller 100 can set the driving frequency of the first display area DA1 and the second display area DA2. For example, in a normal frequency mode, the drive controller 100 drives the first display area DA1 and the second display area DA2 at a normal frequency (e.g., 60Hz). In a multi-frequency mode, the drive controller 100 can drive the first display area DA1 at a first driving frequency (e.g., 60Hz) and drive the second display area DA2 at a low frequency (e.g., 30Hz).

[0092] Figure 5 This is an equivalent circuit diagram of pixel PXij according to an embodiment of the concept of the present invention.

[0093] Figure 5 It shows the relationship with Figure 4 The diagram shows the equivalent circuit diagram of pixel PXij connected to the i-th data line DLi among the multiple data lines DL1 to DLm, the (j-1)-th scan line GLj-1, the j-th scan line GLj, and the (j+1)-th scan line GLj+1 among the multiple scan lines GL0 to GLn+1, and the j-th emission control line EMLj among the multiple emission control lines EML1 to EMLn. Here, i is a natural number equal to or less than m, and j is a natural number equal to or less than n.

[0094] Figure 4 Each of the plurality of pixels PX shown may have the same as Figure 5The equivalent circuit diagram of pixel PXij shown has the same circuit construction. In this embodiment, the pixel circuit unit PXC of pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Furthermore, each of the first transistors T1 to the seventh transistor T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the concept of the invention is not limited to this, and in another embodiment, the first transistors T1 to the seventh transistor T7 may be N-type transistors using oxide semiconductor as the semiconductor layer. In this embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an N-type transistor, and the remainder may be P-type transistors. Furthermore, the circuit construction of the pixel according to the concept of the invention is not limited to... Figure 5 . Figure 5 The pixel circuit unit PXC shown is merely an example, and the construction of the pixel circuit unit PXC can be modified and implemented.

[0095] Reference Figure 5 According to the embodiment, the pixel PXij of the display device DD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. In this embodiment, an example in which a pixel PXij includes one light-emitting diode ED will be described.

[0096] The (j-1)th scan line GLj-1, the jth scan line GLj, the (j+1)th scan line GLj+1, and the jth transmit control line EMLj can respectively transmit the (j-1)th scan signal Gj-1, the jth scan signal Gj, the (j+1)th scan signal Gj+1, and the transmit signal EMj. The i-th data line DL transmits the data signal Di. The data signal Di can have the same characteristics as the input to the display device DD (refer to...). Figure 4 The image signal RGB corresponds to the voltage level. The first driving voltage line VL1, the second driving voltage line VL2, and the third driving voltage line VL3 can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT.

[0097] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted from the i-th data line DLi according to the switching operation of the second transistor T2, and supply the drive current Id to the light-emitting diode ED.

[0098] The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th scan line GLj. The second transistor T2 is turned on according to the j-th scan signal Gj received through the j-th scan line GLj, so that the second transistor T2 can transmit the data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0099] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th scan line GLj. The third transistor T3 can be turned on according to the j-th scan signal Gj received through the j-th scan line GLj, and the first transistor T1 can be diode-connected by connecting the gate electrode and the second electrode of the first transistor T1 to each other.

[0100] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 through which the initialization voltage VINT is transmitted, and a gate electrode connected to the (j-1)th scan signal Gj-1. The fourth transistor T4 can be turned on according to the (j-1)th scan signal Gj-1 received through the (j-1)th scan line GLj-1, and can perform an initialization operation to initialize the voltage of the gate electrode of the first transistor T1 by transmitting the initialization voltage VINT to the gate electrode of the first transistor T1.

[0101] The fifth transistor T5 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th emitter control line EMLj.

[0102] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the j-th emission control line EMLj.

[0103] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the transmission signal EMj received through the j-th transmission control line EMLj, and thus the first driving voltage ELVDD can be compensated by the first transistor T1 connected to the diode, and the first driving voltage ELVDD can be transmitted to the light-emitting diode ED.

[0104] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the (j+1)th scan line GLj+1.

[0105] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2, which transmits the second driving voltage ELVSS. The structure of pixel PXij according to this embodiment is not limited to... Figure 5 The structure shown, including the number of transistors and capacitors in a pixel PXij and the connection relationships, can be modified in various ways.

[0106] Figure 6 It is used for explanation Figure 5 The timing diagram shows the operation of pixel PXij. (Refer to...) Figure 5 and Figure 6 The operation of the display device DD according to the embodiment will be described.

[0107] Reference Figure 5 and Figure 6 During the initialization period within frame F, a low-level (j-1)th scan signal Gj-1 is provided through the (j-1)th scan line GLj-1. The fourth transistor T4 is turned on in response to the low-level (j-1)th scan signal Gj-1, and the initialization voltage VINT is transmitted through the fourth transistor T4 to the gate electrode of the first transistor T1, thereby initializing the first transistor T1.

[0108] Next, when a low-level j-th scan signal Gj is supplied through the j-th scan line GLj during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is diode-connected through the turned-on third transistor T3 and is biased in the positive direction. Additionally, the second transistor T2 is turned on by the low-level j-th scan signal Gj. Then, a compensation voltage Di-Vth, equal to the voltage obtained by subtracting the threshold voltage Vth of the first transistor T1 from the data signal Di, is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage Di-Vth.

[0109] The first driving voltage ELVDD and the compensation voltage Di-Vth are applied to the two ends of the capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the capacitor Cst.

[0110] The seventh transistor T7 is turned on by the low-level scan signal Gj+1 received via the (j+1)th scan line GLj+1. A portion of the drive current Id (i.e., the bypass current Ibp) can escape through the seventh transistor T7.

[0111] Even when the minimum current of the first transistor T1, which displays a black image, flows as the drive current Id, the black image cannot be correctly displayed if the light-emitting diode ED emits light. Accordingly, the seventh transistor T7 in the pixel PXij according to an embodiment of the present invention can allocate a portion of the minimum current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the light-emitting diode ED. Here, the minimum current of the first transistor T1 means the current under the condition that the first transistor T1 is turned off because the gate-source voltage of the first transistor T1 is less than the threshold voltage Vth. In this way, the minimum drive current (e.g., 10 picoamperes (pA) or less) under the condition that the first transistor T1 is turned off is transmitted to the light-emitting diode ED and is represented as a black image. It can be said that when the minimum drive current Id for displaying a black image flows, the effect of the bypass transmission of the bypass current Ibp is large, but when a large drive current Id for displaying an image such as a normal image or a white image flows, there is a small effect of the bypass current Ibp. Therefore, when the drive current Id used to display a black image flows, the emission current Ied of the light-emitting diode ED, which reduces the amount of bypass current Ibp escaping from the drive current Id through the seventh transistor T7, has a minimum current amount to reliably display a black image. Accordingly, the seventh transistor T7 can be used to achieve an accurate black luminance image to improve contrast. In this embodiment, the bypass signal is the low-level j+1th scan signal Gj+1, but it is not limited to this.

[0112] Next, during the transmission period, the transmission signal EMj supplied from the j-th transmission control line EMLj changes from a high level to a low level. During the transmission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level transmission signal EMj. Then, a drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and the drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6 so that the transmission current Ied flows through the light-emitting diode ED.

[0113] Figure 7 This is a block diagram of a scan drive circuit SD according to an embodiment of the concept of the present invention.

[0114] Reference Figure 7 The scan driving circuit SD includes a first scan driving circuit SD1 and a second scan driving circuit SD2. The first scan driving circuit SD1 may correspond to the first display area DA1 (see reference). Figure 1The first scan driving circuit SD1 includes multiple driving stages ST0 to STk, and the second scan driving circuit SD2 includes multiple driving stages STk+1 to STn+1.

[0115] Each of the multiple drive levels ST0 to STn+1 Figure 4 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4. Each of the plurality of drive stages ST0 to STn+1 receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The voltage generator 300 shown is provided.

[0116] In this implementation, multiple driver stages ST0 to STn+1 respectively output multiple scan signals G0 to Gn+1. These multiple scan signals G0 to Gn+1 can be provided to... Figure 4 The scan lines shown are GL0 to GLn+1.

[0117] In the first scan drive circuit SD1, multiple drive stages ST0 to STk receive two corresponding clock signals from the first clock signal CLK1 to the fourth clock signal CLK4. For example, when k is even, multiple drive stages ST0, ST2, ST4, ST6, ..., STk receive the first clock signal CLK1 and the third clock signal CLK3. Multiple drive stages ST1, ST3, ST5, ST7, ..., STk-1 receive the second clock signal CLK2 and the fourth clock signal CLK4. When k is odd, multiple drive stages ST0, ST2, ST4, ST6, ..., STk-1 receive the first clock signal CLK1 and the third clock signal CLK3, and multiple drive stages ST1, ST3, ST5, ST7, ..., STk receive the second clock signal CLK2 and the fourth clock signal CLK4, as shown below. Figure 7 The example shown.

[0118] The first driver stage ST0 in the first scan driver circuit SD1 can receive a start signal FLM as a carry signal. Each of the multiple driver stages ST1 to STk in the first scan driver circuit SD1 has a subordinate connection relationship whereby the scan signal output from the previous driver stage is received as a carry signal. For example, driver stage ST1 receives the scan signal G0 output from the previous driver stage ST0 as a carry signal, and driver stage ST2 receives the scan signal G1 output from the previous driver stage ST1 as a carry signal.

[0119] The first drive stage (i.e., drive stage STk+1) and the second drive stage (i.e., drive stage STk+2) in the second scan drive circuit SD2 both receive the scan signal Gk output from the drive stage STk (i.e., the last drive stage) in the first scan drive circuit SD1 as a carry signal.

[0120] In the second scan drive circuit SD2, odd-numbered drive stages STk+1 to STn+1 can be referred to as first drive stages, and even-numbered drive stages can be referred to as second drive stages. For example, when the total number of drive stages included in the second scan drive circuit SD2 is even, multiple drive stages STk+1, STk+3, STk+5, ..., STn are first drive stages, and multiple drive stages STk+2, STk+4, STk+6, ..., STn+1 are second drive stages. When the total number of drive stages included in the second scan drive circuit SD2 is odd, multiple drive stages STk+1, STk+3, STk+5, ..., STn+1 are first drive stages, and multiple drive stages STk+2, STk+4, STk+6, ..., STn are second drive stages. In the following text, the case where the total number of drive stages included in the second scan drive circuit SD2 is even is assumed.

[0121] Each of the multiple first driver stages STk+3, STk+5, ..., STn has a subordinate connection relationship whereby a scan signal output from the previous first driver stage is received as a carry signal. For example, first driver stage STk+3 receives scan signal Gk+1 output from the previous first driver stage STk+1 as a carry signal, and driver stage STk+5 receives scan signal Gk+3 output from the previous first driver stage STk+3 as a carry signal. Each of the multiple first driver stages STk+1, STk+3, STk+5, ..., STn receives a first clock signal CLK1 and a third clock signal CLK3. The multiple first driver stages STk+1, STk+3, STk+5, ..., STn can output multiple first scan signals Gk+1, Gk+3, Gk+5, ..., Gn to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn respectively (see...). Figure 4 ).

[0122] Each of the multiple second driver stages STk+4, STk+6, ..., STn+1 has a subordinate connection whereby the scan signal output from the preceding second driver stage is received as a carry signal. For example, second driver stage STk+4 receives the scan signal Gk+2 output from the preceding second driver stage STk+2 as a carry signal, and driver stage STk+6 receives the scan signal Gk+4 output from the preceding second driver stage STk+4 as a carry signal. Each of the multiple second driver stages STk+2, STk+4, STk+6, ..., STn+1 receives a second clock signal CLK2 and a fourth clock signal CLK4.

[0123] Multiple second driver stages STk+2, STk+4, STk+6, ..., STn+1 can output multiple second scan signals Gk+2, Gk+4, Gk+6, ..., Gn+1 to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 respectively (see...) Figure 4 ).

[0124] Figure 8 It is used to describe the normal frequency mode. Figure 7 The diagram shows the operation of the scan drive circuit SD.

[0125] Reference Figure 4 , Figure 7 and Figure 8 During normal frequency mode, the drive controller 100 sequentially activates the first clock signal CLK1 to the fourth clock signal CLK4 to a low level.

[0126] During normal frequency mode, multiple driver stages ST0 to STn+1 can sequentially activate multiple scan signals G0 to Gn+1 to low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4.

[0127] The data driving circuit 200 can sequentially provide multiple data signals D1 to Dn to multiple data lines DL1 to DLm. For example, data signal D1 is a data signal to be provided to pixel PX in a row connected to scan line GL1, and data signal Dn is a data signal to be provided to pixel PX in a row connected to scan line GLn.

[0128] The activation period (e.g., low-level period) of the start signal FLM is two horizontal periods, 2H. One horizontal period is the time it takes for a pixel in a row to be driven.

[0129] Figure 9A It is used to interpret the first frame Fs in multi-frequency mode. Figure 7 The diagram shows the operation of the scan drive circuit SD. Figure 9B It is used to interpret the second frame Fs+1 in multi-frequency mode. Figure 7 The diagram shows the operation of the scan drive circuit SD. The second frame Fs+1 is a frame that is temporally continuous with the first frame Fs.

[0130] First, refer to Figure 4 , Figure 7 and Figure 9A In the multi-frequency mode, the first frame Fs includes a first driving period DT1 and a second driving period DT2. The first driving period DT1 is the first display area DA1 (see...). Figure 1 The time during which the second driving period DT2 is driven is the time during which the second display area DA2 is (see...). Figure 1 The time during which it is driven.

[0131] During the first drive period DT1 in the first frame Fs of the multi-frequency mode, the drive controller 100 sequentially activates the first clock signal CLK1 to the fourth clock signal CLK4 to a low level.

[0132] Accordingly, during the first drive period DT1 in the first frame Fs of the multi-frequency mode, multiple drive stages ST0 to STk can sequentially activate multiple scan signals G0 to Gk to low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4.

[0133] The data driving circuit 200 can sequentially provide multiple data signals D1 to Dk to multiple data lines DL1 to DLm during the first driving period DT1 in the first frame Fs of the multi-frequency mode. For example, data signal D1 is a data signal to be provided to pixel PX in a row connected to scan line GL1, and data signal Dk is a data signal to be provided to pixel PX in a row connected to scan line GLk.

[0134] Accordingly, during the first drive period DT1 in the first frame Fs of the multi-frequency mode, the first display area DA1 (see...) Figure 1 It can display images.

[0135] During the second drive period DT2 in the first frame Fs of the multi-frequency mode, the drive controller 100 outputs a first clock signal CLK1 and a third clock signal CLK3. The frequencies of the first clock signal CLK1 and the third clock signal CLK3 in the second drive period DT2 are the same as the frequencies in the first drive period DT1. Therefore, multiple first drive stages STk+1, STk+3, STk+5, ..., STn can output multiple first scan signals Gk+1, Gk+3, Gk+5, ..., Gn with an activation level (e.g., low level) to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn.

[0136] During the second drive period DT2 in the first frame Fs of the multi-frequency mode, the drive controller 100 holds the second clock signal CLK2 and the fourth clock signal CLK4 at an inactive level (e.g., high level). Because the second clock signal CLK2 and the fourth clock signal CLK4 are held at an inactive level, multiple second drive stages STk+2, STk+4, STk+6, ..., STn+1 are inactive. Therefore, multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 are supplied (see...). Figure 4 The multiple second scan signals Gk+2, Gk+4, Gk+6, ..., Gn+1 can be kept at an inactive level (e.g., high level).

[0137] The data driving circuit 200 can sequentially provide multiple data signals Dk+1, Dk+3, Dk+3, ..., Dn to multiple data lines DL1 to DLm during the second driving period DT2 in the first frame Fs of the multi-frequency mode.

[0138] Therefore, during the second driving period DT2 in the first frame Fs of the multi-frequency mode, the pixel PX connected to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn displays the image, while the pixel PX connected to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 does not display the image.

[0139] Reference Figure 4 , Figure 7 and Figure 9B In multi-frequency mode, the second frame Fs+1 includes the third driving period DT3 and the fourth driving period DT4. The third driving period DT3 is the first display area DA1 (refer to...). Figure 1 The time during which the fourth driving period DT4 is driven is the time during which the second display area DA2 is (refer to...). Figure 1 The time during which it is driven.

[0140] During the third drive period DT3 in the second frame Fs+1 of the multi-frequency mode, the drive controller 100 sequentially activates the first clock signal CLK1 to the fourth clock signal CLK4 to a low level.

[0141] Accordingly, during the third drive period DT3 in the second frame Fs+1 of the multi-frequency mode, multiple drive stages ST0 to STk can sequentially activate multiple scan signals G0 to Gk to low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4.

[0142] The data drive circuit 200 can sequentially provide multiple data signals D1 to Dk to multiple data lines DL1 to DLm during the third drive period DT3 in the second frame Fs+1 of the multi-frequency mode.

[0143] Therefore, during the third drive period DT3 in the second frame Fs+1 of the multi-frequency mode, the first display area DA1 (refer to...) Figure 1 It can display images.

[0144] During the fourth drive period DT4 in the second frame Fs+1 of the multi-frequency mode, the drive controller 100 outputs the second clock signal CLK2 and the fourth clock signal CLK4. In the fourth drive period DT4, the frequencies of the second clock signal CLK2 and the fourth clock signal CLK4 are the same as the frequencies of the third drive period DT3. Therefore, multiple second drive stages STk+2, STk+4, STk+6, ..., STn+1 can output multiple second scan signals Gk+2, Gk+4, Gk+5, ..., Gn+1 with an activation level (e.g., low level) to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1.

[0145] During the fourth drive period DT4 in the second frame Fs+1 of the multi-frequency mode, the drive controller 100 holds the first clock signal CLK1 and the third clock signal CLK3 at an inactive level (e.g., high level). Because the first clock signal CLK1 and the third clock signal CLK3 are held at an inactive level, the multiple first drive stages STk+1, STk+3, STk+5, ..., STn do not operate. Correspondingly, the multiple first scan signals Gk+1, Gk+3, Gk+5, ..., Gn supplied to the multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn can be held at an inactive level (e.g., high level).

[0146] The data driving circuit 200 can sequentially provide multiple data signals Dk+2, Dk+4, Dk+5, ..., Dn+1 to multiple data lines DL1 to DLm during the fourth driving period DT4 in the second frame Fs+1 of the multi-frequency mode.

[0147] Therefore, during the fourth driving period DT4 in the second frame Fs+1 of the multi-frequency mode, the pixel PX connected to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn does not display an image, while the pixel PX connected to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 can display an image.

[0148] During multi-frequency mode, the display device DD... Figure 9A The first frame Fs shown in the figure Figure 9B The second frame, Fs+1, is operated alternately to display an image on the display panel DP.

[0149] Figure 10 This is a graph showing the changes in brightness according to the operating mode.

[0150] Reference Figure 4 and Figure 10 In the first display area DA1, the pixel PX connected to the k-th scan line GLk displays an image at a first driving frequency (e.g., 60Hz) in multi-frequency mode.

[0151] The current corresponding to the data signal Di is supplied to the light-emitting diode ED (see...). Figure 5 After that, during the time period Ta of a frame, the brightness B_GLk of the pixel PX connected to the k-th scan line GLk gradually decreases so that the brightness B_GLk reaches the minimum brightness, and then rises to the maximum brightness in the next frame (the brightness difference is H1).

[0152] Pixels PX connected to odd-numbered scan lines (e.g., scan line GLk+1) in the second display area DA2 can display images at a second driving frequency (e.g., 30Hz) in multi-frequency mode.

[0153] In the same manner, pixels PX connected to even-numbered scan lines (e.g., the (k+2)th scan line GLk+2) in the second display area DA2 can display images at a second driving frequency (e.g., 30Hz) in multi-frequency mode.

[0154] During time interval Tb of a frame, the brightness B_GLk+1 of pixel PX connected to scan line k+1 decreases to reach minimum brightness, and thus reaches minimum brightness, before rising again to maximum brightness in the next frame (brightness difference H2). Here, time interval Tb is twice the time interval Ta. During time interval Tb of a frame, the brightness B_GLk+2 of pixel PX connected to scan line k+2 decreases to reach minimum brightness, and thus rises again to maximum brightness in the next frame (brightness difference H3).

[0155] Typically, when the current corresponding to the same data signal Di is supplied to the light-emitting diode ED, the difference in brightness within a frame increases as the time period of a frame lengthens (H1 < H2, H1 < H3).

[0156] like Figure 4As shown, since multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn and multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 are alternately arranged in the second direction DR2, the brightness B_GLk+1 of the pixel PX connected to the (k+1)th scan line GLk+1 and the brightness B_GLk+2 of the pixel PX connected to the (k+2)th scan line GLk+2 can be recognized by the user as brightness B_GLk+1.5 corresponding to the first driving frequency (e.g., 60Hz). The brightness difference H4 of brightness B_GLk+1.5 is close to the brightness difference H1 of the pixel PX connected to the kth scan line GLk in the first display area DA1.

[0157] Figure 11 This is a block diagram of a scan drive circuit SDa according to another embodiment of the concept of the present invention.

[0158] Reference Figure 11 The scan driving circuit SDa includes a first scan driving circuit SD1 and a second scan driving circuit SD2. The first scan driving circuit SD1 may correspond to the first display area DA1 (see reference). Figure 1 The second scan drive circuit SD2 can correspond to the second display area DA2 (see reference). Figure 1 The first scan drive circuit SD1 includes multiple drive stages ST0 to STk, and the second scan drive circuit SD2 includes multiple drive stages STk+1 to STn+1.

[0159] Each of the multiple drive levels ST0 to STn+1 Figure 4 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4. Each of the plurality of drive stages ST0 to STn+1 receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The voltage generator 300 shown is provided.

[0160] In this implementation, multiple driver stages ST0 to STn+1 respectively output multiple scan signals G0 to Gn+1. These multiple scan signals G0 to Gn+1 can be provided to... Figure 4 The multiple scan lines GL0 to GLn+1 are shown.

[0161] Multiple driver stages ST0 to STn+1 receive two corresponding clock signals from the first clock signal CLK1 to the fourth clock signal CLK4. For example, when n is even, multiple driver stages ST0, ST2, ST4, ST6, ..., STn receive the first clock signal CLK1 and the third clock signal CLK3. Multiple driver stages ST1, ST3, ST5, ST7, ..., STn+1 receive the second clock signal CLK2 and the fourth clock signal CLK4, as... Figure 11 The example shown illustrates this. When n is odd, multiple driver stages ST0, ST2, ST4, ST6, ..., STn+1 receive the first clock signal CLK1 and the third clock signal CLK3, and multiple driver stages ST1, ST3, ST5, ST7, ..., STn receive the second clock signal CLK2 and the fourth clock signal CLK4.

[0162] Driver stage ST0 can receive the start signal FLM as a carry signal. Each of the multiple driver stages ST1 to STn+1 has a subordinate connection in which the scan signal output from the previous driver stage is received as a carry signal. For example, driver stage ST1 receives the scan signal G0 output from the previous driver stage ST0 as a carry signal, and driver stage ST2 receives the scan signal G1 output from the previous driver stage ST1 as a carry signal.

[0163] Figure 12 This is a diagram illustrating the connection between pixels and scan lines of a display panel DPa according to an embodiment of the concept of the present invention.

[0164] Reference Figure 12 The display panel DPa can be divided into a first display area DA1 and a second display area DA2. In normal frequency mode NFM (refer to...) Figure 3 In the first display area DA1 and the second display area DA2, the first display area DA1 is driven at a normal frequency (e.g., 60Hz). In the multi-frequency mode, the first display area DA1 can be driven at a first driving frequency, and the second display area DA2 can be driven at a second driving frequency that is lower than the first driving frequency.

[0165] In the first display area DA1, pixels in one row of pixels PX are connected to adjacent scan lines. For example, pixels PX in the first row are connected to scan line GL1, pixels PX in the second row are connected to scan line GL2, and pixels PX in the k-th row are connected to scan line GLk.

[0166] In the second display area DA2, some pixels in a row of pixels PX are connected to adjacent first scan lines, and other pixels in a row of pixels PX are connected to adjacent second scan lines. For example, multiple pixels PX1, PX3, PX5, ..., PXm-1 arranged in the same row on the first direction DR1 are connected to the second scan line arranged below the pixel (i.e., GLk+2). Multiple pixels PX2, PX4, PX6, ..., PXm arranged in the same row on the first direction DR1 are connected to the first scan line arranged above the pixel (i.e., GLk+1).

[0167] Figure 13 It is used to describe the normal frequency mode. Figure 11 The scan drive circuit SDa shown is Figure 12 The diagram shows the operation of the display panel DPa.

[0168] Reference Figure 11 , Figure 12 and Figure 13 In each of the first frame Fs and the second frame Fs+1 in the normal frequency mode, multiple drive stages ST0 to STn+1 can sequentially activate multiple scan signals G0 to Gn+1 to a low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4. Accordingly, all pixels arranged on the display panel DPa can display an image per frame.

[0169] Figure 14 It is used to describe multi-frequency modes Figure 11 The scan drive circuit SDa shown is Figure 12 The diagram shows the operation of the display panel DPa.

[0170] Reference Figure 11 , Figure 12 and Figure 14 During the first drive period DT1 of the first frame Fs in the multi-frequency mode, multiple drive stages ST0 to STk can sequentially activate multiple scan signals G0 to Gk to a low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4. Correspondingly, during the first drive period DT1 of the first frame Fs in the multi-frequency mode, the first display area DA1 (see...) Figure 1 It can display images.

[0171] During the second drive period DT2 in the first frame Fs of the multi-frequency mode, the drive controller 100 outputs the first clock signal CLK1 and the third clock signal CLK3, and keeps the second clock signal CLK2 and the fourth clock signal CLK4 at an inactive level (e.g., high level) (see Figure 9A).

[0172] During the second driving period DT2, Figure 11 The multiple first driver stages STk+1, STk+3, STk+5, ..., STn among the multiple driver stages STk+1 to STn+1 shown can sequentially output multiple first scan signals Gk+1, Gk+3, Gk+5, ..., Gn with an active level (e.g., low level) to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn. Since the multiple second driver stages STk+2, STk+4, STk+6, ..., STn+1 among the multiple driver stages STk+1 to STn+1 are inactive, the multiple second scan signals Gk+2, Gk+4, Gk+6, ..., Gn+1 provided to the multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 can be maintained at an inactive level (e.g., high level) during the second driving period DT2.

[0173] During the third drive period DT3 of the second frame Fs+1 in the multi-frequency mode, multiple drive stages ST0 to STk can sequentially activate multiple scan signals G0 to Gk to a low level in response to the start signal FLM and the first clock signal CLK1 to the fourth clock signal CLK4. Therefore, during the third drive period DT3 of the second frame Fs+1 in the multi-frequency mode, the first display area DA1 (refer to Figure 1) can display an image.

[0174] During the fourth drive period DT4 in the second frame Fs+1 of the multi-frequency mode, the drive controller 100 outputs the second clock signal CLK2 and the fourth clock signal CLK4, and keeps the first clock signal CLK1 and the third clock signal CLK3 at an inactive level (e.g., high level) (see Figure 9B).

[0175] During the fourth drive period DT4 Figure 11The multiple second driver stages STk+2, STk+4, STk+6, ..., STn+1 among the multiple driver stages STk+1 to STn+1 shown can sequentially output multiple second scan signals Gk+2, Gk+4, Gk+6, ..., Gn+1 at an active level (e.g., low level) to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1. Since the multiple first driver stages STk+1, STk+3, STk+5, ..., STn among the multiple driver stages STk+1 to STn+1 are inactive, the multiple first scan signals Gk+1, Gk+3, Gk+5, ..., Gn provided to the multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn can be maintained at an inactive level (e.g., high level) during the fourth drive period DT4.

[0176] During the second driving period DT2 in the first frame Fs of the multi-frequency mode, among the multiple pixels in the second display area DA2 of the display panel DPa, the first pixel PXa connected to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn displays an image, while the second pixel PXb connected to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 does not display an image.

[0177] Additionally, during the fourth driving period DT4 in the second frame Fs+1 of the multi-frequency mode, among the multiple pixels in the second display area DA2 of the display panel DPa, the second pixel PXb connected to multiple second scan lines GLk+2, GLk+4, GLk+6, ..., GLn+1 displays an image, while the first pixel PXa connected to multiple first scan lines GLk+1, GLk+3, GLk+5, ..., GLn does not display an image.

[0178] Since the first pixel PXa displays the image only in the first frame Fs, and the second pixel PXb displays the image only in the second frame Fs+1, the second driving frequency of the second display area DA2 can be half of the first driving frequency of the first display area DA1.

[0179] like Figure 12 As shown, in the second display area DA2, since the first pixel PXa and the second pixel PXb are alternately arranged in the first direction DR1 and the second direction DR2, it is possible to prevent the user from perceiving flickering even if the second driving frequency of the second display area DA2 is lower than the first driving frequency.

[0180] Regarding a display device with this configuration, when displaying a moving image in the first display area and a still image in the second display area, power consumption can be reduced by making the driving frequency of the second display area lower than that of the first display area. Specifically, the second scan drive circuit driving the second display area can minimize the degradation of display quality by alternately driving the first scan line and the second scan line.

[0181] While exemplary embodiments of the inventive concept have been described, it is to be understood that the inventive concept should not be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A display device, comprising: The display panel defines a first display area and a second display area, and includes multiple pixels each connected to a corresponding data line among multiple data lines and several corresponding scan lines among multiple scan lines; A data driving circuit that drives the plurality of data lines; A scan driving circuit that drives the plurality of scan lines; as well as A drive controller receives image signals and control signals, controls the data drive circuit and the scan drive circuit according to the operating mode, and outputs multiple clock signals, including a first clock signal to a fourth clock signal. The scanning driving circuit includes a first scanning driving circuit corresponding to the first display area and a second scanning driving circuit corresponding to the second display area. In the multi-frequency mode, the first frame includes a first driving period and a second driving period, and the second frame, which is consecutive to the first frame, includes a third driving period and a fourth driving period. In the multi-frequency mode, the first scan driving circuit drives multiple scan lines corresponding to the first display area during the first driving period and the third driving period. In the multi-frequency mode, the second scan driving circuit sequentially drives a plurality of first scan lines among the plurality of scan lines corresponding to the second display area during the second driving period, and sequentially drives a plurality of second scan lines among the plurality of scan lines corresponding to the second display area during the fourth driving period. The drive controller outputs a second clock signal and a fourth clock signal at an inactive level during the second drive period, and outputs a first clock signal and a third clock signal at an inactive level during the fourth drive period.

2. The display device as claimed in claim 1, wherein, The plurality of first scan lines and the plurality of second scan lines extend in a first direction and are alternately arranged in a second direction intersecting the first direction.

3. The display device as claimed in claim 2, wherein, During normal frequency mode, the second scan drive circuit sequentially drives the plurality of first scan lines and the plurality of second scan lines in an order arranged in the second direction.

4. The display device as claimed in claim 1, wherein, The second scan driving circuit includes: Multiple first driver stages, each responding to a first clock signal, a third clock signal, and a carry signal, output a first scan signal to a corresponding first scan line among the multiple first scan lines; and Multiple second driver stages, each responding to the second clock signal, the fourth clock signal, and the carry signal, output a second scan signal to a corresponding second scan line among the multiple second scan lines.

5. The display device as claimed in claim 4, wherein, The first scan signal output from the j-th first driver stage among the plurality of first driver stages is provided as the carry signal of the (j+1)-th first driver stage among the plurality of first driver stages. The second scan signal output from the j-th second drive stage among the plurality of second drive stages is provided as the carry signal of the (j+1)-th second drive stage among the plurality of second drive stages. Where j is a natural number.

6. The display device as claimed in claim 4, wherein, The first of the plurality of first driving stages and the first of the plurality of second driving stages receive the scan signal output from the first scan driving circuit as their respective carry signals.

7. The display device as claimed in claim 1, wherein, The first scan driving circuit includes: Multiple driver stages, each responding to a clock signal and carry signal among the multiple clock signals, output scan signals to the scan lines among the multiple scan lines corresponding to the first display area.

8. The display device as claimed in claim 7, wherein, The drive controller provides a start signal to the first scan drive circuit. In this circuit, the first drive stage among the plurality of drive stages receives the start signal as the carry signal.

9. The display device as claimed in claim 1, wherein, The second scan driving circuit includes: Multiple driver stages, each responding to a corresponding clock signal and carry signal among the multiple clock signals, output scan signals to the corresponding scan lines among the multiple first scan lines and the multiple second scan lines.

10. The display device as claimed in claim 9, wherein, The first of the plurality of drive stages of the second scan drive circuit receives the scan signal output from the first scan drive circuit as the carry signal.

11. The display device as claimed in claim 9, wherein, The scan signal output from the j-th drive stage among the plurality of drive stages of the second scan drive circuit is provided as the carry signal of the (j+1)-th drive stage. Where j is a natural number.

12. The display device as claimed in claim 1, wherein, The second display area of ​​the display panel includes: A plurality of first pixels, each of the plurality of first pixels being connected to a corresponding one of the plurality of first scan lines; and A plurality of second pixels, each of the plurality of second pixels being connected to a corresponding one of the plurality of second scan lines.

13. The display device as claimed in claim 12, wherein, The plurality of first pixels and the plurality of second pixels are arranged alternately in a first direction. The plurality of first pixels and the plurality of second pixels are arranged alternately in a second direction intersecting the first direction.

14. The display device as claimed in claim 13, wherein, The plurality of first scan lines and the plurality of second scan lines are arranged alternately in the second direction.

15. A display device, comprising: The display panel defines a first non-folding area, a folding area, and a second non-folding area, and includes multiple pixels, each connected to a corresponding data line among multiple data lines and several corresponding scan lines among multiple scan lines. A data driving circuit that drives the plurality of data lines; A scan driving circuit that drives the plurality of scan lines; as well as A drive controller receives image signals and control signals, controls the data drive circuit and the scan drive circuit according to the operating mode, and outputs multiple clock signals, including a first clock signal to a fourth clock signal. The display panel is divided into a first display area and a second display area. The scan drive circuit includes a first scan drive circuit corresponding to the first display area and a second scan drive circuit corresponding to the second display area. In the multi-frequency mode, the first frame includes a first driving period and a second driving period, and the second frame, which is consecutive to the first frame, includes a third driving period and a fourth driving period. In the multi-frequency mode, the first scan driving circuit drives multiple scan lines corresponding to the first display area during the first driving period and the third driving period. In the multi-frequency mode, the second scan driving circuit sequentially drives a plurality of first scan lines among the plurality of scan lines corresponding to the second display area during the second driving period, and sequentially drives a plurality of second scan lines among the plurality of scan lines corresponding to the second display area during the fourth driving period. The drive controller outputs a second clock signal and a fourth clock signal at an inactive level during the second drive period, and outputs a first clock signal and a third clock signal at an inactive level during the fourth drive period.

16. The display device as claimed in claim 15, wherein, The plurality of first scan lines and the plurality of second scan lines extend in a first direction and are alternately arranged in a second direction intersecting the first direction.

17. The display device as claimed in claim 15, wherein, The second scan driving circuit includes: Multiple first driver stages, each responding to a first clock signal, a third clock signal, and a carry signal, output a first scan signal to a corresponding first scan line among the multiple first scan lines; and Multiple second driver stages, each responding to the second clock signal, the fourth clock signal, and the carry signal, output a second scan signal to a corresponding second scan line among the multiple second scan lines.

18. The display device as claimed in claim 15, wherein, The second display area of ​​the display panel includes: A plurality of first pixels, each of the plurality of first pixels being connected to a corresponding one of the plurality of first scan lines; and A plurality of second pixels, each of which is connected to a corresponding one of the plurality of second scan lines. Wherein, the plurality of first pixels and the plurality of second pixels are arranged alternately in a first direction. The plurality of first pixels and the plurality of second pixels are arranged alternately in a second direction intersecting the first direction.

Images