A wafer-level two-dimensional semiconductor device and its van der Waals integration method and application

Abstract

The present invention discloses a van der Waals integration method for wafer-scale two-dimensional semiconductor devices. The method comprises laminating a carrier-polymer stamp onto the surface of a contact electrode, performing a stripping process, and transferring the metal electrode array in the contact electrode from the contact electrode substrate to the carrier-polymer stamp to obtain a carrier-polymer-metal electrode material. Chemical bonding is imparted between the carrier and the polymer by chemical modification. A two-dimensional transition metal halogen compound material is laminated onto the surface of a back-gate electrode to obtain a back-gate electrode-TMDs composite material. The carrier-polymer-metal electrode material and the back-gate electrode-TMDs composite material are aligned according to the desired integrated circuit method, followed by stripping the carrier-polymer stamp and etching to obtain a wafer-scale two-dimensional semiconductor device. The large-scale van der Waals integration method disclosed herein can pave a path for the reliable integration of two-dimensional semiconductor devices and promote the practical application of two-dimensional semiconductor electronic devices.

Description

Technical Field

[0001] The present invention belongs to the field of nano devices, and in particular relates to the preparation of wafer-level two-dimensional semiconductor devices. Technical Background

[0002] Two-dimensional (2D) semiconductors, such as molybdenum disulfide (MoS2), have attracted extensive research interest in novel device applications. 1-4 Compared with traditional three-dimensional semiconductor materials, two-dimensional semiconductors have the characteristics of atomically thin thickness and no dangling bonds on the surface, and can show excellent electrical properties. Their sub-nanometer thickness and good short channel immunity are conducive to further miniaturization of transistors to the scale of sub-10 nanometer gate length. 5,6 Currently, researchers have reported MoS2 transistors with a gate length of 1nm, which show good switching characteristics and almost ideal subthreshold swing (SS, about 65mV / dec). 7 , showing the huge potential of two-dimensional semiconductors in further miniaturization of transistors.

[0003] Although two-dimensional transistors have the potential for widespread application, their research is mostly limited to exfoliated materials with limited size, which makes them difficult to manufacture in large quantities. Therefore, the large-scale synthesis of two-dimensional semiconductors and high-performance transistor manufacturing processes compatible with the semiconductor industry are the key to achieving practical industrial applications. Fortunately, some research work has been reported in recent years, using chemical vapor deposition (CVD) to 12,13 or Metal Organic Chemical Vapor Deposition (MOCVD) 14 The process enables large-area wafer-scale synthesis of single-layer two-dimensional semiconductors, especially semiconductor transition metal halide compounds (TMDs).

[0004] Although many researchers have achieved wafer-level integration of two-dimensional transistors using traditional standard photolithography processes, the performance of different devices in the same batch usually varies greatly, and device performance (such as on-state current, etc.) is usually an order of magnitude lower than the best-performing research device. 15,16 One of the key challenges in manufacturing high-performance transistors is forming high-quality metal / semiconductor contacts. 17-20 However, conventional photolithography and metal evaporation processes used for contacts often inevitably cause damage to the two-dimensional atomic lattice and cause polymer contamination, which partially degrades device performance, leading to large device performance variations between devices and poor reliability.

[0005] Research in recent years has shown that the use of three-dimensional metal 17,21-23 , two-dimensional metal 24-26 , 2D / 3D laminated metals 27-29Pure van der Waals (vdW) contact can minimize interface damage and effectively improve the quality of the metal / semiconductor contact interface 17,30 . However, most of these methods are based on mechanically stripped materials that cannot be mass-produced and require relatively complex processes. In addition, some researchers have used standard laboratory electron beam evaporation processes to achieve a potentially scalable indium / gold three-dimensional metal van der Waals contact. However, in electron beam exposure or traditional photolithography processes, the direct photolithography process may still produce inevitable contamination and damage on the surface of the two-dimensional semiconductor. In addition, some researchers have grown large-scale two-dimensional metal / semiconductor heterostructures through direct chemical deposition, which may provide a scalable van der Waals integration approach. 31 , but this is mostly limited to specific material systems, and more research and further exploration are needed to avoid thermal or chemical etching of 2D semiconductors during van der Waals epitaxial growth of 2D metal contacts. 1 .

[0006] Recent studies have shown that the integration process of pure physical peeling and release, namely the van der Waals integration method, can be achieved. 32,33 , the photolithographically patterned metal electrode array can be used for direct lift-off, transfer and integration on a two-dimensional semiconductor, thereby forming an almost ideal pin-free metal / semiconductor contact. However, in the current state-of-the-art van der Waals integration process 1,30 , van der Waals metal contacts are usually integrated by unsupported polymer films or using soft stamps (such as PDMS). In this process, wrinkles, interface contamination and interface bubbles are inevitably formed. Therefore, these technical challenges further increase the difficulty of transferring metal electrodes to existing pattern structures with high precision. In traditional microelectronics manufacturing, multi-layer lithography / integration processes often require such high-precision alignment processes. At the same time, it should be emphasized that the difficulty of these problems will increase exponentially with the increase of integration area and steps. Therefore, whether large-area van der Waals metal integration can be achieved on two-dimensional semiconductor materials is still a huge unresolved challenge.

[0007] References

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[0041] In order to solve the current problems of uneven performance and damage during the integration of metal electrodes in large-area two-dimensional semiconductor devices, as well as the challenge of difficult alignment in large-area van der Waals integration processes, the first purpose of the present invention is to provide an effective wafer-level van der Waals integration method for two-dimensional semiconductor devices.

[0042] The second object of the present invention is to provide a large-area van der Waals contact device (also referred to as a wafer-level two-dimensional semiconductor device in the present invention) produced by the van der Waals integration method.

[0043] The third object of the present invention is to provide applications of the prepared large-area van der Waals contact device.

[0044] A van der Waals integration method for wafer-level two-dimensional semiconductor devices comprises laminating a carrier-polymer stamp onto the surface of a contact electrode, performing a stripping process, and transferring the metal electrode array in the contact electrode from the contact electrode substrate to the carrier-polymer stamp to obtain a carrier-polymer-metal electrode material. In the stamp, the carrier is a transparent planar carrier having Si-O bonds on its surface, and the polymer is a polymer having a glass transition temperature of 100 to 150°C. There is a chemical bonding interaction between the carrier and the polymer due to chemical modification.

[0045] Composite a transition metal halogen compound two-dimensional material on the surface of the back gate electrode to obtain a back gate electrode-gate dielectric-TMDs composite material;

[0046] The carrier-polymer-metal electrode material and the back gate electrode-gate dielectric-TMDs structure are aligned according to the required integrated circuit method, and then the carrier-polymer stamp is peeled off and etched to obtain a wafer-level two-dimensional semiconductor device.

[0047] Existing van der Waals integration methods struggle to achieve large-scale integration, circuit alignment, and the yield and quality stability of the integrated circuits are poor. To address these technical difficulties, the present invention, through in-depth research, has discovered that the innovative use of a carrier-polymer stamp, combined with chemical modification of the stamp, can address the existing issues of large-scale two-dimensional materials prone to wrinkling and difficulty in successful transfer and alignment. This allows for successful van der Waals integration of large-scale two-dimensional materials, and also helps improve integration yield, quality stability, and various performance characteristics.

[0048] In this invention, the stamp structure and chemical modification are key to solving the van der Waals integration challenges of large-scale two-dimensional materials. The stamp can address deformation and air bubble issues, improve van der Waals forces, and facilitate flattening, high-fidelity exfoliation, and high-precision alignment of large-area electrodes. This enables high-yield, lossless integration and improves the performance of integrated transistors.

[0049] In the present invention, in the carrier-polymer stamp, the carrier is a silicon-based flat glass, or a flat composite carrier with a silicon dioxide coating on the surface.

[0050] Preferably, the carrier is a quartz plate.

[0051] Preferably, the polymer is at least one of PDMS, PVA, PC, etc.; preferably PDMS;

[0052] Preferably, the thickness of the polymer layer is 0.5 to 2 mm.

[0053] In the present invention, in the carrier-polymer stamp, the chemical modification is oxygen plasma bonding treatment. For example, the polymer and the carrier are subjected to plasma treatment, and then the treated polymer and the carrier are bonded to obtain the carrier-polymer stamp.

[0054] Preferably, the carrier-polymer stamp is a quartz plate-PMDS stamp. Further preferably, the quartz plate-PMDS stamp is prepared by the following steps: oxygen plasma is first used to remove impurities in the reaction chamber, and then the PDMS and quartz plate are placed in an oxygen plasma machine and treated at a power of 60-100W for 10-20 seconds (preferably 10 seconds). After removal, the treated PDMS is bonded to the surface of the quartz plate, and the Si-OH groups on the two surfaces react to form a strong Si-O bond.

[0055] In the present invention, the contact electrode can be prepared based on existing means.

[0056] Preferably, the contact electrode comprises a silicon substrate and a metal electrode array composited on the silicon substrate;

[0057] Preferably, the metal electrode is at least one of Au, Ag, Pt, etc.;

[0058] Preferably, the contact electrode is treated with hydrophobicity. Studies have found that hydrophobic treatment of the contact electrode helps to cooperate with the stamp material of the present invention and helps to further improve the two-dimensional van der Waals integration effect of TMDs.

[0059] Preferably, the contact electrode is prepared by the following steps:

[0060] A sacrificial material is coated on the substrate, and an electrode pattern is obtained using a photolithography process or electron beam exposure technology. The metal electrodes are then composited on the sacrificial material layer of the silicon wafer according to the required array pattern, and then hydrophobic modification is performed and encapsulated using PMMA.

[0061] Preferably, the sacrificial material is at least one of photoresist and PMMA;

[0062] Preferably, the substrate is at least one of a silicon wafer, a quartz wafer, and a sapphire wafer.

[0063] Preferably, the array of metal electrodes is deposited on the sacrificial material layer of the silicon wafer by means of an electron beam evaporation coating machine.

[0064] Preferably, the hydrophobic modification agent used in the hydrophobic modification is at least one of HMDS and TMSCl;

[0065] Further preferably, PMMA is spin-coated on the surface of the hydrophobically modified metal electrode to perform encapsulation treatment;

[0066] Preferably, the number of spin-coated layers is 1 to 3 layers.

[0067] In the present invention, a carrier-polymer stamp is composited on the contact electrode surface (metal electrode surface), bubbles therein are squeezed, and then the carrier is pulled to transfer the metal electrode array in the contact electrode to the stamp.

[0068] In the present invention, the back gate electrode can be prepared based on existing means.

[0069] Preferably, the back gate electrode comprises a back gate substrate, a back gate metal electrode array composited on the back gate substrate, and a gate dielectric coated on the surface of the back gate metal electrode array;

[0070] Preferably, the substrate is at least one of a silicon wafer, a quartz wafer, and a sapphire wafer;

[0071] Preferably, the back gate metal electrode is at least one of Ti / Au, Cr / Au, etc.;

[0072] Preferably, the gate dielectric is at least one of Al2O3 and HfO2;

[0073] Preferably, the back gate electrode is prepared by the following steps:

[0074] A sacrificial layer is formed on the substrate, and a back-gate metal electrode is composited on the substrate sacrificial material layer in a required array using a photolithography process, and then a gate dielectric is encapsulated on the surface of the back-gate metal electrode to obtain the back-gate electrode.

[0075] In the present invention, the transition metal halide two-dimensional materials (TDMs) have a large planar size;

[0076] Preferably, the size of the transition metal halogen compound two-dimensional material is a wafer of 2 inches or more;

[0077] Preferably, the transition metal halogen compound two-dimensional material is at least one of MoS2, WSe2, WS2, MoSe2, etc.;

[0078] Preferably, the transition metal halogen compound two-dimensional material is a continuous film of 1 to 3 layers, preferably a single layer.

[0079] In the present invention, the TDMs can be prepared and stripped by existing means.

[0080] Preferably, the transition metal halogen compound two-dimensional material is obtained by peeling off by the following means: depositing the transition metal halogen compound two-dimensional material on a substrate, spin-coating photoresist and PMMA on the surface in sequence, and then etching in an alkaline solution to obtain the transition metal halogen compound two-dimensional material.

[0081] In the present invention, the two-dimensional material obtained by stripping can be composited on the back gate electrode (gate dielectric surface) by using existing means.

[0082] In the present invention, the carrier-polymer-metal electrode material (metal electrode material surface) and the back gate electrode-TMDs composite material (TMDs material surface) are aligned with the aid of a mark system according to the required integrated circuit requirements.

[0083] The mark system is a conventional alignment equipment system in the field of photolithography.

[0084] In the present invention, thanks to the technical solution, high-precision alignment can be achieved, for example, 1×1 cm 2 For chips of this size, the average alignment error is around 2 to 5 μm.

[0085] Preferably, the carrier-polymer-metal electrode material and the back gate electrode-TMDs composite material are compounded and then the bubbles therein are squeezed out;

[0086] Preferably, the integrated circuit is a logic circuit and / or an electronic circuit; the logic circuit includes at least one of an inverter, a NAND gate, a NOR gate, an AND gate and a half adder;

[0087] The present invention can realize multi-layer logic circuit alignment.

[0088] Preferably, the carrier-polymer stamp is released from the aligned material by heat treatment;

[0089] Preferably, the temperature of the heat treatment is 120-150°C;

[0090] Preferably, after stripping the carrier-polymer stamp, an etching process is performed, wherein the etching step comprises: patterning by electron beam exposure / photolithography so that the material at the device channel is protected by PMMA or photoresist, and then oxygen plasma treatment is performed to make the material at other locations lose conductivity, thereby achieving device independence.

[0091] Preferably, the MoS2 film is patterned by photolithography or electron beam exposure and then etched with O2 plasma. The MoS2 film is patterned by photolithography or electron beam exposure and then etched with O2 plasma to remove the material in the pattern.

[0092] Preferably, the wafer-level two-dimensional semiconductor device structure is a back-gate structure of a high-k gate dielectric and a metal gate.

[0093] In the method described in the present invention, the prepared logic gate circuits and transistor devices are all high-k back-gate devices. The back-gate electrode is first photolithographically processed, and then the gate dielectric Al2O3 or HfO2 is grown by atomic vapor deposition. Then, a single layer of MoS2 is transferred to the back-gate electrode. Then, the contact electrode is transferred to the material with high precision through van der Waals integration. Finally, the excess material is etched away, leaving only the channel area.

[0094] The present invention also provides a wafer-level two-dimensional semiconductor device produced by the preparation method.

[0095] The present invention also provides an application of a wafer-level two-dimensional semiconductor device prepared by the preparation method, which is used in large-scale digital circuits.

[0096] Beneficial effects

[0097] The present invention can realize high-precision van der Waals integration of large-area electrodes through the chemically modified rigid support stamp, and can achieve alignment accuracy close to the overlay accuracy of traditional contact lithography machines.

[0098] The large-area van der Waals integrated devices fabricated by this invention exhibit clean and damage-free metal / semiconductor interfaces, uniform performance, and excellent reproducibility. Furthermore, the integration yield of this technical solution can reach 97% or higher. This technical solution is expected to be applied to two-dimensional semiconductor electronics and large-scale two-dimensional semiconductor integrated circuits.

[0099] The large-area van der Waals integration method implemented by the present invention can achieve high-precision multi-layer integration, thereby realizing logic circuits such as inverters, NAND gates, NOR gates, AND gates, and half adders. Since the contact interface is clean and lossless, the existence of interface states is reduced, and the gain of the inverter is 5V V dd Next, it can reach 585. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] Figure 1 This is an overall schematic diagram of the van der Waals integration of Example 1.

[0101] Figure 2 Schematic diagram of the preparation process of the contact electrode in Example 1.

[0102] Figure 3 Schematic diagram of the preparation of the back gate electrode and the growth of the high-k gate dielectric in Example 1.

[0103] Figure 4 Schematic diagram of the transfer of MoS2 continuous film in Example 1.

[0104] Figure 5 Schematic diagram of the van der Waals integration step in Example 1.

[0105] Figure 6 These are optical photographs of each step in the 2-inch wafer-level van der Waals integration of Example 1.

[0106] Figure 7 1×1 cm of Example 1 2 Optical microscope image of the dimensional van der Waals integration accuracy and a magnified view of a selected area.

[0107] Figure 8 This is an example diagram of the van der Waals integration precision measurement of Example 1.

[0108] Figure 9 1×1 cm of Example 1 2 Statistical data of the dimensional van der Waals integration accuracy in both the X and Y directions.

[0109] Figure 10 The following are photos and SEM images of the van der Waals integrated MoS2 back-gate transistor of Example 2, as well as electrical performance diagrams.

[0110] Figure 11This is a statistical comparison data chart of the performance of the large-area van der Waals integrated device and the traditional evaporation device in Example 3.

[0111] Figure 12 Graph showing the van der Waals integrated inverter and the inverter output curve and gain data of Example 4.

[0112] Figure 13 This is a comparison chart of the gain of the van der Waals integrated inverter of Example 3 and the single-layer TMDs material reported in the literature.

[0113] Figure 14 Optical microscope image and electrical output curve of the van der Waals integrated NOR gate of Example 5.

[0114] Figure 15 The optical microscope image and electrical output curve of the van der Waals integrated NAND gate of Example 5.

[0115] Figure 16 Optical microscope image and electrical output curve of the van der Waals integrated AND gate of Example 5.

[0116] Figure 17 The optical microscope image and electrical output curve of the van der Waals integrated half adder of Example 5.

[0117] Figure 18 This is the product picture of Comparative Example 1.

[0118] Figure 19 This is the product picture of Comparative Example 2. Specific implementation methods

[0119] In the preparation of MoS2: sulfur powder (Alfa, 99.9%) and MoO3 (Alfa, 99.999%)

[0120] Device electrical performance testing: Lakeshore vacuum probe station, semiconductor analyzers (Keysight 2912A and Agilent B1500)

[0121] The present invention is further described below through examples of implementation, but the content of the present invention is not limited to the following content.

[0122] Large-area van der Waals integration methods are shown in Figure 1, which is mainly divided into three steps: electrode peeling, alignment and fixed-point release. The quartz wafer and PDMS are bonded by oxygen plasma, which is a chemical bond. PDMS is not easy to deform laterally under the support of the quartz wafer, and the bubbles at the interface between PDMS and PMMA can be driven away. The PMMA / electrode layer has weakened its bonding with the silicon wafer due to HMDS treatment, making it easy to peel off. The alignment process is carried out under a microscope, and two fields of view are used to observe the alignment simultaneously. The step of releasing the electrode is achieved by heating to 120°C.

[0123] like Figure 2 First, the transfer electrode needs to be prepared in advance. The contact electrode is prepared by photolithography or electron beam exposure process, and then silver / gold (30 / 20nm) is evaporated, followed by fumigation with HMDS vapor in an 80℃ oven, and finally PMMA is spin-coated on the sample. Then, Figure 3 Prepare the back gate electrode and grow Al2O3 gate dielectric using ALD. Figure 4 , transfer the MoS2 film to the sample, and finally Figure 5 The process is carried out through targeted alignment and release to realize the van der Waals integration process.

[0124] Example 1

[0125] Step (1): Preparation of stamp material: Oxygen plasma is first used to remove impurities. Then, the PDMS and quartz plate are placed in an oxygen plasma machine and treated at 80W for 10 seconds. After removal, the treated PDMS is bonded to the surface of the quartz plate to obtain a PDMS / quartz plate stamp.

[0126] Step (2): Contact electrode preparation and stamp peeling ( Figure 2 ); obtain the electrode pattern on the sacrificial substrate (SiO2 / Si) by photolithography or electron beam exposure technology, then use electron beam evaporation coating machine to evaporate silver / gold (30 / 20nm), and finally peel off the silver / gold outside the pattern in acetone solution to finally obtain the contact electrode. Place the contact electrode in an 80℃ oven and treat it with HMDS vapor for hydrophobicity, then spin-coat two layers of PMMA. Slowly stick the stamp on the contact electrode to remove bubbles, then quickly and vertically tear off the quartz sheet / PDMS / PMMA / metal to obtain the stamp-contact electrode, and finally transfer it to the prepared 2-inch back gate electrode substrate.

[0127] Step (3): Preparation of back gate electrode ( Figure 3 ): Using the photolithography process, the back gate metal electrode (Ti / Au (15 / 15nm)) is composited on the substrate (SiO2 / Si) sacrificial material (photoresist) layer according to the required array, and then 12nm Al2O3 is grown by atomic vapor deposition.

[0128] Step (4): Preparation, stripping and compounding of two-dimensional materials on the back gate electrode ( Figure 4 ); MoS2 thin films were grown in a three-zone furnace. Commercially sourced sulfur (Alfa, 99.9%, 6g) and MoO3 (Alfa, 99.999%, 60mg) powders were loaded into two separate inner tubes and placed in Zones I and II, respectively. A 2-inch sapphire substrate was placed in Zone III. During growth, the two inner tubes were then fed with 100sccm Ar and 75 / 3sccm Ar / O2 flows. The S, MoO3, and sapphire substrate heating temperatures were 115°C, 530°C, and 930°C, respectively. The growth chamber pressure was ~1 torr, and the growth time was 40 minutes.

[0129] A layer of BP-212 photoresist was spin-coated on the MoS2 / sapphire substrate at 3000 rpm and then baked at 110°C for 5 minutes. Next, a layer of PMMA was spin-coated at the same speed. Next, a thermal release adhesive was applied to the sample and immersed in a 10% KOH solution for 1 minute. The thermal release adhesive / PMMA / photoresist / MoS2 film was peeled off using tweezers.

[0130] The thermal release adhesive / PMMA / photoresist / MoS2 film was released onto the back gate electrode in step (3) at 120°C using a transfer platform. After complete release, the sample was cleaned in acetone for 30 minutes to remove all polymers. A back gate electrode-gate dielectric-MoS2 structure was obtained.

[0131] Step (5): Alignment, demolding, and etching: Using a custom dual-lens transfer platform, the quartz / PDMS / PMMA / metal layer (the stamp-contact electrode prepared in step (2)) is directly aligned to the target substrate (the back gate electrode-gate dielectric-MoS2 structure prepared in step (4)) using two standard alignment marks under an optical microscope. Finally, we heat the substrate to 120°C to reduce the van der Waals forces between PDMS and PMMA, thereby leaving the PMMA / metal on the target substrate, and finally peel off the quartz / PDMS stamp.

[0132] Step (6): Patterning is achieved through electron beam exposure / photolithography so that the material at the device channel is protected by PMMA / photoresist, and then oxygen plasma treatment is performed to make the material at other locations lose conductivity, thereby achieving device independence.

[0133] In this case, the contact electrode and back gate electrode were prepared on a 2-inch wafer, and a 2-inch wafer-level PDMS / quartz stamp was made. The stamp was slowly attached to the contact electrode to remove bubbles, and then the electrode was torn off the silicon wafer and finally transferred to the prepared 2-inch back gate electrode substrate. The optical photos of each step are shown below. Figure 6As shown. We characterized 1×1cm 2 The size of the van der Waals integration precision, its optical microscope picture is as follows Figure 7 As shown, high-resolution optical microscope images taken at different positions show that 2 On chip scale, the alignment deviation is 0-10μm. Examples of methods for measuring alignment accuracy are as follows: Figure 8 As shown. Finally, the average alignment accuracy is about 2 to 5 μm, as shown Figure 9 The large-area van der Waals integrated device prepared by the present invention has excellent performance and good reproducibility.

[0134] Example 2

[0135] The inventors also prepared a back-gate transistor with a channel length of 145nm. Compared with Example 1, the gate dielectric used was 6nm HfO2, the subthreshold swing was about 77mV / dec, and the maximum output voltage was about 250μA / μm. Figure 10 As shown, the output curve of the device also shows an obvious saturation output shape.

[0136] Example 3

[0137] The inventors also prepared a large number of MoS2 back-gate transistors with van der Waals contacts and evaporation contacts. Compared with Example 2, the channel length is 6μm and the gate dielectric is 12nm Al2O3. Figure 11 As shown, compared with transistors with evaporated contacts, van der Waals contact devices achieve lossless high-quality contacts on monolayer MoS2, so that MoS2 transistors have good performance and reproducibility, with smaller threshold voltage changes, higher on-state current, smaller off-state current, and also have a larger switching ratio and smaller subthreshold swing.

[0138] Example 4

[0139] A fully van der Waals integrated inverter was prepared according to the method of Example 1. Figure 12 As shown, the inventors used two MoS2 transistors to realize the NMOS inverter function with a gain of 585, which achieved a higher gain. Figure 13 As shown, it has great advantages compared with the inverter gain based on single-layer TMDs materials reported in the literature.

[0140] Example 5

[0141] A series of logic gates and logic circuits were prepared according to the method of Example 1, including NOR gates (such as Figure 14 As shown), NAND gate (as Figure 15 As shown), AND gate (as Figure 16 As shown) and adder logic circuit (as Figure 17As shown), all logic gates and logic circuits successfully demonstrated the correct logic output results.

[0142] Comparative Example 1

[0143] Compared with Example 1, the only difference is that in step (1), oxygen plasma treatment is not performed. Other operations and steps are the same as in Example 1.

[0144] The results are as follows Figure 18 As shown in FIG, without oxygen plasma treatment, the electrode is easily wrinkled or even damaged during the process of tearing off the electrode.

[0145] Comparative Example 2

[0146] Compared with Example 1, the only difference is that PDMS is not used in step (1). Other operations and steps are the same as in Example 1.

[0147] See the results Figure 19 Electrodes that do not use PDMS as a support can easily lead to electrode wrinkling, breakage, and interface contamination and interface bubbles.

Claims

1. A van der Waals integration method for wafer-level two-dimensional semiconductor devices, characterized by: A carrier-polymer stamp is composited onto the surface of a contact electrode, subjected to a peeling treatment, and the metal electrode array in the contact electrode is transferred from the contact electrode substrate to the carrier-polymer stamp to obtain a carrier-polymer-metal electrode material; in the stamp, the carrier is a transparent planar carrier having Si-O bonds on its surface, and the polymer is a polymer having a glass transition temperature of 100-150°C, wherein a chemical bonding interaction exists between the carrier and the polymer due to chemical modification; Compounding a transition metal halogen compound two-dimensional material on the surface of the back gate electrode to obtain a back gate electrode-TMDs composite material; The carrier-polymer-metal electrode material and the back gate electrode-TMDs composite material are aligned according to the required integrated circuit method, and then the carrier-polymer stamp is peeled off and etched to obtain a wafer-level two-dimensional semiconductor device.

2. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: In the carrier-polymer stamp, the carrier is silicon-based flat glass, or a flat composite carrier with a silicon dioxide coating on the surface.

3. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 2, wherein: The carrier is a quartz plate.

4. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The polymer is at least one of PDMS, PVA, and PC.

5. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The thickness of the polymer layer is 0.5~2 mm.

6. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: In the carrier-polymer stamp, the chemical modification is oxygen plasma bonding.

7. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 6, wherein: The carrier-polymer stamp is a quartz sheet-PMDS stamp.

8. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 7, wherein: The quartz plate-PMDS stamp is prepared by the following steps: placing the PDMS and quartz plate in an oxygen plasma machine and treating them at a power of 60-100 W for 10-20 seconds; then laminating the treated PDMS to the surface of the quartz plate, allowing the Si-OH groups on the two surfaces to react, thereby forming a strong Si-O bond.

9. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The contact electrode comprises a silicon substrate and a metal electrode array composited on the silicon substrate.

10. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 9, wherein: The metal electrode is at least one of Au, Ag, and Pt.

11. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The contact electrode is treated with hydrophobic modification.

12. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 11, wherein: A sacrificial material is coated on the substrate, and the electrode pattern is obtained using photolithography or electron beam exposure technology. The metal electrode is then composited on the sacrificial material layer of the silicon wafer according to the required array pattern, followed by hydrophobic modification and encapsulation using PMMA.

13. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 12, wherein: The sacrificial material is at least one of photoresist and PMMA.

14. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 12, wherein: The metal electrode array is composited on the sacrificial material layer of the silicon wafer by using an electron beam evaporation coating machine.

15. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 12, wherein: The hydrophobic modification agent used in the hydrophobic modification is at least one of HMDS and TMSCI.

16. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 15, wherein: PMMA is spin-coated on the surface of the hydrophobically modified metal electrode for encapsulation.

17. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 16, wherein: The number of spin coating layers is 1 to 3 layers.

18. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The carrier-polymer stamp is composited on the surface of the contact electrode, the bubbles therein are squeezed out, and then the carrier is pulled up to transfer the metal electrode array in the contact electrode to the stamp.

19. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The back gate electrode comprises a back gate substrate, a back gate metal electrode array composited on the back gate substrate, and a gate dielectric coated on the surface of the back gate metal electrode array.

20. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 19, wherein: The substrate is at least one of a silicon wafer, a sapphire wafer, and a quartz wafer; The back gate metal electrode is at least one of Ti / Au and Cr / Au; The gate dielectric is at least one of Al2O3 and HfO2.

21. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 20, wherein: The back gate electrode is prepared by the following steps: A sacrificial layer is formed on the substrate, and a back-gate metal electrode is composited on the substrate sacrificial material layer in a required array using a photolithography process, and then a gate dielectric is encapsulated on the surface of the back-gate metal electrode to obtain the back-gate electrode.

22. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The transition metal halogen compound two-dimensional material has a large planar size.

23. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 22, wherein: The size of the transition metal halide compound two-dimensional material is a wafer of 2 inches or more.

24. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 22, wherein: The transition metal halogen compound two-dimensional material is at least one of MoS2 two-dimensional material, WSe2, WS2, and MoSe2.

25. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 22, wherein: The transition metal halogen compound two-dimensional material is a continuous film of 1 to 3 layers.

26. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 25, wherein: The transition metal halogen compound two-dimensional material is obtained by peeling off by the following means: A transition metal halogen compound two-dimensional material is deposited on a substrate, photoresist and PMMA are spin-coated on the surface in sequence, and then the surface is etched in an alkaline solution to obtain the transition metal halogen compound two-dimensional material.

27. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The carrier-polymer-metal electrode material and back gate electrode-TMDs composite material are aligned with the aid of a mark system according to the required integrated circuit requirements.

28. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 27, wherein: The bubbles in the carrier-polymer-metal electrode material and the back gate electrode-TMDs composite material are squeezed out after being compounded.

29. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 27, wherein: The integrated circuit is a logic circuit and / or an electronic circuit; the logic circuit includes at least one of an inverter, a NAND gate, a NOR gate, an AND gate and a half adder.

30. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 27, wherein: The carrier-polymer stamp is released from the aligned material by heat treatment.

31. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 30, wherein: The heat treatment temperature is 120-150°C.

32. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 30, wherein: After stripping the carrier-polymer stamp, an etching process is performed. The etching process is as follows: patterning is achieved through electron beam exposure / photolithography so that the material at the device channel is protected by PMMA or photoresist, and then oxygen plasma treatment is performed to make the material at other locations lose conductivity, thereby achieving device independence.

33. The van der Waals integration method of wafer-level two-dimensional semiconductor devices according to claim 1, wherein: The wafer-level two-dimensional semiconductor device structure is a back-gate structure of a high-k gate dielectric and a metal gate.

34. A wafer-level two-dimensional semiconductor device manufactured by the van der Waals integration method according to any one of claims 1 to 33.

35. An application of a wafer-level two-dimensional semiconductor device produced by the van der Waals integration method according to any one of claims 1 to 33, characterized in that: It is used in large-scale digital circuits.

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