Semiconductor device

Abstract

The semiconductor device of the present embodiment includes a wiring substrate, a semiconductor chip, and a resin layer. The wiring substrate has an insulating member and a pad exposed from the insulating member and electrically connected to a wiring provided on the insulating substrate. The height of the insulating member differs depending on the position on the wiring substrate. The semiconductor chip has a bump connected to the pad on a first surface opposite to the wiring substrate. The resin layer covers the periphery of the bump between the wiring substrate and the semiconductor chip.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-125554, filed on July 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This embodiment relates to a semiconductor device. Background Technology

[0003] Methods for flip-chip bonding of semiconductor chips to wiring substrates include mass reflow and thermoforming. In thermoforming flip-chip bonding, when the semiconductor chip is mounted on the wiring substrate, the solder is melted by heat, and the bumps of the semiconductor chip are thermoformed and bonded to the pads of the wiring substrate.

[0004] However, during flip chip bonding, the semiconductor chip may warp due to heating, resulting in poor connection between the semiconductor chip and the wiring substrate. Furthermore, in thermoforming, voids may become trapped within the resin (adhesive) protecting the connection point with the substrate. Moisture within these voids can become a path for electrical leakage, potentially causing malfunctions in the semiconductor chip. Summary of the Invention

[0005] The object of this invention is to provide a semiconductor device capable of suppressing defects in flip chip interconnects.

[0006] The semiconductor device of this technical solution includes a wiring substrate, a semiconductor chip, and a resin layer. The wiring substrate has an insulating member and pads exposed from the insulating member and electrically connected to wiring disposed on the insulating substrate. The height of the insulating member varies depending on its position on the wiring substrate. The semiconductor chip has bumps on a first surface opposite the wiring substrate that connect to the pads. The resin layer covers the area around the bumps between the wiring substrate and the semiconductor chip.

[0007] Based on the above structure, a semiconductor device capable of suppressing defects in flip chip interconnects can be provided. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing a structural example of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a cross-sectional view showing a structural example of the wiring substrate, resin layer and their surroundings according to the first embodiment.

[0010] Figure 3 This is a cross-sectional view showing the wiring substrate, resin layer and their surrounding structure of Modified Example 1.

[0011] Figure 4 This is a cross-sectional view showing the wiring substrate, resin layer and their surrounding structure in Modified Example 2.

[0012] Figure 5 This is a cross-sectional view showing the wiring substrate, resin layer and their surrounding structure in Modified Example 3.

[0013] Figure 6 This is a plan view showing the configuration example of the metal bumps of the controller chip in Modified Example 4.

[0014] Figure 7A It means Figure 6 A cross-sectional view of the wiring substrate, resin layer and their surrounding structure of the A-A' line.

[0015] Figure 7B It means Figure 6 A cross-sectional view of the wiring substrate, resin layer and their surrounding structure of the B-B' line.

[0016] Figure 8 This is a cross-sectional view showing a structural example of the wiring substrate and its surrounding area according to the second embodiment.

[0017] Figure 9 This is a cross-sectional view showing the wiring substrate and its surrounding structure in Modified Example 5. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the invention. In the following embodiments, the vertical direction of the wiring substrate refers to the relative direction when the surface on which the semiconductor chip is mounted is facing upwards, and may differ from the vertical direction following the acceleration due to gravity. The drawings are schematic or conceptual, and the proportions of the parts are not necessarily the same as in reality. In the specification and drawings, the same reference numerals are used for elements that have been described previously with respect to the figures, and detailed descriptions are omitted where appropriate.

[0019] (First Embodiment)

[0020] Figure 1 This is a cross-sectional view showing a structural example of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 in this embodiment is, for example, a NAND flash memory. The semiconductor device 1 includes a wiring substrate 10, a controller chip 30 which is a semiconductor chip, a resin layer 35, a resin layer 90, a resin layer 40, spacers 50, a NAND flash memory chip (hereinafter referred to as a memory chip) 60 which is a semiconductor chip, and bonding wires 80. The resin layer 90 is a so-called molding resin, which is an encapsulating resin. Furthermore, this embodiment is not limited to NAND flash memory and can be applied to flip-chip interconnect semiconductor devices.

[0021] The wiring substrate 10 includes an insulating substrate 11, wiring 12, contact plugs 13, metal pads 14, solder balls 15, and solder resist 16. The insulating substrate 11 is, for example, a pre-preg composite material made of fibrous reinforcing materials such as glass fiber and thermosetting resins such as epoxy. Alternatively, insulating materials such as glass epoxy resin or ceramics (alumina-based, AlN-based) may be used in the insulating substrate 11. Wiring 12 is disposed on the surface, back, or interior of the insulating substrate 11, electrically connecting the metal pads 14 and solder balls 15. The metal pads 14 may be part of the wiring 12. The contact plugs 13 are disposed through the insulating substrate 11, electrically connecting the wiring 12. The metal pads 14 are connected to the metal bumps 31 of the controller chip 30 on the surface of the wiring substrate 10. The solder balls 15 are connected to the wiring 12 on the back of the wiring substrate 10. In the wiring 12, contact plug 13, and metal pads 14, conductive materials such as Cu, Ni, Au, Sn, Ag, Bi, and Pd are used in monomer films, composite films, and alloy films. In the solder balls 15, conductive materials such as Sn, Ag, Cu, Au, Bi, Zn, In, Sb, and Ni are used in monomer films, composite films, and alloy films. Solder resist 16 is provided on the surface and back of the wiring substrate 10, between adjacent metal pads 14 and around the metal pads 14 or between adjacent solder balls 15, to electrically insulate them. In addition, solder resist 16 can also cover the surface of the wiring 12 to protect the wiring 12.

[0022] More specifically, the wiring substrate 10 has a solder resist 16 and metal pads 14 exposed from the solder resist 16 and electrically connected to wiring 12 disposed on the insulating substrate 11.

[0023] The controller chip 30 has a surface F1 opposite to the wiring substrate 10 and a surface F2 on the opposite side of surface F1. A plurality of metal bumps 31 are provided on surface F1. The metal bumps 31 are bonded (fused) to the metal pads 14 of the wiring substrate 10. That is, the controller chip 30 is flip-chip bonded to the wiring substrate 10. The metal bumps 31 are, for example, made of conductive metal such as solder. The substrate of the semiconductor chip can be a silicon substrate, a GaAg substrate, a SiC substrate, etc.

[0024] The controller chip 30 is thinned and has semiconductor elements on surface F1 or surface F2. The controller chip 30 may warp during the formation of the semiconductor elements. The warping of the controller chip 30 can be, for example, mountain-shaped, bowl-shaped, or saddle-shaped. Figure 1 The warping of the controller chip 30 is not shown in the diagram.

[0025] The resin layer 35 fills the space between the wiring substrate 10 and the surface F1 of the controller chip 30. The resin layer 35 is, for example, an underfill material, using a liquid, non-conductive resin material. The resin layer 35 covers the area around the metal pads 14 and the metal bumps 31. Thus, the resin layer 35 supports the connection between the metal pads 14 and the metal bumps 31, and suppresses breakage between them.

[0026] The resin layer 35 can be made of materials such as epoxy resin, silicone resin, epoxy / silicone mixed resin, acrylic resin, polyimide resin, polyamide resin or phenolic resin as the base material.

[0027] Furthermore, the resin layer 35 contains a reducing material, such as an alcohol or organic acid, as an additive to remove the metal oxide film formed on the surface of the metal bump 31. Examples of alcohols include at least one selected from methanol, ethanol, isopropanol, polyvinyl alcohol, ethylene glycol, propylene glycol, diethylene glycol, glycerol, triethylene glycol, tetraethylene glycol, carbitol, and ethylene glycol ethyl ether. Alkyl ethers may also be used. Examples include diethylene glycol monobutyl ether and triethylene glycol dimethyl ether. Alkanes and amine compounds may also be used. Examples include formamide and dimethylformamide. These can be used individually or in combination. Organic acids may also be added to these materials. Examples of organic acids include formic acid, acetic acid, benzoic acid, abietic acid, parstoline acid, dehydrorosinic acid, isopyric acid, neoabsinolic acid, piratic acid, and rosin. These can be used individually or in combination. The resin layer 35 is applied using methods such as dispensing (spraying, spiraling), printing, etc. Furthermore, the resin layer 35 has the function of reducing and removing oxide films (SnO, SnO2) on the surface of the metal bumps 31 or metal pads 14.

[0028] Spacers 50 are provided on the wiring substrate 10 surrounding the controller chip 30, separated by a resin layer 40. The resin layer 40 is, for example, a DAF (Die Attach Film). The spacers 50 are bonded to the wiring substrate 10 through the resin layer 40. The spacers 50 are at a height approximately equal to the height of surface F2 of the controller chip 30 and support the memory chip 60. The spacers 50 are, for example, shaped like a quadrilateral frame or a quadrilateral surrounding the controller chip 30, and are provided on the surface of the wiring substrate 10 in a manner that surrounds the controller chip 30 on all four sides (not shown). The spacers 50 are made of materials such as silicon, glass, ceramic, insulating substrate, metal plate, etc. To improve adhesion, organic films such as polyimide resin, polyamide resin, epoxy resin, acrylic resin, phenolic resin, silicone resin, and PBO (Polybenzoxazole) resin may also be formed on the spacers 50.

[0029] The memory chip 60 is disposed above the controller chip 30 and is fixed to the controller chip 30 and the spacer 50 by the resin layer 40. The memory chip 60, for example, has a three-dimensional memory cell array in which multiple memory cells are arranged in three dimensions. The resin layer 40 is disposed on the surface F2 of the controller chip 30 and the spacer 50, fixing the memory chip 60 to the controller chip 30 and the spacer 50.

[0030] Alternatively, multiple resin layers 40 and multiple memory chips 60 can be alternately stacked on the controller chip 30 and the spacer 50. In this way, even when multiple memory chips 60 are stacked on top of the controller chip 30, the warpage of the controller chip 30 is reduced, and therefore the multiple memory chips 60 are less susceptible to the effects of the controller chip 30's warpage. That is, the multiple memory chips 60 are less prone to damage and less likely to peel off from the resin layer 40.

[0031] A bonding wire 80 electrically connects a metal pad 70 of the memory chip 60 to a metal pad 14 of the wiring substrate 10. A resin layer 90 completely covers and protects the structures on the wiring substrate 10, including the controller chip 30, the memory chip 60, and the bonding wire 80. Furthermore, the resin layer 90 is filled between the wiring substrate 10 and the surface F1 of the controller chip 30, and is disposed in such a way that it covers the area around the metal bump 31.

[0032] In addition, Figure 1 Within the same semiconductor package, a controller chip 30 connected by a flip chip and a memory chip 60 connected by wire bonding are both disposed. That is, in Figure 1The middle part is a hybrid multi-chip package. However, in this embodiment, multiple memory chips 60 can also be flip-chip connected to the controller chip 30. In this case, the controller chip 30 and the multiple memory chips 60 can also be electrically connected via a through-silicon via (TSV).

[0033] Alternatively, you can leave it unset. Figure 1 The spacer 50 is shown. In this case, for example, the controller chip 30 is embedded from above by a thicker resin layer 40, and the memory chip 60 is provided above the resin layer 40. Alternatively, if no other chips are mounted on the upper part of the controller chip 30, the resin layer 90 may not be present on the controller chip 30.

[0034] Next, the wiring substrate 10 and the resin layer 35 will be described.

[0035] Figure 2 This is a cross-sectional view showing a structural example of the wiring substrate 10, resin layer 35, and their periphery according to the first embodiment. Additionally, as... Figure 2 As shown, electrode posts 32 can also be provided on surface F1 of the controller chip 30. The electrode posts 32 are connected to metal bumps 31. The electrode posts 32 are made of a conductive metal, such as copper. Furthermore, the height of the plurality of electrode posts 32 is, for example, approximately constant. The height of the plurality of metal pads 14 is, for example, approximately constant. Furthermore, in Figure 2 In the example shown, the lower surfaces of the metal pads 14 and the solder resist 16 correspond to the upper surface of the insulating substrate 11.

[0036] exist Figure 2 In the example shown, the resin layer 35 is, for example, NCF (Non-Conductive Film) or NCP (Non-Conductive Paste). Furthermore, the controller chip 30 is bonded to the wiring substrate 10, for example, by thermoforming. The NCF is, for example, attached to surface F1 of the controller chip 30 or the wiring substrate 10 before thermoforming. The NCP is, for example, coated onto the wiring substrate 10 before thermoforming. Hereinafter, as an example, the case where the NCF, as the resin layer 35, is attached to surface F1 will be described. However, it is not limited to thermoforming; it can be performed whenever the resin layer 35 is filled during flip chip bonding, or flip chip bonding can be performed ultrasonically.

[0037] Here, in the thermoforming method, the controller chip 30 is mounted on the wiring substrate 10 while being heated and pressed. In this case, the resin layer 35 is only pressed and has difficulty flowing. Therefore, the gaps (pores) V between the wiring substrate 10 and the resin layer 35, or within the resin layer 35, are difficult to drain and are easily trapped within the resin layer 35. If moisture enters into these gaps V, a leakage path occurs through the electrical connection between the gaps V. This leakage path may cause malfunction of the controller chip 30.

[0038] Therefore, as Figure 2 As shown, the solder resist (insulator) 16 has different heights (thicknesses) depending on its position on the wiring substrate 10. This allows the pressed resin layer 35 to flow easily on the wiring substrate 10. In other words, the pressure difference within the resin layer 35 created by the difference in the thickness of the solder resist 16 facilitates the flow of the pressed resin layer 35.

[0039] More specifically, the solder resist 16 gradually decreases in thickness from the center of the opposing controller chip 30 to its outer periphery. During thermoforming, the center of the controller chip 30 first contacts the center of the resin layer 35. This is because the solder resist 16 is thickest below the center of the controller chip 30. If the resin layer 35 is further pressed, pressure is also applied to its outer periphery. At this point, because the solder resist 16 is thickest, the pressure on the resin layer 35 at the center is the highest. On the other hand, as the solder resist 16 thins from the center of the controller chip 30 to its outer periphery, the pressure on the resin layer 35 also decreases. Therefore, the resin layer 35 easily flows towards the outer periphery of the controller chip 30 where the pressure is lower. Thus, as Figure 2 As shown, the voids V within the resin layer 35 also tend to move towards the outer periphery of the controller chip 30, as indicated by the arrow. Consequently, the voids V are easily expelled from the resin layer 35.

[0040] Furthermore, more specifically, the maximum height of the solder resist 16 opposite to the controller chip 30 is less than or equal to the height of the metal pad 14. The thickness of the metal pad 14 is, for example, approximately 10 μm. The thickness of the solder resist 16 below the center of the controller chip 30 is, for example, less than or equal to the thickness of the metal pad 14, approximately 8 μm to approximately 10 μm. The thickness of the solder resist 16 decreases in a stepped manner, for example, towards the outer periphery of the controller chip 30, in steps of approximately 2 μm.

[0041] Furthermore, more specifically, the height of the solder resist 16 around the metal pad 14 is approximately constant. This allows the metal bumps 31 to more easily and evenly contact the metal pad 14 around it. Consequently, the connection reliability of the metal bumps 31 can be improved. Furthermore, in Figure 2In the example shown, the thickness of the solder resist 16 varies in a stepped manner at a specified location between the metal pads 14.

[0042] The steps of the solder resist 16 appear approximately concentric circles when viewed from above surface F2 of the controller chip 30. In this case, the resin layer 35 flows smoothly with less bias. However, the shape of the steps when viewed from above surface F2 is not limited to approximately circular; for example, it could also be approximately quadrilateral. In this case, it is easier to correspond to the configuration of the metal pads 14, making the design simpler.

[0043] Furthermore, more specifically, the height of the solder resist 16 opposite the controller chip 30 varies according to each at least one metal pad 14. Figure 2 In the example shown, the solder resist 16 is thinned per metal pad 14. However, it is not limited to this; the solder resist 16 may also be thinned per multiple metal pads 14.

[0044] Solder resist 16 of varying thicknesses can be formed, for example, through a thinning process. For instance, the solder resist 16 coated on the wiring substrate 10 (insulating substrate 11) is exposed, the wiring substrate 10 is immersed in a solution, the solder resist 16 soaked in the solution is removed, and the wiring substrate 10 is cleaned. By repeating this process, a stepped solder resist 16 can be formed. Then, a curing process is performed on the solder resist 16. Furthermore, to increase the number of steps in the solder resist 16, it is sufficient to simply thicken the pre-coated solder resist 16 and repeatedly perform the thinning process. For example, a film-like solder resist 16 with a thickness of approximately 20 μm to approximately 30 μm can be provided before the thinning process to fill the metal pads 14.

[0045] As described above, the height of the solder resist 16 varies depending on its position on the wiring substrate 10. This allows the resin layer 35 to flow easily during the mounting of the controller chip 30. Furthermore, the solder resist 16 gradually decreases in height from the center of the opposing controller chip 30 to its outer periphery. This facilitates the removal of voids V from the resin layer 35. Consequently, for example, it is possible to suppress malfunctions of the controller chip 30 caused by voids V.

[0046] As another method for eliminating gaps, there is a known method of deforming the central portion of a semiconductor chip downwards in a convex spherical shape and mounting the semiconductor chip to a substrate. However, in this case, the deformation of the semiconductor chip may make the connection to the substrate via flip-chip bonding difficult.

[0047] In contrast, in the first embodiment, by changing the thickness of the solder resist 16 to promote the flow of the resin layer 35, the voids V can be discharged without affecting the flip chip connection.

[0048] Alternatively, the controller chip 30 can also be other semiconductor chips connected via flip-chip. The controller chip 30 can also be DRAM (Dynamic Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or NAND flash memory, etc.

[0049] Furthermore, the solder resist 16 does not have an opening 161 through which the insulating substrate 11 is exposed (see reference). Figure 3 The opening 161 is typically a hole formed when the metal pad 14 is exposed from the solder resist 16. The insulating substrate 11 absorbs moisture from the atmosphere. If the insulating substrate 11 is exposed from the solder resist 16, moisture within the insulating substrate 11 can easily enter the resin layer 35 or the voids V within the resin layer 35. In contrast, in the first embodiment, the insulating substrate 11 is at least covered with a thinner layer of solder resist 16 and is not exposed from the solder resist 16. This suppresses the entry of moisture into the resin layer 35. As a result, HAST (High Accelerated Stress Test) tolerance is improved. HAST is one of the insulation evaluation tests used to evaluate moisture resistance.

[0050] (Variation Example 1)

[0051] Figure 3 This is a cross-sectional view showing the wiring substrate 10, resin layer 35, and their surrounding structure in Modified Example 1. Modified Example 1 of the first embodiment differs from the first embodiment in that it has an opening (hole) 161.

[0052] That is, the solder resist 16 has an opening 161 that exposes the insulating substrate 11. As a result, the difference between the minimum and maximum thickness of the solder resist 16 becomes larger. Consequently, the resin layer 35 can flow more easily, and the voids V can be easily discharged.

[0053] The other structures of the semiconductor device 1 in Modified Example 1 are the same as those of the corresponding structure of the semiconductor device 1 in the first embodiment, so detailed descriptions are omitted. The semiconductor device 1 in Modified Example 1 can achieve the same effects as the first embodiment.

[0054] (Variation Example 2)

[0055] Figure 4 This is a cross-sectional view showing the wiring substrate 10, resin layer 35, and their surrounding structure in Modified Example 2. Modified Example 2 of the first embodiment differs from the first embodiment in that the solder resist 16 is made thicker at the outer periphery of the controller chip 30 so that it functions as a dam.

[0056] The wiring substrate 10 also has a protrusion 17 that protrudes from the solder resist 16 toward the outer periphery of the controller chip 30, and whose upper surface height is above the height of the metal pad 14. The protrusion 17 is, for example, made of the same material as the solder resist 16. In this case, the protrusion 17 is integrally formed with the solder resist 16. The protrusion 17 is provided, for example, along the outer periphery of the controller chip 30. The protrusion 17 functions as a dam to block the flowing resin layer 35 at the outer periphery of the controller chip 30. This prevents the resin layer 35 from over-expanding due to excessive flow. Furthermore, the pressure of the resin layer 35 can be increased, which can break the voids V that have moved to the outer periphery of the controller chip 30. Furthermore, the effects of low-molecular-weight compounds seeping (leaking) from the resin layer 35 can be suppressed. Additionally, Figure 4 The protrusion 17 shown is located on the outer side of the controller chip 30 when viewed from above surface F2. However, it is not limited to this; a portion of the protrusion 17 may also be on the inner side of the controller chip 30.

[0057] Furthermore, the thickness of the protrusion 17 (and solder resist 16) can be approximately the same as the thickness of the thickest solder resist 16 below the controller chip 30, such as at the center of the controller chip 30. This further reduces the number of thinning processes.

[0058] The other structures of the semiconductor device 1 in Modified Example 2 are the same as those of the corresponding structure of the semiconductor device 1 in the first embodiment, so detailed descriptions are omitted. The semiconductor device 1 in Modified Example 2 can achieve the same effects as the first embodiment. Furthermore, the semiconductor devices 1 of Modified Example 1 and Modified Example 2 can be combined.

[0059] (Variation Example 3)

[0060] Figure 5 This is a cross-sectional view showing the wiring substrate 10, resin layer 35, and their surrounding structure in Modified Example 3. Modified Example 3 differs from the first embodiment in that the wiring substrate 10 is coated with solder resist multiple times. Furthermore, in... Figure 5 In the example shown, as explained in Variation 2, a protrusion 17 is provided. However, as in the first embodiment, the protrusion 17 may not be provided.

[0061] like Figure 5As shown, the solder resist 16 includes solder resists 16a and 16b. Solder resist 16a is disposed at the lower part of the solder resist 16, and solder resist 16b is disposed at the upper part of the solder resist 16. Solder resists 16a and 16b are made of different materials. For example, the material of solder resist 16a is a material with high reliability, but it is difficult to make thickness adjustments based on thinning processes. On the other hand, the material of solder resist 16b is a material that is easy to make thickness adjustments based on thinning processes. Thus, multiple materials can be used to balance insulation properties and ease of thinning processes. In addition, solder resists 16a and 16b, like solder resist 16, can also be other insulating materials besides solder resists.

[0062] Solder resists 16a and 16b are formed by a thinning process. First, solder resist 16a is applied to the insulating substrate 11 in a manner that buries the metal pads 14. The solder resist 16a is then thinned as a whole by a thinning process, followed by a hardening process. Then, solder resist 16b is applied to the solder resist 16a. Similar to the first embodiment, solder resists 16b of different thicknesses can be formed by a thinning process.

[0063] Alternatively, the same material can be used in solder resists 16a and 16b. That is, it is not necessarily just a thinning process; a step difference in solder resist 16 can also be formed by adding a new solder resist 16.

[0064] The other structures of the semiconductor device 1 in Modified Example 3 are the same as those of the corresponding structure of the semiconductor device 1 in the first embodiment, so detailed descriptions are omitted. The semiconductor device 1 in Modified Example 3 can achieve the same effects as the first embodiment. Furthermore, the semiconductor devices 1 in Modified Examples 1 and 2 can be combined with those in Modified Example 3.

[0065] (Variation Example 4)

[0066] Figure 6 This is a plan view showing an example of the configuration of the metal bumps 31 of the controller chip 30 in Modified Example 4. Modified Example 4 of the first embodiment differs from the first embodiment in that the solder resist 16 is locally thickened.

[0067] R1 represents the area on surface F1 of the controller chip 30 where metal bumps 31 are provided. R2 represents the area on surface F1 of the controller chip 30 where metal bumps 31 are not provided.

[0068] Figure 7A It means Figure 6 A cross-sectional view of the wiring substrate 10 of the A-A' line, the resin layer 35 and their surrounding structure. Figure 7B It means Figure 6 A cross-sectional view of the wiring substrate 10, resin layer 35, and their surrounding structure of the B-B' line. Additionally, in... Figure 7A In the example shown, as explained in Variation 2, a protrusion 17 is provided. However, as in the first embodiment, the protrusion 17 may not be provided.

[0069] The solder resist 16 opposite region R1 of surface F1 is higher than the solder resist 16 opposite region R2 of surface F1 outside region R1. Therefore, as... Figure 7A and Figure 7B As shown, the resin layer 35 can flow from region R1 to region R2. Therefore, the voids V in region R1 can be moved to region R2.

[0070] Furthermore, as described above, region R1 is the region where the metal bumps 31 are provided. Therefore, the gap V can be moved away from the metal bumps 31 and the metal pads 14. Since the gap V may become a leakage path, it is possible to suppress, for example, conduction between adjacent metal pads 14 or between adjacent metal bumps 31.

[0071] Furthermore, more specifically, the solder resist 16 in region R1 thins from the center to the outer periphery of region R1. This allows voids V to be easily expelled from region R1. However, not limited to this, the thickness of the solder resist 16 in region R1 can also be varied in a manner that allows the resin layer 35 to flow in the desired direction.

[0072] Alternatively, region R1 can also be a region with metal bumps 31 through which power supply signals pass. Figure 6 In the example shown, the central region R1 and the peripheral region R1 can also be designated as region R2. The metal bumps 31 in the peripheral region R1 include, for example, signal electrodes. These signal electrodes are used for transmitting and receiving signals between the wiring substrate 10 and the controller chip 30. Signal electrodes are sometimes positioned on the outer periphery of the controller chip 30 to shorten signal wiring. On the other hand, the metal bumps 31 in the central region R1 include, for example, power electrodes and ground electrodes. The power electrodes are connected to power wiring within the wiring substrate 10. The ground electrodes are connected to ground wiring within the wiring substrate 10. For example, even if a gap V exists between the ground electrodes as a leakage path, it has almost no effect on the operation of the controller chip 30. However, if a gap V exists between the signal electrodes, it may affect the operation of the controller chip 30. Therefore, it is possible to make the solder resist 16 only thicker near the metal bumps 31 that serve as signal electrodes.

[0073] The other structures of the semiconductor device 1 in Modification 4 are the same as those of the corresponding structure of the semiconductor device 1 in the first embodiment, so detailed descriptions are omitted. The semiconductor device 1 in Modification 4 can achieve the same effects as the first embodiment. Furthermore, the semiconductor devices 1 in Modifications 1 to 3 can be combined with those in Modification 4.

[0074] (Second Implementation)

[0075] Figure 8 This is a cross-sectional view showing a structural example of the wiring substrate 10 and its surrounding area according to the second embodiment. The second embodiment differs from the first embodiment in that the solder resist 16 gradually thickens from the center to the outer periphery.

[0076] Figure 8 For example, a cross-sectional view showing the wiring substrate 10 and the controller chip 30 in a flip-chip connection based on a mass reflow method. Figure 8 In the example shown, after flip chip bonding, a resin layer 35 (not shown) is supplied. The resin layer 35, for example, is an underfill material that enters between the wiring substrate 10 and the controller chip 30, covering the area around the metal bumps 31. Furthermore, since the resin layer 35 is filled while flowing, voids V are less likely to form within it. Additionally, the heights of the plurality of electrode posts 32 are, for example, approximately constant. The heights of the plurality of metal pads 14 are, for example, approximately constant. The amount of the plurality of metal bumps 31 (brazing) is, for example, approximately constant.

[0077] also, Figure 8 The controller chip shown is warped in a convex manner. This is because it is heated during flip-chip bonding.

[0078] Typically, the controller chip 30 warps upwards at room temperature and downwards at the high temperatures (e.g., above 240°C) during flip-chip bonding. This is because the silicon layer on the F2 side is less prone to expansion, while the device layer on the F1 side, including PI (polyimide) and copper, is more prone to expansion. When the controller chip 30 warps downwards, the electrode posts 32 located on the outer periphery of the controller chip 30 may become difficult to connect to the metal pads 14 due to their greater distance from the pads.

[0079] Therefore, as Figure 8As shown, the thickness of the solder resist 16 varies depending on its position on the wiring substrate 10. More specifically, the solder resist 16 gradually increases in thickness from the center of the opposing controller chip 30 to its outer periphery. Below the center of the controller chip 30, the solder resist 16 is thinner, and the sides of the metal pads 14 are exposed. Therefore, the metal bumps 31 wet the sides of the metal pads 14. On the other hand, below the outer periphery of the controller chip 30, the solder resist 16 is thicker, and the sides of the metal pads 14 are covered by the solder resist 16. Therefore, the metal bumps 31 do not wet the sides of the metal pads 14. Furthermore, at the connection between the metal bumps 31 and the metal pads 14, the solder resist 16 prevents them from sticking. As a result, the metal bumps 31 can easily remain in the area between the metal pads 14 and the electrode posts 32. Consequently, even if the metal pads 14 and the electrode posts 32 separate, the connection can be made more stable. That is, it can suppress the insufficiency of metal bump 31 caused by metal bump 31 wetting the side of metal pad 14.

[0080] Alternatively, the maximum height of the solder resist 16 opposite the controller chip 30 can be greater than the height of the metal pad 14. That is, the solder resist 16 can also be thicker than the metal pad 14. This allows the metal bump 31 to be pushed upwards while maintaining the connection between the upper surface of the metal pad 14 and the metal bump 31. As a result, the connection between the metal pad 14 and the electrode post 32 can be made more stable.

[0081] More specifically, the solder resist 16 is set to a height corresponding to the warpage of the controller chip 30 when connected to the wiring substrate 10. The magnitude of the warpage of the controller chip 30 can be predicted in advance, for example, based on the generation of the controller chip 30, the chip size, and the position of the metal bump 31 relative to the controller chip 30. Alternatively, there may be a case where the difference between the maximum and minimum values ​​of the solder resist 16 thickness is greater than the warpage of the controller chip 30. In this case, the thickness of the solder resist 16 only needs to be set to vary within the range between the maximum and minimum values.

[0082] In addition, Figure 8 In the example shown, the solder resist 16 has an opening 161. This allows for a smaller minimum thickness (approximately zero) of the solder resist 16. Consequently, the solder resist 16 can be easily made to correspond to the warp of the controller chip 30.

[0083] The other structures of the semiconductor device 1 in the second embodiment are the same as the corresponding structures of the semiconductor device 1 in the first embodiment, so detailed descriptions are omitted.

[0084] (Variation Example 5)

[0085] Figure 9This is a cross-sectional view showing the wiring substrate 10 and its surrounding structure in Modified Example 5. Modified Example 5 of the Second Embodiment differs from the Second Embodiment in that it does not have an opening 161.

[0086] That is, the solder resist 16 does not have an opening 161 that exposes the insulating substrate 11 through the solder resist 16. In this case, as described in the first embodiment, HAST tolerance can be improved.

[0087] The other structures of the semiconductor device 1 in Modification 5 are the same as those of the corresponding structure of the semiconductor device 1 in the second embodiment, so detailed descriptions are omitted. The semiconductor device 1 in Modification 5 can achieve the same effects as the second embodiment.

[0088] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: A wiring substrate has an insulating element and pads exposed from the insulating element and electrically connected to wiring disposed on the insulating substrate; A semiconductor chip has bumps on a first surface of the wiring substrate that are connected to the pads; and A resin layer covers the area around the bumps between the wiring substrate and the semiconductor chip. The aforementioned semiconductor chip has a first region located near the center of the semiconductor chip, a second region located outside the first region, a third region located outside the second region, and a fourth region located outside the third region. The height of the insulating member opposite to the first region, the second region, the third region and the fourth region is as follows: it decreases from the first region toward the second region, increases from the second region toward the third region, and decreases from the third region toward the fourth region.

2. The semiconductor device of claim 1, wherein, The insulating member opposite to the first region gradually decreases in height from the center to the outer periphery of the first region. The insulating member opposite to the third region gradually decreases in height from the center of the third region to the ends of the second and fourth regions.

3. The semiconductor device as claimed in claim 1, wherein, The insulating member opposite to the first region and the third region is higher than the insulating member opposite to the second region and the fourth region.

4. The semiconductor device of claim 3, wherein, The first region and the third region mentioned above are regions where the aforementioned protrusions are provided.

5. The semiconductor device of claim 3, wherein, The first region and the third region mentioned above are regions where the aforementioned protrusions are provided for the passage of power supply signals.

6. The semiconductor device according to any one of claims 2 to 5, wherein, The aforementioned wiring substrate also has a protrusion that protrudes from the aforementioned insulating member toward the outer periphery of the aforementioned semiconductor chip, and the height of the upper surface is greater than the height of the aforementioned pad.

7. The semiconductor device according to any one of claims 2 to 5, wherein, The maximum height of the insulating member opposite the semiconductor chip is less than or equal to the height of the pad.

8. The semiconductor device of claim 1, wherein, When the height of the insulating member opposite the first region of the semiconductor chip is defined as a first height, and the height of the insulating member opposite the second region of the semiconductor chip is defined as a second height, When the distance between the semiconductor chip in the first region and the wiring substrate is defined as a first distance, and the distance between the semiconductor chip in the second region and the wiring substrate is defined as a second distance, The first distance mentioned above is smaller than the second distance mentioned above, and the first height mentioned above is higher than the second height mentioned above.

9. The semiconductor device of claim 8, wherein, The aforementioned insulating element also has a protrusion in the region opposite to the aforementioned semiconductor chip that is higher than the height of the aforementioned pad.

10. The semiconductor device of claim 8, wherein, The aforementioned insulating element also has a protrusion on the outer side of the aforementioned fourth region that is higher than the height of the aforementioned pad.

11. The semiconductor device of claim 1, wherein, The aforementioned insulating member covers the entire area of ​​the wiring substrate opposite to the semiconductor chip, except for the openings of the plurality of pad openings.

12. The semiconductor device of claim 1, wherein, The height of the insulating material surrounding the aforementioned pads is approximately constant.

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