Three-dimensional structure ternary content addressable memory

Abstract

The present invention discloses a three-dimensional structure ternary content addressable memory, which includes a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer is arranged on a first plane and extends along a first direction parallel to the first plane. The second transistor layer is arranged on the first plane, parallel to the first transistor layer, and extends along the first direction. The third transistor layer is stacked on the first transistor layer in a second direction perpendicular to the first plane. The fourth transistor layer is stacked on the second transistor layer in the second direction. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first storage unit of the ternary content addressable memory. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second storage unit of the ternary content addressable memory.

Description

Technical Field

[0001] The invention relates to a three-dimensional ternary content addressable memory. Background Art

[0002] Ternary Content-Addressable Memory (TCAM) is a memory that can store three states (e.g., 0, 1, and the third state). TCAM can be applied to complex routing and big data that do not require precise matching searches. With the development of data science, the application of TCAM is becoming more and more extensive. In view of the increasing demand for TCAM, the circuit layout of TCAM will be one of the focuses of industry research. Summary of the invention

[0003] One aspect of the present invention discloses a three-dimensional structure ternary content addressable memory, which includes a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer is arranged on a first plane and extends along a first direction parallel to the first plane. The second transistor layer is arranged on the first plane, parallel to the first transistor layer, and extends along the first direction. The third transistor layer is stacked on the first transistor layer in a second direction perpendicular to the first plane. The fourth transistor layer is stacked on the second transistor layer in the second direction. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first storage unit of the ternary content addressable memory. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second storage unit of the ternary content addressable memory.

[0004] Another aspect of the present invention discloses a three-dimensional structure ternary content addressable memory, which includes a first transistor channel layer, a second transistor channel layer, a third transistor channel layer and a fourth transistor channel layer. The first transistor channel layer is arranged on a first plane and extends along a first direction parallel to the first plane. The second transistor channel layer is arranged on the first plane, parallel to the first transistor layer, and extends along the first direction. The third transistor channel layer is stacked on the first transistor channel layer in a second direction perpendicular to the first plane. The fourth transistor channel layer is stacked on the second transistor channel layer in the second direction. The first transistor channel layer and the third transistor channel layer belong to a first transistor of a storage unit of the ternary content addressable memory. The second transistor channel layer and the fourth transistor channel layer belong to a second transistor of a storage unit of the ternary content addressable memory.

[0005] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of a portion of a ternary content addressable memory (TCAM) according to an embodiment of the present invention is shown.

[0007] Figure 2 A block diagram of three memory cells according to an embodiment of the present invention is shown.

[0008] Figure 3 FIG. 4 is a schematic diagram showing a portion of a TCAM structure according to an embodiment of the present invention.

[0009] Figure 4A A schematic diagram of a cross section at line AA' is shown.

[0010] Figure 4B , 4C The diagram shows how the cross section at line AA' changes.

[0011] Figure 5 FIG. 4 is a schematic diagram showing a portion of a TCAM structure according to another embodiment of the present invention.

[0012] Figure 6 FIG. 4 is a schematic diagram showing a portion of a TCAM structure according to yet another embodiment of the present invention.

[0013] Fig. 7A A schematic diagram of the cross section at line BB' is shown.

[0014] Figures 7B to 7D The diagram shows how the cross section changes at line BB'.

[0015] Fig. 8A FIG. 4 is a schematic diagram showing a portion of a TCAM structure according to yet another embodiment of the present invention.

[0016] Figure 8B Draw Fig. 8A Block diagram of the equivalent circuit of a memory cell.

[0017]

Explanation of symbols

[0018] 10: Ternary Content Addressable Memory

[0019] 102-11~102-33: Storage unit

[0020] T1-11~T1-31, T1: first transistor

[0021] T2-11~T2-31, T2: The second transistor

[0022] R1-11~R1-31: First storage element

[0023] R2-11~R2-31: Second storage element

[0024] ML: Match Line

[0025] BL: Bit Line

[0026] ML1: First Match Line

[0027] ML2: Second matching line

[0028] ML3: Third Match Line

[0029] BL1: First line

[0030] BL2: Second bit line

[0031] BL3: Third bit line

[0032] SL1-1, SL1: First search line

[0033] SL2-1, SL2: Second search line

[0034] SLc: Common Search Line

[0035] SLc-1: First common search line

[0036] SLc-2: Second common search line

[0037] GO: Gate Oxide

[0038] FL: Ferroelectric layer

[0039] C1~C16: Connecting material DETAILED DESCRIPTION

[0040] Please refer to Figure 1 , Figure 1 A block diagram of a portion of a ternary content addressable memory (TCAM) according to an embodiment of the present invention is shown. TCAM 10 may include a plurality of storage units 102-11 to 102-33. The details of each storage unit may be referred to in Figure 2 , Figure 2A block diagram of three memory cells 102-11, 102-21, and 102-31 of the TCAM 10 is shown. Each memory cell includes a first transistor, a second transistor, a first storage element, a second element, a first search line, a second search line, a match line, and a bit line. Taking the memory cell 102-11 as an example, the memory cell 102-11 includes a first transistor T1-11, a second transistor T2-11, a first storage element R1-11, a second storage element R2-11, a first search line SL1-1, a second search line SL2-1, a match line ML1, and a bit line BL1. A first end of the first transistor T1-11 is coupled to the match line ML1 through the first storage element R1-11. A second end of the first transistor T1-11 is coupled to the bit line BL1. A control end of the first transistor T1-11 is coupled to the first search line SL1-1. A first end of the second transistor T2-11 is coupled to the match line ML1 through the second storage element R2-11. A second end of the second transistor T2-11 is coupled to the bit line BL1. A control end of the second transistor T2-11 is coupled to the second search line SL2-1, wherein the signal on the second search line SL2-1 is the inverse of the signal on the first search line SL1-1, that is, when the signal on the first search line SL1-1 is 0, the signal on the second search line SL2-1 is 1; when the signal on the first search line SL1-1 is 1, the signal on the second search line SL2-1 is 0. The memory cells 102-21 and 102-31 are similar to the memory cell 102-11, however, it should be noted that the memory cells 102-11, 102-21, and 102-31 are memory cells belonging to different rows, and therefore do not share match lines and bit lines.

[0041] In this embodiment, the first transistor and the second transistor may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a stacked-nanowire, a stacked-nanosheet, a stacked-finFET, a stacked-forksheet, a stacked junctionless FET (JL-FET), a stacked ferroelectric transistor (stacked FeFET), etc. The first transistor and the second transistor may be both N-type or P-type. The first storage element and the second storage element are variable resistance memory, such as transition metal oxide (TMO) ReRAM, phase-change memory (PCRAM), conduction bridge RAM, spin-transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, ferroelectric tunnel junction (FTJ), ferroelectric memory (FeRAM), etc. That is, each of the first storage element and the second storage element can have a high resistance state and a low resistance state. Each memory cell stores data by a combination of the high resistance state and the low resistance state of the first storage element and the second storage element.

[0042] In conventional technology, TCAM is a two-dimensional array for integrated circuit layout. In order to further save area, the present invention proposes a three-dimensional stacked layout TCAM structure. Figure 3 , Figure 3 FIG. 4 is a schematic diagram of a portion of a TCAM structure according to an embodiment of the present invention. Figure 3 The picture shows Figure 2The circuit layout of the three memory cells in the embodiment. The first transistor T1-11 and the second transistor T2-11 of the first memory cell 102-11 are arranged on a first plane PL1. In one embodiment, the first transistor T1-11 and the second transistor T2-11 of the first memory cell 102-11 extend along a first direction DR1 parallel to the first plane PL1 and are parallel to each other. The first transistor T1-21 and the second transistor T2-21 of the second memory cell 102-21 are stacked on the first transistor T1-11 and the second transistor T2-11 of the first memory cell 102-11 in a second direction DR2 perpendicular to the first plane PL1, respectively. In one embodiment, the first transistor T1-21 and the second transistor T2-21 of the second memory cell 102-21 extend along the first direction DR1 and are parallel to each other. The first transistor T1-31 and the second transistor T2-31 of the third storage unit 102-31 are stacked on the first transistor T1-21 and the second transistor T2-21 of the second storage unit 102-21 in the second direction DR2. In one embodiment, the first transistor T1-31 and the second transistor T2-31 of the third storage unit 102-31 extend along the first direction DR1 and are parallel to each other. The first transistor T1-11 of the first storage unit 102-11, the first transistor T1-21 of the second storage unit 102-21, and the first transistor T1-31 of the third storage unit 102-31 run through the first search line SL1-1. The first transistor T1-11 of the first storage unit 102-11, the first transistor T1-21 of the second storage unit 102-21, and the first transistor T1-31 of the third storage unit 102-31 are connected to the first search line SL1-1 through a gate oxide GO. The second transistor T2-11 of the first storage unit 102-11, the second transistor T2-21 of the second storage unit 102-21, and the second transistor T2-31 of the third storage unit 102-31 run through the second search line SL2-1. The second transistor T2-11 of the first storage unit 102-11, the second transistor T2-21 of the second storage unit 102-21, and the second transistor T2-31 of the third storage unit 102-31 are connected to the second search line SL2-1 through a gate oxide GO, respectively. A first connecting material C1 is disposed at the first end of the first transistor T1-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first matching line ML1 through the first storage element R1-11. A second connecting material C2 is disposed at the second end of the first transistor T1-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first bit line BL1. A third connecting material C3 is disposed at the first end of the first transistor T1 - 21 of the second storage unit 102 - 21 , extends along the second direction, and is connected to the second matching line ML2 through the first storage element R1 - 21 .A fourth connection material C4 is disposed at the second end of the first transistor T1-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second bit line BL2. A fifth connection material C5 is disposed at the first end of the first transistor T1-31 of the third storage unit 102-31, extends along the second direction, and is connected to the third match line ML3 through the first storage element R1-31. A sixth connection material C6 is disposed at the second end of the first transistor T1-31 of the third storage unit 102-31, extends along the second direction, and is connected to the third bit line BL3. A seventh connection material C7 is disposed at the first end of the second transistor T2-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first match line ML1 through the second storage element R2-11. An eighth connection material C8 is disposed at the second end of the second transistor T2-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first bit line BL1. A ninth connecting material C9 is disposed at a first end of the second transistor T1-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second match line ML2 through the second storage element R2-21. A tenth connecting material C10 is disposed at a second end of the second transistor T2-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second bit line BL2. An eleventh connecting material C11 is disposed at a first end of the second transistor T2-31 of the third storage unit 102-31, extends along the second direction, and is connected to the third match line ML3 through the second storage element R2-31. A twelfth connecting material C12 is disposed at a second end of the second transistor T2-31 of the third storage unit 102-31, extends along the second direction, and is connected to the third bit line BL3.

[0043] Please refer to Figure 4A , Figure 4A Draw Figure 3 In this embodiment, each first transistor has one channel connected to the first search line, and the channel type is gate-all around (GAA). In another embodiment, each first transistor may have two (or more) channels connected to the first search line, such as Figure 4B In another embodiment, the first transistors may also be a combination of a tri-gate FET and a gate full-ring FET, such as Figure 4C The same is true for the second transistor.

[0044] It should be noted that although the above embodiment is described with three transistors stacked, the present invention is not limited thereto. Any TCAM structure that stacks two or more transistors in three dimensions falls within the scope of the present invention.

[0045] Please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a portion of a TCAM structure according to another embodiment of the present invention. Figure 3 The embodiment is similar to the embodiment of the present invention, except that the doping type of the first transistors T1-11, T1-21, T1-31 is different from the doping type of the second transistors T2-11, T2-21, T2-31. For example, the first transistors T1-11, T1-21, T1-31 are N-type, while the second transistors T2-11, T2-21, T2-31 are P-type. Since the first transistors T1-11, T1-21, T1-31 and the second transistors T2-11, T2-21, T2-31 are different types of transistors, they can share a search line, that is, the first search line SL1-1 and the second search line SL2-1 can be integrated into a common search line SLc-1. Compared to Figure 3 This embodiment can further save the area of ​​circuit layout.

[0046] Please refer to Figure 6 , Figure 6 FIG. 4 is a schematic diagram of a portion of a TCAM structure according to another embodiment of the present invention. Figure 6 The structure shown includes Figure 1 The memory cells 102-11, 102-21, 102-12, and 102-22 in FIG. The detailed circuit of each memory cell can be referred to Figure 2 In this embodiment, the doping type of the first transistors T1-11, T1-21, T1-12, T1-22 is different from the doping type of the second transistors T2-11, T2-21, T2-21, T2-22. For example, the first transistors T1-11, T1-21, T1-12, T1-22 are N-type, and the second transistors T2-11, T2-21, T2-12, T2-22 are P-type. Therefore, the first transistor T1-11, the second transistor T2-11 of the first memory cell 102-11 and the first transistor T1-21, the second transistor T2-21 of the second memory cell 102-21 can share a first common search line SLc-1, and the first transistor T1-12, the second transistor T2-12 of the third memory cell 102-12 and the first transistor T1-22, the second transistor T2-22 of the fourth memory cell 102-22 can share a second common search line SLc-2.

[0047] The first transistor T1-11 of the first memory cell 102-11 and the first transistor T1-12 of the third memory cell 102-12 are disposed on a first plane PL1. In one embodiment, the first transistor T1-11 of the first memory cell 102-11 and the first transistor T1-12 of the third memory cell 102-12 extend along a first direction DR1 parallel to the first plane PL1 and are parallel to each other. The second transistor T2-11 of the first memory cell 102-11 and the second transistor T2-12 of the third memory cell 102-12 are stacked on the first transistor T1-11 of the first memory cell 102-11 and the first transistor T1-12 of the third memory cell 102-12 in a second direction DR2 perpendicular to the first plane PL1, respectively. In one embodiment, the second transistor T2-11 of the first memory cell 102-11 and the second transistor T2-12 of the third memory cell 102-12 extend along the first direction DR1 and are parallel to each other. The first transistor T1-21 of the second memory cell 102-21 and the first transistor T1-22 of the fourth memory cell 102-22 are stacked on the second transistor T2-11 of the first memory cell 102-11 and the second transistor T1-22 of the third memory cell 102-12 in a second direction DR2 perpendicular to the first plane PL1. In one embodiment, the first transistor T1-21 of the second memory cell 102-21 and the first transistor T1-22 of the fourth memory cell 102-22 extend along the first direction DR1 and are parallel to each other. The second transistor T2-21 of the second memory cell 102-21 and the second transistor T2-22 of the fourth memory cell 102-22 are stacked on the first transistor T1-21 of the second memory cell 102-21 and the first transistor T1-22 of the fourth memory cell 102-22 in a second direction DR2 perpendicular to the first plane PL1. In one embodiment, the second transistor T2 - 21 of the second memory cell 102 - 21 and the second transistor T2 - 22 of the fourth memory cell 102 - 22 extend along the first direction DR1 and are parallel to each other.

[0048] The first transistor T1-11, the second transistor T2-11 of the first storage unit 102-11, the first transistor T1-21, the second transistor T2-21 of the second storage unit 102-21 run through the first common search line SLc-1. The first transistor T1-11, the second transistor T2-11 of the first storage unit 102-11, the first transistor T1-21, the second transistor T2-21 of the second storage unit 102-21 are connected to the first common search line SLc-1 through a gate oxide GO respectively. The first transistor T1-12, the second transistor T2-12 of the third storage unit 102-12, the first transistor T1-22, the second transistor T2-22 of the fourth storage unit 102-22 run through the second common search line SLc-2. The first transistor T1-12 and the second transistor T2-12 of the third storage unit 102-12, the first transistor T1-22 and the second transistor T2-22 of the fourth storage unit 102-22 are respectively connected to the second common search line SLc-2 through a gate oxide GO.

[0049] A first connection material C1 is disposed at a first end of the first transistor T1-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first match line ML1 through the first storage element R1-11. A second connection material C2 is disposed at a second end of the first transistor T1-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first match line ML1. A third connection material C3 is disposed at a first end of the second transistor T2-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first match line ML1 through the second storage element R2-11. A fourth connection material C4 is disposed at a second end of the second transistor T2-11 of the first storage unit 102-11, extends along the second direction, and is connected to the first match line ML1. A fifth connection material C5 is disposed at a first end of the first transistor T1-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second match line ML2 through the first storage element R1-21. A sixth connection material C6 is disposed at the second end of the first transistor T1-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second bit line BL2. A seventh connection material C7 is disposed at the first end of the second transistor T2-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second match line ML2 through the second storage element R2-21. An eighth connection material C8 is disposed at the second end of the second transistor T2-21 of the second storage unit 102-21, extends along the second direction, and is connected to the second bit line BL2. A ninth connection material C9 is disposed at the first end of the first transistor T1-12 of the third storage unit 102-12, extends along the second direction, and is connected to the first match line ML1 through the first storage element R1-12. A tenth connection material C10 is disposed at the second end of the first transistor T1-12 of the third storage unit 102-12, extends along the second direction, and is connected to the first bit line BL1. An eleventh connecting material C11 is disposed at a first end of the second transistor T2-12 of the third storage unit 102-12, extends along the second direction, and is connected to the first match line ML1 through the second storage element R2-12. A twelfth connecting material C12 is disposed at a second end of the second transistor T2-12 of the third storage unit 102-12, extends along the second direction, and is connected to the first bit line BL1. A thirteenth connecting material C13 is disposed at a first end of the first transistor T1-22 of the fourth storage unit 102-22, extends along the second direction, and is connected to the second match line ML2 through the first storage element R1-22. A fourteenth connecting material C14 is disposed at a second end of the first transistor T1-22 of the fourth storage unit 102-22, extends along the second direction, and is connected to the second bit line BL2.A fifteenth connecting material C15 is disposed at the first end of the second transistor T2-22 of the fourth memory cell 102-22, extends along the second direction, and is connected to the second match line ML2 through the second memory element R2-22. A sixteenth connecting material C16 is disposed at the second end of the second transistor T2-22 of the fourth memory cell 102-22, extends along the second direction, and is connected to the second bit line BL2.

[0050] In this embodiment, the first transistor and the second transistor of the same memory cell can be stacked in the same stack. In addition, the memory cells in the same column can also be stacked in the same stack because they can share a common search line.

[0051] Please refer to Fig. 7A , Fig. 7A The picture shows Figure 6 The first transistor T1-11 and the second transistor T2-11 of the first memory cell 102-11 and the first transistor T1-21 and the second transistor T2-21 of the second memory cell 102-21 are stacked in sequence from bottom to top, and the doping types of the transistors can be N, P, N, P in sequence from bottom to top. In another embodiment, Figure 7B As shown, the doping types of the first transistor T1-11, the second transistor T2-11 of the first memory cell 102-11 and the first transistor T1-21, the second transistor T2-21 of the second memory cell 102-21 may be P, N, P, N in sequence from bottom to top, or as shown in FIG. Figure 7C N, P, P, N as shown, or Fig.7D P, N, N, P shown.

[0052] Please refer to Fig. 8A , Fig. 8A FIG. 4 is a schematic diagram of a portion of a TCAM structure according to another embodiment of the present invention. Fig. 8A The structure shown includes only a single storage unit. Figure 8BAs shown, this memory cell includes a first transistor T1, a second transistor T2, a first search line SL1, a second search line SL2, a matching line ML and a bit line BL. Since the first transistor T1 and the second transistor T2 are ferroelectric gate field-effect transistors (FeFET), the first transistor T1 and the second transistor T2 themselves can be used as memory elements. In this embodiment, the first transistor T1 and the second transistor T2 both include three channel layers. A first channel layer L1-1 of the first transistor T1 and a first channel layer L1-2 of the second transistor T2 are disposed on a first plane PL1. In one embodiment, the first channel layer L1-1 of the first transistor T1 and the first channel layer L1-2 of the second transistor T2 extend along a first direction DR1 parallel to the first plane PL1 and are parallel to each other. The second channel layer L2-1 of the first transistor T1 and the second channel layer L2-2 of the second transistor T2 are stacked on the first channel layer L1-1 of the first transistor T1 and the first channel layer L1-2 of the second transistor T2 in a second direction DR2 perpendicular to the first plane PL1. In one embodiment, the second channel layer L2-1 of the first transistor T1 and the second channel layer L2-2 of the second transistor T2 extend along the first direction DR1 and are parallel to each other. The third channel layer L3-1 of the first transistor T1 and the third channel layer L3-2 of the second transistor T2 are stacked on the second channel layer L2-1 of the first transistor T1 and the second channel layer L2-1 of the second transistor T2 in a second direction DR2 perpendicular to the first plane PL1. In one embodiment, the third channel layer L3-1 of the first transistor T1 and the third channel layer L3-2 of the second transistor T2 extend along the first direction DR1 and are parallel to each other. The first channel layer L1-1, the second channel layer L2-1 and the third channel layer L3-1 of the first transistor T1 run through the first search line SL1 together, and are connected to the first search line SL1 through a gate oxide GO and a ferroelectric material layer FL respectively. The first channel layer L1-2, the second channel layer L2-2 and the third channel layer L3-2 of the second transistor T2 run through the second search line SL2 together, and are connected to the second search line SL2 through a gate oxide GO and a ferroelectric material layer FL respectively. A first end of the first channel layer L1-1, a first end of the second channel layer L2-1 and a first end of the third channel layer L3-1 of the first transistor T1 and a first end of the first channel layer L1-2, a first end of the second channel layer L2-2 and a first end of the third channel layer L3-2 of the second transistor T2 are respectively provided with a connecting material C1, C3, C5, C7, C9, C11, and each connecting material C1, C3, C5, C7, C9, C11 extends along the second direction and is connected to the matching line ML.A second end of the first channel layer L1-1 of the first transistor T1, a second end of the second channel layer L2-1, and a second end of the third channel layer L3-1, and a second end of the first channel layer L1-2 of the second transistor T2, a second end of the second channel layer L2-2, and a second end of the third channel layer L3-2 are respectively provided with a connecting material C2, C4, C6, C8, C10, C12, and each connecting material C2, C4, C6, C8, C10, C12 extends along the second direction and is connected to the bit line BL.

[0053] In this embodiment, a plurality of channel layers of the first transistor and the second transistor are stacked along the second direction. Such a stacking structure can increase the leakage rate of the memory cell. In other words, when searching for data stored in the TCAM, the search result can be obtained more quickly.

[0054] In the above embodiments, the first plane PL1 is, for example, located on a surface of a substrate (not shown). In addition, each connecting material can be a conductive metal or other conductive material that can transmit electrical signals. Figures 3 to 7D The transistor in the transistor layer can also be called a transistor layer or a channel layer of the transistor. In addition, the cross section of each transistor (or transistor layer, channel layer of the transistor) (e.g. Figures 4A to 4C , the cross-section shown in 7A to 7D) can be any shape, such as square, rectangle, trapezoid, diamond, circle, ellipse, triangle, etc., and the cross-sectional shapes of different transistors may be different.

[0055] It should be noted that in the schematic diagrams of the above-mentioned three-dimensional TCAM structures, only the parts related to the present invention are drawn. For example, in the actual structure, an insulating layer may be provided between the stacked transistors, but it is not drawn in the figure. In other words, the structure of the present invention may include any functional or semiconductor process inherent layer.

[0056] In summary, although the present invention has been disclosed by way of embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the appended claims.

Claims

1. A three-dimensional ternary content addressable memory, comprising: A first transistor layer, disposed on a first plane and extending along a first direction parallel to the first plane; a second transistor layer, disposed on the first plane, parallel to the first transistor layer, and extending along the first direction; a third transistor layer, stacked on the first transistor layer in a second direction perpendicular to the first plane; as well as a fourth transistor layer, stacked on the second transistor layer in the second direction, wherein two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first storage unit of the ternary content addressable memory, and another two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second storage unit of the ternary content addressable memory; Wherein, two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first storage unit of the ternary content addressable memory, specifically comprising: The first transistor and the second transistor are respectively a first transistor and a second transistor of the first memory cell; or The third transistor and the fourth transistor are respectively a first transistor and a second transistor of the first memory cell; or When the doping types of the first transistor and the third transistor are different, the first transistor and the third transistor are respectively a first transistor and a second transistor of the first memory cell; or When the doping types of the second transistor and the fourth transistor are different, the second transistor and the fourth transistor are respectively a first transistor and a second transistor of the first memory cell.

2. The three-dimensional structure ternary content addressable memory according to claim 1, wherein the first transistor layer is the first transistor of the first storage unit, the second transistor layer is the second transistor of the first storage unit, the third transistor layer is the first transistor of the second storage unit, and the fourth transistor layer is the second transistor of the second storage unit. The first transistor layer and the third transistor layer jointly penetrate a first search line and are respectively connected to the first search line through a gate oxide. The second transistor layer and the fourth transistor layer jointly penetrate a second search line and are respectively connected to the second search line through a gate oxide. 3 . The three-dimensional structure ternary content addressable memory as claimed in claim 2 , wherein the doping types of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are all N-type or P-type.

4. The three-dimensional structure ternary content addressable memory according to claim 1, wherein the first transistor layer is the first transistor of the first storage unit, the third transistor layer is the second transistor of the first storage unit, the second transistor layer is the first transistor of the second storage unit, and the fourth transistor layer is the second transistor of the second storage unit. The first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer all run through a common search line and are respectively connected to the common search line through a gate oxide.

5. The three-dimensional ternary content addressable memory according to claim 4, further comprising: A first connecting material is disposed at a first end of the first transistor layer, extends along the second direction, and is connected to a first matching line through a first storage element belonging to the first storage unit; A second connecting material is disposed at a second end of the first transistor layer, extends along the second direction, and is connected to a first bit line; a third connecting material, disposed at a first end of the third transistor layer, extending along the second direction, and connected to the first matching line through a second storage element belonging to the first storage unit; a fourth connecting material, disposed at a second end of the third transistor layer, extending along the second direction, and connected to the first bit line; a fifth connecting material, disposed at a first end of the second transistor layer, extending along the second direction, and connected to a second matching line through a third storage element belonging to the second storage unit; a sixth connecting material, disposed at a second end of the second transistor layer, extending along the second direction, and connected to a second bit line; a seventh connecting material, disposed at a first end of the fourth transistor layer, extending along the second direction, and connected to the second matching line through a fourth storage element belonging to the second storage unit; as well as An eighth connecting material is disposed at a second end of the fourth transistor layer, extends along the second direction, and is connected to the second bit line.

6. The three-dimensional structure ternary content addressable memory according to claim 1, wherein the first transistor layer is the first transistor of the first memory cell, the third transistor layer is the second transistor of the first memory cell, the second transistor layer is the first transistor of the second memory cell, and the fourth transistor layer is the second transistor of the second memory cell. The first transistor layer and the third transistor layer jointly penetrate a first common search line and are respectively connected to the first common search line through a gate oxide. The second transistor layer and the fourth transistor layer jointly penetrate a second common search line and are respectively connected to the second common search line through a gate oxide.

7. The three-dimensional ternary content addressable memory according to claim 6, further comprising: A first connecting material is disposed at a first end of the first transistor layer, extends along the second direction, and is connected to a matching line through a first storage element belonging to the first storage unit; A second connecting material is disposed at a second end of the first transistor layer, extends along the second direction, and is connected to a bit line; a third connecting material, disposed at a first end of the third transistor layer, extending along the second direction, and connected to the matching line through a second storage element belonging to the first storage unit; a fourth connecting material, disposed at a second end of the third transistor layer, extending along the second direction, and connected to the bit line; a fifth connecting material, disposed at a first end of the second transistor layer, extending along the second direction, and connected to the matching line through a third storage element belonging to the second storage unit; a sixth connecting material, disposed at a second end of the second transistor layer, extending along the second direction, and connected to the bit line; a seventh connecting material, disposed at a first end of the fourth transistor layer, extending along the second direction, and connected to the matching line through a fourth storage element belonging to the second storage unit; as well as An eighth connecting material is disposed at a second end of the fourth transistor layer, extends along the second direction, and is connected to the bit line.

8. The three-dimensional structured three-state content addressable memory as described in claim 4 or 6, wherein the doping type of one of the first transistor layer and the third transistor layer is N-type and the doping type of the other is P-type, and the doping type of one of the second transistor layer and the fourth transistor layer is N-type and the doping type of the other is P-type.

9. The three-dimensional structure ternary content addressable memory as claimed in claim 1, wherein the first transistor layer is the first transistor of the first memory cell, the second transistor layer is the second transistor of the first memory cell, the third transistor layer is the first transistor of the second memory cell, and the fourth transistor layer is the second transistor of the second memory cell. The first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer all run through a common search line and are respectively connected to the common search line through a gate oxide.

10. The three-dimensional ternary content addressable memory according to claim 2 or 9, further comprising: A first connecting material is disposed at a first end of the first transistor layer, extends along the second direction, and is connected to a first matching line through a first storage element belonging to the first storage unit; A second connecting material is disposed at a second end of the first transistor layer, extends along the second direction, and is connected to a first bit line; a third connecting material, disposed at a first end of the second transistor layer, extending along the second direction, and connected to the first matching line through a second storage element belonging to the first storage unit; a fourth connecting material, disposed at a second end of the first transistor layer, extending along the second direction, and connected to the first bit line; a fifth connecting material, disposed at a first end of the third transistor layer, extending along the second direction, and connected to a second matching line through a third storage element belonging to the second storage unit; a sixth connecting material, disposed at a second end of the third transistor layer, extending along the second direction, and connected to a second bit line; a seventh connecting material, disposed at a first end of the fourth transistor layer, extending along the second direction, and connected to the second matching line through a fourth storage element belonging to the second storage unit; as well as An eighth connecting material is disposed at a second end of the fourth transistor layer, extends along the second direction, and is connected to the second bit line.

11. The three-dimensional structured three-state content addressable memory as described in claim 9, wherein the doping type of one of the first transistor layer and the second transistor layer is N-type and the doping type of the other is P-type, and the doping type of one of the third transistor layer and the fourth transistor layer is N-type and the doping type of the other is P-type.

12. A three-dimensional ternary content addressable memory, comprising: A first transistor channel layer is disposed on a first plane and extends along a first direction parallel to the first plane; a second transistor channel layer, disposed on the first plane, parallel to the first transistor layer, and extending along the first direction; a third transistor channel layer, stacked on the first transistor channel layer in a second direction perpendicular to the first plane; as well as a fourth transistor channel layer, stacked on the second transistor channel layer in the second direction, The first transistor channel layer and the third transistor channel layer belong to a first transistor of a storage unit of the ternary content addressable memory, and the second transistor channel layer and the fourth transistor channel layer belong to a second transistor of the storage unit of the ternary content addressable memory.

13. The three-dimensional structure three-state content addressable memory as described in claim 12, wherein the first transistor channel layer and the third transistor channel layer jointly penetrate a first search line, and are connected to the first search line through a gate oxide and a ferroelectric material layer respectively, and the second transistor channel layer and the fourth transistor channel layer jointly penetrate a second search line, and are connected to the second search line through a gate oxide and a ferroelectric material layer respectively.

14. The three-dimensional ternary content addressable memory according to claim 12, further comprising: A first connecting material is disposed at a first end of the first transistor channel layer, extends along the second direction, and is connected to a matching line; A second connecting material is disposed at a second end of the first transistor channel layer, extends along the second direction, and is connected to a bit line; A third connecting material is disposed at a first end of the second transistor channel layer, extends along the second direction, and is connected to the matching line; a fourth connecting material, disposed at a second end of the second transistor channel layer, extending along the second direction, and connected to the bit line; a fifth connecting material, disposed at a first end of the third transistor channel layer, extending along the second direction, and connected to the matching line; a sixth connecting material, disposed at a second end of the third transistor channel layer, extending along the second direction, and connected to the bit line; a seventh connecting material, disposed at a first end of the fourth transistor channel layer, extending along the second direction, and connected to the matching line; as well as An eighth connecting material is disposed at a second end of the fourth transistor channel layer, extends along the second direction, and is connected to the bit line.

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