Method for forming a semiconductor structure

Abstract

The present application provides a method for forming a semiconductor structure. The method includes: providing a substrate, where the substrate includes a device region and an auxiliary region; forming a dielectric layer on the surface of the substrate; forming a buffer layer on the surface of the dielectric layer; forming a connection structure in the device region that penetrates through the buffer layer and the dielectric layer; forming an auxiliary trench in the auxiliary region that penetrates through the buffer layer and the dielectric layer and extends into the substrate; forming a magnetic tunnel junction material layer on the sidewalls and bottom of the auxiliary trench and on the surfaces of the buffer layer and the connection structure, and the magnetic tunnel material layer does not fill the auxiliary trench; etching the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure. The buffer layer can improve the quality of the auxiliary trench, thereby improving the position accuracy of the magnetic tunnel junction. In addition, the buffer layer can also improve the uniformity during chemical mechanical polishing of the connection structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three major types: logic, memory, and analog circuits, among which memory devices account for a relatively large proportion in integrated circuit products.

[0003] In memory devices, magnetic random access memory (MRAM) is a non-volatile memory. The so-called "non-volatile" means that the memory can remain intact after the power is turned off. In terms of performance, MRAM not only has the high integration of dynamic random access memory (DRAM), but also has the high-speed read and write capabilities of static random access memory (SRAM), as well as the non-volatility of flash memory (FLASH). At the same time, it can withstand an infinite number of repeated writes, and is a "fully functional" solid-state memory. In addition, because its magnet is inherently radiation-resistant, it has extremely high reliability, and MRAM cells can be easily embedded into logic circuit chips. Therefore, its application prospect is very promising and is expected to dominate the next-generation memory market.

[0004] However, there are still problems such as insufficient position accuracy of the magnetic tunnel junction in the current MRAM formation method. Therefore, it is necessary to provide a more reliable and effective technical solution. Summary of the Invention

[0005] This application provides a method for forming a semiconductor structure, which can improve the accuracy of the position of the formed magnetic tunnel junction.

[0006] This application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a device region and an auxiliary region; forming a dielectric layer on the surface of the substrate; forming a buffer layer on the surface of the dielectric layer; forming a connection structure penetrating through the buffer layer and the dielectric layer in the device region; forming an auxiliary trench penetrating through the buffer layer and the dielectric layer and extending into the substrate in the auxiliary region; forming a magnetic tunnel junction material layer on the sidewalls and bottom of the auxiliary trench and on the surfaces of the buffer layer and the connection structure, the magnetic tunnel material layer not filling the auxiliary trench; etching the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure.

[0007] In some embodiments of this application, the dielectric layer includes an NDC layer on the surface of the substrate and a TEOS layer on the surface of the NDC layer.

[0008] In some embodiments of the present application, the method of forming a connection structure penetrating the buffer layer and the dielectric layer in the device region includes: forming a patterned photoresist on the surface of the buffer layer, and the patterned photoresist defines the position of the connection structure; using the patterned photoresist as a mask to etch the buffer layer and the TEOS layer to form a first trench; exposing the patterned photoresist to the surface of the buffer layer on both sides of a part of the first trench, and etching away the exposed buffer layer and the NDC layer at the bottom of the first trench.

[0009] In some embodiments of the present application, the material of the buffer layer includes nitrogen-rich titanium nitride.

[0010] In some embodiments of the present application, the thickness of the buffer layer is 100 angstroms to 200 angstroms.

[0011] In some embodiments of the present application, the device region of the substrate includes a metal interconnect structure, and the connection structure is electrically connected to the metal interconnect structure.

[0012] In some embodiments of the present application, the magnetic tunnel junction includes a first ferromagnetic layer on the surface of the connection structure, a non-magnetic insulating layer on the surface of the first ferromagnetic layer, and a second ferromagnetic layer on the surface of the non-magnetic insulating layer.

[0013] In some embodiments of the present application, the material of the first ferromagnetic layer includes cobalt, iron, tantalum, etc.; the material of the second ferromagnetic layer includes cobalt, iron, tantalum, etc.

[0014] In some embodiments of the present application, the method of etching the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure includes: forming a patterned photoresist on the surface of the magnetic tunnel junction material layer, and the patterned photoresist defines the position of the magnetic tunnel junction; using the patterned photoresist as a mask to etch the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure.

[0015] In some embodiments of the present application, the method of forming an auxiliary trench penetrating the buffer layer and the dielectric layer and extending into the substrate in the auxiliary region includes: forming a patterned photoresist on the surface of the buffer layer and the connection structure, and the patterned photoresist defines the position of the auxiliary trench; using the patterned photoresist as a mask to etch the buffer layer, the dielectric layer and the substrate to form an auxiliary trench penetrating the buffer layer and the dielectric layer and extending into the substrate.

[0016] A method for forming a semiconductor structure according to the present application forms a buffer layer on the surface of the dielectric layer. The buffer layer can improve the quality of the auxiliary trench, thereby improving the position accuracy of the magnetic tunnel junction. In addition, the buffer layer can also improve the uniformity during chemical mechanical polishing of the connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings detail exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for illustrative and descriptive purposes and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0018] Figure 1 is a flowchart of the method for forming a semiconductor structure according to an embodiment of the present application;

[0019] Figures 2 to 14 is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and without departing from the spirit and scope of the present application, the general principles defined here can be applied to other embodiments and applications. Therefore, the present application is not limited to the shown embodiments, but to the broadest scope consistent with the claims.

[0021] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0022] Figure 1 is a flowchart of the method for forming a semiconductor structure according to an embodiment of the present application.

[0023] Referring Figure 1 as shown, the method for forming a semiconductor structure according to an embodiment of the present application includes:

[0024] Step S110: Provide a substrate, the substrate including a device area and an auxiliary area;

[0025] Step S120: Form a dielectric layer on the surface of the substrate;

[0026] Step S130: Form a buffer layer on the surface of the dielectric layer;

[0027] Step S140: Form a connection structure in the device area that penetrates the buffer layer and the dielectric layer;

[0028] Step S150: Form an auxiliary trench in the auxiliary area that penetrates the buffer layer and the dielectric layer and extends into the substrate;

[0029] Step S160: Form a magnetic tunnel junction material layer on the sidewalls and bottom of the auxiliary trench and on the surfaces of the buffer layer and the connection structure, and the magnetic tunnel material layer does not fill the auxiliary trench;

[0030] Step S170: Etch the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure.

[0031] In the method for forming the semiconductor structure according to the embodiment of the present application, a buffer layer is formed on the surface of the dielectric layer. The buffer layer can improve the quality of the auxiliary trench, thereby improving the position accuracy of the magnetic tunnel junction. In addition, the buffer layer can also improve the uniformity during chemical mechanical polishing of the connection structure.

[0032] Figures 2 to 12 FIG. is a schematic structural diagram of each step in the method for forming the semiconductor structure according to the embodiment of the present application. The method for forming the semiconductor structure according to the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0033] Reference Figure 2 , Step S110, provide a substrate 200, the substrate 200 includes a device area 201 and an auxiliary area 202. The device area 201 is used to form active devices, such as metal interconnect structures, magnetic tunnel junctions, etc. The auxiliary area 202 is used to form an auxiliary trench, and the auxiliary trench is used as an etching mark to improve the etching accuracy when etching to form a magnetic tunnel junction. The position of the auxiliary area 202 can be arbitrary, as long as the auxiliary area 202 can be used as an etching mark for the etching process of the device area 201.

[0034] In some embodiments of the present application, in order to improve the area utilization rate of the substrate 200 and reduce the overall size of the substrate 200, the auxiliary area 202 may be adjacent to the device area 201.

[0035] In some embodiments of the present application, the substrate 200 may include, but is not limited to, a semiconductor substrate and corresponding active devices formed on the semiconductor substrate (such as a metal interconnect structure 203 located in the device area 201, etc.).

[0036] Reference Figure 3 , Step S120, form a dielectric layer 210 on the surface of the substrate 200.

[0037] In some embodiments of the present application, the method of forming the dielectric layer 210 includes a chemical vapor deposition process, a physical vapor deposition process, or the like.

[0038] In some embodiments of the present application, the dielectric layer 210 includes an NDC layer 211 on the surface of the substrate 200 and a TEOS layer 212 on the surface of the NDC layer. In some embodiments of the present application, the thickness of the NDC layer 211 is 100 angstroms to 150 angstroms; the thickness of the TEOS layer is 400 angstroms to 500 angstroms.

[0039] Reference Figure 4 , step S130, forming a buffer layer 220 on the surface of the dielectric layer 210. The buffer layer 220 can improve the quality of the subsequently formed auxiliary trench, thereby improving the position accuracy of the magnetic tunnel junction. In addition, the buffer layer 220 can also serve as a polishing stop layer during subsequent chemical mechanical polishing of the connection structure, and improve the uniformity during chemical mechanical polishing of the connection structure.

[0040] In some embodiments of the present application, the material of the buffer layer 220 includes titanium nitride rich in nitrogen. The titanium nitride rich in nitrogen has a high light transmittance, which can provide good positioning for lithography when forming auxiliary trenches subsequently, and form good auxiliary trenches.

[0041] In some embodiments of the present application, the thickness of the buffer layer 220 is 100 angstroms to 200 angstroms, such as 120 angstroms, 150 angstroms, or 180 angstroms, etc.

[0042] In some embodiments of the present application, the method of forming the buffer layer 220 includes a chemical vapor deposition process, a physical vapor deposition process, or the like.

[0043] Reference Figures 5 to 10 , step S140, forming a connection structure 230 penetrating the buffer layer 220 and the dielectric layer 210 in the device region 201. The connection structure 230 is electrically connected to the metal interconnect structure 203 in the substrate 200.

[0044] Reference Figure 5 , forming a patterned photoresist 231 on the surface of the buffer layer 220, and the patterned photoresist 231 defines the position of the connection structure. The method of forming the patterned photoresist 231 includes: spin-coating a photoresist on the surface of the buffer layer 220; performing an exposure process on the photoresist.

[0045] Reference Figure 6 , etching the buffer layer 220 and the TEOS layer 212 using the patterned photoresist 231 as a mask to form a first trench 232. The etching includes wet etching, dry etching, or the like.

[0046] Reference Figure 7 Repair the patterned photoresist 231 to expose the surface of the buffer layer 220 on both sides of the partial first trench 232. The method for repairing the patterned photoresist 231 includes ashing.

[0047] Reference Figure 8 Etch and remove the exposed buffer layer 220 and the NDC layer 211 at the bottom of the first trench 232. The etching includes wet etching or dry etching, etc.

[0048] Reference Figure 9 Remove the patterned photoresist 231; form a connection structure 230 on the surface of the TEOS layer and the surface of the buffer layer 220 in the first trench 232. The method for removing the patterned photoresist 231 is, for example, ashing. The method for forming the connection structure 230 includes chemical vapor deposition process or physical vapor deposition process, etc.

[0049] Reference Figure 10 Use a chemical mechanical polishing process (CMP) to polish the connection structure 230 until the top surface of the connection structure 230 is coplanar with the buffer structure 220.

[0050] In some methods for forming a semiconductor structure, due to the absence of the buffer layer 220, when using the CMP process, either the dielectric layer 210 may be over-polished to reduce its thickness, or the polishing may be insufficient and there may be residues on the surface of the dielectric layer 210, thereby affecting the subsequent auxiliary trenches formed in the auxiliary region 202. In the method for forming a semiconductor structure according to the embodiments of the present application, the buffer layer 220 can be used as a buffer layer and a stop layer for the CMP process to improve the uniformity of the CMP process.

[0051] Reference Figure 11 Step S150, form an auxiliary trench 240 in the auxiliary region 202 that penetrates the buffer layer 220 and the dielectric layer 210 and extends into the substrate 200. The purpose of the auxiliary trench 240 is to provide a mark for the etching process when forming a magnetic tunnel junction in subsequent etching, improve the etching accuracy, and thereby improve the position accuracy of the magnetic tunnel junction.

[0052] In some embodiments of the present application, the method of forming the auxiliary trench 240 in the auxiliary region 202, which penetrates through the buffer layer 220 and the dielectric layer 210 and extends into the substrate 200, includes: forming a patterned photoresist on the surfaces of the buffer layer 220 and the connection structure 230, where the patterned photoresist defines the position of the auxiliary trench 240; using the patterned photoresist as a mask to etch the buffer layer 220, the dielectric layer 210, and the substrate 200 to form the auxiliary trench 240 that penetrates through the buffer layer 220 and the dielectric layer 210 and extends into the substrate 200.

[0053] In some embodiments of the present application, the width of the auxiliary trench 240 is 1000 nanometers to 4000 nanometers. The width of the auxiliary trench 240 (i.e., the dimension in the horizontal direction) should be wide enough to prevent the magnetic tunnel junction material layer formed subsequently from filling the auxiliary trench 240.

[0054] In some methods for forming semiconductor structures, since there is no buffer layer 220, and both the dielectric layer 210 and the connection structure 230 are opaque materials, when forming the auxiliary trench 240 by lithography, there is no good reference object, and the quality of the formed auxiliary trench 240 is poor, such as the size and position are not good, which in turn affects the accuracy of the position of the magnetic tunnel junction formed by subsequent etching. In the method for forming the semiconductor structure according to the embodiments of the present application, the buffer layer 220 has high light transmittance, which can provide a reference when forming the auxiliary trench 240 by lithography, form a good auxiliary trench 240, and thus improve the accuracy of the position of the magnetic tunnel junction formed by subsequent etching.

[0055] Reference Figure 12 , step S160, forming a magnetic tunnel junction material layer 250a on the sidewalls and bottom of the auxiliary trench 240 and on the surfaces of the buffer layer 220 and the connection structure 230, where the magnetic tunnel material layer 250a does not fill the auxiliary trench 240. Since the width of the auxiliary trench 240 is wide enough, the magnetic tunnel junction material layer 250a will not fill the auxiliary trench 240.

[0056] The auxiliary trench 240 cannot be filled because the auxiliary trench 240 is required as an etching mark when subsequently etching the magnetic tunnel junction material layer 250a to form a magnetic tunnel junction.

[0057] In some embodiments of the present application, the method of forming the magnetic tunnel junction material layer 250 includes chemical vapor deposition process or physical vapor deposition process, etc.

[0058] In some embodiments of the present application, the magnetic tunnel junction material layer 250a includes a first ferromagnetic material layer 251a located on the connection structure 230, the buffer layer 220, and the surface of the sidewall of the trench, a non-magnetic insulating material layer 252a located on the surface of the first ferromagnetic material layer 251a, and a second ferromagnetic material layer 253a located on the surface of the non-magnetic insulating material layer 252a.

[0059] In some embodiments of the present application, the material of the first ferromagnetic material layer 251a includes cobalt, iron, tantalum, etc.; the material of the second ferromagnetic material layer 253a includes cobalt, iron, tantalum, etc.

[0060] In some embodiments of the present application, the material of the non-magnetic insulating material layer 252a includes alumina, etc.

[0061] Reference Figure 13 In step S170, the magnetic tunnel junction material layer 250a and the buffer layer 220 are etched to form a magnetic tunnel junction 250 on the surface of the connection structure 230. The auxiliary trench 240 can be used as an etching mark for positioning during the etching of the magnetic tunnel junction material layer 250a, improving the position accuracy of the magnetic tunnel junction 250.

[0062] In some methods for forming a semiconductor structure, due to the absence of the buffer layer 220, the quality of the auxiliary trench 240 is poor, thereby affecting the position accuracy of the magnetic tunnel junction 250. In the method for forming a semiconductor structure according to the embodiments of the present application, a buffer layer 220 is formed on the surface of the dielectric layer 210. The buffer layer 220 can improve the quality of the auxiliary trench 240, thereby improving the position accuracy of the magnetic tunnel junction 250.

[0063] In some embodiments of the present application, the magnetic tunnel junction 250 includes a first ferromagnetic layer 251 located on the surface of the connection structure 230, a non-magnetic insulating layer 252 located on the surface of the first ferromagnetic layer 251, and a second ferromagnetic layer 253 located on the surface of the non-magnetic insulating layer 252.

[0064] In some embodiments of the present application, the material of the first ferromagnetic layer 251 includes cobalt, iron, tantalum, etc.; the material of the second ferromagnetic layer 253 includes cobalt, iron, tantalum, etc.

[0065] In some embodiments of the present application, the material of the non-magnetic insulating layer 252 includes alumina, etc.

[0066] In some embodiments of the present application, a method for etching the magnetic tunnel junction material layer 250a and the buffer layer 220 to form a magnetic tunnel junction 250 on the surface of the connection structure 230 includes: forming a patterned photoresist on the surface of the magnetic tunnel junction material layer 250a, and the patterned photoresist defines the position of the magnetic tunnel junction 250; using the patterned photoresist as a mask to etch the magnetic tunnel junction material layer 250a and the buffer layer 220 to form a magnetic tunnel junction 250 on the surface of the connection structure 230.

[0067] Reference Figure 14 , the method for forming the semiconductor structure described in the present application further includes: forming an interlayer dielectric layer 260 in the auxiliary trench 240, on the surface of the dielectric layer 230, and on the surface of the magnetic tunnel junction 250; forming a contact structure 270 that penetrates the interlayer dielectric layer 260 and electrically connects the magnetic tunnel junction 250 in the interlayer dielectric layer 260.

[0068] In some embodiments of the present application, the method for forming the interlayer dielectric layer 260 includes a chemical vapor deposition process.

[0069] In some embodiments of the present application, the material of the contact structure 270 includes aluminum or copper, etc.

[0070] In the method for forming the semiconductor structure described in the present application, a buffer layer is formed on the surface of the dielectric layer. The buffer layer can improve the quality of the auxiliary trench, thereby improving the position accuracy of the magnetic tunnel junction. In addition, the buffer layer can also improve the uniformity during chemical mechanical polishing of the connection structure.

[0071] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0072] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0073] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element.

[0074] It should also be understood that the terms "comprises", "comprising", "includes" or "including", as used in this application document, specify the presence of the recited features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0075] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0076] In addition, the present application specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Accordingly, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a device region and an auxiliary region; Forming a dielectric layer on the surface of the substrate; Forming a buffer layer on the surface of the dielectric layer, the material of the buffer layer including titanium nitride rich in nitrogen; Forming a connection structure in the device region that penetrates the buffer layer and the dielectric layer; Forming an auxiliary trench in the auxiliary region that penetrates the buffer layer and the dielectric layer and extends into the substrate; Forming a magnetic tunnel junction material layer on the sidewalls and bottom of the auxiliary trench and on the surfaces of the buffer layer and the connection structure, the magnetic tunnel material layer not filling the auxiliary trench; Etching the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure.

2. The method for forming a semiconductor structure according to claim 1, wherein, The dielectric layer includes an NDC layer located on the surface of the substrate and a TEOS layer located on the surface of the NDC layer.

3. The method for forming a semiconductor structure according to claim 2, wherein, The method of forming a connection structure in the device region that penetrates the buffer layer and the dielectric layer includes: Forming a patterned photoresist on the surface of the buffer layer, the patterned photoresist defining the position of the connection structure; Using the patterned photoresist as a mask to etch the buffer layer and the TEOS layer to form a first trench; Exposing the surface of the buffer layer on both sides of a part of the first trench by the patterned photoresist; Etching and removing the exposed buffer layer and the NDC layer at the bottom of the first trench.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein, The thickness of the buffer layer is 100 angstroms to 200 angstroms.

5. The method for forming a semiconductor structure according to claim 1, wherein, The device region of the substrate includes a metal interconnect structure, and the connection structure is electrically connected to the metal interconnect structure.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein The magnetic tunnel junction includes a first ferromagnetic layer located on the surface of the connection structure, a non-magnetic insulating layer located on the surface of the first ferromagnetic layer, and a second ferromagnetic layer located on the surface of the non-magnetic insulating layer.

7. The method for forming the semiconductor structure according to claim 6, wherein The material of the first ferromagnetic layer includes cobalt, iron or tantalum; the material of the second ferromagnetic layer includes cobalt, iron or tantalum.

8. The method for forming a semiconductor structure as described in claim 1, wherein, The method of etching the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure includes: Forming a patterned photoresist on the surface of the magnetic tunnel junction material layer, the patterned photoresist defining the position of the magnetic tunnel junction; Using the patterned photoresist as a mask to etch the magnetic tunnel junction material layer and the buffer layer to form a magnetic tunnel junction on the surface of the connection structure.

9. The method for forming a semiconductor structure as claimed in claim 1, wherein The method of forming an auxiliary trench in the auxiliary region that penetrates the buffer layer and the dielectric layer and extends into the substrate includes: Forming a patterned photoresist on the surfaces of the buffer layer and the connection structure, the patterned photoresist defining the position of the auxiliary trench; Using the patterned photoresist as a mask to etch the buffer layer, the dielectric layer and the substrate to form an auxiliary trench that penetrates the buffer layer and the dielectric layer and extends into the substrate.

Images