Analog chip circuit winding method

Abstract

The present invention relates to the technical field of analog chips, and in particular to a circuit wiring method for analog chips. The method automatically completes block-level wiring by constructing a wiring space, calculating basic parameters of the wiring, calculating the shortest connection according to a layout, searching for and completing the calculation of a wiring scheme, drawing physical connections according to the wiring scheme, and outputting data. The method has fast wiring speed, reasonable layout, high DRC accuracy, and high connectivity rate.

Description

Technical Field

[0001] The invention relates to the field of analog chips, in particular to a circuit winding method for analog chips. Background Art

[0002] The existing commercial products of wire routing tools are mainly for digital chip algorithms, which are relatively mature. The wire routing tools for analog chips have slow calculation speed and poor winding results, and basically no company uses them. The automation tools for analog chips are a difficult problem that has not been solved, and the wire routing algorithm for analog chips is one of the major problems. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an analog chip circuit wiring method, which can automatically complete the wiring of the analog chip after the analog chip is designed and laid out.

[0004] The analog chip circuit winding method of the present invention comprises the steps of:

[0005] S1. Divide the winding area in multiple winding layers;

[0006] S2, calculate the width of the connection line through the current data in the connection line;

[0007] S3. Calculate the shortest connection line according to the device placement;

[0008] S4, searching for a routing path in the winding space;

[0009] S5. Arrange the line sequence of the entrance and exit of the area, and arrange it according to the direction of the line, whether there is a crossover causing jumper, and whether there is enough space in the current winding area;

[0010] S6. Calculate the solution of jumper wires in the channel according to the device environment around the wiring area and the number of horizontal and vertical wires;

[0011] S7, determining whether the line in the channel needs to turn, and calculating the number of turns;

[0012] S8, update the channel space usage according to the routing situation and the devices around the channel; if there are still routings, return to steps S4-S7 until all routings are planned;

[0013] S9, calculate the mutual influence of the routing between channels, reduce the space usage of the affected area and repair the solution, if it cannot be repaired, return to step S4 and re-wrap the wires;

[0014] S10, calculating the real coordinate positions of all connecting lines according to the wiring plan;

[0015] S11, complete the calculation and output the winding results.

[0016] Furthermore, the detailed steps in step S1 include:

[0017] S101, divide the routing area in the metal layer of the chip according to the existing space conditions, and plan the area according to the process rules;

[0018] S102, obtaining information of additional layers of the Poly layer and the Diff layer, and dividing the non-routing areas and the routing process rules of different areas by analyzing the device model.

[0019] The beneficial effects of the present invention are as follows: the analog chip circuit wiring method of the present invention automatically completes block-level wiring by constructing a wiring space, calculating basic wiring parameters, calculating the shortest wiring according to the layout, searching for and completing the calculation of the wiring plan, drawing physical wiring according to the wiring plan, and outputting data, etc., with fast wiring speed, reasonable layout, and high DRC accuracy and connectivity rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative work:

[0021] Figure 1 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0022] like Figure 1 As shown: The analog chip circuit winding method of this embodiment includes the steps;.

[0023] S1. Divide the wiring area in multiple winding layers and find the area in the metal connection layer that can be wired:

[0024] S101. Specifically, for example, if it is planned to wire on Metal1 and Metal2, Metal is the metal connection layer. The wiring area (usually a rectangle) is divided on the Metal and Metal2 of the chip according to the existing space occupancy to form a routing area, and the area is planned according to the process rules. Metal performs wiring according to the plan.

[0025] Different processes have different spacing requirements for different widths of metal. The area in the routing area where the wiring can be routed will be affected differently by the devices and wiring in the adjacent areas. Therefore, before routing, the redundant space between the routing area and the adjacent devices must be calculated to plan the area where the wiring can actually be routed, that is, the space outside the redundant space.

[0026] S102, obtain the information of additional layers such as Poly and Diff. The Poly layer is the transistor layer, and the Diff is the switching area. By analyzing the device model, etc., the areas where routing is not allowed and the process rules for routing in different areas are divided. For example, the areas where Poly and Diff overlap cannot be routed, and some high-voltage areas cannot be routed. These areas need to be clearly marked in advance; through this step, the areas where routing is not allowed in the routing areas found in S101 are found and excluded. In this way, the areas where routing can be performed are found.

[0027] S2. Analyze the current data of each NET and deduce the width of the connection. If the current of the chip is larger, the connection needs to be wider; otherwise, the connection can be narrower.

[0028] S3. Calculate the shortest connection according to the placement of transistor devices in the Poly transistor layer. The shortest connection follows the horizontal and vertical wiring principles. According to the use of space and in subsequent calculations, adjust the plan in real time.

[0029] S4. Search for a routing path in the winding space.

[0030] S5. Arrange the line sequence of the area entrance and exit. The arrangement rules are mainly based on three factors: (1) the direction of the line; (2) whether there is a crossover that causes jumpers; and (3) whether there is enough space in the current winding area.

[0031] First, it is necessary to determine whether the lines will cross. If there is no crossing, determine in which area the lines are best to jump. The judgment conditions are mainly based on the space usage of each area and follow the shortest principle. After calculating the crossing, dynamically determine the direction of the existing lines and the direction of the lines being planned, and finally determine the order of the lines at the entrances and exits of the winding area.

[0032] S6. Calculate the jumper solution within the channel. The jumper solution is mainly determined based on the device environment around the line area and the number of horizontal and vertical lines. Lines that are already in the upper layer are given priority to jumpers. At the same time, based on the number of horizontal and vertical lines and the layer where the line is located, decide which direction the line jumps. The connection line may be both horizontal and vertical in the area, because the line will change direction in the area, so at this time it is necessary to judge based on the total space usage.

[0033] S7. Determine whether the line in the channel needs to turn, and calculate the number of turns.

[0034] There are three main modes of connection within the routing area: (1) opposite-side routing; (2) side routing; and (3) same-side routing. Taking opposite-side routing as an example, the two ends of the connection can directly pass through the two opposite sides of the routing area without turning. It is also possible to serpentine the routing in sections, which will cause multiple turns, resulting in increased line resistance and an increase in wiring area. The number of turns required internally depends on the distribution of various internal wires; whether serpentine routing is required depends on the direction of the wire, which is calculated through the relative geometric positions of each winding area; whether to route horizontally in the current area depends on the space usage of each area. The calculation rules for other routing methods are similar.

[0035] S8. Update the channel space usage according to the routing conditions and the devices around the channel; if there are still routings, return to steps S4-S7 until all routing is planned.

[0036] S9, complete all the routing plans. Since millions of iterations are required when searching for routing plans, the impact of some details will not be taken into account. In this step, all the details are calculated clearly:

[0037] S901. Calculate the mutual influence of routing between routing channels: due to jumpers or connections across devices, the routing of a certain routing area will use the space of adjacent areas, sometimes causing a chain reaction across multiple areas, resulting in insufficient space in some areas.

[0038] S902, automatically mining the space in other areas through a space search heuristic algorithm, thereby reducing the space usage of the affected area, and repairing the solution.

[0039] S903: If the error cannot be repaired, remove the erroneous line and return to steps S4-S7.

[0040] S10. Calculate the real coordinates of all routing lines according to the routing plan:

[0041] S101. Plan the specific order of each physical line in the routing channel.

[0042] S102, calculate the key point coordinates of all entity lines in the line (jump line position, turning position, etc.), and calculate the coordinate position of VIA.

[0043] S11, complete the calculation and output the winding results.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for analog chip circuit winding, characterized in that: Includes steps: S1. Divide the winding area in multiple winding layers; S2, calculate the width of the connection line through the current data in the connection line; S3. Calculate the shortest connection line according to the device placement; S4, searching for a routing path in the winding space; S5. Arrange the line sequence of the entrance and exit of the area, and arrange it according to the direction of the line, whether there is a crossover causing jumper, and whether there is enough space in the current winding area; S6. Calculate the solution of jumper wires in the channel according to the device environment around the wiring area and the number of horizontal and vertical wires; S7, determining whether the line in the channel needs to turn, and calculating the number of turns; S8, update the channel space usage according to the routing situation and the devices around the channel; if there are still routings, return to steps S4-S7 until all routings are planned; S9, calculate the mutual influence of the routing between channels, reduce the space usage of the affected area and repair the solution, if it cannot be repaired, return to step S4 and re-wrap the wires; S10, calculating the real coordinate positions of all connecting lines according to the wiring plan; S11, complete the calculation and output the winding results.

2. The analog chip circuit winding method according to claim 1, characterized in that: The detailed steps in step S1 include: S101, dividing the area where wiring can be routed in the metal layer of the chip according to the occupancy of the existing space, and planning the area according to the process rules; S102 , obtaining information of additional layers of the Poly layer and the Diff layer, and dividing the non-routable areas and the process rules for routing in different areas by analyzing the device model.

Images