Integrated circuit wiring method and system, and device and medium

Abstract

Disclosed in the present application are an integrated circuit routing method and system, and a device and a medium. The method comprises: acquiring an integrated circuit layout model; performing routing area generation processing on the integrated circuit layout model on the basis of a particle swarm optimization algorithm, so as to obtain a routing area; performing routing processing on the routing area on the basis of an improved A* search algorithm, so as to obtain a routing path; on the basis of the routing path, removing a redundant segment, so as to obtain a post-processed path; and performing dictionary conversion processing on the post-processed path, so as to obtain a routing layout. In the embodiments of the present application, a discrete particle swarm optimization algorithm can be used to reduce a routing search space, and a detailed routing area is determined by means of an improved A* search algorithm, thereby further enhancing routing speed, and improving the routing efficiency of an integrated circuit. The embodiments of the present application can be widely applied to the field of integrated circuits.

Description

Integrated circuit wiring method, system, device and medium Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit wiring method, system, device and medium. Background Art

[0002] As the feature sizes of modern ultra-large-scale integrated circuits (VLSIs) continue to shrink, on-chip communication becomes increasingly complex, increasing the difficulty of integrated circuit wiring design. Traditional wiring methods, such as the maze algorithm and Dijkstra's algorithm, struggle to meet the speed and performance requirements of wiring. As wiring scale continues to increase, the search space becomes excessively large, significantly limiting wiring speed and quality. They can even lead to memory leaks, impacting the efficiency of integrated circuit wiring.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Technical issues

[0004] The main purpose of the embodiments of the present application is to provide an integrated circuit wiring method, system, device and medium, which can improve the wiring efficiency of the integrated circuit. Technical Solutions

[0005] To achieve the above objectives, an embodiment of the present application provides an integrated circuit wiring method, the method comprising:

[0006] obtaining an integrated circuit layout model;

[0007] Performing wiring area generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a wiring area;

[0008] Performing routing processing on the routing area according to the improved A-star search algorithm to obtain a routing path;

[0009] Removing redundant line segments according to the wiring path to obtain a post-processing path;

[0010] Dictionary conversion is performed on the post-processing path to obtain a wiring layout.

[0011] In some embodiments, the generating of the wiring area on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain the wiring area includes:

[0012] Performing rectangular Steiner tree generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a rectangular Steiner tree;

[0013] Determine the pin connection relationship and connection method according to the right-angle Steiner tree;

[0014] Dividing the integrated circuit layout model according to the pin connection relationship and the wiring mode to obtain a wiring buffer;

[0015] A routing local area of ​​the integrated circuit layout model is determined according to the vertex coordinates of the routing buffer.

[0016] In some embodiments, the generating of a rectangular Steiner tree on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a rectangular Steiner tree includes:

[0017] obtaining an acceptance probability and a layout parameter of the integrated circuit layout model;

[0018] Initializing the layout parameters and generating a randomly distributed initial particle population in the solution space according to the layout parameters;

[0019] Performing fitness calculation processing on the initial particle population according to a fitness function to obtain an initial fitness;

[0020] Updating the initial particle population to obtain an updated particle population;

[0021] Performing fitness calculation processing on the updated particle population according to the fitness function to obtain updated fitness;

[0022] Comparing the updated fitness according to the acceptance probability and the initial fitness to obtain a comparison result;

[0023] When the comparison result satisfies a termination condition, generating a rectangular Steiner tree according to the updated particle population;

[0024] Otherwise, return to the step of updating the initial particle population.

[0025] In some embodiments, obtaining the acceptance probability includes:

[0026] Set the initial temperature and temperature update formula;

[0027] According to the temperature update formula, the initial temperature is lowered to obtain a temperature adjustment table;

[0028] The acceptance probability is obtained according to the temperature adjustment table.

[0029] In some embodiments, performing routing processing on the routing area according to the improved A-star search algorithm to obtain a routing path includes:

[0030] Get the cost weight factor;

[0031] Determining a heuristic function of the improved A-star search algorithm according to the Manhattan distance;

[0032] Performing cost optimization processing on the improved A-star search algorithm according to the cost weight factor and the heuristic function to obtain an optimized cost function;

[0033] Search and route the routing area according to the optimized cost function to obtain a routing path.

[0034] In some embodiments, performing routing processing on the routing area according to the optimized cost function to obtain a routing path includes:

[0035] Performing a search point check process on the wiring area to determine a neighboring node to be selected;

[0036] Performing cost calculation on the neighboring nodes to be selected using the optimized cost function to obtain a node cost;

[0037] A target node is determined according to the node cost, and backtracing processing is performed on the target node to obtain a wiring path.

[0038] In some embodiments, removing redundant line segments according to the routing path to obtain a post-processing path includes:

[0039] Checking and processing the wiring path according to the wiring rules to obtain the through-hole position and redundant line segments;

[0040] The wiring path is reset according to the through-hole position and the redundant line segment to obtain a post-processing path.

[0041] To achieve the above objectives, another aspect of the present application provides an integrated circuit wiring system, the system comprising:

[0042] The first module is used to obtain an integrated circuit layout model;

[0043] The second module is configured to perform wiring area generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a wiring area;

[0044] The third module is used to perform wiring processing on the wiring area according to the improved A-star search algorithm to obtain a wiring path;

[0045] A fourth module is configured to remove redundant line segments according to the wiring path to obtain a post-processing path;

[0046] The fifth module is used to perform dictionary conversion processing on the post-processing path to obtain a wiring layout.

[0047] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned method when executing the computer program.

[0048] To achieve the above objectives, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented. Beneficial effects

[0049] The embodiments of the present application include at least the following beneficial effects: The present application provides a base-layer circuit wiring method, system, device and medium, which uses a particle swarm optimization algorithm to generate a wiring area for an integrated circuit layout model to obtain a wiring area, which can determine the connection relationship and wiring range, and reduce the wiring search space; the solution also uses an improved A-star search algorithm to perform wiring processing on the wiring area to determine the detailed wiring area, and at the same time improves the A-star search algorithm to perform exponential function optimization on the cost function, further improving the wiring speed and improving the wiring efficiency of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a flow chart of an integrated circuit wiring method provided by an embodiment of the present application;

[0051] FIG2 is a schematic diagram showing a wiring area visualization provided by an embodiment of the present application;

[0052] FIG3 is a schematic diagram of a wiring example provided in an embodiment of the present application;

[0053] FIG4 is a wiring layout provided in an embodiment of the present application;

[0054] FIG5 is a schematic structural diagram of an integrated circuit wiring system provided in an embodiment of the present application;

[0055] FIG6 is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present application. Best Mode for Carrying Out the Invention

[0056] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0057] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0058] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0060] Before explaining the embodiments of the present application in detail, some of the nouns and terms involved in the embodiments of the present application are first explained. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0061] The Dijkstra algorithm, proposed by Dutch computer scientist Dijkstra in 1959, is also known as the Dijkstra algorithm. It is a shortest path algorithm from one vertex to all other vertices, solving the shortest path problem in weighted graphs. The main feature of the Dijkstra algorithm is that it starts from a starting point and uses a greedy algorithm strategy, traversing the nearest unvisited neighboring nodes until it reaches the end point.

[0062] The Steiner tree problem is a combinatorial optimization problem, similar to the minimum spanning tree, a type of shortest network. A minimum spanning tree seeks the shortest network from a given set of points and edges, connecting all points. The minimum Steiner tree, on the other hand, allows for the addition of additional points beyond the given set, minimizing the cost of the resulting shortest network.

[0063] The wiring area refers to an area with wiring track resources. The wiring track refers to the horizontal or vertical wires.

[0064] A very large scale integration circuit (VLSI) is an integrated circuit that combines a large number of transistors into a single chip, with a higher level of integration than an LSI.

[0065] With the continuous development of integrated circuit technology, chip size is getting smaller and smaller, while the scale of interconnect lines is getting larger and larger. Physical design is one of the fastest-growing and most automated fields in the field. As the features and size of integrated circuits continue to decrease, the scale of circuits and large-scale integrated circuit processes, as well as Moore's Law, have experienced tremendous progress. The increasing complexity of integrated circuit design further increases the difficulty of automated physical design.

[0066] Routing is an integral part of physical back-end design. As the feature sizes of modern VLSI designs continue to shrink, on-chip communications have become extremely complex. The increasing density of circuit elements and interconnects poses significant challenges to modern VLSI routers. The increasing number of connections between different networks and the concentration of routing congestion, coupled with the limited routing resources on the chip, make today's designed chips more difficult to route. The massive routing demands imposed by VLSIs make it impractical to route directly based on routing requirements and design rules. Various constraints make the routing process complex and time-consuming. Traditional routing methods, such as the maze algorithm and Dijkstra's algorithm, struggle to meet routing speed and performance requirements. The A-star search algorithm has garnered widespread attention due to its excellent performance, but as the routing scale continues to grow, the search space becomes excessively large, significantly limiting routing speed and quality, and even leading to memory leaks.

[0067] In view of this, an embodiment of the present application provides an integrated circuit wiring method, system, device and medium. This scheme combines the wiring pin position relationship, optimization algorithm, and wiring algorithm to carry out an integrated circuit wiring method of joint particle swarm optimization and A-star search. Among them, the discrete particle swarm optimization (DPSO) algorithm is used to construct a rectangular Steiner tree to determine the connection relationship and the approximate wiring range, thereby reducing the wiring search space. At the same time, a simulated annealing strategy is added when the particles are updated to avoid falling into the local optimal situation; and an improved A-star search algorithm is used to determine the detailed wiring area, and the cost function is optimized by exponential function to further improve the wiring speed and improve the wiring efficiency.

[0068] The integrated circuit wiring method provided in the embodiment of the present application relates to the field of integrated circuit design technology. The integrated circuit wiring method provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server, and can also be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or can be configured as a server cluster or distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements the integrated circuit wiring method, etc., but is not limited to the above forms.

[0069] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0070] FIG1 is an optional flowchart of an integrated circuit wiring method provided in an embodiment of the present application. The method in FIG1 may include but is not limited to steps S101 to S105 .

[0071] Step S101, obtaining an integrated circuit layout model;

[0072] Step S102, performing wiring area generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a wiring area;

[0073] Step S103, performing wiring processing on the wiring area according to the improved A-star search algorithm to obtain a wiring path;

[0074] Step S104, removing redundant line segments according to the wiring path to obtain a post-processing path;

[0075] Step S105 , performing dictionary conversion processing on the post-processing path to obtain a wiring layout.

[0076] In steps S101 to S106 shown in the embodiment of the present application, the integrated circuit layout model is obtained and a rectangular Steiner tree (RSMT) is determined based on the discrete particle swarm optimization (DPSO) algorithm to perform preliminary planning of the wiring area. The improved A-star search algorithm is then used to further perform detailed wiring processing on the wiring area to obtain a wiring path. After all the wire nets are routed using the improved A-star search algorithm, the post-processing path is obtained by removing redundant wire segments in the wiring path. The post-processing path is then converted into a production-ready layout GDSII format based on a dictionary. The GDSII stream format is a database file format used for data conversion of integrated circuit layouts and has become a de facto industry standard. The wiring layout in the embodiment of the present application is a binary file that contains the geometric shapes, text or labels, and other relevant information of the planes in the integrated circuit layout and can be composed of a hierarchical structure, thereby being used to reconstruct all or part of the layout information and can be used to make a photolithography mask.

[0077] In step S101 of some embodiments, the integrated circuit layout model may be obtained by performing layout modeling on the integrated circuit. Alternatively, the integrated circuit layout model may be obtained by other methods such as computers, without limitation.

[0078] In step S102 of some embodiments, performing wiring area generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain the wiring area includes:

[0079] Step S1021: performing rectangular Steiner tree generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a rectangular Steiner tree;

[0080] Step S1022: determining the pin connection relationship and connection mode according to the rectangular Steiner tree;

[0081] Step S1023: dividing the integrated circuit layout model according to the pin connection relationship and the wiring mode to obtain a wiring buffer;

[0082] Step S1024 : determining a routing region of the integrated circuit layout model according to the vertex coordinates of the routing buffer.

[0083] In step S1021 of some embodiments, a rectangular Steiner tree generation process is performed on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a rectangular Steiner tree. The rectangular Steiner tree aims to find a tree connecting all given points so that all edges in the tree are horizontal or vertical, rather than diagonal lines. In integrated circuit design, this tree structure is used to minimize the total length of wiring, thereby reducing circuit delay and power consumption. The rectangular Steiner tree can be generated by the particle swarm optimization algorithm. The particle swarm optimization algorithm is a swarm intelligence algorithm. The particle swarm S is a group containing multiple particles in a multidimensional continuous solution space. Each particle has its own position and velocity. By updating the position and velocity of the particle, a rectangular Steiner tree is generated. The embodiment of the present application uses the discrete particle swarm optimization (DPSO) algorithm to construct a rectangular Steiner tree, thereby determining the connection relationship and approximate wiring range of the integrated circuit, thereby reducing the search space for integrated circuit wiring.

[0084] In some embodiments, in step S1021, performing rectangular Steiner tree generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain the rectangular Steiner tree includes:

[0085] obtaining an acceptance probability and a layout parameter of the integrated circuit layout model;

[0086] Initializing the layout parameters and generating a randomly distributed initial particle population in the solution space according to the layout parameters;

[0087] Performing fitness calculation processing on the initial particle population according to a fitness function to obtain an initial fitness;

[0088] Updating the initial particle population to obtain an updated particle population;

[0089] Performing fitness calculation processing on the updated particle population according to the fitness function to obtain updated fitness;

[0090] Comparing the updated fitness according to the acceptance probability and the initial fitness to obtain a comparison result;

[0091] When the comparison result satisfies a termination condition, generating a rectangular Steiner tree according to the updated particle population;

[0092] Otherwise, return to the step of updating the initial particle population.

[0093] In the embodiment of the present application, the acceptance probability and the layout parameters of the integrated circuit layout model are first obtained. The specific method of obtaining the acceptance probability is described below and will not be described in detail here. The layout parameters of the integrated circuit layout model can be data such as pin coordinates. By initializing the corresponding parameters and generating a randomly distributed initial particle population in the solution space, the particle population is then initialized according to the response function. (where L is the total line length, α is a weighting factor, and bends is the number of turns.) The corresponding fitness value is calculated for each particle, and the individual optimal solution for each particle and the global optimal solution for the population are recorded. This fitness value is denoted as f_old. The initial particle population is then updated, updating the position and velocity of each particle to obtain an updated particle population. For each new particle position, a fitness value is calculated, denoted as f_new. The acceptance probability is compared with the fitness f_old of the particle's current individual optimal solution. If f_new is superior (i.e., higher than the fitness f_old of the particle's current individual optimal solution), the new position is accepted and the individual optimal solution is updated accordingly. If f_new is inferior (i.e., lower than the fitness f_old of the particle's current individual optimal solution), the new position is accepted with an acceptance probability p. The acceptance probability p decreases gradually at a certain cooling rate, which is determined based on the specific network conditions. The acceptance rule can be a simulated annealing algorithm, which controls the rate at which the probability p decreases by setting an initial temperature and a temperature cooling rate. The specific method for obtaining the acceptance probability is described below. Finally, the global optimal solution of the population is recalculated. When the comparison result meets the termination condition, a rectangular Steiner tree is generated based on the updated particle population. That is, the termination condition is checked to see if it is met. If so, the tree stops; otherwise, the particle positions and velocities are continuously updated. The termination condition can be the optimal solution or the number of iterations reached. By constructing a rectangular Steiner tree using a particle swarm optimization algorithm, the present embodiment can reduce the wiring search space and improve the wiring efficiency of the integrated circuit.

[0094] The obtaining of the acceptance probability includes:

[0095] Set the initial temperature and temperature update formula;

[0096] According to the temperature update formula, the initial temperature is lowered to obtain a temperature adjustment table;

[0097] The acceptance probability is obtained according to the temperature adjustment table.

[0098] In this embodiment, a temperature adjustment table is constructed by setting an initial temperature T0 and a temperature update formula. The initial temperature T0 directly affects the initial value of the acceptance probability p. If T0 is set too high, the process will accept too many poor solutions; if it is set too low, fewer poor solutions will be accepted. Therefore, a suitable T0 can be determined through preliminary experiments, keeping the initial p value around 0.7-0.8. The temperature update formula can be set to decrease the temperature every certain number of iterations (for example, every 50 iterations). Common update formulas include: Tnew = α*Told or, more recently, Tnew = Told – ΔT, where α is the temperature attenuation coefficient, typically ranging from 0.8 to 0.99, and ΔT is a fixed descent gradient. In this embodiment, the acceptance probability is used to compare and determine particle updates. When the fitness value of a new particle update is poor, it is accepted with probability p: p = exp(-(fnew - fold) / T). The higher the temperature T, the larger the P value. Then, a minimum temperature value or a lower limit on the number of times a poor solution is accepted can be set as the termination condition. This method can be used to design a gradually decreasing temperature adjustment table. The acceptance probability p is then obtained from the temperature adjustment table, and the acceptance probability p is controlled to decrease at an appropriate rate, fully utilizing the ability to escape local optima. This embodiment of the present application avoids falling into local optima by accepting poor solutions with a certain probability when updating particles, enhancing the algorithm's global optimization capabilities and improving the efficiency of integrated circuit wiring.

[0099] In step S1022 of some embodiments, the pin connection relationship and wiring method are determined based on a rectangular Steiner tree, where the rectangular Steiner tree problem is to connect all pins through some additional points (called Steiner points) to minimize the line length. Therefore, by generating a rectangular Steiner tree, the pin connection relationship and wiring method of the integrated circuit wiring can be determined.

[0100] In step S1023 of some embodiments, the integrated circuit layout model is partitioned based on the pin connection relationship and the wiring method to obtain routing buffers. After obtaining the pin connection relationship and the wiring method, the integrated circuit wiring model can be partitioned based on the pin positions and corresponding wiring rules to obtain appropriate routing buffers.

[0101] In step S1024 of some embodiments, referring to FIG. 2 , the wiring locality of the integrated circuit layout model may be determined based on the vertex coordinates of the wiring buffer, wherein the wiring buffer may be a rectangular buffer, thereby obtaining the vertex coordinates of the rectangular buffer as the wiring area.

[0102] In step S103 of some embodiments, performing routing processing on the routing area according to the improved A-star search algorithm to obtain a routing path includes:

[0103] Step S1031: Obtain a cost weight factor;

[0104] Step S1032: determining a heuristic function of the improved A-star search algorithm according to the Manhattan distance;

[0105] Step S1033: performing cost optimization processing on the improved A-star search algorithm according to the cost weight factor and the heuristic function to obtain an optimized cost function;

[0106] Step S1034 : performing search and routing processing on the routing area according to the optimized cost function to obtain a routing path.

[0107] In step S1031 of some embodiments, a cost weight factor is obtained, wherein the cost weight factor includes a weight factor for controlling a wiring speed, which needs to be determined according to specific wiring requirements.

[0108] In step S1032 of some embodiments, a heuristic function for improving the A-star search algorithm is determined based on the Manhattan distance. Since integrated circuit wiring generally stipulates that routing can only be horizontal or vertical paths, the embodiment of the present application uses the Manhattan distance as a heuristic function for further improvement.

[0109] In step S1033 of some embodiments, the improved A-star search algorithm is subjected to cost optimization processing according to the cost weight factor and the heuristic function to obtain an optimized cost function. Among them, the A-star algorithm is a commonly used heuristic search algorithm, which is usually used to find the shortest path or optimal solution in a graph or network. It combines the characteristics of the shortest path search and greedy optimization search of the Dijkstra algorithm to find the optimal path from the starting point to the target point in the graph in an efficient way. The A-star algorithm uses the total cost f(n) to evaluate the priority of each node. The total cost consists of two parts: the actual cost g(n) from the starting point to the current node, and the estimated cost h(n) from the current node to the target node. That is, f(n) = g(n) + h(n). When the vertical coordinates of the pins are very large, the traditional A-star search algorithm is used for wiring. Due to the large solution space, it is very easy to cause a decrease in wiring speed, or even memory leaks, resulting in wiring failure. To address this problem, the present invention makes corresponding optimizations to the cost function, and the optimized cost function is: f(n) = g(n) + h(n) * w, where w= α is a weight factor that controls the routing speed and needs to be determined based on the specific routing requirements. After changing to this cost function, the algorithm will search for points with lower costs more quickly in the initial search phase, significantly improving the overall routing efficiency.

[0110] In step S1032 of some embodiments, performing routing processing on the routing area according to the optimized cost function to obtain a routing path includes:

[0111] Performing a search point check process on the wiring area to determine a neighboring node to be selected;

[0112] Performing cost calculation on the neighboring nodes to be selected using the optimized cost function to obtain a node cost;

[0113] A target node is determined according to the node cost, and backtracing processing is performed on the target node to obtain a wiring path.

[0114] In an embodiment of the present application, a routing dictionary containing known connection relationships and routing areas is fed into an A-star routing algorithm optimized based on an exponential function. The coordinates of obstacles are also fed into the algorithm, allowing for a search point check within the routing area. During the A-star search process, the search point is first checked to see if it is within the routing area. If not, it is skipped. If it is, the search is checked to see if it is within an obstacle. If so, the node is skipped. If a point is both within the routing area and not within an obstacle, the node is considered a candidate neighbor node. The cost function is used to calculate the cost of each node, and the node with the lowest cost is selected as the new starting point, resulting in the candidate neighbor node. Once the target node is found, the termination condition is triggered, and the algorithm, starting from the target node, traces back along the parent nodes until it reaches the starting node. At each step, the algorithm sets the current node as its parent node until it reaches the starting node. During this process, each node on the path is added to the final path list. Finally, repeat the wiring for the next pair of pins. When all pins in a subnet are wired, add the information of the area around the net to the obstacle according to the wiring rules. It is important to avoid short circuits with other nets during the addition process. Repeat the above process for the next subnet until all nets are wired. With reference to Figure 3, the wiring path is obtained. The embodiment of the present application further improves the wiring speed and efficiency by improving the A-star algorithm to determine the detailed wiring area and optimizing the cost function through exponential function.

[0115] In step S104 of some embodiments, removing redundant line segments according to the routing path to obtain a post-processing path includes:

[0116] Checking and processing the wiring path according to the wiring rules to obtain the through-hole position and redundant line segments;

[0117] The wiring path is reset according to the through-hole position and the redundant line segment to obtain a post-processing path.

[0118] In the embodiment of the present application, after the improved A-star search algorithm completes routing for all nets, the routing path needs to be post-processed. Specifically, the routing path is checked by obtaining the corresponding routing rules to determine the via locations, and redundant line segments are removed based on the via locations to obtain a post-processed path. The embodiment of the present application improves the reliability of integrated circuit routing by post-processing the routing path to remove redundant line segments.

[0119] In step S105 of some embodiments, referring to FIG. 4 , after dictionary conversion processing is performed on the post-processing path, a wiring layout can be obtained.

[0120] Below, the solution of the embodiment of the present application is described in detail and explained in combination with specific application scenarios:

[0121] The embodiment of the present application is applied to the wiring scenario of integrated circuits. By combining the wiring pin position relationship, optimization algorithm, and wiring algorithm, an integrated circuit wiring method of joint particle swarm optimization and A-star search is carried out. Among them, the wiring pin position relationship is determined by using the discrete particle swarm optimization (DPSO) algorithm to construct a rectangular Steiner tree to determine the connection relationship and the approximate wiring range, thereby reducing the wiring search space. At the same time, the optimization algorithm adopts a simulated annealing strategy when updating particles to avoid falling into the local optimal situation; the wiring algorithm adopts an improved A-star search algorithm to determine the detailed wiring area, and at the same time performs exponential function optimization on the cost function to further improve the wiring speed and improve the wiring efficiency.

[0122] Referring to FIG. 5 , an embodiment of the present application further provides an integrated circuit wiring system that can implement the above-mentioned integrated circuit wiring method. The system includes:

[0123] The first module 501 is used to obtain an integrated circuit layout model;

[0124] The second module 502 is configured to perform wiring area generation processing on the integrated circuit layout model according to a particle swarm optimization algorithm to obtain a wiring area;

[0125] The third module 503 is configured to perform routing processing on the routing area according to the improved A-star search algorithm to obtain a routing path;

[0126] The fourth module 504 is configured to remove redundant line segments according to the wiring path to obtain a post-processing path;

[0127] The fifth module 505 is configured to perform dictionary conversion processing on the post-processing path to obtain a wiring layout.

[0128] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0129] The present application also provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned integrated circuit wiring method when executing the computer program. The electronic device can be any smart terminal including a tablet computer, an in-vehicle computer, or the like.

[0130] It can be understood that the contents of the above method embodiments are applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0131] Please refer to FIG6 , which illustrates a hardware structure of an electronic device according to another embodiment. The electronic device includes:

[0132] The processor 601 may be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0133] The memory 602 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called by the processor 601 to execute the XXX method of the embodiments of this application.

[0134] Input / output interface 603, used to implement information input and output;

[0135] Communication interface 604, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0136] Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 );

[0137] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0138] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned XXX method is implemented.

[0139] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiment, the functions specifically implemented by the present storage medium embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0140] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0141] The integrated circuit wiring method, system, device and medium provided in the embodiments of the present application determine a rectangular Steiner tree based on a discrete particle swarm optimization algorithm to perform preliminary planning of the wiring area, and then use an improved A-star search algorithm to further perform detailed wiring of the wiring area to obtain a wiring path. The discrete particle swarm optimization algorithm can be used to construct a rectangular Steiner tree to determine the connection relationship and the approximate wiring range, thereby reducing the wiring search space. At the same time, a simulated annealing strategy is added when the particles are updated to avoid falling into the local optimal situation; the improved A-star search algorithm is used to determine the detailed wiring area, and the cost function is optimized by exponential function to further improve the wiring speed and improve the wiring efficiency.

[0142] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0143] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0144] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0145] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0146] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0147] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0151] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0152] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. An integrated circuit wiring method, characterized in that, The method includes: Obtaining an integrated circuit layout model; Performing wiring area generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a wiring area, and performing wiring processing on the wiring area according to the improved A* search algorithm to obtain a wiring path; Performing redundant line segment removal processing on the wiring path to obtain a post-processing path; Performing dictionary conversion processing on the post-processing path to obtain a wiring layout.

2. The method according to claim 1, wherein The performing wiring area generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a wiring area includes: Performing right-angled Steiner tree generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a right-angled Steiner tree; Determining pin connection relationships and wiring methods according to the right-angled Steiner tree; Performing partitioning processing on the integrated circuit layout model according to the pin connection relationships and the wiring methods to obtain a wiring buffer; Determining the wiring area of the integrated circuit layout model according to the vertex coordinates of the wiring buffer.

3. The method according to claim 2, characterized in that, The performing right-angled Steiner tree generation processing on the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a right-angled Steiner tree includes: Obtaining an acceptance probability and layout parameters of the integrated circuit layout model; Performing initialization processing on the layout parameters and generating an initial particle population randomly distributed in the solution space according to the layout parameters; Performing fitness calculation processing on the initial particle population according to a fitness function to obtain an initial fitness; Performing update processing on the initial particle population to obtain an updated particle population; Performing fitness calculation processing on the updated particle population according to the fitness function to obtain an updated fitness; Comparing the updated fitness with the initial fitness according to the acceptance probability to obtain a comparison result; When the comparison result satisfies a termination condition, generating a right-angled Steiner tree according to the updated particle population; Otherwise, returning to the step of performing update processing on the initial particle population.

4. The method according to claim 3, wherein The obtaining the acceptance probability includes: Setting an initial temperature and a temperature update formula; Performing reduction processing on the initial temperature according to the temperature update formula to obtain a temperature adjustment table; Obtaining the acceptance probability according to the temperature adjustment table.

5. The method according to claim 1, wherein The performing wiring processing on the wiring area according to the improved A* search algorithm to obtain a wiring path includes: Obtaining a cost weight factor; Determining a heuristic function of the improved A* search algorithm according to the Manhattan distance; Performing cost optimization processing on the improved A* search algorithm according to the cost weight factor and the heuristic function to obtain an optimized cost function; Performing search wiring processing on the wiring area according to the optimized cost function to obtain a wiring path.

6. The method according to claim 5, wherein The performing wiring processing on the wiring area according to the optimized cost function to obtain a wiring path includes: Performing search point inspection processing on the wiring area to determine candidate neighbor nodes; Performing cost calculation processing on the candidate neighbor nodes through the optimized cost function to obtain node costs; Determining target nodes according to the node costs and performing backtracking processing on the target nodes to obtain a wiring path.

7. The method according to any one of claims 1 to 6, characterized in that Performing a removal process on the redundant line segments according to the wiring path to obtain a post - processed path, including: Checking the wiring path according to wiring rules to obtain the via positions and redundant line segments; Resetting the wiring path according to the via positions and the redundant line segments to obtain a post - processed path.

8. An integrated circuit wiring system, characterized in that, The system includes: A first module for obtaining an integrated circuit layout model; A second module for generating a wiring area for the integrated circuit layout model according to the particle swarm optimization algorithm to obtain a wiring area; A third module for performing a wiring process on the wiring area according to the improved A* search algorithm to obtain a wiring path; A fourth module for performing a removal process on the redundant line segments according to the wiring path to obtain a post - processed path; A fifth module for performing a dictionary conversion process on the post - processed path to obtain a wiring layout.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the method according to any one of claims 1 to 7 is implemented.

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