Method and device for forming yield map, readable storage medium and terminal

Abstract

A yield wafer map forming method and device, readable storage medium and terminal, the method comprising: determining a first shape wafer map based on a preset number of lateral chips and a number of longitudinal chips; determining the number and position of failed chips in the first shape wafer map based on a set pattern formed by the failed chips; and obtaining a second shape yield wafer map corresponding to the first shape wafer map based on the number and position of failed chips in the first shape wafer map. The present application has the opportunity to improve the accuracy and convenience of failed chip marking, and can effectively reduce the total amount of drawing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a yield wafer map forming method and device, readable storage medium and terminal. BACKGROUND

[0002] Yield wafer map refers to a main body being a circular pattern that distinguishes chips that can work normally and chips that cannot work normally on a wafer by using different numbers and / or different colors. The chips that cannot work normally can also be referred to as "failed chips".

[0003] The positions of failed chips caused by different production process problems on the wafer are often different, and the patterns formed by the failed chips are often different. Therefore, the pattern features formed by the failed chips gathered on the yield wafer map can be used as an important clue to find the causes of failure.

[0004] With the development of mathematical models, the analysis technology of failed chips also uses the model to identify the causes of failure. In the process of identification, a large number of yield wafer maps with known failure causes are needed to train the model. However, in the prior art, the machine automatically draws, which has the problems of large amount of calculation and easy to produce calculation error. SUMMARY

[0005] The technical problem solved by the present application is to provide a yield wafer map forming method and device, readable storage medium and terminal, which can improve the accuracy and convenience of failed chip marking, and can effectively reduce the total amount of drawing.

[0006] To solve the above technical problem, the present application provides a yield wafer map forming method, comprising: determining a first shape wafer map based on a preset number of horizontal chips and a number of vertical chips; determining the number and position of failed chips in the first shape wafer map based on the formed pattern of the failed chips; obtaining a second shape yield wafer map corresponding to the first shape wafer map based on the number and position of failed chips in the first shape wafer map.

[0007] Optionally, the determining the first shape wafer map based on the preset number of horizontal chips and the number of vertical chips comprises: determining the number of horizontal chips and the number of vertical chips of the wafer map; using one of the number of horizontal chips and the number of vertical chips as a semi-major axis length and the other as a semi-minor axis length to form a first ellipse; forming an elliptical wafer map based on the first ellipse, wherein each chip in the elliptical wafer map is represented by a square with a unit length of side length.

[0008] Optionally, based on the first ellipse, forming an elliptical wafer map comprises: determining a first integer solution set satisfying the following formula:

[0009]

[0010] Marking the position of the chip with the coordinates corresponding to each pair of integer solutions in the first integer solution set to obtain the elliptical wafer map; wherein the integer solutions in the integer solution set correspond one-to-one to the chips in the elliptical wafer map, and each integer solution corresponds to the unit length abscissa and unit length ordinate of the chip respectively; a is the number of chips in the transverse direction, and b is the number of chips in the longitudinal direction.

[0011] Optionally, based on the pattern formed by the set of failed chips, determining the number and position of failed chips in the first shape wafer map comprises: determining the failure type based on the pattern formed by the set of failed chips; and marking the failed chips in the elliptical wafer map according to the determined failure type.

[0012] Optionally, marking the failed chips in the elliptical wafer map comprises: determining a yield value; and determining a second integer solution set satisfying the following formula:

[0013]

[0014] In the second integer solution set, a number of integer solutions equal to P×(1-g%) are selected, where P represents the number of integer solutions in the second integer solution set, and g% represents the yield value; and the position of the failed chips is marked with the selected integer solutions as coordinates to obtain a failed yield wafer map; wherein a is the number of chips in the transverse direction, and b is the number of chips in the longitudinal direction.

[0015] Optionally, marking the failed chips in the elliptical wafer map comprises: determining a first axis length ratio and a chip failure ratio, the values of the first axis length ratio and the chip failure ratio being taken from between 0 and 1; and determining a third integer solution set satisfying the following formula:

[0016]

[0017] In the third integer solution set, a number of integer solutions equal to Q×f% are selected, where Q represents the number of integer solutions in the third integer solution set, and f% represents the chip failure ratio; and the position of the failed chips is marked with the selected integer solutions as coordinates to obtain a center failed yield wafer map; wherein r1 represents the first axis length ratio, a is the number of chips in the transverse direction, and b is the number of chips in the longitudinal direction.

[0018] Optionally, the method further comprises: determining a second axis length ratio, wherein the second axis length ratio is selected from a range of 0 to 1, and the second axis length ratio is greater than the first axis length ratio; determining a fourth integer solution set satisfying the following formula:

[0019]

[0020] removing, from the fourth integer solution set, integer solutions coinciding with the third integer solution set to obtain a fifth integer solution set; selecting integer solutions with a number of Sxf% from the fifth integer solution set, wherein S represents the number of integer solutions in the fifth integer solution set; and marking positions of the failed chips with each selected integer solution as a coordinate to obtain a ring-shaped failure yield wafer map, wherein r2 represents the second axis length ratio, and r2 is selected from a range of 0 to 1.

[0021] Optionally, the method further comprises: determining a sixth integer solution set satisfying the following formula:

[0022]

[0023] removing, from the sixth integer solution set, integer solutions coinciding with the fourth integer solution set to obtain a seventh integer solution set; selecting integer solutions with a number of Txf% from the seventh integer solution set, wherein T represents the number of integer solutions in the seventh integer solution set; and marking positions of the failed chips with each selected integer solution as a coordinate to obtain an edge failure yield wafer map.

[0024] Optionally, the marking of the failed chips in the elliptical wafer map comprises: determining an eighth integer solution set satisfying the following formula:

[0025]

[0026] randomly selecting two integer solutions from the eighth integer solution set; forming a first straight line passing through the two integer solutions as coordinates; moving the first straight line to obtain one or more moved first straight lines; determining, for each moved first straight line, a ninth integer solution set of the moved first straight line; determining intersection integer solutions of the eighth integer solution set and the ninth integer solution set; and marking positions of the failed chips with the intersection integer solutions of the eighth integer solution set and the ninth integer solution set as coordinates to obtain a linear failure yield wafer map, wherein a represents the number of horizontal chips, and b represents the number of vertical chips.

[0027] Optionally, the marking of the failed chips in the elliptical wafer map comprises: determining a tenth integer solution set satisfying the following formula:

[0028]

[0029] From the tenth set of integer solutions, a single integer solution (x) is randomly selected. 10 1 , y 10 1); Determine x≥x in the tenth integer solution set. 10 1 and y≤y 10 The eleventh integer solution set of 1, and determining x < x in the tenth integer solution set. 10 1 and y≤(y 10 The twelfth integer solution set of 1-1); using the integer solutions in the eleventh integer solution set and the twelfth integer solution set as coordinates, mark the position of the failed chip to obtain the test abnormal yield wafer map; where a is the number of horizontal chips and b is the number of vertical chips.

[0030] Optionally, marking failed chips in the elliptical wafer diagram includes: determining the set of thirteenth integer solutions that satisfy the following formula:

[0031]

[0032] From the thirteenth set of integer solutions, a single integer solution (x) is randomly selected. 13 1 , y 13 1); with the integer solution (x) 13 1 , y 13 1) is the coordinate system, originating from the center of the elliptical wafer diagram and passing through the integer solution (x). 13 1 ,y 13 1) The second straight line of coordinates; determine the distance M× from the starting point on the second straight line. The endpoint is defined, where M is a positive rational number and M > 1; with the endpoint as the center, and N×a and N×b as the semi-major axis and semi-minor axis respectively, a second ellipse is formed, which covers a portion of the chips in the elliptical wafer diagram, where N is a positive rational number and N > 1; the fourteenth integer solution set of the second ellipse is determined; the intersection integer solution of the thirteenth integer solution set and the fourteenth integer solution set is determined; the position of the failed chip is marked with the intersection integer solution of the thirteenth integer solution set and the fourteenth integer solution set as coordinates to obtain an arc-shaped failure yield wafer diagram; where a is the number of horizontal chips and b is the number of vertical chips.

[0033] Optionally, marking the failed chips in the elliptical wafer map comprises: determining each exposure square in the elliptical wafer map, the number of chips contained in each exposure square in the transverse direction being the same, and the number of chips contained in each exposure square in the longitudinal direction being the same; determining a fifteenth integer solution set satisfying the following formula:

[0034]

[0035] In the fifteenth integer solution set, a single integer solution (x 15 1 , y 15 1) is randomly selected; the exposure square to which the chip corresponding to the integer solution (x 15 1 , y 15 1) belongs is determined, and a first adjacent chip of the chip corresponding to the integer solution (x 15 1 , y 15 1) is randomly selected in the exposure square, then one of one or more second adjacent chips adjacent to the first adjacent chip is randomly selected, then one of one or more third adjacent chips adjacent to the second adjacent chip is randomly selected, until the number of selections reaches j, where j is a positive integer, and 1 15 1 , y 15 1), the first adjacent chip, and the jth adjacent chip obtained by j times of random selection are taken as coordinates, and the position of the failed chip is marked; the position of the failed chip is copied in at least part of the other exposure squares to obtain a step-failed-yield wafer map; where a is the number of chips in the transverse direction, and b is the number of chips in the longitudinal direction.

[0036] Optionally, marking the failed chips in the elliptical wafer map comprises: determining a sixteenth integer solution set satisfying the following formula:

[0037]

[0038] In the sixteenth integer solution set, a single integer solution (x 16 1 , y 16 1) is randomly selected; the exposure square to which the chip corresponding to the integer solution (x 16 1 , y 161) the first adjacent chip of the corresponding chip, then randomly selecting one of the one or more second adjacent chips adjacent to the first adjacent chip, then randomly selecting one of the one or more third adjacent chips adjacent to the second adjacent chip, until the number of selections reaches k, wherein k is a positive integer, and 1 < k < (K x e%), K is the number of integer solutions in the sixteenth set of integer solutions, and e% is a first preset percentage; taking the integer solution (x 16 1 , y 16 1) of the kth adjacent chip obtained by the kth random selection as the coordinates of the failed chip, and marking the position of the failed chip, to obtain a block failure yield wafer map; wherein a is the number of chips in the lateral direction, and b is the number of chips in the longitudinal direction.

[0039] Optionally, after marking the failed chips in the elliptical wafer map, the method further comprises: determining a seventeenth set of integer solutions that satisfy the following formula:

[0040]

[0041] In the seventeenth set of integer solutions, one or more integer solutions (x 17 i , y 17 i) are randomly selected, wherein i is used to represent the ith integer solution; in the elliptical wafer map, the union integer solution of the one or more integer solutions (x 17 i , y 17 i) and the integer solutions of the marked failed chips is determined; taking the union integer solution as the coordinates of the failed chip, the position of the failed chip is updated to obtain the elliptical yield wafer map; wherein a is the number of chips in the lateral direction, and b is the number of chips in the longitudinal direction.

[0042] Optionally, the first shape wafer map is an elliptical wafer map, and the second shape wafer map is a circular wafer map; obtaining the second shape yield wafer map corresponding to the first shape wafer map based on the number and position of the failed chips in the first shape wafer map comprises: converting the elliptical yield wafer map into a circular yield wafer map.

[0043] Optionally, before converting the elliptical yield wafer map into a circular yield wafer map, the method for forming a yield wafer map further comprises: in the elliptical yield wafer map, marking a preset proportion of failed chips as normal chips.

[0044] Optionally, in the elliptical yield wafer map, marking the failure chips of the preset proportion as normal chips comprises: performing random sampling by using a random sampling function to obtain the failure chips of the preset proportion; and updating the positions of the failure chips in the elliptical yield wafer map by taking the integer solutions corresponding to the failure chips after the random sampling as coordinates.

[0045] Optionally, converting the elliptical yield wafer map into a circular yield wafer map comprises: for the integer solution corresponding to each failure chip in the elliptical yield wafer map, determining the integer solution corresponding to the failure chip in the circular yield wafer map by using the following formula:

[0046] (x c ,y c )= (D / a × x E , D / b × y E )

[0047] marking the positions of the failure chips in the circular yield wafer map by taking the integer solution corresponding to each failure chip in the circular yield wafer map as coordinates; wherein D is used to represent the diameter of the wafer, (x E , y E ) is used to represent the integer solution corresponding to the failure chip in the elliptical yield wafer map, (x c ,y c ) is used to represent the integer solution corresponding to the failure chip in the circular yield wafer map, and each integer solution corresponds to the unit length abscissa and unit length ordinate of the chip respectively.

[0048] To solve the above technical problem, an embodiment of the present application provides a yield wafer map forming device, comprising: a first shape forming module configured to determine a first shape wafer map based on a preset number of lateral chips and a preset number of longitudinal chips; a failure determining module configured to determine the number and positions of failure chips in the first shape wafer map based on a preset pattern formed by the failure chips; and a second shape obtaining module configured to obtain a second shape yield wafer map corresponding to the first shape wafer map based on the number and positions of the failure chips in the first shape wafer map.

[0049] To solve the above technical problem, an embodiment of the present application provides a readable storage medium having a computer program stored thereon, wherein the computer program is run on a processor to perform the steps of the yield wafer map forming method.

[0050] To solve the above technical problem, an embodiment of the present application provides a terminal comprising a memory and a processor, wherein the memory has a computer program stored thereon, the computer program is capable of being run on the processor, and the processor is run to perform the steps of the yield wafer map forming method when the computer program is run.

[0051] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0052] In the embodiment of the present application, first, the first shape wafer map is determined based on the preset number of chips in the transverse direction and the number of chips in the longitudinal direction, then the number and position of the failed chips in the first shape wafer map are determined based on the set pattern formed by the failed chips, and then the second shape yield wafer map corresponding to the first shape wafer map is obtained, so that the accuracy and convenience of the failed chip marking are improved through shape conversion. In addition, the yield wafer map is drawn based on the number of chips in the transverse direction and the number of chips in the longitudinal direction, and each number of chips can correspond to a large number of chip sizes. For example, for a yield wafer map composed of 100x50 chips, the width of the chips can be any value between 2.95mm and 3.05mm. Therefore, compared with determining the shape wafer map based on the chip size, the total amount of drawing can be effectively reduced by using the scheme of the embodiment of the present application.

[0053] Further, one of the number of chips in the transverse direction and the number of chips in the longitudinal direction is used as the semi-major axis length, and the other is used as the semi-minor axis length to form a first ellipse, and based on the first ellipse, an elliptical wafer map is formed, wherein each chip in the elliptical wafer map is represented by a square with a unit length of side. By using the above scheme, no matter what the aspect ratio of the chip is, each chip can be marked as a square with a unit length of side in the elliptical wafer map, so that in the automatic drawing process of the machine, for each failed chip, the four corner coordinates of the failed chip do not need to be calculated, but the square with a unit length of side is directly marked, thereby effectively reducing the amount of calculation, and in the same failure mode, the positions of the failed chips are unified, and there is no calculation error.

[0054] Further, after the elliptical wafer map is formed, the positions and numbers of the failed chips can be obtained according to the preset failure types and the standard equation of the ellipse to form a plurality of types of elliptical yield wafer maps, thereby meeting the demand that a large number of yield wafer maps can be drawn under a plurality of failure causes.

[0055] Further, in the elliptical wafer map, the set of integer solutions (x 17 i , y 17 i) randomly selected one or more integer solutions and the integer solutions of the marked failed chips can be added to various types of elliptical yield wafer maps, which can make the automatically formed yield wafer map closer to the actual yield result.

[0056] Further, in the elliptical yield wafer map, the failure chips of a preset proportion are marked as normal chips, so that the difference between the pattern formed by the failure chips in the automatically formed yield wafer map and the yield wafer map obtained in actual production can be avoided, and the automatically formed yield wafer map is further closer to the actual yield result. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 is a schematic diagram of a circular yield wafer map in the prior art;

[0058] Figure 2 is a flowchart of a yield wafer map forming method in an embodiment of the present application;

[0059] Figure 3 is a schematic diagram of an elliptical wafer map in an embodiment of the present application;

[0060] Figure 4 is a schematic diagram of an elliptical random failure yield wafer map in an embodiment of the present application;

[0061] Figure 5 is a schematic diagram of an elliptical center failure yield wafer map in an embodiment of the present application;

[0062] Figure 6 is a schematic diagram of an elliptical ring failure yield wafer map in an embodiment of the present application;

[0063] Figure 7 is a schematic diagram of an elliptical edge failure yield wafer map in an embodiment of the present application;

[0064] Figure 8 is a schematic diagram of an elliptical line failure yield wafer map in an embodiment of the present application;

[0065] Figure 9 is a schematic diagram of an elliptical test abnormality yield wafer map in an embodiment of the present application;

[0066] Figure 10 is a schematic diagram of an elliptical arc failure yield wafer map in an embodiment of the present application;

[0067] Figure 11 is a schematic diagram of an elliptical step failure yield wafer map in an embodiment of the present application;

[0068] Figure 12 is a schematic diagram of an elliptical block failure yield wafer map in an embodiment of the present application;

[0069] Figure 13 is a schematic diagram of an elliptical yield wafer map after adding randomly selected failure chips in an embodiment of the present application;

[0070] Figure 14 is a schematic diagram of converting an elliptical yield wafer map into a circular yield wafer map in an embodiment of the present application;

[0071] Figure 15 is a structural schematic diagram of a yield wafer map forming device in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In the prior art, when a model is established to identify and classify failure causes, a large number of yield wafer maps with known failure causes are needed to train the model. In addition, for newly established chip production enterprises, models and software need to be purchased to analyze the produced wafers. Due to the lack of sufficient actual yield results, the performance of these products in terms of function, effectiveness, accuracy, speed and other aspects cannot be evaluated and compared.

[0073] Specifically, there are currently many commercial software that can automatically achieve the purpose of "automatically classifying yield wafer maps according to different failure characteristics", such as Odyssey products, Ace products and some emerging artificial intelligence team products. However, the creators of these products are electronic design automation (EDA) or software companies, and they do not have, nor can they obtain, yield wafer map data from chip companies for training.

[0074] On the one hand, because these wafer map data contain rich details and business secrets, such as how the yield level of the enterprise is, how much the monthly shipment is, what the main possible yield problems and quality concerns are, etc., which can be inferred from the yield wafer map, they are often protected as business secrets. On the other hand, in the yield wafer map based on real production, there may be more than one error type, resulting in poor model training effect.

[0075] As can be seen from the above, in the prior art, a large number of yield wafer maps with known failure causes are needed to train the model. However, in the prior art, machine automatic drawing is used, which has the problems of large amount of calculation and easy calculation error.

[0076] REFERENCE Figure 1 , Figure 1 is a schematic diagram of a circular yield wafer map in the prior art. The circular yield wafer map contains a plurality of regularly arranged chips, one or more of which are defective chips.

[0077] In the machine automatic drawing process, for each defective chip, the area where the defective chip is located needs to be labeled, such as labeling the entire chip as red.

[0078] The inventor of the present application has found through research that in the prior art, for each failed chip, the four corner coordinates of the failed chip need to be calculated, and then the area where the failed chip is located is labeled. Because the aspect ratios of chips in different wafers often differ greatly, for example, chips with aspect ratios of 10:1 and 10:9 will form very different patterns under the same failure mode. Therefore, in the step of calculating the four corner coordinates of the failed chip, the amount of calculation is very large, resulting in low drawing efficiency and being prone to calculation errors.

[0079] In the embodiment of the present application, the first shape wafer map is determined based on the preset number of chips in the horizontal direction and the number of chips in the vertical direction, then the number and position of the failed chips in the first shape wafer map are determined based on the set position of the failed chips, and a second shape yield wafer map corresponding to the first shape wafer map is obtained, so that through shape conversion, there is an opportunity to improve the accuracy and convenience of failed chip labeling. In addition, the yield wafer map is drawn based on the number of chips in the horizontal direction and the number of chips in the vertical direction, and each chip number can correspond to countless chip sizes. For example, a yield wafer map composed of 100x50 chips, the width of the chip can be any value between 2.95mm and 3.05mm. Therefore, compared with determining the shape wafer map based on the chip size, the scheme of the embodiment of the present application can effectively reduce the total amount of drawing.

[0080] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0081] Reference Figure 2 , Figure 2 is a flowchart of a yield wafer map forming method in an embodiment of the present application. The yield wafer map forming method can include steps S21 to S23:

[0082] Step S21: determining a first shape wafer map based on a preset number of chips in the horizontal direction and a number of chips in the vertical direction;

[0083] Step S22: determining the number and position of failed chips in the first shape wafer map based on the pattern formed by the failed chips;

[0084] Step S23: obtaining a second shape yield wafer map corresponding to the first shape wafer map based on the number and position of failed chips in the first shape wafer map.

[0085] In the implementation of step S21, the step of determining the first shape wafer map based on the preset number of lateral chips and the number of longitudinal chips can include: determining the number of lateral chips and the number of longitudinal chips of the wafer map; taking one of the number of lateral chips and the number of longitudinal chips as a semi-major axis length and the other as a semi-minor axis length to form a first ellipse; and forming an elliptical wafer map based on the first ellipse, wherein each chip in the elliptical wafer map is represented by a square with a unit length of side.

[0086] Referring to Figure 3 , Figure 3 is a schematic diagram of an elliptical wafer map in an embodiment of the present application. The elliptical wafer map is converted from the circular wafer map shown in Figure 1

[0087] In the elliptical wafer map formed by taking one of the number of lateral chips and the number of longitudinal chips as a semi-major axis length and the other as a semi-minor axis length, the shape of each chip is a square. Therefore, in the actual manufacturing process, no matter what the aspect ratio of the chip is, each chip can be marked as a square with a unit length in the elliptical wafer map.

[0088] In the drawing process, the chips in the elliptical wafer map can be represented by a square with a unit length of side, and each chip can be represented by a unit length x a unit length, for example, can be simplified to 1 x 1, thereby further reducing the complexity of the operation.

[0089] Further, the step of forming an elliptical wafer map based on the first ellipse can include: determining a first set of integer solutions that satisfy the following formula:

[0090]

[0091] Marking the position of each chip with the coordinates corresponding to each pair of integer solutions in the first set of integer solutions to obtain the elliptical wafer map; wherein the integer solutions in the set of integer solutions correspond one-to-one to the chips in the elliptical wafer map, and each integer solution corresponds to the unit length horizontal coordinate and the unit length vertical coordinate of the chip; a is the number of lateral chips and b is the number of longitudinal chips.

[0092] Specifically, after determining the one-to-one correspondence between the integer solutions in the set of integer solutions and the chips in the elliptical wafer map, each chip can be represented by an integer solution (x, y) to indicate the position. As shown in Figure 3 two chips can be represented by integer solution (1, 1) and integer solution (2, 1), respectively.

[0093] ​In the embodiment of the present application, one of the transverse chip quantity and the longitudinal chip quantity is taken as a semi-major axis length, and the other is taken as a semi-minor axis length to form a first ellipse, and based on the first ellipse, an elliptical wafer map is formed, wherein each chip in the elliptical wafer map is represented by a square with a unit length of side. With the above scheme, no matter what the length-width ratio of the chip is, each chip can be marked as a square with a unit length of side in the elliptical wafer map, so that in the automatic drawing process, for each failed chip, the four corner coordinates of the failed chip do not need to be calculated, but the square with a unit length of side is directly marked, thereby effectively reducing the amount of calculation, and in the same failure mode, the positions of the failed chips are unified, and there is no calculation error.

[0094] With reference to the above description Figure 2 In the implementation of step S22, the step of determining the number and position of the failed chips in the first-shaped wafer map based on the set failed chip-formed pattern can include: determining a failure type based on the set failed chip-formed pattern; and marking the failed chips in the elliptical wafer map according to the determined failure type.

[0095] After the elliptical wafer map is formed, the positions and number of the failed chips can be obtained according to the preset failure type and the elliptical standard equation, and a plurality of types of elliptical yield wafer maps are formed, thereby meeting the demand that a large number of yield wafer maps can be drawn under a plurality of failure causes.

[0096] As a non-limiting example, the set position of the failed chips can include the following types: a random failure type, a center failure type, a ring failure type, an edge failure type, a line failure type, a test abnormality type, an arc failure type, a step failure type, and a block failure type.

[0097] As understood by those skilled in the art, the failure type is determined by the arrangement and layout of the failed chips on the wafer pattern, for example, if the main shape of the failed chips is a ring, it is a ring failure type, if the failed chips are irregularly distributed, it is a random failure type, if the failed chips are mainly concentrated in the center of the wafer pattern, it is a center failure type, if the failed chips are mainly distributed on the edge of the wafer, it is an edge failure type, if the failed chips mainly form a line, it is a line failure type, if the failed chips mainly form a ring, it is a ring failure type, if the failed chips mainly form a shape that repeatedly appears from one exposure shot to another, it is a step failure type, if the failed chips are only distributed in other chips measured before a certain chip is measured, it is a test abnormality type, and if the failed chips are gathered within a certain range, it is a block failure type.

[0098] It should be noted that there can be more than one type of failure distribution in a wafer, which can be in a combined manner.

[0099] It should be noted that other failure types or combinations of multiple failure types can be set according to specific requirements, so that the yield wafer map formed can better train the model.

[0100] Referring to Figure 4 , Figure 4 is a schematic diagram of an elliptical random failure yield wafer map in an embodiment of the present application.

[0101] Specifically, the step of marking the failed chips in the elliptical wafer map can include: determining a yield value; determining a second integer solution set that satisfies the following formula:

[0102]

[0103] In the second integer solution set, select integer solutions with a quantity of P x (1-g%), where P represents the number of integer solutions in the second integer solution set, and g% represents the yield value; mark the positions of the failed chips with each selected integer solution as a coordinate to obtain a failure yield wafer map; where a is the number of transverse chips, and b is the number of longitudinal chips.

[0104] Further, in the second integer solution set, the step of selecting integer solutions with a quantity of P x (1-g%) can include: randomly selecting integer solutions with a quantity of P x (1-g%) or sequentially selecting integer solutions with a quantity of P x (1-g%).

[0105] Wherein, after randomly selecting integer solutions with a quantity of P x (1-g%), the positions of the failed chips are marked with each selected integer solution as a coordinate, and a random failure yield wafer map can be obtained, that is Figure 4 the elliptical random failure yield wafer map shown in FIG.

[0106] In an embodiment of the present application, by changing the value of g% (which can make g% step between 0~100%), random failure yield wafer maps with different yield levels can be generated.

[0107] Referring to Figure 5 , Figure 5 is a schematic diagram of an elliptical center failure yield wafer map in an embodiment of the present application.

[0108] Specifically, the step of marking the failed chips in the elliptical wafer map can include: determining a first axis length ratio and a chip failure ratio, both of which are taken from 0 to 1; determining a third integer solution set satisfying the following formula:

[0109]

[0110] In the third integer solution set, a number of Q×f% integer solutions are selected, where Q represents the number of integer solutions in the third integer solution set, and f% represents the chip failure ratio; the positions of the failed chips are marked with the selected integer solutions as coordinates to obtain a center failure yield wafer map; where r1 represents the first axis length ratio, a represents the number of horizontal chips, and b represents the number of vertical chips.

[0111] Specifically, as shown by the dashed line in Figure 5 , r1×a is less than a, and r1×b is less than b. A dashed line ellipse is formed with the center of the first ellipse as the center, one of r1×a and r1×b as the semi-major axis length, and the other as the semi-minor axis length. The failed chips are located within the dashed line ellipse to form a center failure yield wafer map.

[0112] In a specific implementation, in the third integer solution set, a number of Q×f% integer solutions are selected, and by changing f%, center failure yield wafer maps of different yield levels can be generated.

[0113] It should be noted that by changing r1, center failure yield wafer maps of different failure severity levels can be generated.

[0114] Further, the yield wafer map forming method can further include: determining a second axis length ratio, the value of which is taken from 0 to 1, and the second axis length ratio is greater than the first axis length ratio; determining a fourth integer solution set satisfying the following formula:

[0115]

[0116] In the fourth integer solution set, integer solutions coinciding with the third integer solution set are removed to obtain a fifth integer solution set; in the fifth integer solution set, a number of S×f% integer solutions are selected, where S represents the number of integer solutions in the fifth integer solution set; the positions of the failed chips are marked with the selected integer solutions as coordinates to obtain a ring-shaped failure yield wafer map; where r2 represents the second axis length ratio, and the value of r2 is taken from 0 to 1.

[0117] Referring to Figure 6 , Figure 6is a schematic diagram of an elliptical ring-shaped failure yield wafer map in an embodiment of the present application.

[0118] Specifically, as shown by the dashed lines in Figure 6 , r1x a, r2x a are all less than a, and r1x b, r2x b are all less than b. Taking one of r1x a and r1x b as a semi-major axis length and the other as a semi-minor axis length, a dashed-line ellipse of a smaller size is formed at the center of the first ellipse, and taking one of r2x a and r2x b as a semi-major axis length and the other as a semi-minor axis length, a dashed-line ellipse of a larger size is formed at the center, and the failure chips are located between the two dashed-line ellipses to form a ring-shaped failure yield wafer map.

[0119] In a specific implementation, in the fifth integer solution set, a number of Sxf% integer solutions are selected, and by changing f%, a center failure yield wafer map of different yield levels can be generated.

[0120] It should be noted that by changing r1 and r2, a center failure yield wafer map of different failure severity levels can be generated.

[0121] Further, the method for forming the yield wafer map can further include: determining a sixth integer solution set that satisfies the following formula:

[0122]

[0123] In the sixth integer solution set, integer solutions that coincide with the fourth integer solution set are removed to obtain a seventh integer solution set; in the seventh integer solution set, a number of Txf% integer solutions are selected, where T represents the number of integer solutions in the seventh integer solution set; and the positions of the failure chips are marked with the selected integer solutions as coordinates to obtain an edge failure yield wafer map.

[0124] Referring to Figure 7 , Figure 7 is a schematic diagram of an elliptical edge failure yield wafer map in an embodiment of the present application.

[0125] Specifically, as shown by the dashed lines in Figure 7 , r2x a are all less than a, and r2x b are all less than b. Taking one of r2x a and r2x b as a semi-major axis length and the other as a semi-minor axis length, a dashed-line ellipse is formed, and the failure chips are located outside the dashed-line ellipse and in the edge area to form an edge failure yield wafer map.

[0126] In a specific implementation, in the fifth integer solution set, a number of Txf% integer solutions are selected, and by changing f%, an edge failure yield wafer map of different yield levels can be generated.

[0127] It should be noted that by changing r2, edge failure yield wafer maps of different failure severity can be generated.

[0128] It should be particularly noted that the edge failure yield wafer map can also be determined by the following steps:

[0129] The fourth integer solution set satisfying r2=1 is determined by the following formula:

[0130] , and r2=1;

[0131] The integer solutions coinciding with the third integer solution set are removed from the fourth integer solution set of r2=1 to obtain the seventh integer solution set; in the seventh integer solution set, integer solutions with a number of Txf% are selected, where T represents the number of integer solutions in the seventh integer solution set; and the positions of the failed chips are marked with the selected integer solutions as coordinates to obtain the edge failure yield wafer map.

[0132] Specifically, r2 can be expanded to the edge of the wafer, a dotted oval is formed with the center of the first oval as the center, one of r1x a and r1x b as the half major axis length, and the other as the half minor axis length, the failed chips are located outside the dotted oval and in the edge area to form the edge failure yield wafer map.

[0133] Referring to Figure 8 , Figure 8 is a schematic diagram of an oval linear failure yield wafer map in an embodiment of the present application.

[0134] The step of marking the failed chips in the oval wafer map can include determining an eighth integer solution set satisfying the following formula:

[0135]

[0136] In the eighth integer solution set, two integer solutions are randomly selected; a first straight line passing through the coordinates of the two integer solutions is formed with the two integer solutions as coordinates; the first straight line is moved to obtain one or more moved first straight lines; for each moved first straight line, a ninth integer solution set of the moved first straight line is determined; the intersection integer solutions of the eighth integer solution set and the ninth integer solution set are determined; the positions of the failed chips are marked with the intersection integer solutions of the eighth integer solution set and the ninth integer solution set as coordinates to obtain the linear failure yield wafer map; where a is the number of horizontal chips and b is the number of vertical chips.

[0137] The step of moving the first straight line to obtain one or more translated first straight lines can include: moving the first straight line up and / or down by w chips and / or moving the first straight line left and / or right by w chips, where w can be selected from 1 to W, where W is a positive integer, to form the translated first straight line.

[0138] It should be noted that the plurality of translated first straight lines can also be combined, and a line-shaped failure yield wafer map with different failure severity levels can be simulated.

[0139] Referring to Figure 9 , Figure 9 is a schematic diagram of an oval-shaped test abnormal yield wafer map in an embodiment of the present application.

[0140] The step of marking the failure chip in the oval-shaped wafer map can include: determining a tenth set of integer solutions that satisfy the following formula:

[0141]

[0142] In the tenth set of integer solutions, a single integer solution (x 10 1 , y 10 1) is randomly selected; a twelfth set of integer solutions in which x 10 1 and y≤(y 10 1-1) is determined from the tenth set of integer solutions, and an eleventh set of integer solutions in which x≥x 10 1 and y≤y 10 1 is determined from the tenth set of integer solutions; the positions of the failure chips are marked with the integer solutions in the eleventh set of integer solutions and the twelfth set of integer solutions as coordinates to obtain a test abnormal yield wafer map; where a is the number of chips in the horizontal direction and b is the number of chips in the vertical direction.

[0143] Specifically, the first chip is randomly selected as a base point, and all chips measured before the chip are failure chips, that is, the twelfth set of integer solutions in which x 10 1 and y≤(y 10 1-1) and the eleventh set of integer solutions in which x≥x 10 1 and y≤y 10 1 are outlined with dashed lines.

[0144] Referring to Figure 10 , Figure 10 is a schematic diagram of an oval-shaped arc-shaped failure yield wafer map in an embodiment of the present application.

[0145] The step of marking the failure chip in the oval-shaped wafer map can include: determining a thirteenth set of integer solutions that satisfy the following formula:

[0146]

[0147] From the thirteenth set of integer solutions, a single integer solution (x) is randomly selected. 13 1 , y 13 1); with the integer solution (x) 13 1 , y 13 1) is the coordinate system, originating from the center of the elliptical wafer diagram and passing through the integer solution (x). 13 1 ,y 13 1) The second straight line of coordinates; determine the distance M× from the starting point on the second straight line. The endpoint is defined, where M is a positive rational number and M > 1; with the endpoint as the center, and N×a and N×b as the semi-major axis and semi-minor axis respectively, a second ellipse is formed, which covers a portion of the chips in the elliptical wafer diagram, where N is a positive rational number and N > 1; the fourteenth integer solution set of the second ellipse is determined; the intersection integer solution of the thirteenth integer solution set and the fourteenth integer solution set is determined; the position of the failed chip is marked with the intersection integer solution of the thirteenth integer solution set and the fourteenth integer solution set as coordinates to obtain an arc-shaped failure yield wafer diagram; where a is the number of horizontal chips and b is the number of vertical chips.

[0148] It is understood that, in the embodiments of the present invention, there is no restriction on whether the second ellipse is located inside or outside the first ellipse, that is, there is no restriction on the size relationship between M and N.

[0149] exist Figure 10 The illustrated method for forming a wafer image with arc-shaped failure simulates the fundamental mechanism of arc-shaped failure caused by chemical mechanical polishing (CMP) in actual production. When the polishing head rotates, impurities in the polishing slurry can cause scratches on the wafer surface, resulting in arc-shaped failure. The second ellipse can be considered a schematic diagram of the polishing head.

[0150] Reference Figure 11 , Figure 11 This is a schematic diagram of an elliptical step failure yield wafer diagram in an embodiment of the present invention.

[0151] The step of marking failed chips in the elliptical wafer diagram may include: determining each exposure square (shot) in the elliptical wafer diagram, wherein the horizontal number of chips contained in each exposure square is the same, and the vertical number of chips contained in each exposure square is the same; and determining the fifteenth integer solution set satisfying the following formula:

[0152]

[0153] In the fifteenth integer solution set, a single integer solution (x 15 1 , y 15 1) is randomly selected; the exposure square to which the chip corresponding to the integer solution (x 15 1 , y 15 1) belongs is determined, and within the exposure square, a first adjacent chip of the chip corresponding to the integer solution (x 15 1 , y 15 1) is randomly selected, then one of one or more second adjacent chips adjacent to the first adjacent chip is randomly selected, and then one of one or more third adjacent chips adjacent to the second adjacent chip is randomly selected, until the number of selections reaches j, where j is a positive integer, and 1 < j < J, and J is the number of chips contained in a single exposure square; the integer solution of the integer solution (x 15 1 , y 15 1), the first adjacent chip, and the jth adjacent chip obtained by j times of random selection is taken as the coordinates, and the position of the failed chip is marked; in at least a part of other exposure squares, the position of the failed chip is copied to obtain a by-shot yield wafer map; where a is the number of chips in the horizontal direction, and b is the number of chips in the vertical direction.

[0154] Wherein, j can be stepped between 2 and (J-1) to form a more comprehensive block yield wafer map.

[0155] Further, the step of determining the exposure square to which the chip corresponding to the integer solution (x 15 1 , y 15 1) belongs can include: determining the number of horizontal exposure squares H and the number of vertical exposure squares V; determining the number of chips in the horizontal direction of each exposure square as the integer value of 2a / H, and determining the number of chips in the vertical direction of each exposure square as the integer value of 2a / V; and determining the exposure square to which each chip, including the chip corresponding to the integer solution (x 15 1 , y 15 1), belongs according to the number of chips in the horizontal direction and the number of chips in the vertical direction of each exposure square.

[0156] Wherein, the number of horizontal exposure squares and the number of vertical exposure squares can be a positive integer between 5 and 20 in a random manner, for example.

[0157] As shown by the arrow direction in the figure, from the second selection, in each selection, a chip adjacent to the previous chip is randomly selected, and the adjacent chips can be 2-8 in the exposure grid.

[0158] In Figure 11 the step-by-step failure yield wafer map shown, if the selection number includes randomly selecting a single integer solution (x 15 1 , y 15 1) as the first selection, then j=5; if the selection number excludes the step of randomly selecting a single integer solution (x 15 1 , y 15 1), then j=4.

[0159] In Figure 11 the step-by-step failure yield wafer map formation method shown, the basic mechanism of the step-by-step failure caused by the photoetching process in actual production is simulated.

[0160] Referring to Figure 12 , Figure 12 is a schematic diagram of an elliptical cluster failure yield wafer map in an embodiment of the present application.

[0161] The step of marking the failure chip in the elliptical wafer map can include: determining a sixteenth integer solution set satisfying the following formula:

[0162]

[0163] In the sixteenth integer solution set, a single integer solution (x 16 1 , y 16 1) is randomly selected; a first adjacent chip of the chip corresponding to the integer solution (x 16 1 , y 16 1) is randomly selected, then one of one or more second adjacent chips adjacent to the first adjacent chip is randomly selected, then one of one or more third adjacent chips adjacent to the second adjacent chip is randomly selected, until the selection number reaches k, where k is a positive integer, and 1 16 1 , y 16 1), the first adjacent chip, and the kth adjacent chip obtained by the kth random selection are taken as coordinates, the position of the failure chip is marked, to obtain a cluster failure yield wafer map; where a is the number of horizontal chips, and b is the number of vertical chips.

[0164] Wherein, k can be stepped value between 2 to (K x e%-1), so as to form more comprehensive block failure yield wafer map.

[0165] In Figure 12 The adjacent chips can be 2-8 in the step-by-step failure yield wafer map shown, which are randomly selected in each selection since the second selection. Figure 11 Since there is no exposure square limit, most of the adjacent chips of the chips are 8.

[0166] It should be pointed out that in Figures 4 to 12 The method for forming the yield wafer map shown can first determine the integer solution of all chips satisfying the elliptical standard equation, and then select the chip marked as a failure chip based on the integer solution of all chips and the preset failure type.

[0167] Wherein, the integer solution of all chips satisfying the elliptical standard equation satisfies the following formula:

[0168]

[0169] In the embodiments of the present application, after forming the elliptical wafer map, the position and number of failure chips are obtained according to the preset failure type and the elliptical standard equation, and a plurality of types of elliptical yield wafer maps are formed respectively, so as to meet the demand that a large number of yield wafer maps can be drawn under a plurality of failure reasons.

[0170] Referring to Figure 13 , Figure 13 is a schematic diagram of an elliptical yield wafer map with a randomly selected failure chip in the embodiments of the present application.

[0171] Specifically, after marking the failure chip in the elliptical wafer map, the method for forming the yield wafer map can further include: determining a seventeenth integer solution set satisfying the following formula:

[0172]

[0173] In the seventeenth integer solution set, one or more integer solutions (x 17 i , y 17 i) are randomly selected, wherein i is used to represent the i-th integer solution; in the elliptical wafer map, the one or more integer solutions (x 17 i , y 17i) The set of integer solutions of the marked failed chips; using the set of integer solutions as coordinates, update the position of the marked failed chips to obtain the elliptical yield wafer map; where a is the number of horizontal chips and b is the number of vertical chips.

[0174] In an embodiment of the present invention, in the elliptical wafer diagram, one or more randomly selected integer solutions (x) are determined. 17 i , y 17 i) The set of integer solutions with the marked failed chips can be used to add randomly selected failed chips to the elliptical yield wafer diagrams of various types, so that the automatically generated yield wafer diagrams can be closer to the actual yield results.

[0175] exist Figure 13 In China, with Figure 5 The example shown is a center failure yield wafer diagram. It can be understood that, based on other types of elliptical yield wafer diagrams, randomly selected failed chips can also be added to make the automatically generated yield wafer diagram closer to the actual yield result.

[0176] Continue to refer to Figure 1 In a specific implementation of step S13, the first shape wafer map is an elliptical wafer map, and the second shape wafer map is a circular wafer map. The step of obtaining a second shape yield wafer map corresponding to the first shape wafer map based on the number and location of the failed chips in the first shape wafer map may include: converting the elliptical yield wafer map into a circular yield wafer map.

[0177] Furthermore, before converting the elliptical yield wafer map into a circular yield wafer map, the method for forming the yield wafer map may further include: marking a preset proportion of failed chips as normal chips in the elliptical yield wafer map.

[0178] For example, when the preset ratio is set to 50%, 50% of the failed chips can be randomly selected from the elliptical yield wafer diagram and restored to normal chips.

[0179] In this embodiment of the invention, in the elliptical yield wafer diagram, a preset proportion of failed chips are marked as normal chips. This can remove a portion of the chips that have already been marked as failed chips, thereby avoiding a large difference between the pattern formed by the failed chips in the automatically generated yield wafer diagram and the yield wafer diagram obtained from actual production. This further makes the automatically generated yield wafer diagram closer to the actual yield result.

[0180] Further, in the elliptical yield wafer map, marking the failure chips of the preset proportion as normal chips can comprise: performing random sampling by using a random sampling function to obtain the failure chips of the preset proportion; and updating the positions of the failure chips in the elliptical yield wafer map by taking the integer solutions corresponding to the failure chips after the random sampling as coordinates.

[0181] Further, the random sampling can be performed by using a random sampling function in Python software or Excel software.

[0182] Referring to Figure 14 , Figure 14 is a schematic diagram of converting an elliptical yield wafer map into a circular yield wafer map in an embodiment of the present application.

[0183] The step of converting the elliptical yield wafer map into the circular yield wafer map can comprise: for each integer solution corresponding to a failure chip in the elliptical yield wafer map, determining the integer solution corresponding to the failure chip in the circular yield wafer map by using the following formula:

[0184] (x c ,y c )= (D / a × x E , D / b × y E )

[0185] marking the positions of the failure chips in the circular yield wafer map by taking the integer solutions corresponding to each failure chip in the circular yield wafer map as coordinates; wherein D is used to represent the diameter of the wafer, (x E , y E ) is used to represent the integer solution corresponding to the failure chip in the elliptical yield wafer map, (x c ,y c ) is used to represent the integer solution corresponding to the failure chip in the circular yield wafer map, and each integer solution corresponds to the unit length abscissa and unit length ordinate of the chip, respectively.

[0186] It should be noted that in the circular yield wafer map shown in Figure 14 , compared with the elliptical yield wafer map shown in Figure 13 , the relative positions of the chips remain unchanged in the process of converting the elliptical yield wafer map into the circular yield wafer map. However, the absolute positions and sizes of the chips can change.

[0187] As a non-limiting example, taking a = 30, b = 20, and the chip coordinate (20, 12) as an example, after the entire elliptical yield wafer map is converted into the circular yield wafer map, the coordinate is (100, 90).

[0188] In the embodiment of the present application, the first shape wafer map is determined based on the preset lateral chip quantity and longitudinal chip quantity, then the quantity and position of the failed chips in the first shape wafer map are determined based on the set position of the failed chips, and the second shape yield wafer map corresponding to the first shape wafer map is obtained, so that the accuracy and convenience of the failed chip marking are improved through shape conversion. In addition, the yield wafer map is drawn based on the lateral chip quantity and longitudinal chip quantity, and each chip quantity can correspond to a large number of chip sizes. For example, the yield wafer map composed of 100x50 chips can have a chip width of any value in the range of 2.95mm to 3.05mm. Therefore, compared with the scheme for determining the shape wafer map based on the chip size, the scheme of the embodiment of the present application can effectively reduce the total amount of drawing.

[0189] Reference Figure 15 , Figure 15 is a structural schematic diagram of a yield wafer map forming device in the embodiment of the present application. The yield wafer map forming device can include:

[0190] The first shape forming module 151 is configured to determine a first shape wafer map based on preset lateral chip quantity and longitudinal chip quantity.

[0191] The failed chip determining module 152 is configured to determine the quantity and position of the failed chips in the first shape wafer map based on the set pattern formed by the failed chips.

[0192] The second shape obtaining module 153 is configured to obtain a second shape yield wafer map corresponding to the first shape wafer map based on the quantity and position of the failed chips in the first shape wafer map.

[0193] The principle, specific implementation and beneficial effects of the yield wafer map forming device are described above in the related description of the yield wafer map forming method, and will not be described here again.

[0194] The embodiment of the present application further provides a readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the above method are executed. The readable storage medium can be a computer readable storage medium, for example, can include a non-volatile memory or a non-transitory memory, and can also include an optical disc, a mechanical hard disk, a solid state disk, etc.

[0195] The embodiment of the present application further provides a terminal including a memory and a processor. The memory stores a computer program capable of running on the processor. When the processor runs the computer program, the steps of the above method are executed. The terminal includes but is not limited to a server, a mobile phone, a computer, a tablet computer, etc.

[0196] Specifically, in the embodiments of the present application, the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor.

[0197] It should also be understood that the memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile memory can be a read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0198] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A method for forming a yield wafer pattern, characterized in that, include: Based on a preset number of horizontal and vertical chips, a first-shaped wafer pattern is determined, including: determining the number of horizontal and vertical chips in the wafer pattern; using one of the horizontal and vertical chip numbers as the semi-major axis and the other as the semi-minor axis to form a first ellipse; and based on the first ellipse, forming an elliptical wafer pattern, wherein each chip in the elliptical wafer pattern is represented by a square with a side length of unit length. Based on the pattern formed by the defined failed chips, determine the number and location of the failed chips in the first shaped wafer pattern; Based on the number and location of failed chips in the first shaped wafer diagram, a second shaped yield wafer diagram corresponding to the first shaped wafer diagram is obtained, including: converting the elliptical yield wafer diagram into a circular yield wafer diagram.

2. The method for forming a yield wafer pattern according to claim 1, characterized in that, Based on the first ellipse, forming an elliptical wafer pattern includes: Determine the first set of integer solutions that satisfy the following formula: ； The chip position is marked with the coordinates corresponding to each pair of integer solutions in the first integer solution set to obtain the elliptical wafer diagram; The integer solutions in the set of integer solutions correspond one-to-one with the chips in the elliptical wafer diagram, and each integer solution corresponds to the horizontal coordinate and vertical coordinate of the chip per unit length. a represents the number of horizontal chips, and b represents the number of vertical chips.

3. The method for forming a yield wafer pattern according to claim 1, characterized in that, Determining the number and location of failed chips in the first shaped wafer pattern based on the pattern formed by the defined failed chips includes: Based on the pattern formed by the defined failed chip, the failure type is determined; Based on the determined failure type, the failed chip is marked on the elliptical wafer diagram.

4. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the yield value; Determine the second set of integer solutions that satisfy the following formula: ； In the second set of integer solutions, select an integer solution of number P×(1-g%), where P represents the number of integer solutions in the second set of integer solutions and g% represents the yield value; Using the selected integer solutions as coordinates, the positions of the failed chips are marked to obtain a wafer map of the failure yield. Where a is the number of horizontal chips and b is the number of vertical chips.

5. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the first axis length ratio and the chip failure ratio, where the values ​​of the first axis length ratio and the chip failure ratio are both between 0 and 1; Determine the set of third integer solutions that satisfy the following formula: ； From the third set of integer solutions, select an integer solution of number Q×f%, where Q represents the number of integer solutions in the third set of integer solutions and f% represents the chip failure rate. Using the selected integer solutions as coordinates, the positions of the failed chips are marked to obtain a wafer map of the center failure yield. Where r1 represents the first axis length ratio, a is the number of horizontal chips, and b is the number of vertical chips.

6. The method for forming a yield wafer pattern according to claim 5, characterized in that, Also includes: Determine the second axis length ratio, the value of which is between 0 and 1, and the second axis length ratio is greater than the first axis length ratio; Determine the set of fourth integer solutions that satisfy the following formula: ； Remove the integer solutions that overlap with the third integer solution set from the fourth integer solution set to obtain the fifth integer solution set; From the fifth set of integer solutions, select an integer solution of size S×f%, where S represents the number of integer solutions in the fifth set of integer solutions. Using the selected integer solutions as coordinates, the positions of the failed chips are marked to obtain a ring-shaped failure yield wafer diagram; Wherein, r2 is used to represent the second axis length ratio, and the value of r2 is between 0 and 1.

7. The method for forming a yield wafer pattern according to claim 6, characterized in that, Also includes: Determine the set of the sixth integer solutions that satisfy the following formula: ； Remove the integer solutions that overlap with the fourth integer solution set from the sixth integer solution set to obtain the seventh integer solution set; From the seventh set of integer solutions, select a number of integer solutions of T×f%, where T represents the number of integer solutions in the seventh set of integer solutions; Using the selected integer solutions as coordinates, the positions of the failed chips are marked to obtain an edge failure yield wafer map.

8. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the set of the eighth integer solutions that satisfy the following formula: ； Two integer solutions are randomly selected from the eighth set of integer solutions; Using the two integer solutions as coordinates, form a first straight line passing through the coordinates of the two integer solutions; The first straight line is moved to obtain one or more translated first straight lines; For each moved first line, determine the ninth integer solution set for that moved first line; Determine the integer solutions at the intersection of the eighth integer solution set and the ninth integer solution set; Using the intersection of the eighth integer solution set and the ninth integer solution set as coordinates, the position of the failed chip is marked to obtain a linear failure yield wafer diagram; Where a is the number of horizontal chips and b is the number of vertical chips.

9. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the set of tenth integer solutions that satisfy the following formula: ； From the tenth set of integer solutions, a single integer solution (x) is randomly selected. 10 1, y 10 1); Determine x≥x in the tenth integer solution set 10 1 and y≤y 10 The eleventh integer solution set of 1, and determining x < x in the tenth integer solution set. 10 1 and y≤(y 10 The set of the twelfth integer solutions to (1-1); Using the integer solutions in the eleventh and twelfth integer solution sets as coordinates, the positions of the failed chips are marked to obtain a wafer diagram of abnormal test yield. Where a is the number of horizontal chips and b is the number of vertical chips.

10. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the set of the thirteenth integer solutions that satisfy the following formula: ； From the thirteenth set of integer solutions, a single integer solution (x) is randomly selected. 13 1, y 13 1); With the integer solution (x) 13 1, y 13 1) is the coordinate system, originating from the center of the elliptical wafer diagram and passing through the integer solution (x). 13 1, y 13 1) The second straight line of coordinates; The distance between the starting point and the second straight line is determined to be M×. The endpoint of , where M is a positive rational number and M > 1; With the endpoint as the center, and N×a and N×b as the semi-major axis and semi-minor axis respectively, a second ellipse is formed. The second ellipse covers a portion of the chip in the elliptical wafer diagram, where N is a positive rational number and N>1. Determine the set of the fourteenth integer solutions to the second ellipse; Determine the integer solutions at the intersection of the thirteenth set of integer solutions and the fourteenth set of integer solutions; Using the integer solutions of the intersection of the thirteenth and fourteenth integer solution sets as coordinates, the positions of the failed chips are marked to obtain an arc-shaped failure yield wafer diagram; Where a is the number of horizontal chips and b is the number of vertical chips.

11. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Each exposure square in the elliptical wafer diagram is determined such that the horizontal number of chips contained in each exposure square is the same, and the vertical number of chips contained in each exposure square is the same. Determine the set of the fifteenth integer solutions that satisfy the following formula: ； From the fifteenth set of integer solutions, a single integer solution (x) is randomly selected. 15 1, y 15 1); Determine the integer solution (x) 15 1, y 15 1) The corresponding exposure grid of the chip, and within that exposure grid, randomly select the integer solution (x) 15 1, y 15 1) The first adjacent chip of the corresponding chip, then randomly select one of the one or more second adjacent chips adjacent to the first adjacent chip, and then randomly select one of the one or more third adjacent chips adjacent to the second adjacent chip, until the number of selections reaches j, where j is a positive integer and 1 < j < J, and J is the number of chips contained in a single exposure square. With the integer solution (x) 15 1, y 15 1) The integer solutions from the first adjacent chip up to the j-th adjacent chip obtained by the j-th random selection are used as coordinates to mark the position of the failed chip; In at least a portion of the other exposed squares, the location of the failed chip is copied to obtain a step-failure yield wafer map; Where a is the number of horizontal chips and b is the number of vertical chips.

12. The method for forming a yield wafer pattern according to claim 3, characterized in that, Marking failed chips in the elliptical wafer diagram includes: Determine the set of the sixteenth integer solutions that satisfy the following formula: ； From the sixteenth set of integer solutions, a single integer solution (x) is randomly selected. 16 1, y 16 1); Randomly select the integer solution (x) 16 1, y 16 1) The first adjacent chip of the corresponding chip, then randomly select one of the second adjacent chips adjacent to the first adjacent chip, and then randomly select one of the third adjacent chips adjacent to the second adjacent chip, until the number of selections reaches k, where k is a positive integer and 1 < k < (K × e%), K is the number of integer solutions in the sixteenth integer solution set, and e% is the first preset percentage; With the integer solution (x) 16 1, y 16 1) The integer solutions of the first adjacent chip up to the kth adjacent chip obtained by the kth random selection are used as coordinates to mark the position of the failed chip, so as to obtain the wafer map of block failure yield; Where a is the number of horizontal chips and b is the number of vertical chips.

13. The method for forming a yield wafer pattern according to any one of claims 3 to 12, characterized in that, After marking the failed chip in the elliptical wafer diagram, the method further includes: Determine the set of the seventeenth integer solutions that satisfy the following formula: ； From the seventeenth set of integer solutions, one or more integer solutions (x) are randomly selected. 17 i, y 17 i), where i represents the i-th integer solution; In the elliptical wafer diagram, determine the one or more integer solutions (x) 17 i, y 17 i) The set of integer solutions to the marked failed chips; Using the integer solutions of the set as coordinates, update the position of the failed chip to obtain the elliptical yield wafer diagram; Where a is the number of horizontal chips and b is the number of vertical chips.

14. The method for forming a yield wafer pattern according to claim 1, characterized in that, Before converting the elliptical yield wafer map into a circular yield wafer map, the process also includes: In the elliptical yield wafer diagram, a preset proportion of failed chips are marked as normal chips.

15. The method for forming a yield wafer pattern according to claim 14, characterized in that, In the elliptical yield wafer diagram, marking a preset proportion of failed chips as normal chips includes: Random sampling is performed using a random sampling function to obtain a preset proportion of failed chips; Using the integer solutions corresponding to the randomly sampled failed chips as coordinates, the positions of the failed chips are updated and marked in the elliptical yield wafer diagram.

16. The method for forming a yield wafer pattern according to claim 1, characterized in that, Converting the elliptical yield wafer map into a circular yield wafer map includes: For each failed chip in the elliptical yield wafer diagram, the integer solution corresponding to the failed chip in the circular yield wafer diagram is determined using the following formula: (x c ,y c )= (D / a × x E , D / b × y E ) ; Using the integer solutions corresponding to each failed chip in the circular yield wafer diagram as coordinates, the positions of the failed chips are marked in the circular yield wafer diagram; Where D represents the diameter of the wafer, (x E , y E (x) is used to represent the integer solution corresponding to the failed chip in the elliptical yield wafer diagram. c ,y c ) is used to represent the integer solutions corresponding to the failed chips in the circular yield wafer diagram, and each integer solution corresponds to the horizontal coordinate and vertical coordinate of the chip per unit length.

17. An apparatus for forming a yield wafer pattern, characterized in that, include: A first shape forming module is used to determine a first shape wafer pattern based on a preset number of horizontal chips and a number of vertical chips. Specifically, it determines the number of horizontal chips and the number of vertical chips in the wafer pattern; uses one of the number of horizontal chips and the number of vertical chips as the semi-major axis and the other as the semi-minor axis to form a first ellipse; and forms an elliptical wafer pattern based on the first ellipse, wherein each chip in the elliptical wafer pattern is represented by a square with a side length of unit length. The failure determination module is used to determine the number and location of the failed chips in the first-shaped wafer pattern based on the pattern formed by the set failed chips. The second shape acquisition module is used to obtain a second shape yield wafer map corresponding to the first shape wafer map based on the number and location of the failed chips in the first shape wafer map, specifically by converting the elliptical yield wafer map into a circular yield wafer map.

18. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor, it performs the steps of the method for forming a yield wafer pattern according to any one of claims 1 to 16.

19. A terminal comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the method for forming a yield wafer pattern according to any one of claims 1 to 16.

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